SANYO LC749880T

Ordering number : ENA1186
LC749880T
CMOS IC
Silicon gate
Image controller LSI for LCD-TV
Overview
LC749880T is an LSI to display the converted NTSC/PAL analog video signals in the liquid crystal panel of maximum
VGA size.
This product performs A/D conversion, YC separation, color decoding, IP conversion, resolution conversion, and various
enhancements according to the panel.
When combined with a microcomputer and LCD panel, this product can readily makes up a video signal processing
circuit for flat panel display
Features
(1) Analog input
• 3ch A/D converter incorporated
• CVBS, S-Video,YCbCr/YPbPr input
(2) YC separation video decoder
• Adaptive 3-line comb filter
• AGC, ACC
(3) Resolution conversion
• Interlace - progressive conversion
• Expansion/compression possible independently in horizontal and vertical directions
(4) Enhancing functions
• Adjusting the TV picture quality: Contour correction, color, hue, luminance, contrast
• Adjusting the panel display picture quality: White balance, black balance,γ correction
• Color exciter (6-phase RGBYMC independent saturation adjustment)
• Shadow adjuster (emphaizing the three-dimensionality)
• Dither (8bit/6bit)
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
51408HKIM 20080319-S00007 No.A1186-1/17
LC749880T
Continued from preceding page.
(5) Panel interface
• Video signal of either RGB 24-bit (single phase) or 18-bit signal output
• Timing controller output for panel driver
(6) Others
• OSD I/F: R, G, B, EN
• Clock generator (PLL) incorporated
• I2C bus interface incorporated
LSI Specifications
• Supply voltage Core: 1.8V, I/O block: 3.3V
• Maximum operating frequency: 27MHz
• Package: TQFP120
Principal Applications
• LCD TV
Analog Input
CVBS×2ch: Composite video input 2channels
S-Video: S video input 1channel
YCbCr/YPbPr (480i/576i input compatible): Component input 1channel
YC Separation Video Decoder
A video decoder that converts either the NTSC/PAL video signal or component video signal into the digital video
signal is incorporated, which is compatible with the composite video signal, S video signal, and component video
signal (480i).
Resolution Conversion
Two-dimensional IP conversion, and expansion/contraction processings available
1. Interlace progressive conversion (IP conversion)
Two-dimensional IP conversion possible for NTSC/PAL input
2. Horizontal vertical scaler functions
Expansion/contraction to VGA size possible. Expansion/contraction possible independently in horizontal and
vertical directions. Full-screen display and zoom display possible.
Enhancement Functions
Various enhancement functions are available. Picture quality adjustment can be made appropriate to characteristics
of LCD-TV.
1. Adjusting the TV picture quality
1-1. Contour correction (horizontal vertical)
Contour correction of the input luminance signal. Adquate peaks are added around the contour.
In this case, coring adjustment is possible to prevent emphasizing of the peak amount and extremely small
noises.
1-2. Color
Saturation can be adjusted by adjusting the color gain of input color-difference signal.
1-3. Hue
The hue of the screen as a whole can be adjusted.
1-4. Luminance
Luminance of the screen as a whole can be adjusted.
1-5. Contrast
Brightness of the screen as a whole can be adjusted.
No.A1186-2/17
LC749880T
2. Adjusting the panel picture quality
2-1. White balance
White balance adjustment appropriate to LCD-TV is possible.
2-2. Black balance
Black balance adjustment appropriate to LCD-TV is possible.
2-3. γ correction
γ correction appropriate to LCD-TV is possible. The γ correction curve may be made programmable by means
of LUT γ correction can be made independently by RGB.
3. Color exciter
A total of 12 colors including red, green, blue, magenta, yellow, cyan, and colors between these colors can be
adjusted independently in terms of saturation.
4. Shadow adjuster
The three-dimensionality can be emphasized by adding the shading through addition of the adequate peaks before
and after the detected input signal contour.
5. Dither
In the case of 6-bit output, pseudo-mulltiple tone processing enables the output equivalent to the 8-bit output.
Panel Interface
1. Video output
Digital RGB 24-bit/18-bit output possible
2. Synchronizing signal (timing controller) output
Timing controller output and synchronizing signal output (horizontal/vertical synchronizing signal, data enable)
possible.
The output can be selected according to specifications of LCD module.
Others
1. OSD interface
This LSI has no OSD.
OSD can be interfaced with the external OSD microcomputer by means of the input pin (Pin Nos.: 105 to 108) and
output pin (Pin Nos.: 96,103,104).
Interlace synchronization/progressive synchronization can be changed over according to register setting.
The closed caption can be displayed.
2. I2C bus interface
The internal register is controlled by means of I2C. The slave address can be changed over by controlling the
“I2CSEL” pin (Pin No: 33) according to the system.
“L”
Slave address “88H”
I2CSEL
I2CSEL
“H”
Slave address “8AH”
I/O Specifications
1. Input Signals
Signal type
Video signal
No. of pins
Pin symbol
Description
1
CVBS1
1
CVBS2
1
CRIN
Component video signal input Cr
1
CBIN
Component video signal input Cb
1
YIN
Component video signal input Y
1
SY
S-Video signal input Y
Analog I/F
Remarks
Composite video signal input 1
Composite video signal input 2
1
SC
Synchronizing
1
VSI
Vertical synchronization
S-Video signal input C
Vertical synchronizing signal input pin (From Sync. Sep)
signal
1
HSI
Horizontal synchronization
Horizontal synchronizing signal input pin
OSD signal
1
BLKIN
OSD I/F
OSD signal input enable (From μ-CON)
(From Sync. Sep.)
1
RIN
OSD signal R input pin (From μ-CON)
1
GIN
OSD signal G input pin (From μ-CON)
1
BIN
OSD signal B input pin (From μ-CON)
Continued on next page
No.A1186-3/17
LC749880T
Continued from preceding page.
Signal type
No. of pins
Pin symbol
1
XIN
(1)
(DCLKO3)
Clock
Description
Remarks
Clock
Crystal oscillator input pin (27MHz)
Clock
Clock input when MODE≠0, 1
(GPIO pin)
System reset
1
RESET
System reset
System reset input pin (Lo-Active)
I/F mode selection
3
MODE
I/F mode selection
I/F mode selection signal input pin
0: Two-phase 6-bit output (TCON signal output)
1: Single-phase 8-bit/6-bit output
(RGB, TCON signal output)
DCLKO3; 3.375MHz output
2: Single-phase 8-bit/6-bit output
(RGB, TCON signal output)
DCLKO3; Clock input
3,4: Decoder output (RGB/YCbCr/YC
(register setting), synchronizing signal output)
5: Single-phase 8-bit/6-bit output
(RGB, synchronizing signal output)
* Others not applicable because they are not defined.
2. Output Signals
Signal type
Video signal
No. of pins
Pin symbol
(36)
(VP)
Description
Remarks
Digital I/F
Video signal output pin. MODE pin. Pin function changed
(GPIO pin)
through register setting. 6-bit output for output after dither
processing
For single-phase 8-bit output(MODE≠0)
VP00 to VP07: R0 to R7(Cb0 to Cb7)
VP08 to VP15: B0 to B7(Cb0 to Cr7/CbCr0 to CbCr7)
VP16 to VP23: G0 to G7(Y0 to Y7)
* ( ) shows the YCbCr
4:4:4/4:2:2 output (MODE=3,4)
For single-phase 6-bit output (MODE≠0)
VP00 to VP05: R0 to R5
VP08 to VP13: B0 to B5
VP16 to VP21: G0 to G5
For two-phase 6-bit output (MODE=0)
VP00 to VP05: RO0 to RO5
VP18 to VP23: RE0 to RE5
VP06 to VP11: BO0 to BO5
VP24 to VP29: BE0 to BE5
VP12 to VP17: GO0 to GO5
VP30 to VP35: GE0 to GE5
* xO: Odd-numbered picture elements
xE: Even-numbered picture elements
Synchronizing
1
SVO
(1)
(TIM1)
signal
(1)
Data enable
signal
(1)
(TIM2)
(TIM0)
Analog I/F
Internal analog video signal output
Vertical synchronizing
Applicable when MODE=3, 4, and 5. Synchronizing
(GPIO pin)
period, Polarity reversal possible
Horizontal synchronization
Applicable when MODE≠0. Synchronizing period.
(GPIO pin)
Polarity reversal possible
Data enable
Applicable when MODE=3, 4, and 5. H,V composite
(GPIO pin)
data enable output. Position, polarity reversal possible
Continued on next page
No.A1186-4/17
LC749880T
Continued from preceding page.
Signal type
TCON signal
No. of pins
Pin symbol
(1)
(GRST)
Description
Remarks
TCON signal
When MODE=0, the gate reset signal output/clamp
(GPIO pin)
pulse output/PWM3 output selectable through register selection
When MODE≠0, the gate reset signal output/clamp
pulse output selectable through register selection
GRST: Pulse width, position, and polarity reversal possible
1
FLM
When MODE=0, 1, and 2, gate start pulse signal output
Pulse width, position, polarity reversal possible. Hi-Z
when FLM2 is used
1
OE
When MODE=0, 1, and 2, gate output enable signal output.
Pulse width, position, polarity reversal possible.
1
CPV
When MODE=0, 1, and 2, gate clock signal output.
Pulse width, position, polarity reversal possible.
1
STRB
When MODE=0, 1, and 2, source strobe signal output.
Pulse width, position, polarity reversal possible.
1
SP
When MODE=0, 1, and 2, source start pulse signal output.
Pulse width, position, polarity reversal possible. Hi-Z
when SP2 is used
1
DEXR
When MODE=0, 1, and 2, source picture element reversal signal
output.
When MODE=0, DEXR output of odd-numbered picture
elements
1
POL
When MODE=0, 1, and 2, source voltage polarity
selection signal output.
Position adjustment, 1 line/2 line reversal and 1 frame/2
frame reversal possible
(1)
(TIM0)
When MODE=0, 1, and 2, FLM2 output through register setting
Pulse width, position, polarity reversal possible. Hi-Z
when FLM is used
(1)
(TIM1)
When MODE=0,1, and 2, SP2 output through register setting
Pulse width, position, polarity reversal possible. Hi-Z
when SP2 is used
(1)
(TIM2)
1
DCLKO
1
(DCLKO3)
1
XOUT
1
VSO
When MODE=0, DEXR (DEXR_E) output of
even-numbered picture elements
Clock
Dot clock
Picture element clock output. Polarity reversal, 1/2
output possible
For OSD signal
Clock
When MODE=0 and 1, clock output (3.357MHz)
Crystal oscillator output pin
OSD I/F
Vertical synchronizing signal output for OSD (To μ-CON)
Pulse width, position, polarity reversal possible.
1
Horizontal synchronizing signal output for OSD (To μ-CON)
HSO
Pulse width, position, polarity reversal possible.
1
DCLKO2
(1)
(VP32)
(1)
(VP35)
Picture-element clock output for OSD (To μ-CON)
Polarity reversal, 1/2 output possible
PWM output
PWM signal
(GPIO pin)
When MODE≠0, PWM1 output through register setting.
Pulse width, position, polarity reversal possible.
When MODE≠0, PWM2 output/PWM3 output/clamp pulse output
selectable through register setting.
PWM2, 3: Pulse width, position, polarity reversal possible.
(1)
(GRST)
When MODE=0, PWM3 output/GRST output/clamp pulse output
selectable through register setting
PWM3: Pulse width, position, polarity reversal possible.
Clamp pulse
(1)
(VP35)
Clamp pulse
When MODE≠0, clamp pulse output/PWM2 output/PWM3 output
(GPIO pin)
selectable through register setting
Clamp pulse: Pulse width and position adjustment possible.
(1)
(GRST)
When MODE=0, clamp pulse output/GRST output/PWM3 output
selectable through register setting.
When MODE≠0, clamp pulse output/GRST output selectable
through register setting
Clamp pulse: Pulse width and position adjustment possible.
* The signals in parentheses show that one pin has multiple functions or acts as the I/O pin.
Selection can be made with the MODE pin or through register setting.
No.A1186-5/17
LC749880T
3. Control Signal
Signal type
No. of pins
2
I C bus
Pin symbol
2
1
I CSEL
1
Description
Remarks
2
Slave changeover
I C BUS bus slave address setting (normally “L”)
SDA
Data bus
Slave address for internal register setting and internal status
1
SCL
Bus clock
output: ”1000100+(R/W)”
No. of pins
Pin symbol
1
SCANEN
“L”: 88H, “H”: 8AH
4. Other Signals
Signal type
SCAN test
Description
SCAN test
Remarks
Test pin (Normally, ”L”)
1
SCANMOD
Test
1
TEST
Test
Test pin (Normally, ”L”)
ADC/AFE
3
VRT
ADC/AFE
ADC top level reference output
AGC
PLL
Test pin (Normally, ”L”)
3
VRB
1
NBIAS
ADC bias voltage output
1
VREF
ADC reference output
1
VRTC
1
LPFO
1
LPFVDD
1
CHAGPUP
1
VCOR
ADC bottom level reference output
AGC
AGC control voltage input
AGC PWM output
AGC PWM output buffer power supply
PLL
Charge pump output for built-in PLL
Range resistor for built-in PLL
Package Dimensions
unit : mm (typ)
3257A
14.0
16.0
0.5
16.0
14.0
120
1
0.4
0.15
0.125
0.1
1.2MAX
(1.0)
(1.2)
SANYO : TQFP120(14X14)
No.A1186-6/17
LC749880T
Pin Assignment
90
85
75
80
70
65
DVSS
DVDD33
DVDD18
VP12(GO0/B4)
VP13(GO1/B5)
VP14(GO2/B6)
VP15(GO3/B7)
VP16(GO4/G0)
VP17(GO5/G1)
VP18(RE0/G2)
VP19(RE1/G3)
VP20(RE2/G4)
VP21(RE3/G5)
VP22(RE4/G6)
VP23(RE5/G7)
VP24(BE0/-)
VP25(BE1/-)
VP26(BE2/-)
VP27(BE3/-)
VP28(BE4/-)
DVDD33
DVSS
DVDD18
VP29(BE5/-)
VP30(GE0/-)
VP31(GE1/-)
VP32(GE2/EXCTR1 or PWM1)
VP33(GE3/EXCTR2)
61
60
95
55
100
50
LC749880T
105
45
110
40
115
35
120
5
10
15
20
25
30
60
VP11(BO5/B3)
VP10(BO4/B2)
VP09(BO3/B1)
VP08(BO2/B0)
VP07(BO1/R7)
VP06(BO0/R6)
VP05(RO5/R5)
VP04(RO4/R4)
VP03(RO3/R3)
VP02(RO2/R2)
VP01(RO1/R1)
VP00(RO0/R0)
TIM2(DEXR_E/Hsync)
TIM1(FLM2/Vsync)
TIM0(SP2/DE)
POL(*1)
DEXR(*1)
DVDD18
DVSS
DVDD33
SP(*1)
STRB(*1)
CPV(*1)
OE(*1)
FLM(*1)
GRST
RESET
2
I CSEL
SCANMOD
SCANEN
31
CRIN
VRT1
VRB1
AVSS33
CBIN
AVSS33
SC
AVDD33
VRT2
VRB2
NBIAS
VREF1
AVSS18
SVO
AVDD18
YIN
AVSS33
SY
AVSS33
CVBS1
AVSS33
CVBS2
AVSS33
VRT3
VRB3
VRTC
RVSS33
RVDD33
LPFO
LPFVDD
91 AVSS18
CHAGPUP
VCOR
AVDD18
DCLKO3
DCLKO2
DVDD18
DVDD33
XIN
XOUT
DVSS
DCLKO
VSI
HSI
RIN
GIN
BIN
BLKIN
HSO
VSO
PDWN
SCL
SDA
TEST
MODE0
MODE1
MODE2
DVDD33
DVSS
DV
DD18
120
VP34(GE4/-)
VP35(GE5/PWM2 or PWM3)
90
Top view
*1: NC for the mode in which built-in TCON is not to be used.
No.A1186-7/17
LC749880T
Pin Functions
Pin No.
I/O format
Pin symbol
I/O
Format
1
CRIN
I
A
2
VRT1
O
A
3
VRB1
O
A
4
AVSS33
P
5
CBIN
I
6
AVSS33
P
7
SC
I
8
AVDD33
P
Connected to
Analog IF
Remarks
Analog CR input (ADC1)
Top level reference voltage connection pin for ADC1
Bottom level reference voltage connection pin for ADC1
Analog GND
A
Analog IF
A
Analog IF
Analog CB input (or S-C) (ADC2)
Analog GND
Analog S-C input (ADC2)
Analog 3.3V
9
VRT2
O
A
Top level reference voltage connection pin for ADC2
10
VRB2
O
A
Bottom level reference voltage connection pin for ADC2
11
NBIAS
O
A
Bias voltage connection pin for ADC
12
VREF1
O
A
Reference voltage connection pin for ADC
13
AVSS18
P
14
SVO
O
15
AVDD18
P
16
YIN
I
17
AVSS33
P
18
SY
I
19
AVSS33
P
20
CVBS1
I
21
AVSS33
P
Analog GND
A
ADC3 input internal analog video signal output
Analog 1.8V
A
Analog IF
Analog Y input (or S-Y,CVBS) (ADC3)
Analog GND
A
Analog IF
Analog S-Y input (or CVBS) (ADC3)
Analog GND
A
Analog IF
Analog CVBS1 input (ADC3)
Analog GND
22
CVBS2
I
23
AVSS33
P
A
Analog IF
Analog CVBS2 input (ADC3)
24
VRT3
O
A
Top level reference voltage connection pin for ADC3
25
VRB3
O
A
Bottom level reference voltage connection pin for ADC3
26
VRTC
I
A
27
RVSS33
P
Analog GND
VREF generator circuit analog GND
28
RVDD33
P
Analog 3.3V
VREF generator circuit analog 3.3V
29
LPFO
O
A
AGC PWM output
30
LPFVDD
I
A
AGC PWM output buffer power supply
31
SCANEN
I
C
Test pin (Normally, Lo)
32
SCANMOD
I
C
Test pin (Normally, Lo)
33
I2CSEL
I
C
I2C slave addresses L=0×88, H=0×8A
34
RESET
I
B
System reset (Active Lo)
35
GRST
I/O
G
Gate reset signal (or test input)
36
FLM
I/O
G
Gate start signal (or test input)
37
OE
I/O
G
Gate OE signal (or test input)
38
CPV
I/O
G
Gate lock signal (or test input)
39
STRB
I/O
G
Source strobe signal (or test input)
40
SP
I/O
G
Source start signal (or test input)
41
DVDD33
P
Digital 3.3V
42
DVSS
P
Digital GND
43
DVDD18
P
Digital 1.8V
44
DEXR
I/O
G
Source picture element reversal signal (or test input)
45
POL
I/O
G
Source line reversal signal (or test input)
46
TIM0
O
E
Data enable signal output/FLM2 (register selection)
47
TIM1
O
E
Vertical synchronizing signal output/SP2 (register selection)
Analog GND
AGC control voltage input
48
TIM2
O
E
Horizontal synchronizing signal output
49
VP00
O
E
Video signal output R0/R_ODD_0 (MODE pin select=0)
50
VP01
O
E
Video signal output R1/R_ODD_1 (MODE pin select=0)
51
VP02
O
E
Video signal output R2/R_ODD_2 (MODE pin select=0)
Continued on next page.
No.A1186-8/17
LC749880T
Continued from preceding page.
Pin No.
I/O format
Pin symbol
I/O
Connected to
Remarks
Format
52
VP03
O
E
Video signal output R3/R_ODD_3 MODE pin select=0)
53
VP04
O
E
Video signal output R4/R_ODD_4 (MODE pin select=0)
54
VP05
O
E
Video signal output R5/R_ODD_5 (MODE pin select=0)
55
VP06
O
E
Video signal output R6/B_ODD_0 (MODE pin select=0)
56
VP07
O
E
Video signal output R7/B_ODD_1 (MODE pin select=0)
57
VP08
O
E
Video signal output B0/B_ODD_2 (MODE pin select=0)
58
VP09
O
E
Video signal output B1/B_ODD_3 (MODE pin select=0)
59
VP10
O
E
Video signal output B2/B_ODD_4 (MODE pin select=0)
60
VP11
O
E
Video signal output B3/B_ODD_5 (MODE pin select =0)
61
DVDD33
P
Digital 3.3V
62
DVSS
P
Digital GND
63
DVDD18
P
64
VP12
O
E
Video signal output B4/G_ODD_0 (MODE pin select=0)
65
VP13
O
E
Video signal output B5/G_ODD_1 (MODE pin select=0)
66
VP14
O
E
Video signal output B6/G_ODD_2 (MODE pin select=0)
67
VP15
O
E
Video signal output B7/G_ODD_3 (MODE pin select=0)
68
VP16
O
E
Video signal output G0/G_ODD_4 (MODE pin select=0)
69
VP17
O
E
Video signal output G1/G_ODD_5 (MODE pin select=0)
70
VP18
O
E
Video signal output G2/R_EVEN_0 (MODE pin select=0)
71
VP19
O
E
Video signal output G3/R_EVEN_1 (MODE pin select=0)
72
VP20
O
E
Video signal output G4/R_EVEN_2 (MODE pin select=0)
73
VP21
O
E
Video signal output G5/R_EVEN_3 (MODE pin select=0)
74
VP22
O
E
Video signal output G6/R_EVEN_4 (MODE pin select=0)
75
VP23
O
E
Video signal output G7/R_EVEN_5 (MODE pin select=0)
76
VP24
I/O
G
-/Video signal output B_EVEN_0 (MODE pin select=0)
77
VP25
I/O
G
-/Video signal output B_EVEN_1 (MODE pin select=0)
78
VP26
I/O
G
-/Video signal output B_EVEN_2 (MODE pin select=0)
79
VP27
I/O
G
-/Video signal output B_EVEN_3 (MODE pin select=0)
80
VP28
I/O
G
-/Video signal output B_EVEN_4 (MODE pin select=0)
81
DVDD33
P
Digital 3.3V
82
DVSS
P
Digital GND
83
DVDD18
P
84
VP29
I/O
G
-/Video signal output B_EVEN_5 (MODE pin select=0)
85
VP30
I/O
G
-/Video signal output G_EVEN_0 (MODE pin select=0)
86
VP31
I/O
G
-/Video signal output G_EVEN_1 (MODE pin select=0)
87
VP32
I/O
G
-/Video signal output G_EVEN_2 (MODE pin select=0)
88
VP33
I/O
G
-/Video signal output G_EVEN_3 (MODE pin select=0)
89
VP34
I/O
G
PWM signal/Video signal output G_EVEN_4 (MODE pin select=0)
90
VP35
I/O
G
91
AVSS18
P
92
CHAGPUP
O
A
Charge pump output
93
VCOR
I
A
Range resistor for PLL
Digital 1.8V
Digital 1.8V
PWM signal/Video signal output G_EVEN_5 (MODE pin select=0)
Analog GND
94
AVDD18
P
95
DCLKO3
I/O
H
Analog 1.8V
Clock I/O
96
DCLKO2
O
F
Clock output (dedicated to microcomputer, with 1/2 or DE)
97
DVDD18
P
Digital 1.8V
98
DVDD33
P
Digital 3.3V
99
XIN
I
100
XOUT
O
101
DVSS
P
102
DCLKO
O
103
VSI
I
B
Vertical synchronizing signal input
104
HSI
I
B
Horizontal synchronizing signal input
Crystal oscillator connection pin (27MHz)
D
Crystal oscillator connection pin
Digital GND
F
Panel clock output
Continued on next page.
No.A1186-9/17
LC749880T
Continued from preceding page.
Pin No.
I/O format
Pin symbol
I/O
Format
Connected to
Remarks
105
RIN
I
C
R input of microcomputer OSD
106
GIN
I
C
G input of microcomputer OSD
107
BIN
I
C
B input of microcomputer OSD
108
BLKIN
I
C
BLK input of microcomputer OSD
109
HSO
O
E
Horizontal synchronizing signal output for microcomputer
110
VSO
O
E
Vertical synchronizing signal output for microcomputer
111
PDWN
I
B
Power DOWN (Active Lo)
112
SCL
I
B
I2C bus clock
113
SDA
I/O
G
I2C bus data
114
TEST
I
C
Test pin (normally, Lo)
115
MODE0
I
C
I/F mode pin
116
MODE1
I
C
I/F mode pin
117
MODE2
I
C
118
DVDD33
P
Digital 3.3V
119
DVSS
P
Digital GND
120
DVDD18
P
Digital 1.8V
I/F mode pin
No.A1186-10/17
LC749880T
Pin Type
I/O type
A
Function
Analog I/O
Equivalent circuit
Applicable pins
CRIN, VRT1, VRB1, CBIN, SC, VRT2, VRB2,
NBIAS, VREF1, SVO, YIN, SY, CVBS1,
CVBS2, VRT3, VRB3, VRTC, LPFO, LPFVDD,
CHAGPUP, VCOR
B
5V withstand
RESET,
Schmidt trigger
VSI, HSI,
CMOS input*
PDWN, SCL
5V withstand
SCANEN, SCANMOD, I2CSEL,
With Pull-down
RIN, GIN, BIN, BLKIN, TEST,
CMOS input*
MODE0, MODE1, MODE2
D
Oscillator circuit I/O
XIN, XOUT
E
8mA 3-STATE drive
TIM0, TIM1, TIM2, VP00, VP01, VP02,
CMOS output*
VP03, VP04, VP05, VP06, VP07, VP08,
C
VP09, VP10, VP11, VP12, VP13, VP14,
VP15, VP16, VP17, VP18, VP19, VP20,
VP21, VP22, VP23, HSO, VSO
F
12mA 3-STATE drive
DCLKO2, DCLKO
CMOS output*
G
8mA 3-STATE drive
GRST, FLM, OE, CPV, STRB, SP, DEXR,
CMOS I/O*
POL, VP24, VP25, VP26, VP27, VP28, VP29,
VP30, VP31, VP32, VP33, VP34, VP35,
SDA
H
12mA 3-STATE drive
DCLKO3
CMOS I/O*
*: 5V Tolerant
No.A1186-11/17
LC749880T
Electrical Characteristics
Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V
Parameter
Symbol
Rating
Unit
Maximum supply voltage (I/O)
DVDD33
Maximum supply voltage (core)
AVDD33
DVDD18
Digital input voltage
AVDD18
VI
-0.5 to 6.0
V
Digital output voltage
VO
-0.3 to VDD + 0.3
V
Storage temperature
Tstg
-55 to +125
°C
Operating temperature
Topr
-30 to +70
°C
0.6
W
Maximum allowable loss
-0.3 to +4.0
V
-0.3 to +2.2
V
Pd max
Allowable Operation Range at Ta = -30 to +70°C
Parameter
Symbol
Supply voltage (I/O)
DVDD33
AVDD33
Supply voltage (core)
DVDD18
Input voltage range
AVDD18
VIN
min
typ
max
Unit
3.15
3.3
3.45
V
1.71
1.8
1.89
V
5.5
V
0
I/O Pin Capacity at Ta = 25°C, VDD = VI = 0V
Parameter
Symbol
Conditions
min
typ
max
Unit
Input pin
CIN
f=1MHz
10
pF
Output pin
COUT
f=1MHz
10
pF
I/O pin
CI/O
f=1MHz
10
pF
DC Characteristics at Ta = -30 to +70°C, DVDD33 = 3.3V±5%, DVDD18 = 1.8V±5%
Parameter
Input high-level voltage
Input low-level voltage
Input high-level current
Symbol
VIH
VIL
IIH
Conditions
min
typ
max
Unit
CMOS compatible
2.0
5.5
CMOS compatible schmidt
2.0
5.5
V
Oscillator circuit input
2.0
3.465
V
CMOS compatible
-0.3
+0.8
V
CMOS compatible schmidt
-0.3
+0.8
V
Oscillator circuit input
-0.3
+0.8
V
VI=VDD
-10
+10
μA
VI=VDD
with pull-down resistor
+10
+100
μA
+10
μA
V
Input low-level current
IIL
VI=VSS
-10
Output high-level voltage
VOH
CMOS
2.4
V
Oscillator circuit output
2.4
V
Output low-level voltage
VOL
CMOS
0.4
V
Oscillator circuit output
0.4
V
μA
118
kΩ
IOZ
Pull-down resistor
RDN
Operating current
IDDOP
tck=27MHz
Operating current (AVDD33)
IDDOP
tck=27MHz gray scale
15
Operating current (AVDD18)
tck=27MHz gray scale
70
mA
Operating current (DVDD33)
tck=27MHz gray scale
20
mA
Operating current (DVDD18)
tck=27MHz gray scale
90
mA
Output release,VI=VSS or VDD
10
μA
Current drain at rest *1
IDDST
At output of high-impedance
+10
Output leak current
-10
43
58
mA
mA
*1: There is an input pin incorporating pull-down resistor. Note that, depending on circuit composition, the current
drain at rest may not be guaranteed.
No.A1186-12/17
LC749880T
A/D Convertor Characteristics at Ta = -30 to +70°C, DVSS = 0V, AVSS = 0V
Parameter
Symbol/pin
min
typ
Clock frequency
Fclk
Clamp pulse width
Tcl
0.45
Analog video pin
0.01
max
Unit
27
MHz
μs
External capacitance
Analog input coupling capacitance
μF
10
Top level reference fixed capacitance
VRTx pin
0.01
μF
Bottom level reference capacitance
VRBx pin
0.01
μF
VREF1 bias fixed capacitance
VREF1 pin
0.01
μF
NBIAS bias fixed capacitance
NBIAS pin
0.01
Analog input frequency
μF
FAIN
4
MHz
1.0
Vp-p
1.1
Vp-p
Analog input amplitude (Max amplitude)
In the non-AGC operation mode
FS1AIN
In the AGC operation mode *1
FS2AIN
0.6
ADC reference input voltage
In the non-AGC operation mode
Bottom level reference input
VRBI
0.65
V
VRBI
0.65
V
In the AGC operation mode
Bottom level reference input
DC Characteristics at Ta=25°C, VDD3=3.3V±5%,VDD=1.8V±5%, DVSS = 0V, AVSS = 0V
Parameter
Symbol
Operating supply current
Conditions
IDD3
VDD3=3.3V
IDD
VDD=1.8V
Fclk=27MHz
ISB3
VDD3=3.3V
ISB
VDD=1.8V
Fclk=0MHz
min
typ
3.3V power supply
1.8V power supply
Standby supply current
3.3V power supply
1.8V power supply
max
Unit
16
mA
16
mA
-10
+10
μA
-10
+10
μA
ADC Conversion Characteristics at Ta=25°C,VDD3=3.3V±5%,VDD=1.8V±5%, DVSS = 0V, AVSS = 0V
Parameter
Symbol
Resolution
Conditions
min
typ
max
RES
Unit
10
bits
I/O Data Timing
(1) Input data timing 1
tCK
tHI
VDD33/2
XIN
tSU
tHD
tLO
VDD33/2
Input data
Pin name
XIN
VP24-34
Parameter
Symbol
max
Unit
Clock L-level time
tLO
18.5
ns
Clock H-level time
tHI
18.5
ns
Clock cycle
tCK
37
ns
Input data setup time
tSU
3.5
ns
Input data hold time
tHD
3.5
ns
POL, FLM, OE, CPV, STRB
SP, DEXR
min
RIN, GIN, BIN, BLKIN
* The recommended duty ratio of input clock is 50%
No.A1186-13/17
LC749880T
(2) Input data timing 2
tHI
tCK
VDD33/2
DCLKO3
SDCLK
tSU
tLO
tHD
VDD33/2
Input data
Pin name
DCLKO3
Parameter
Symbol
min
max
Unit
Clock L-level time
tLO
18.5
Clock H-level time
tHI
18.5
ns
ns
Clock cycle
tCK
37
ns
VSI
Input data setup time
tSU
3.5
ns
HSI
Input data hold time
tHD
3.5
ns
(3) Output data timing (1)
tCK
tHI
VDD33/2
DCLKO
tAC
tLO
tHD
VDD33/2
Output data
Pin name
Parameter
DCLKO
VP00-31
Symbol
min
Unit
tLO
18.5
ns
Clock H-level time
tHI
18.5
ns
Clock cycle
tCK
37
ns
Output data delay time
tAC
-3.5
Output data hold time
tHD
TIM0, TIM1, TIM2
POL, FLM, OE, CPV, STRB
max
Clock L-level time
+3.5
30.0
SP, DEXR, GRST
ns
ns
(3) Output data timing (2)
tCK
tHI
VDD33/2
DCLKO2
tAC
tLO
tHD
VDD33/2
Output data
Pin name
DCLKO2
VSO,HSO
Parameter
Symbol
min
max
Clock L-level time
tLO
Clock H-level time
tHI
Clock cycle
tCK
37
Output data delay time
tAC
-3.5
Output data hold time
tHD
30.0
Unit
18.5
ns
18.5
ns
ns
+3.5
ns
ns
No.A1186-14/17
LC749880T
I/O Clock Timing
(1) Input system clock timing
tHI
tCK
Input XIN
VDD33/2
tLO
tOUT1
Output DCLKO
VDD33/2
tOUT2
Output DCLKO2
VDD33/2
tOUT3
Output DCLKO3
Pin name
XIN
VDD33/2
Parameter
Symbol
min
max
Unit
Clock L-level time
tLO
18.5
ns
Clock H-level time
tHI
18.5
ns
Clock cycle
tCK
37
ns
DCLKO
DCLKO delay time
tOUT1
18.5
ns
DCKLO2
DCLKO2 delay time
tOUT2
18.5
ns
DCKLO3
DCLKO3 delay time
tOUT3
12.5
ns
No.A1186-15/17
LC749880T
Sample Application Circuit
AU1
LV1116
AU2
LA4635A
Multiplex
Tuner
(2in1)
LC749880T
R
CVBS1
CVBS2
S-Y
S-C
Y
AFE
&
ADC
YC
Sep.
&
Chroma
Dec.
Cb
NoiseCanceller
Scaler
Color
Tint
Color Exitor
Shadow Adjuster
Cr
SVO
Sharpness
Brightness
Contrast
&
White
Balance
&
Black
Balance
&
γ Correction
G
B
Timing
Controller
DCLK
LCD
Panel
(VGA)
Timings
DHS
DVS
DDE
CNT1
HSI
VSI
Inverter
PLL
SDA
XIN
SCL
XOUT
RIN
HSO
X’tal
VSO
CLKO
LC87xxxx
(μ-CON)
Others (for TEST ⋅ ⋅ ⋅)
GIN
BIN
27.0MHz
EN
LV78200
(Sync. Sep.)
X’tal
32.768kHz
No.A1186-16/17
LC749880T
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of May, 2008. Specifications and information herein are subject
to change without notice.
PS No.A1186-17/17