Ordering number : ENA1647
CMOS IC
LC74950BG
Silicon gate
40/30MSPS Analog Display
I/F LSI
Overview
The LC74950BG is an analog display I/F IC that converts analog video signals into equivalent digital video signals.
It incorporates 3 channels of ADC and a PLL circuit.
Features
• Maximum sampling frequency: 40MSPS
• 8-bit output
• Supports self-clamp (bottom/center switching) and digital clamp
• Input signal: 1.0Vp-p maximum
• External clock input
• Low jitter PLL
• Power down mode
• Low power consumption
• Input format: Supports RGB and YCbCr
• Built-in I2C bus interface
LSI Specifications
• Supply voltage Core: 1.5±10%
I/O: 3.3V±0.3V (40MHz) or 2.4V to 3.6V (30MHz)
• Maximum operating frequency: 40MHz
• Package: FBGA96
Principal Applications
• Small-size monitors
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
31710HKIM 20091215-S00006 No.A1647-1/37
LC74950BG
Functions & Overview
1. Input
All the inputs listed below can be connected to the analog ports. It is also possible to switch between the inputs of
two systems and use the one selected.
YCbCr/YPbPr input (480I/576I, 480P/576P): Component input
RGB: RGB input
External clock supported
2. Output
Digital 8-bit/channel output
3. Clamp
Analog clamping and digital clamping supported
4. Gain
Digital gain adjustment
5. PLL circuit
This circuit can be used as the H lock or frequency-multiplied clock. It is also possible to use the PLL circuit and
analog-digital converter (ADC) independently.
H lock PLL circuit: This makes it possible to generate a clock synchronized with the external H sync signal.
Frequency-multiplier PLL circuit: This makes it possible to generate clocks synchronized with an external clock.
6. External interface
I2C: This supports the 100kHz mode. It is possible to select slave addresses by establishing pin settings.
Slave addresses: 0x98, 0x9A
7. PDOWN
Power-down of the whole system can be controlled using the PDOWN pin. Alternatively, the ADC, PLL and other
circuits can be powered down separately using register settings. This makes it possible to limit the power as required.
Specifications
Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage (I/O)
DVDD33
AVDD33
-0.3 to +3.95
V
Maximum supply voltage (core)
DVDD15
AVDD15
-0.3 to +1.8
V
VI
Digital input voltage
-0.3 to +5.5
V
VI
(when in low voltage)
-0.3 to DVDD33+0.3
V
Digital output voltage
VO
-0.3 to DVDD33+0.3
V
Operating temperature
Topr
-30 to +70
°C
Storage temperature
Tstg
-55 to +125
°C
Allowable Operating Ranges at Ta = -30 to +70°C
Parameter
Supply voltage (I/O)
Symbol
AVDD33
DVDD33
Supply voltage (I/O)
DVDD15
AVDD15
Input voltage range
VIN5
(5V withstand voltage pin)
Input voltage range
(non-5V withstand voltage pin)
Conditions
VIN
Ratings
min
typ
unit
max
3.00
3.3
3.60
V
Max 40MHz
3.00
3.3
3.60
V
Max 30MHz
2.40
3.3
3.60
V
1.35
1.5
1.65
V
0
5.5
V
0
3.9
V
No.A1647-2/37
LC74950BG
DC Characteristics at Ta = -30 to +70°C, DVDD33 = 3.3V±0.3V (other than low-voltage support models),
DVDD15= 1.5±10%
Parameter
Symbol
Input high-level voltage
VIH
Ratings
Conditions
min
CMOS level inputs
5.5
V
0.8DVDD33
DVDD33
V
2.0
5.5
V
0.8DVDD33
DVDD33
V
CMOS level inputs
0
0.2VDD33
V
CMOS level Schmitt inputs
0
0.2VDD33
V
10
μA
CMOS level inputs (2.4V to 3.6V or
non-5V withstand voltage pin)
CMOS level Schmitt inputs
(5V withstand voltage pin)
CMOS level Schmitt inputs (2.4V to 3.6V or
non-5V withstand voltage pin)
VIL
Input high-level current
IIH
Input low-level current
IIL
Output high-level voltage
VOH
unit
max
0.8DVDD33
(5V withstand voltage pin)
Input low-level voltage
typ
VI=DVDD
VI=DVDD, with pull-down resistance
μA
100
VI=VSS
CMOS (Pin G/I: IOH=-4mA, Pin F: when
set to -6mA)
-10
μA
DVDD-0.6
V
Output low-level voltage
VOL
CMOS
Output leak current
IOZ
At output of high-impedance
Pull-down resistor
RDN
3.0V to 3.6V
58
kΩ
2.4V to 3.6V
70
kΩ
Dynamic supply current
IDDOP
13
mA
7
mA
52
mA
0.1
mA
10
μA
-10
Outputs open, tck=27MHz
(DVDD33)
natural image, Ta=25°C
Dynamic supply current
tck=27MHz: natural image, Ta=25°C
(DVDD15)
Dynamic supply current
tck=27MHz: natural image, Ta=25°C
(AVDD33)
Dynamic supply current
(AVDD15)
Static supply current: *1
tck=27MHz: natural image, Ta=25°C
IDDST
Outputs open, VI=VSS, Ta=25°C
0.4
V
10
μA
*1: There is an input terminal which builds in pull down resistance. Please note that there is no guarantee about static
consumption current depending on circuit composition.
A/D Convertor Characteristics at Ta = 25°C, DVSS = 0V, AVSS = 0V
Parameter
Symbol/pin
min
typ
max
ADC resolution
Clock frequency
Fclk
5
Unit
9
bit
40
MHz
SNR
48
DNL
±0.5
LSB
INL
±1.0
LSB
dB
External capacitance
Analog input coupling capacitance
Analog video pin
0.1
μF
Top level reference fixed capacitance
VRTx pin
0.01
μF
Bottom level reference capacitance
VRBx pin
0.01
μF
Analog input frequency
Analog input amplitude
ADC stabilization time (time required to restore from
standby mode)
PLL lock time
FAIN
10
1.0
MHz
V
500
ms
3
ms
No.A1647-3/37
LC74950BG
Package Dimensions: FBGA96
unit: mm (typ)
3387
TOP VIEW
BOTTOM VIEW
SIDE VIEW
6.0
0.75
0.5
6.0
0.75
1 2 3 4 5 6 7 8 9 10
0.5
K J H GF E D C B A
1.05 MAX
0.1
SIDE VIEW
0.29
SANYO : ISB96(6.0X6.0)
Pin Assignment
LC74950BG
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
Top view
No.A1647-4/37
LC74950BG
Block Diagram
LC74950BG
G/Y
G/Y
SW
Clamp
ADC
B / Cb
B / Cb
SW
Clamp
R / Cr
R / Cr
SW
Clamp
9
8
Clamp
Gain
ADC
Clamp
Gain
B / Cb
ADC
Clamp
Gain
R / Cr
SW
SW
G/Y
CLK
SW
HS / VS
PLL
HS / VS
DE
SDA
SCL
2
IC
CLK
Power Down
RESET
Pin Functions
In/output format
Connecting
Pin No.
Pin symbol
A1
ADC2AVSS33
P
A2
CBOUT0
I/O
A3
CBOUT2
I/O
A4
CBOUT4
I/O
A5
CBOUT6
I/O
I
3.3V CMOS
Digital
Video signal output Cb or B
A6
PDWN
I
B
3.3V CMOS
Digital
Power DOWN ”L” Power DOWN
A7
AVSS33_PLL
P
GND
Analog
A8
CHRGPMP
O
I/O
Remarks
destination
Format
GND
Analog
It must be treated in the same way as an NC pin.
I
3.3V CMOS
Digital
Video signal output Cb or B (LSB)
I
3.3V CMOS
Digital
Video signal output Cb or B
I
3.3V CMOS
Digital
Video signal output Cb or B
A
Analog
Filter input
PLL power supply
A9
AVDD33_PLL
P
3.3V
Analog
A10
DVDD15
P
1.5V
Digital
B1
VRT2
I
B2
ADC2AVSS33
P
GND
Analog
B3
CBOUT1
I/O
I
3.3V CMOS
Digital
Video signal output Cb or B
B4
CBOUT3
I/O
I
3.3V CMOS
Digital
Video signal output Cb or B
A
Analog
Top level reference voltage connection pin for ADC2
B5
CBOUT5
I/O
I
3.3V CMOS
Digital
Video signal output Cb or B
B6
CBOUT7
I/O
I
3.3V CMOS
Digital
Video signal output Cb or G (MSB)
B7
DVSS
P
GND
Digital
B8
AVSS33_PLL
P
GND
Analog
B9
DVDD15
P
1.5V
Digital
It must be treated in the same way as an NC pin.
B10
HSIN
I
B
3.3V CMOS
Digital
Horizontal synchronizing signal
C1
CRIN1
I
A
to 1.0Vp-p
Analog
Analog CR or R input (ADC2)
C2
VRB2
I
A
Analog
Bottom level reference voltage connection pin for ADC2
C3
ADC2AVDD33A
P
3.3V
Analog
C4
DVSS
P
GND
Digital
C5
DVSS
P
GND
Digital
C6
DVSS
P
GND
Digital
C7
DVDD15
P
1.5V
Digital
C8
DVDD15
P
1.5V
Digital
C9
VSIN
I
B
3.3V CMOS
Digital
Vertical synchronizing signal
C10
RESET
I
B
3.3V CMOS
Digital
System reset “L” reset
Continued on next page.
No.A1647-5/37
LC74950BG
Continued from preceding page.
Pin No.
Pin symbol
D1
VRT1
In/output format
I/O
Format
I
A
A
Connecting
Remarks
destination
Top level reference voltage connection pin for ADC1
D2
CRIN0
I
to 1.0Vp-p
Analog
D3
ADC1AVSS33
P
GND
Analog
D4
DVSS
P
GND
Digital
D5
DVSS
P
GND
Digital
D6
DVSS
P
GND
Digital
D7
DVDD15
P
1.5V
Digital
D8
DVDD15
P
1.5V
Digital
Analog CR or R input (ADC2)
D9
CLKOUT2
O
F
3.3V CMOS
Digital
CLKOUT1×2 output or PLL output
D10
CLKOUT1
O
F
3.3V CMOS
Digital
Datasynchronization clock output
E1
CBIN1
I
A
to 1.0Vp-p
Analog
Analog CB or B input (ADC1)
A
E2
VRB1
I
E3
ADC1AVDD33A
P
3.3V
Analog
Bottom level reference voltage connection pin for ADC1
E4
DVSS
P
GND
Digital
E7
DVDD15
P
1.5V
Digital
E8
I2CSEL
I
C
E9
SCL
I
D
E10
COAST
I
B
I2C slave addresses L=0×98, H=0×9A
3.3V CMOS
Digital
3.3V CMOS
Digital
Connected to GND
Analog
Top level reference voltage connection pin for ADC0
to 1.0Vp-p
Analog
Analog CB or B input (ADC1)
Analog
F1
VRT0
I
A
F2
CBIN0
I
A
F3
ADC0AVSS33
P
GND
F4
DVSS
P
GND
Digital
F7
DVDD15
P
1.5V
Digital
F8
TEST
I
H
3.3V CMOS
Digital
F9
SDA
I/O
G
F10
CLKIN
I
D
3.3V CMOS
Digital
G1
YGIN1
I
A
to 1.0Vp-p
Analog
Analog Y or G input (ADC0)
A
Analog
Bottom level reference voltage connection pin for ADC0
3.3V
Analog
Test pin (normally fixed low)
Digital
System clock (Must be connected to GND when not to be
used)
G2
VRB0
I
G3
ADC0AVDD33
P
G4
SCANEN
I
3.3V CMOS
Digital
G5
DVDD33
P
3.3V
Digital
G6
DVDD33
P
3.3V
Digital
G7
DVDD33
P
3.3V
Digital
G8
DVDD33
P
3.3V
Digital
G9
HSOUT
I/O
I
3.3V CMOS
Digital
Horizontal synchronizing signal
G10
VSOUT
I/O
I
3.3V CMOS
Digital
Vertical synchronizing signal
H1
ATB
O
A
H2
YGIN0
I
A
to 1.0Vp-p
Analog
Analog Y or G input (ADC0)
H3
AVDD15_OSC
P
1.5V
Analog
Power supply for the RC oscillator
H4
SCANMOD
I
H
3.3V CMOS
Digital
Test pin (normally, Lo)
H5
DVDD33
P
3.3V
Digital
H6
DVDD33
P
3.3V
Digital
H7
DVDD33
P
3.3V
Digital
H8
DVDD33
P
3.3V
Digital
H9
CROUT7
I/O
I
3.3V CMOS
Digital
Video signal output Cr or R (MSB)
H10
DEOUT
I/O
I
3.3V CMOS
Digital
Data enable. It must be held open when not to be used.
H
Test pin (normally, Lo)
Analog output for testing the ADC. It must be held open
when not to be used.
Continued on next page.
No.A1647-6/37
LC74950BG
Continued from preceding page.
Pin No.
Pin symbol
In/output format
I/O
Format
A
J1
SVO
O
J2
AVSS_OSC
P
J3
YGOUT1
I/O
J4
YGOUT7
I/O
J5
YGOUT4
J6
J7
J8
Connecting
Remarks
destination
to 1.0Vp-p
Analog
GND
Analog
Test pin. It must be held open when not to be used.
I
3.3V CMOS
Digital
I
3.3V CMOS
Digital
Video signal output Y or G (MSB)
I/O
I
3.3V CMOS
Digital
Video signal output Y or G
CROUT0
I/O
I
3.3V CMOS
CROUT3
I/O
I
3.3V CMOS
Digital
Video signal output Cr or R
CROUT5
I/O
I
3.3V CMOS
Digital
Video signal output Cr or R
3.3V
Digital
I
3.3V CMOS
Digital
Video signal output Cr or R
GND
Analog
It must be treated in the same way as an NC pin.
Video signal output Y or G
Video signal output Cr or R (LSB)
J9
DVDD33
P
J10
CROUT6
I/O
K1
AVSS_OSC
P
K2
YGOUT0
I/O
I
3.3V CMOS
Digital
Video signal output Y or G (LSB)
K3
YGOUT2
I/O
I
3.3V CMOS
Digital
Video signal output Y or G
K4
YGOUT3
I/O
I
3.3V CMOS
Digital
Video signal output Y or G
K5
YGOUT5
I/O
I
3.3V CMOS
Digital
Video signal output Y or G
K6
YGOUT6
I/O
I
3.3V CMOS
Digital
Video signal output Y or G
K7
CROUT1
I/O
I
3.3V CMOS
K8
CROUT2
I/O
I
3.3V CMOS
K9
CROUT4
I/O
I
3.3V CMOS
Digital
Video signal output Cr or R
K10
DVDD33
P
3.3V
Digital
It must be treated in the same way as an NC pin.
Video signal output Cr or R
Digital
Video signal output Cr or R
No.A1647-7/37
LC74950BG
Pin Type
In/Output form
A
Function
Analog input/output
Equivalent circuit
Application Terminal
CHRGPMP,
CRIN0, CRIN1, VRT2, VRB2,
CBIN0, CBIN1, VRT1, VRB1,
YGIN0, YGIN1, VRT0, VRB0,
SVO, ATB
B
5V withstand
HSIN, PDWN, VSIN, COAST, RESET
Schmitt trigger
CMOS input *
C
5V withstand
I2CSEL
CMOS input with built-in
pull-down resistor *
D
5V withstand
CLKIN, SCL
CMOS input *
F
12mA switching
CKOUT1, CKOUT2
3-STATE drive
CMOS output
G
8mA 3-STATE drive
SDA
CMOS input/output *
(5V withstand)
H
CMOS input with built-in
TEST, SCANEN, SCANMOD
pull-down resistor
I
8mA 3-STATE drive
HSOUT, VSOUT, DEOUT,
CMOS input/output
CROUT0, CROUT1, CROUT2, CROUT3,
CROUT4, CROUT5, CROUT6, CROUT7,
CBOUT4, CBOUT5, CBOUT6, CBOUT7,
CBOUT0, CBOUT1, CBOUT2, CBOUT3,
YGOUT0, YGOUT1, YGOUT2, YGOUT3,
YGOUT4, YGOUT5, YGOUT6, YGOUT7
*: 5V Tolerant
No.A1647-8/37
LC74950BG
Pin Connection
1) ADC and its peripherals
VRTx
VRBx
0.1μF
10μF
0.1μF
0.1μF
VRTx: VRT0, VRT1, VRT2
VRBx: VRB0, VRB1, VRB2
10μF
0.1μF
xINx
YGIN0, YGIN1
CRIN0, CRIN1
CBIN0, CBIN1
Terminal
resistor
2) PLL and its pereipherals
3) Output pin (recommended)
CHRGPMP
CBOUT0-3
3.3kΩ
5pF
0.068μF
0.0039μF
4) Power supplies
The analog A** and digital D** power supplies must be supplied separately without fail. In addition, the power
supply for the PLL circuit must also be provided separately as it will affect the jitter characteristics of the PLL circuit.
For ADC power supply, it is desirable to provide separate power for eachof the ADC channel.
AVDD33_PLL : Must be separated by L components, etc.
ADC2AVDD33A : Separating by L components, etc. recommended
ADC1AVDD33A : Separating by L components, etc. recommended
ADC0AVDD33A : Separating by L components, etc. recommended
5) Unused pin treatment
YGIN0, 1/CBIN0, 1/CRIN0, 1: Open
PDWN: Pull up
CHRGPMP: Open (when PLL is not in use)
***OUT* (e.g., YGOUT0): Open
HSIN/VSIN: Must always be configured for input.
RESET: Must always be configured for input.
COAST: Must be connected to DVSS.
TEST, SCANEN, SCANMOD: DVSS
CLKIN: DVSS
HSOUT, VSOUT, DEOUT: Open
SVO, ATB: Open
* The specified voltage of power must be applied to each of the power supply pin even if it is not to be used
(PLL is not to be used, for example).
No.A1647-9/37
LC74950BG
I/O Data Timing
(1) Input data timing
tCK
tHI
VDD33/2
CLKIN
tSU
tHD
tLO
VDD33/2
Input data
Pin name
CLKIN
Parameter
Symbol
Clock cycle
min
tCK
typ
unit
ns
Duty
50
Input data setup time
(DVDD33=3.0 to 3.6V)
Input data setup time
HSIN, VSIN
max
25
(DVDD33=2.4 to 3.6V)
Input data hold time
(DVDD33=3.0 to 3.6V)
Input data hold time
(DVDD33=2.4 to 3.6V)
%
tSU
3.0
ns
tSU
3.0
ns
tHD
3.0
ns
tHD
3.0
ns
*: The recommended duty cycle of input clock is 50%
(2) Output data timing
tHI
tCK
VDD33/2
CLKOUT1
tAC
tHD
tLO
VDD33/2
Output data
Pin name
CLKOUT1
Parameter
Clock cycle
Symbol
tCK
min
typ
Duty
Output data delay time
(3.0 to 3.6V)
Output data delay time
YGOUT*, CBOUT*, CROUT*,
HSOUT ,VSOUT, DEOUT
(2.4 to 3.6V)
Output data hold time
(3.0 to 3.6V)
Output data hold time
(2.4 to 3.6V)
max
25
unit
ns
50
%
tAC
0
2.0
ns
tAC
0
3.0
ns
tHD
3.0
ns
tHD
3.0
ns
* When CLKOUT1 is set to the forward rotation output.
No.A1647-10/37
LC74950BG
Timing Chart
N+1
N
N+2
Analog input
CLKIN
Output data
N-50
N-49
N
N+1
Note: For the initial setting of the registers
Details of the functions
1. Selection of input pins
Registers related to the selection of input pins
Name
AINSEL
Functions
Sub address
bit width
0x22
1
Video input select control
Analog video input select
0: YGIN0/CBIN0/CRIN0
1: YGIN1/CBIN1/CRIN1
• Video input selector function
The video input signal used for actual processing can be selected out of the two systems of video input.
AINSEL=0: YGIN0/CBIN0/CRIN0
AINSEL=1: YGIN1/CBIN1/CRIN1
2. Input format
Registers related to the selection of the input format
Name
SELYCRGB
Functions
Sub address
bit width
0x14
1
0x1B
1
This register switches between the YCbCr input and RGB input.
0: YCbCr, 1: RGB
SYNCON
For YCbCr input, this register, by cutting off the digitally clamped sync component of the
Y video signal, sets the applicable gain adjustment function to ON or OFF.
This must be set to 0 for the RGB input (SELYCRGB=1).
0: ON, 1: OFF
All the inputs listed below can be connected to the analog ports. It is also possible to switch between the inputs of two
systems and use the one selected.
YCbCr/YPbPr input (480I/576I, 480P/576P): Component input
RGB: RGB input
3. Operating modes
Register related to the selection of operating mode
Name
CLKSEL
Functions
Operating mode selection
Sub address
bit width
0x00
3
000: External clock mode (PLL not used)
001: External clock mode (PLL used)
010: H lock PLL mode
011: Panel PLL mode <1>
100: Panel PLL mode <2>
No.A1647-11/37
LC74950BG
1) External clock mode (PLL not used: CLKOUT1=CLKIN/2, CLKOUT2=CLKIN)
Example: Component input (NTSC) (down sample)
LC74950BG
8
G/Y
B/Cb
G OUT
ADC
Analog Selfclamping
Digital
Clamp
8
Gain
Offset
B OUT
8
R/Cr
R OUT
CKGEN
1/2
CLK IN (27MHz)
HS IN
S
E
L
1/2
13.5MHz
S
E
L
S
E
L
PLL
27MHz
CLKOUT1
CLKOUT2
VS OUT
VS IN
Timing
Generator
HS OUT
DE OUT
PDOWN
RESET
2
IC
2) External clock mode (PLL used: CLKOUT1=CLKIN, CLKOUT2=CLKIN*2)
Example: Component input (NTSC) (2× clock generation)
LC74950BG
8
G/Y
B/Cb
ADC
Analog Selfclamping
Digital
Clamp
Gain
Offset
G OUT
8
B OUT
8
R/Cr
R OUT
CKGEN
1/2
CLK IN (13.5MHz)
HS IN
S
E
L
1/2
PLL
13.5MHz
S
E
L
S
E
L
27MHz
CLKOUT1
CLKOUT2
VS OUT
VS IN
PDOWN
RESET
Timing
Generator
HS OUT
DE OUT
2
IC
No.A1647-12/37
LC74950BG
3) H-lock PLL mode (PLL used: CLKOUT1=HS/Divide, CLKOUT2=CLKOUT1*2)
Example: Component input (NTSC) (2× clock generation)
LC74950BG
8
G/Y
B/Cb
G OUT
ADC
Analog Selfclamping
Digital
Clamp
Gain
Offset
8
B OUT
8
R/Cr
R OUT
CKGEN
1/2
CLK IN
HS IN
VS IN
S
E
L
1/2
13.5MHz
S
E
L
S
E
L
PLL
27MHz
CLKOUT1
CLKOUT2
VS OUT
Timing
Generator
HS OUT
DE OUT
PDOWN
RESET
2
IC
4) ADC/PLL independent mode <1>
(External clock input, PLL configured independently: CLKOUT1=CLKIN/2, CLKOUT2=CLKIN/In-Divide*OutDivide)
Example: Component (ADC down sample), PLL: Generation of separate system clock
LC74950BG
8
G/Y
B/Cb
ADC
Analog Selfclamping
Digital
Clamp
Gain
Offset
G OUT
8
B OUT
8
R/Cr
R OUT
CKGEN
1/2
CLK IN (27MHz)
HS IN
S
E
L
1/2
PLL
13.5MHz
S
E
L
S
E
L
33MHz
CLKOUT1
CLKOUT2
VS OUT
VS IN
PDOWN
RESET
Timing
Generator
HS OUT
DE OUT
2
IC
No.A1647-13/37
LC74950BG
5) ADC/PLL independent mode <2>
(External clock input, PLL configured separately: CLKOUT1=CLKIN, CLKOUT2=CLKIN/In-Divide*Out-Divide)
Example: Component (ADC down sample), PLL: Generation of separate system clock
LC74950ADC
8
G/Y
ADC
Analog Selfclamping
B/Cb
Digital
Clamp
Gain
Offset
G OUT
8
B OUT
8
R/Cr
R OUT
CKGEN
1/2
S
E
L
CLK IN (13.5MHz)
HS IN
13.5MHz
S
E
L
1/2
S
E
L
PLL
33MHz
CLKOUT2
VS OUT
Timing
Generator
VS IN
CLKOUT1
HS OUT
DE OUT
PDOWN
RESET
2
IC
4. Clock system
1) Clock system diagram
CLKSEL
00h, bit2-0
CLKIN
POWERIN
1/2
Divider
CLKSEL
00h, bit2-0
CLKININV
00h, bit4
CLKINDIV
/
40h, bit5-0
6
1/1 to 1/64
Divider
HSIN
FIN *2
3
/
CLKOUT1INV
00h, bit6
CLKADC
*2
ADC
C
CLKADCINV
00h, bit3
FOUT *1
PLL
FOUTX2 *1
HSINV
03h, bit3
CLKOUT1
CLKOUT *1
CLKOUTINV
01h, bit7
logic
CLKOUT2 *2
3
CLKSEL
00h, bit2-0 /
CLKOUT2INV
00h, bit7
*1 Explanation of signals
FOUT:
A clock generated in the PLL circuit and synchronized with the reference signal (FIN). The frequency of
FIN and PLL divider value (HPLDIV, 28h-29h, bits 15-0) determine the frequency of FOUT.
FOUTX2: A clock generated in the PLL circuit and synchronized with the reference signal (FIN). The frequency of
FOUTX2 is two times of the frequency of FOUT.
CLKOUT: A clock generated in the ADC. To output the clock it is necessary to adjust the phase of the sampling clock
(CLKADC) in order that the rising edge of the clock does not occur near the change point of the ADC
sampled data.
No.A1647-14/37
LC74950BG
Registers related to the control of clock
Name
Functions
Sub address
bit width
CLKININV
This register controls the inversion of CLKIN when the CLKIN input is used as a
0x00
2
0x02
1
0x40
6
0x00
3
0x00
1
0x01
1
0x00
1
0x00
1
reference clock to PLL.
0: Uses CLKIN in its original form
1: Uses CLKIN in its inverted form
HSINV
This register controls the inversion of HSIN input. The HSIN must be used in its
inverted form when the polarity of HSIN input is negative.
0: Original form (when HSIN is positive)
1: Inverted form (when HSIN is negative)
CLKINDIV
This register sets the frequency division ratio of CLKIN to an arbitrary value
(1/1 to1/64) when the CLKIN is used as a reference clock to PLL.
1/(CLKINDIV[5:0]+1) division
CLKSEL
This register selects the operating mode.
000: (External clock mode (PLL not used)
001: (External clock mode (PLL used)
010: H-lock PLL mode
011: Panel PLL mode <1>
100: Panel PLL mode <2>
CLKADCINV
This register controls the inversion of the ADC sampling clock (CLKADC).
0: Uses CLKADC in its original form
1: Uses CLKADC in its inverted form
CLKOUTINV
This register controls the inversion of the ADC-generated clock. (CLKOUT).
0: Uses CLKOUT in its original form
1: Uses CLKOUT in its inverted form
CLKOUT1INV
This register controls the inversion of CLKOUT (video clock output).
0: Original form
1: Inverted form
CLKOUT2INV
This register controls the inversion of CLKOUT2 (panel clock output).
0: Original form
1: Inverted form
*2 Clock control register (CLKSEL, 00h, bits 2-0) specifications
CLKSEL
CLKADC*3
FIN
CLKOUT2
(bit2-0)
(ADC sampling clock)
(PLL reference)
(Clock output)
000
CLKIN/2 (13.5MHz)
L fixed (PLL not used)
CLKIN(27MHz)
001
FOUT (PLL output)
CLKIN *4
010
FOUT (PLL output)
HSIN *5
011
CLKIN/2
CLKIN *4
FOUT (PLL output)
Panel PLL mode <1>
100
CLKIN
CLKIN *4
FOUT (PLL output)
Panel PLL mode <2>
FOUTX2
(PLL output X2)
Remarks
External clock mode (PLL not used)
External clock mode (PLL used)
FOUTX2
(PLL output X2)
H-lock PLL mode
*3: Register CLKADCINV (00h, bit 3) allows for clock inversion.
*4: Register CLKINDIV (40h, bits 5-0) allows for division of clock frequency (1/1 to 1/64).
*5: Register HSINV (03h, bit 3) allows for HSIN inversion.
No.A1647-15/37
LC74950BG
2) PLL circuit
CLKIN
POWERIN
CLKSEL
00h, bit2-0
CLKININV
00h, bit4
CLKINDIV
40h, bit5-0
/
6
1/1 to 1/64
Divider
FIN
PLL
HSIN
VCO
HSINV
03h, bit3
Feedback
Divider
(N=2 to 4097)
FOUTX2 frequency=(FIN frequency)×M×2×N
FOUT frequency=(FIN frequency) ×M×N
Output
Divider
(M=1 to 16)
FOUT×2
1/2
FOUT
This circuit can be used as the H lock or frequency-multiplied clock. It is also possible to use the PLL circuit and
analog-digital converter (ADC) independently.
H lock PLL circuit: This makes it possible to generate a clock that is synchronized with the external H sync signal.
Frequency-multiplier PLL circuit: This makes it possible to generate clocks that are synchronized with an external clock.
Registers related to the setting of PLL circuit
Name
Functions
Sub address
bit width
CLKININV
This register controls the inversion of CLKIN when the CLKIN input is used as a
0x00
2
0x02
1
0x40
6
0x00
3
This register sets the output divider (M-1, NTSC, 480i=3).
0x28
4
This register sets the feedback divider (N-2, NTSC, 480i=856).
0x28
12
H-lock PLL output frequency (1x)=Hsync frequency×N
0x29
reference clock to PLL.
0: Uses CLKIN in its original form
1: Uses CLKIN in its inverted form
HSINV
This register controls the inversion of HSIN input. The HSIN must be used in its
inverted form when the polarity of HSIN input is negative.
0: Original form (when HSIN is positive)
1: Inverted form (when HSIN is negative)
CLKINDIV
This register sets the frequency division ratio of CLKIN to an arbitrary value
(1/1 to 1/64) when the CLKIN is used as a reference clock to PLL.
1/(CLKINDIV[5:0] 1) division
CLKSEL
This register selects the PLL reference input.
000: L fixed (PLL not used)
001: External clock input (CLKIN)
010: External Hsync input (HSIN)
011: External clock input (CLKIN)
100: External clock input (CLKIN)
HPLDIV15-12
HPLDIV11-0
H-lock PLL output frequency (2x)=Hsync frequency×N×2
* After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get
stabilized.
Continued on next page.
No.A1647-16/37
LC74950BG
Continued from preceding page.
Name
Functions
PLLGAIN
This register switches the setting of Fmin, Fmax, and Gain of the H-lock PLL VCO.
Sub address
bit width
0x27
3
0x27
1
0x27
1
0x2A
4
000: Fmin=60MHz, Fmax=240MHz, Gain=120MHz/V←Standard setting
001: Fmin=Standard, Fmax=Standard-20%, Gain=Standard-22.5%
010: Fmin=Standard-20%, Fmax=Standard, Gain=Standard+2.5%
011: Fmin=Standard-20%, Fmax=Standard-20%, Gain=Standard-20.0%
100: Fmin=Standard+20%, Fmax=Standard+10%, Gain=Standard+8.75%
101: Fmin=Standard+20%, Fmax=Standard-10%, Gain=Standard-13.75%
110: Fmin=Standard, Fmax=Standard+10%, Gain=Standard+11.25%
111: Fmin=Standard, Fmax=Standard-10%, Gain=Standard-11.25%
* After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get
stabilized.
PLLCTL2
H-lock PLL power down mode
0: Normal operation
1: H-lock PLL power OFF
PLLCTL1
H-lock PLL Normal Mode FOUT Disable
0: Normal operation
1: H-lock PLL output= L fixed
CPIS_COAST
These registers set the PLL charge pump constant current
CPIS_ORG
(make sure that CPIS_COAST=CPIS_ORG)
0000: 40μA
0001: 60μA
0010: 120μA
0011: 180μA
0100: 200μA
0110: 280μA
0101: 300μA
1000: 360μA
0111: 420μA
1010: 440μA ←Standard setting
1100: 520μA
1001: 540μA
1110: 600μA
1011: 660μA
1101: 780μA
1111: 900μA
* After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get
stabilized.
PLL setting example (when using as H-lock PLL)
Ref
CLKSEL
PLLDIV
PLLDIV
FVCO*
FOUTX2
FOUT
CPIS
PLLGAIN
[kHz]
[2:0]
15-12
11-0
[MHz]
[MHz]
[MHz]
[3:0]
[2:0]
NTSC
15.734
2h
3h
6B2h
216
(54)
27
Ch
0h
NTSC
15.734
2h
7h
358h
216
27
13.5
Ch
0h
PAL
15.630
2h
3h
6BEh
216
(54)
27
Ch
0h
PAL
15.630
2h
7h
35Eh
216
27
13.5
Ch
0h
PAL-N
15.630
2h
7h
35Eh
216
27
13.5
Ch
0h
PAL-M
15.734
2h
7h
358h
216
27
13.5
Ch
0h
QVGA
15.70
2h
Fh
1A6h
213
13.3
6.68
Ch
0h
VGA
31.5
2h
3h
31Eh
201
(50.4)
25.2
Ch
0h
WVGA
31.0
2h
3h
41Eh
262
(65.4)
32.7
Dh
0h
*20MHz < FVCO < 340MHz
No.A1647-17/37
LC74950BG
5. Timing control
1) DEOUT (enable output) setting
Registers related to the setting of enable
Name
HBLKS
HBLKE
VBLKS
VBLKE
Sub address
bit width
This register specifies the 1H start position of DEOUT in dot units.
Functions
0x04
12
Set value smaller than HBLKE.
0x05
This register specifies the 1H end position of DEOUT in dot units.
0x04
Set the value that is larger than HBLKS and does not overlap the next Hsync.
0x06
This register specifies the 1V start position of DEOUT in line units.
0x07
Set the value smaller than VBLKE.
0x08
This register specifies the 1V end position of DEOUT in line units.
0x07
Set the value that is larger than VBLKS and does not overlap the next Vsync.
0x09
12
11
11
• Setting of horizontal enable
CLKOUT1
HSOUT
CROUT7-0
R0
R1
R2
...
R1439
YGOUT7-0
G0
G1
G2
...
G1439
CBOUT7-0
B0
B1
B2
...
B1439
DEOUT
HBLKS [11:0]
HBLKE [11:0] *1
*1: DEOUT is forcibly disabled at the leading edge of the next HSOUT even if HBLKE[11:0] is set with a value larger
than the total pixel count of 1H.
• Setting of vertical enable
HSOUT
VSOUT
CROUT7-0
Active Line
YGOUT7-0
Active Line
CBOUT7-0
Active Line
DEOUT
VBLKS [10:0]
VBLKE [10:0] *2
*2: DEOUT is forced disabled at the leading edge of the next VSOUT even if VBLKE[10:0] is set with a value larger
than the total line count of 1V.
No.A1647-18/37
LC74950BG
2) SYNC width adjustment (H-lock PLL mode only) of horizontal sync output (HSOUT)
Registers related to SYNC width adjustment of HSOUT
Name
Functions
HSPLLSEL
This register selects the horizontal sync signal (SHOUT) in the H-lock PLL mode.
Sub address
bit width
0x01
1
0x27
1
0x2B
12
0: HSIN
1: This is the signal that is fed back to the phase detector after dividing the VCO output
of the PLL.
*: SYNC width adjustment for HSOUT must be turned on when HSPLLSEL is set to 1.
CORREN
This register turns on and off the SYNC width adjustment for HSOUT.
0: OFF, 1: ON
CORRHSS
SYNC width adjustment register for HSOUT (to be described below)
0x2C
CORRHSE
SYNC width adjustment register for HSOUT (to be described below)
0x2B
12
0x2D
When "1" is set for HSPLLSEL in the H lock PLL mode, the horizontal sync output signal is not HSIN but the signal
that is fed back to the phase detector after dividing the VCO output of the PLL. The duty ratio of this signal is 50%,
which means when it is to be used as the horizontal sync signal, the sync width must be determined. Furthermore, if "0"
is set for HSPLLSEL, the horizontal sync input (HSIN) signal can be output in its original form even in the H lock PLL
mode.
Feedback signal to the
phase detector
HSOUT
(HSOUTINV=0)
(CORRHSS [11:0] + 3) clock *1
CORRHSE [11:0] *2
*1: Clock is expressed in units of CLKOUT1.
*2: A value equivalent to about three-fourths of one HSOUT period (640 or so with the NTSC system) must be set as
the CORRHSE[11:0] value.
No.A1647-19/37
LC74950BG
3) Offset adjustment of video output
Registers related to video output offset adjustment
Name
ASYG
Functions
Sub address
bit width
This register adjusts the offset for the Y/G video signal. It is used when the timing between
0x01
3
0x02
3
0x02
3
0x03
3
0x03
3
the video signal and sync signals is off.
The Y/G video signal can be shifted by an amount equivalent to (ASYG + 1) locks.
ASCRR
This register adjusts the offset for the CR/R video signal. It is used when the timing
between the video signal and sync signals is off.
The CR/R video signal can be shifted by an amount equivalent to (ASCRR + 1) clocks.
ASCBB
This register adjusts the offset for the CB/B video signal. It is used when the timing
between the video signal and sync signals is off.
The CB/B video signal can be shifted by an amount equivalent to (ASVBBYG + 1) clocks.
ASVS
This register adjusts the offset for the VSOUT video signal. It is used when the timing
between the video signal and sync signals is off.
The vertical sync signal can be shifted by an amount equivalent to (ASVS + 1) clocks.
ASHS
This register adjusts the offset for the HSOUT. It is used when the timing between the
video signal and sync signals is off.
The horizontal sync signal can be shifted by an amount equivalent to (ASHS + 1) clocks.
• Offset adjustment method
If the following fluctuations are present between the video outputs when ASYG[2:0] = 000b, ASCRR[2:0] = 000b and
ASCBB[2:0] = 000b:
CLKOUT1
CROUT7-0
R0
R1
YGOUT7-0
CBOUT7-0
B0
B1
B2
R2
...
G0
G1
R1439
G2
...
...
G1439
B1439
Then, by setting ASYG[2:0] = 010b, ASCRR[2:0] = 000b and ASCBB[2:0] = 011b, the video outputs can be aligned
as shown below. The maximum shift width of the video signals is 8 clocks. If the ASVS[2:0] and ASHS[2:0] registers
are used in line with the video signal shift, the sync signals (VSOUT and HSOUT) can also be shifted in line with the
video signals. (DEOUT is also shifted following HSOUT.)
CLKOUT1
CROUT7-0
R0
R1
R2
...
R1439
YGOUT7-0
G0
G1
G2
...
G1439
CBOUT7-0
B0
B1
B2
...
B1439
No.A1647-20/37
LC74950BG
6. ADC
1) Analog clamp
Registers related to analog clamp control
Name
STBB
Functions
This register controls the band gap VREF circuit.
Sub address
bit width
0x21
1
1
0: Band gap VREF circuit enters standby mode.
1: Band gap VREF circuit enters normal operating mode.
* This must be set in line with the operation mode of ADC.
STBB_Y
These registers control the AFE standby mode (Y: STBB_Y, B: STBB_B, R: STBB_R)
0x21
STBB_B
0: AFE standby mode
0x23
STBB_R
1: AFE normal operating mode
0x25
* This must be set in line with the operation mode of ADC.
SELFCLPSTBB_Y
These registers control self-clamp.
0x21
SELFCLPSTBB_B
(Y: SELFCLPSTBB_Y, B: SELFCLPSTBB_B, R: SELFCLPSTBB_R)
0x23
SELFCLPSTBB_R
0: Self-clamp function is OFF
0x25
1
1: Self-clamp function is ON
*1: This is disabled when STBB_x=0 (self-clamp function is OFF).
*2: The clamp level is set to MAINCLPLVCNT_x[1:0].
MAINCLPLVCNT_Y
These registers control the clamp level.
0x22
MAINCLPLVCNT_B
(Y: MAINCLPLVCNT_Y, B: MAINCLPLVCNT_B, R: MAINCLPLVCNT_R)
0x24
MAINCLPLVCNT_R
00: 0.35V (sink tip clamp)
0x26
2
01: 0.50V (pedestal clamp)
10: 0.85V (center clamp)
11: Inhibited.
*: This is enabled when the self-clamp is ON.
(STBB_x=1, SELFCLPSTBB_x=1)
HPFCLPON_Y
These registers control HPF center clamp.
0x22
HPFCLPON_B
(Y: HPFCLPON_Y, B: HPFCLPON_B, R: HPFCLPON_R)
0x24
HPFCLPON_R
0: HPF center clamp is OFF
0x26
1
1: HPF center clamp is ON
*: This must be set OFF unless the center clamp is selected.
(MAINCLPLVCNT_x[1:0]=10).
CLPLPFON_Y
These registers control clamp LPF.
0x22
CLPLPFON_B
(Y: CLPLPFON_Y, B: CLPLPFON_B, R: CLPLPFON_R)
0x24
CLPLPFON_R
0: LPF function is OFF
0x26
1
1: LPF function is ON
*: This is appropriate for rejecting high-frequency noises in a weak electric field
(cut-off frequency is 1MHz).
This must be set OFF when the video signals equivalent to HD specifications is input.
No.A1647-21/37
LC74950BG
• Analog clamp function
This function performs sync tip clamping and pedestal clamping to the video input selected by AINSEL. When the
analog clamp function is not used, it can be placed in the standby status using the SELFCLPSTBB_x setting.
STBB_x
SELFCLPSTBB_x
State
Clamping Voltage
0
*
Analog clamp function OFF
-
1
0
Analog clamp function OFF
-
1
1
Analog clamp function ON
Subjected to the clamp level control
• Analog clamp level control
When the analog clamp function is ON, sync tip clamp, pedestal clamp and center clamp can be selected using the
settings below.
MAINCLPLVCNT[1:0]
Clamp Level
State/Use
00
0.35V
Sync tip clamp
01
0.50V
Pedestal clamp
10
0.85V
Center clamp
11
-
Inhibited
The clamp levels applied to the YCbCr and RGB inputs are given below.
AFE CH
YCbCr
RGB
Y
Sync chip clamp
Pedestal clamp
B
Center clamp
Pedestal clamp
R
Center clamp
Pedestal clamp
No.A1647-22/37
LC74950BG
• Sync tip clamp specifications
Analog input
Digital output
ADC output code
511
439
1.55V
1.35V
S/H gain setting
GAIN=L
1× gain
1.0Vp-p
0.85V
(ADC-input reference)
256
0.65V
73
0.35V
0.15V
1
1.4Vp-p range
The figures represent the set values set under ideal conditions.
Clamp settings
Self-clamp setting
SELFCLPSTBB
H: Self-clamp ON
Main clamp level setting
MAINCLPLVCNT [1:0]
00: Main clamp level set to 0.35V
HPF center clamp setting
HPFCLPON
L: HPF clamp OFF
S/H gain setting
GAIN
L: 1× gain
• Center clamp specifications
Analog input
Digital output
1.55V
1.375V
1.20V
Digital output
511
448
S/H gain setting
GAIN=H
1.5× gain
0.7Vp-p
0.85V
(ADC-input reference)
256
0.50V
0.325V
0.15V
64
1
1.4Vp-p range
*The figures represent the set values set under ideal conditions.
Clamp settings
Main clamp level setting
MAINCLPLVCNT [1:0]
10: Main clamp level set to 0.85V
Self-clamp setting
SELFCLPSTBB
L: Self-clamp OFF
HPF center clamp setting
HPFCLPON
H: HPF clamp ON
S/H gain setting
GAIN
H: 1.5× gain
No.A1647-23/37
LC74950BG
• Pedestal clamp specifications
Analog input
Digital output
Digital output
511
1.55V
448
1.375V
S/H gain setting
GAIN=H
1.5× gain
1.20V
0.7Vp-p
0.85V
(ADC-input reference)
256
0.50V
0.325V
64
0.15V
1
1.4Vp-p range
* The figures represent the set values set under ideal conditions.
Clamp settings
Self-clamp setting
SELFCLPSTBB
H: Self-clamp ON
Main clamp level setting
MAINCLPLVCNT [1:0]
01: Main clamp level set to 0.50V
HPF center clamp setting
HPFCLPON
L: HPF clamp OFF
S/H gain setting
GAIN
H: 1.5× gain
• Clamp LPF function
A primary LPF with a 1MHz cutoff frequency has been inserted in the stage before the self-clamp circuit as a measure
to deal with the high-frequency noise that is present in weak electrical fields. The clamp LPF function is for
minimizing shifts in the clamp levels of the self-clamp and sub-clamp when high-frequency noise components are
present in the video signals. The LPF can be set to ON or OFF using the CLPLPFON setting. It must be set to ON
when SD standard signals are input, and set to OFF when HD standard signals are input. The cutoff frequency of the
LPF is 1MHz. Care must therefore be taken when the LPF is set to ON since the clamp level will drop when HD
standard signals are input because it is not possible to track frequencies corresponding to the sync width.
Sink tip clamp
when LPF is off.
Input video signal (SD)
Sink tip clamp
when LPF is on.
High-frequency noise with
frequencies of 1MHz and above
0.35V
0V
Clamping is performed at the lower limit
level of the noise components. Due to
the effect of the noise, the clamp level
shifts.
Clamping is performed at the level at which
the noise components are removed. It is
clamped at its original position.
No.A1647-24/37
LC74950BG
2) ADC
Registers related to ADC control
Name
Functions
Sub address
bit width
4
STBL_Y
These registers control the ADC standby mode (Y: STBL_Y, B: STBL_B, R: STBL_R).
0x21
STBL_B
0000: ADC standby mode
0x23
STBL_R
1111: ADC normal operating mode
0x25
*1: Any other settings than above inhibited.
*2: This must be set in line with the operating mode of ADC.
ICNT_Y
These registers control the internal bias current of ADC (Y: ICNT_Y, B: ICNT_B,
0x39
ICNT_B
R: ICNT_R).
0x3A
ICNT_R
Bias current generating resistor values:
0x3B
3
000: 600Ω (recommended)
001: 540Ω
010: 480Ω
011: 420Ω
100: 360Ω
101: 300Ω
110: 240Ω
111: 180Ω
7. Digital Clamp
1) Digital clamp pulses
Registers related to digital clamp pulse control
Name
OSEL
Functions
This register sets the digital clamp pulse output to ON or OFF.
Sub address
bit width
0x2E
3
1
It is used to adjust the position of the digital clamp pulses.
000: Normal operation
101: The Y digital clamp pulse is output from the YGOUT7 pin and the C digital clamp
pulse is output from the CBOUT7 pin.
DCLPYON
These registers set the digital clamp pulse to ON and OFF
0x0A
DCLPCON
(Y: DCLPYON, C: DCLPCON).
0x0F
0: OFF, 1: ON
DCPYSET
These registers set the digital clamp pulse positions (Y: DCPYSET, C: DCPCSET).
0x0A
DCPCSET
They are set in 4-clock increments using the trailing edge of Hsync as a reference.
0x0F
DCLPYW
These set the digital clamp pulse width. It can be set in 1 clock increments.
0x0B
DCLPCW
0 specifies a pulse width of 0.
0x10
DCLPYV
These registers set the disable function of the digital clamp pulses during the vertical
0x0B
DCLPCV
blanking period to ON or OFF.
0x10
6
Setting range: -32 (00h) to +31 (3Fh), default value: +/-0 (20h)
6
(Y: DCLPYW, C: DCLPCW)
1
(Y: DCLPYV, C: DCLPCV)
0: OFF, 1: ON
DCPYVMS
These specify the start line at which the digital clamp pulses are enabled within 1V.
0x0C-0x0D
DCPCVMS
As a basic rule, the same values as the V-enable start line (VBLKS[10:0]) are set.
0x11-0x12
DCPYVME
These specify the end line at which the digital clamp pulses are enabled within 1V.
0x0C-0x0E
DCPCVME
As a basic rule, the same values as the V-enable end line (VBLKS[10:0]) are set.
0x11-0x13
11
11
Digital clamp pulse settings (how to output the clamp pulses)
OSEL[2:0] *1
YGOUT7
CBOUT7
101
Digital clamp pulse (Y)
Digital clamp pulse (C)
*1: The "000" setting must be used during normal operation.
No.A1647-25/37
LC74950BG
• Digital clamp pulse settings (how to establish settings in the horizontal direction)
CLKOUT1
HSOUT
DEOUT
YGOUT7<1>
→ DCPYSET [5:0]
>When 20h
DCPYSET [5:0]×4-1
YGOUT7<2>
→ When
DCPYSET [5:0]
When < 20h
DCLPYW [5:0]
DCLPYW [5:0]
DCPYSET [5:0]×4+1
YGOUT7<3>
→ DCPYSET [5:0]
When = 20h
1clock
DCLPYW [5:0]
*2: The digital clamp pulse positions must be set so that they come within the horizontal blanking period (DEOUT = L).
*3: The digital clamp pulse (C) setting method is the same as that described above. However, DCPCSET[5:0] (0Fh,
bit5-0) must be used for the pulse position setting, and DCLPCW[5:0] (10h, bit5-0) must be used for the pulse width
setting.
• Digital clamp pulse settings (how to establish settings in the vertical direction)
HSOUT
VSOUT
DEOUT
YGOUT7
DCPYVMS [10:0]
DCPYVME [10:0]
*4: By using the digital clamp pulse disable function (Y: DCLPYV = 1, C: DCLPCV = 1), the digital clamp pulse in the
vertical blanking period can be set to OFF. The same values as the vertical enable settings (VBLKS[10:0],
VBLKE[10:0]) must be used for the mask period settings (DCPYVMS[10:0], DCPYVME[10:0]).
*5: The digital clamp pulse (C) setting method is the same as that described above. However, DCPCVMS[10:0] and
DCPVME[10:0] must be used for the mask period settings.
No.A1647-26/37
LC74950BG
2) Digital clamp
Registers related to digital clamp control
Name
SELYCRGB
Functions
This register switches between the YCbCr input and RGB input.
Sub address
bit width
0x14
1
0x14
6
0x15
6
0x16
6
0x15
1
0x17
5
0x17
3
0: YCbCr, 1: RGB
STDLEVY
YG digital clamp levels (SELYCRGB=0: Y, SELYCRGB=1: G)
The 9-bit (0-511) YG video signals are clamped by the values determined assuming the pedestal
levels (Y: STDLEVY[5:0] + 118, G: STDLEVY[5:0]).
Setting range: Y (118-181), G (0-63)
STDLEVCB
CBB digital clamp levels (SELYCRGB=0: CB, SELYCRGB=1: B)
The 9-bit (0-511) CBB video signals are clamped by the value determined assuming the center level
(STDLEVCB[5:0] + 225) for CB and the pedestal level (STDLEVCB[5:0]) for B.
Setting range: CB (225-288), B (0-63)
STDLEVCR
CRR digital clamp levels (SELYCRGB=0: CR, SELYCRGB=1: R)
The 9-bit (0-511) CRR video signals are clamped by the value determined assuming the center level
(STDLEVCR[5:0] + 225) for CR and the pedestal level (STDLEVCR[5:0]) for R.
Setting range: CR (225-288), R (0-63)
DCLINE
This sets the digital clamp update unit.
0: 1V, 1: 1H (used for testing)
FRAMEDC
[When the digital clamp update unit is 1V (DCLINE=0)]
This register sets the number of update frames (FRAMEDC[4:0] + 1).
Setting range: 0-31 (1 to 32 frames)
TCDIGCLP
This register sets the digital clamp time constant.
000: 1/1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
110: 1/64
111: 1/128
• Digital clamp specifications
The 9-bit (0-511) video signals output from the ADC are clamped at the set digital clamp pulse position to the set
digital clamp level.
511
Input signal
Pedestal level setting value
Pedestal level
Sync level
Sink tip level
Digital clamp pulse
0
Digital clamp pulse
The digital clamp level setting values are given below.
Y=118+STDLEVY[5:0]
Cb/Cr=225+(STDLEVCB[5:0]/STDLEVCR[5:0])
R, G, B=STDLEVY[5:0]/STDLEVCB[5:0]/STDLEVCR[5:0]
No.A1647-27/37
LC74950BG
• Concerning the time constant setting
A difference between the pedestal level of the 9-bit (0-511) video signals and set digital clamp level is obtained
through digital clamp processing as shown in the figure below. The result of multiplying this difference by the 1/X
time constant is added to the input signals and output. In this way, the level is changed gradually to the set digital
clamp level. The time constant is set using TCDIGCLP[2:0].
Digital clamp level
setting value
Input
Pedestal level detection
-
1/X
Output
8. Gain
1) Gain adjustments
Registers related to gain adjustments
Name
SELYCRGB
Functions
This register switches between YCbCr input and RGB input.
Sub address
bit width
0x14
1
0x1B
1
0x19
1
0x1C
5
0x19
7
0x1A
7
0x1B
7
0: YCbCr, 1: RGB
SYNCON
This register turns ON and OFF the function to adjust the gain by cutting off the sync
component of the digitally clamped Y video signal for YCbCr input.
This must be set to 0 for the RGB input (SELYCRGB=1).
0: ON, 1: OFF
CNLINE
This register sets the nonlinear gain adjustment to ON or OFF.
0: OFF (linear gain adjustment)
1: ON (nonlinear gain adjustment)
COFFSET
This register adjusts the nonlinear gain region when the nonlinear gain adjustment is ON
(CNLINE=1).
GAINY
Linear gain adjustment (YG)
The multipliers for linear gain adjustment are given below.
Y (SELYCRGB=0): (32+GAINY[6:0])/64
G (SELYCRGB=1): (48+GAINY[6:0])/64
GAINCB
Linear gain adjustment (CBB)
The multiplier is set to (48+GAINCB[6:0])/64 for linear gain adjustment.
GAINCR
Linear gain adjustment (CRR)
The multiplier is set to (48+GAINCR[6:0])/64 for linear gain adjustment.
• Gain adjustment specifications
The digitally clamped 9-bit video signals are converted into 8-bit video signals as shown in the figure below. In this
case, the digital clamp level is shifted to the LSB of the 8 bits, and gain is adjusted in such a way that the components
(video signals) above the digital clamp level fit in the 8-bit range.
9 bits
8 bits
No.A1647-28/37
LC74950BG
• Non-linear gain adjustment
When CNLINE = 1, the output obtained in response to the input near the saturation region is made non-linear. When
the non-linear gain adjustment parameter (CONPARA), obtained from the formula below, is less than the multiplier
(RGB: (32 + GAIN_x[6:0])/64, YCbCr: (48 + 12A_GAIN_x[6:0])/64) that is used when the non-linear gain is
adjusted, the input is multiplied by the non-linear gain adjustment parameter, resulting in a non-linear output. The
non-linear start position and maximum non-linear output value can be adjusted using COFFSET[4:0].
CONPARA = (1023 − 9-bit video signals) × (64 + COFFSET[4:0])/64
The figure below shows the gain adjustment output when the input is Y and GAIN_Y[6:0] = 63.
GAIN_Y=63 (AMP=1.73)
1200
1000
800
OUTPUT(LSB)
600
INPUT
CNLINE=0
CNLINE=1, COFFSET=0
CNLINE=1, COFFSET=4
CNLINE=1, COFFSET=8
CNLINE=1, COFFSET=12
CNLINE=1, COFFSET=15
CNLINE=1, COFFSET=20
400
200
0
0
200
400
600
INPUT(LSB)
800
1000
1200
2) DC level adjustment
Registers related to DC level adjustment
Name
SELYCRGB
Functions
This register switches between the YCbCr input and RGB input.
Sub address
bit width
0x14
1
0x1D
7
0x19
1
0x1A
1
0x1C
5
0: YCbCr, 1: RGB
BRADJ
This register adjusts the DC level. When the gain adjustment + DC level adjustment
output is linear (BNLINE = 0), BRADJ is offset from the video signals produced after the
gain adjustment (the Y signal is further offset by 64).
Setting range: -64 to +63, default value: ±0 (40h)
CNLINE
This register sets the applicable non-linear gain adjustment,
when the gain adjustment + DC level adjustment is used (BRADJ<40h), to ON or OFF.
0: OFF (linear gain adjustment)
1: ON (non-linear gain adjustment)
BNLINE
This register sets the applicable non-linear gain adjustment,
when the gain adjustment + DC level adjustment is used (BRADJ>40h), to ON or OFF.
0: OFF (linear gain adjustment)
1: ON (nonlinear gain adjustment)
COFFSET
This register adjusts the non-linear gain region when the non-linear gain adjustment is
ON (BNLINE = 1)
No.A1647-29/37
LC74950BG
• DC level adjustment specifications
AMP
Input signal
Output signal
Gain adjustment
Digital clamp level
DC level adjustment value
The DC level is adjusted by adding BRADJ[6:0] to the Y signal or RGB signals subjected to gain adjustment
processing.
• Non-linear gain adjustment + DC level adjustment
When CNLINE = 1 and BRADJ[6:0]<0x40 (minus), the output corresponding to the input near the saturation region is
made non-linear. When the non-linear gain adjustment parameter (CONPARA) obtained from the formula below is
less than the multiplier (RGB: (32 + GAIN_x[6:0])/64, YCbCr: (48 + GAIN_x[6:0])/64) that is used when the linear
gain is adjusted, the input is multiplied by the non-linear gain adjustment parameter, resulting in a non-linear output.
The non-linear start position and maximum non-linear output value can be adjusted using COFFSET[4:0].
CONPARA = (1023 − 9-bit video signal) × (64 + COFFSET[4:0])/64 − BRADJ[6:0]/2
Similarly, when BNLINE = 1 and BRADJ[6:0]>0x40 (plus), the output corresponding to the input near the saturation
region is made non-linear. When the DC adjustment parameter (BRPARA), obtained from the formula below, is less
than BRADJ[6:0], the extent to which the output is to be non-linear is adjusted by adding the DC adjustment
parameter to the Y signal or RGB signals subjected to non-linear gain adjustment processing.
BRPARA = (127 − non-linear gain output/16) × (64 + COFFSET[4:0])/64
The figure below shows the output obtained when the gain adjustment and DC level adjustment have been performed
(when GAIN_Y[6:0] = 63, COFFSET[4:0] = 8).
GAIN_Y=63 (AMP=1.73)
1200
1000
800
OUTPUT(LSB)
600
INPUT
CNLINE=0
400
CNLINE=0, BNLINE=1, BRADJ=64
CNLINE=0, BNLINE=1, BRADJ=0
200
CNLINE=0, BNLINE=1, BRADJ=127
0
0
200
400
600
INPUT(LSB)
800
1000
1200
No.A1647-30/37
LC74950BG
9. External interface
I2C: 100kHz mode is supported. The slave address can be selected using the pin settings.
Slave address: 0x98, 0x9A
1) Control specifications
Slave operations in the standard mode (100kHz) are supported.
These must be used for setting the internal registers and setting the internal status output and γ correction
characteristics. The slave addresses are listed in the table below. Two addresses can be selected using the I2CSEL pin.
Slave address:
(I2CSEL=0)
Slave address:
(I2CSEL=1)
1
0
0
1
1
0
0
R/W
1
0
0
1
1
0
1
R/W
2) Control and timing specifications
(1) Receive mode
As shown below, the slave address W, sub-address and input data must be set in this sequence after the start
condition. The data of each sub-address can be input in auto address increments consecutively from the data of the
sub-address specified. The data must be set consecutively with ACK between one data and the next. The stop
condition must be set last.
Slave address W
SDA
1
SCL
tH_S
ACK
8
9
tH_D
tS_D
Parameter
Sub-address
tR
tF
tHI
ACK
Input data
ACK
tLO
Symbol
tS_P
min
max
unit
fSCL
0
Start condition hold time
tH_S
4.0
μs
Data hold time
tH_D
0
μs
Data setup time
tS_D
250
SCL clock frequency
100
kHz
ns
SDA and SCL rise time
tR
1000
ns
SDA and SCL fall time
tF
300
ns
SCL high level hold time
tHI
4.0
μs
SCL low level hold time
tLO
4.7
μs
Stop condition setup time
tS_P
4.7
μs
No.A1647-31/37
LC74950BG
(2) Send mode
As shown below, slave address W and the sub-address must be set after the start condition. The stop condition must
be set last.
SDA
Slave address W
ACK
Sub-address
ACK
SCL
Slave address R must then be set after the start condition. The data of each sub-address is output in auto address
increments consecutively from the data of the specified sub-address. The stop condition must be set last.
SDA
Slave address R
ACK
Input data
ACK
Input data
ACK
SCL
(3) Register settings
The registers can be broadly divided into receive and send registers. Receive registers are setting registers for
internal control; send registers are for outputting the internal statuses to an external destination. The receive register
settings can also be output to an external destination.
No.A1647-32/37
LC74950BG
3) Register map
Sub
bit7
Address
(MSB)
bit6
bit5
bit4
bit3
CLKHSYIINV
CLKINININV
bit2
bit1
bit0
Initial
(LSB)
Value
Clock I/O control
00H
R/W
CLKOUT2INV
CLKOUT1INV
01H
R/W
CLKOUTINV
-
02H
R/W
VSOUTINV
ASCRR[2:0]
03H
R/W
HOUTINV
ASVS[2:0]
CLKADCIINV
CLKSEL[2:0]
08h
HSPLLSEL
ASYG[2:0]
88h
VSINV
ASCBB[2:0]
08h
HSINV
ASHS[2:0]
08h
Synchronous I/O control/offset adjustment control
-
-
H/V enable control
04H
R/W
HBLKS[11: 8]
05H
R/W
HBLKS[7:0]
06H
R/W
HBLKE[7:0]
07H
R/W
08H
R/W
09H
R/W
-
HBLKE[11: 8]
VBLKS[10: 8]
03h
7Ah
4Ah
-
VBLKE[10: 8]
01h
VBLKS[7:0]
11h
VBLKE[7:0]
02h
Digital clamp
0AH
R/W
DCLPYON
DIGCLPON
0BH
R/W
DCLPYV
0CH
R/W
-
0DH
R/W
DCPYSET[5:0]
A7h
DCLPYW[5:0]
DCPYVMS[10: 8]
C4h
DCPYVME[10: 8]
-
01h
DCPYVMS[7:0]
0EH
R/W
0FH
R/W
DCLPCON
-
10H
R/W
DCLPCV
-
11h
DCPYVME[7:0]
A7h
DCLPCW[5:0]
DCPCVMS[10: 8]
-
02h
DCPCSET[5:0]
84h
DCPCVME[10: 8]
11H
R/W
12H
R/W
DCPCVMS[7:0]
-
01h
11h
13H
R/W
DCPCVME[7:0]
02h
14H
R/W
SELYCRGB
-
STDLEVY[5:0]
15H
R/W
DCLINE
-
STDLEVCB[5:0]
20h
16H
R/W
EXSYNCON
-
STDLEVCR[5:0]
20h
17H
R/W
18H
R/W
TCDIGCLP[2:0]
-
-
A0h
FRAMEDC[4:0]
40h
-
20h
Sub-contrast/brightness
19H
R/W
CNLINE
GAINY[6:0]
20h
1AH
R/W
BNLINE
GAINCB[6:0]
20h
1BH
R/W
SYNCON
GAINCR[6:0]
20h
1CH
R/W
-
-
-
COFFSET[4:0]
1DH
R/W
-
BRADJ[6:0]
1EH
R/W
-
-
1FH
R/W
20H
R/W
-
-
08h
40h
40h
-
-
-
00h
-
00h
AFE/ADC
21H
R/W
STBB
-
22H
R/W
AINSEL
-
23H
R/W
-
-
24H
R/W
-
-
25H
R/W
-
-
26H
R/W
-
-
SELFCLPSTBB_Y
STBB_Y
MAINCLPLVCNT_Y[1:0]
SELFCLPSTBB_B
-
STBB_B
MAINCLPLVCNT_B[1:0]
SELFCLPSTBB_R
STBL_Y[3:0]
CLPLPFON_Y
GAIN_Y
STBL_B[3:0]
-
STBB_R
MAINCLPLVCNT_R[1:0]
HPFCLPON_Y
BFh
HPFCLPON_B
CLPLPFON_B
GAIN_B
STBL_R[3:0]
-
HPFCLPON_R CLPLPFON_R
12h
3Fh
12h
3Fh
GAIN_R
12h
Continued on next page.
No.A1647-33/37
LC74950BG
Continued from preceding page.
Sub
bit7
Address
(MSB)
bit6
bit5
bit4
bit3
bit2
bit0
Initial
(LSB)
Value
PLLCTL2
PLLCTL1
C0h
73h
bit1
PLL
27H
R/W
CORREN
-
PLLGAIN[2:0]
28H
R/W
HPLDIV15
HPLDIV14
HPLDIV13
HPLDIV12
HPLDIV11
HPLDIV10
HPLDIV9
HPLDIV8
29H
R/W
HPLDIV7
HPLDIV6
HPLDIV5
HPLDIV4
HPLDIV3
HPLDIV2
HPLDIV1
HPLDIV0
2AH
R/W
CPIS_COAST[3:0]
CORRHSS[11: 8]
CPIS_ORG[3:0]
58h
AAh
2BH
R/W
2CH
R/W
CORRHSS[7:0]
CORRHSE[11: 8]
35h
2DH
R/W
CORRHSE[7:0]
1Ch
2EH
R/W
2FH
R/W
30H
R/W
31H
R/W
32H
R/W
33H
OSEL[2:0]
-
-
-
02h
-
-
-
-
-
-
-
-
01h
06h
00h
-
-
-
R/W
-
-
34H
R
-
-
35H
R
-
36H
R
-
37H
R/W
38H
R/W
-
-
39H
R/W
-
-
-
-
ICNT_Y[2:0]
0Ch
3AH
R/W
-
-
-
-
ICNT_B[2:0]
0Ch
-
-
80h
-
08h
-
-
20h
-
-
00h
00h
00h
-
-
-
-
01h
-
-
-
ICNT_R[2:0]
00h
3BH
R/W
-
-
3CH
R/W
-
-
-
-
-
-
-
-
0Ch
00h
3DH
R/W
-
-
-
-
-
-
-
-
00h
3EH
R/W
-
-
-
-
-
-
-
-
00h
3FH
R/W
-
-
-
-
-
-
-
-
92h
PLL and others
40H
R/W
-
-
FEH
R/W
-
-
CLKINDIV[5:0]
-
-
-
-
1Fh
-
-
80h
No.A1647-34/37
LC74950BG
PDOWN
Complete power-down can be controlled using the PDWN pin. ADC, PLL and other items can be powered down
individually by means of register settings. This makes it possible to limit the power consumption as required.
Internal states based on the PDWN pin setting
PDWN
ADC
PLL
Logic
Communication
Remarks
0
PowerDown
PowerDown
Clocks stopped
Stopped
Registers reset state
1
Operating
Operating
Operating
Operating
Power Down control by controlling registers
Item
ADC
Power-down can be controlled using dedicated registers. See below for the relevant registers.
PLL
Power-down can be controlled using dedicated registers. See below for the relevant registers.
Logic
Output pin
Communication
External input is selected and the external clock is stopped.
Similarly, the clock is stopped by selecting the PLL mode and power down the PLL circuit.
Output-enable (Hi-Z) can be set by using the dedicated registers.
Cannot be stopped.
Name
Functions
Sub address
bit width
STBL_Y
These registers control the ADC standby mode (Y: STBL_Y, B: STBL_B, R: STBL_R).
0x21
4
STBL_B
0000: ADC standby mode
0x23
STBL_R
1111: ADC normal operating mode
0x25
*1: Any other setting than above inhibited.
*2: These must be set in accordance with the operating mode of AEC.
STBB
This register controls the band gap VREF circuit.
0x21
1
1
0: Places the band gap VREF circuit into the standby mode.
1: Places the band gap VREF circuit into the normal operating mode.
*: This must be set in accordance with the operating mode of ADC.
STBB_Y
These registers control the AFE standby mode (Y: STBB_Y, B: STBB_B, R: STBB_R).
0x21
STBB_B
0: AFE standby mode
0x23
STBB_R
1: AFE normal operating mode
0x25
*: These must be set in accordance with the operating mode of ADC.
PLLCTL2
This register controls the H-lock PLL power down mode
0x27
1
0: Normal operating mode
1: H-lock PLL power off
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Other (usage precautions)
1. Precaution when turning on the power
As shown in the figure below, start the transfer of the I2C bus command after factoring in the power-on time (A),
PDWN operation time (B), RESET operation time (C) and command transfer start time (D).
DVDD33
AVDD33
DVDD15
AVDD15
3.0V
1.35V
2V
PDWN
0.2VDD
2V
RESET
0.2VDD
0.75VDD
Command
A
B
C
D
A: Power-on time
This is the time taken from power-on to when the *VDD15 operating supply voltage has reached the lowest level
(1.35V) and operation has stabilized. The power-on-time depends on the characteristics of the power ICs and other
components, so it must be checked separately. With regard to *VDD33 and *VDD15, *VDD15 must be turned on
after *VDD33 has turned on.
B: PDWN operation time
This is the time during which the "L" level must be applied continuously for a period of 10ms or more to the PDWN
pin after the lowest level (1.35V) of the *VDD15 operating supply voltage has been reached and operation has
stabilized.
C: RESET operation time
This is the time during which the "L" level must be applied continuously for a period of 10ms or more to the RESET
pin after the PDWN is released ("H" level).
D: Command transfer start time
At least an interval of 10ms is required from the time the RESET pin is released ("H" level) to the start of command
transfer.
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2. Precaution when turning off the power
3.0V
DVDD33
AVDD33
DVDD15
AVDD15
1.35V
A
As a basic rule, power-off must be performed in the reverse sequence of power-on. However, no problems are posed if
there is no wait time.
A: Power-off time
This is the time it takes to reach the IO supply voltage and for operation to stabilize from the lowest level (1.35V) of
the *VDD15 operating supply voltage. With regard to *VDD33 and *VDD15, *VDD33 must be turned off after
*VDD15 has been turned off or they must be turned off at the same time.
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PS No.A1647-37/37