Ordering number : EN8299B LC875G32A LC875G24A LC875G16A LC875G08A CMOS IC ROM 32K/24K/16K/8K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller Overview The SANYO LC875G32A/24A/16A/08A are 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 32K/24K/16K/8K-byte ROM, 1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-ofday clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-bit/8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 22-source 10-vector interrupt feature. Features ROM • 32768 × 8 bits (LC875G32A) • 24576 × 8 bits (LC875G24A) • 16384 × 8 bits (LC875G16A) • 8192 × 8 bits (LC875G08A) RAM • 1024 × 9 bits (LC875G32A/24A/16A/08A) Minimum Bus Cycle • 100ns (10MHz) Note: The bus cycle time here refers to the ROM read speed. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.3.00 52307HKIM 20070123-S00015 No.8299-1/23 LC875G32A/24A/16A/08A Minimum Instruction Cycle Time • 300ns (10MHz) Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units 30 (P1n,P2n,P30 to P36,P70 to P73,PWM0,PWM1,XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P0n) • Normal withstand voltage input port 1 (XT1) • Dedicated oscillator ports 2 (CF1, CF2) • Reset pins 1 (RES) • Power pins 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2-channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time-schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real time. SIO • SIO 0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO 1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART • Full duplex • 7/8/9 bit data bits selectable • 1stop bit (2-bit in continuous data transmission) • Built-in baudrate generator No.8299-2/23 LC875G32A/24A/16A/08A AD Converter : 12-bits/8-bits×12-channels • 12-bits/8-bits AD converter selectable • Automatic reference voltage generation controllable PWM : Multifrequency 12-bit PWM×2-channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Interrupts • 22 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L INT0 Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/T4/T5/PWM0, PWM1 • Priority Level: X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16-bits×8-bits (5 tCYC execution time) • 24-bits×16-bits (12 tCYC execution time) • 16-bits÷8-bits (8 tCYC execution time) • 24-bits÷16-bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • Frequency variable RC oscillation circuit (internal): For system clock For system clock, with internal Rf For low-speed system clock, with internal Rf For system clock System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs (at a main clock rate of 10MHz). No.8299-3/23 LC875G32A/24A/16A/08A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt. • HOLD mode : Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port 0. • X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port. (4) Having an interrupt source established in the base timer circuit. Package Form • QIP48E(14×14): “Lead-free type” • SQFP48(7×7): “Lead-free type” Development Tools • Evaluation chip: LC87EV690 • Emulator: EVA62S+ECB876600D+SUB875G00+POD48QFP ICE-B877300+SUB875G00+POD48QFP • Onchip debugger: TCB87 TypeA+LC87F5G32A TCB87 TypeB+LC87F5G32A Flash ROM Version • LC87F5G32A No.8299-4/23 LC875G32A/24A/16A/08A Package Dimensions Package Dimensions unit : mm (typ) 3156A unit : mm (typ) 3163B 0.8 14.0 25 36 36 0.5 9.0 7.0 17.2 25 37 24 48 13 24 17.2 14.0 7.0 9.0 37 13 48 1 12 0.5 1 0.15 (0.75) 12 1.0 0.18 0.15 0.35 3.0max (1.5) 0.1 (2.7) 1.7max (1.5) 0.1 SANYO : SQFP48(7X7) SANYO : QIP48E(14X14) 36 35 34 33 32 31 30 29 28 27 26 25 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P07/T7O/AN7 P06/T6O/AN6 P05/CKO/AN5 P04/AN4 Pin Assignment LC875G32A LC875G24A LC875G16A LC875G08A 24 23 22 21 20 19 18 17 16 15 14 13 P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P36 P35 VDD3 VSS3 P34 P33 P32 P31 P30 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN Top view SANYO: QIP48E(14×14) "Lead-free Type" SANYO: SQFP48(7×7) "Lead-free Type" No.8299-5/23 LC875G32A/24A/16A/08A SQFP/QIP NAME SQFP/QIP NAME 1 P73/INT3/T0IN 25 P04/AN4 2 RES 26 P05/CKO/AN5 3 XT1/AN10 27 P06/T6O/AN6 4 XT2/AN11 28 P07/T7O/AN7 5 VSS1 29 P20/UTX/INT4/T1IN 6 CF1 30 P21/URX/INT4/T1IN 7 CF2 31 P22/INT4/T1IN 8 VDD1 32 P23/INT4/T1IN 9 P10/SO0 33 P24/INT5/T1IN 10 P11/SI0/SB0 34 P25/INT5/T1IN 11 P12/SCK0 35 P26/INT5/T1IN 12 P13/SO1 36 P27/INT5/T1IN 13 P14/SI1/SB1 37 P36 14 P15/SCK1 38 P35 15 P16/T1PWML 39 VDD3 16 P17/T1PWMH/BUZ 40 VSS3 17 PWM1 41 P34 18 PWM0 42 P33 19 VDD2 43 P32 20 VSS2 44 P31 21 P00/AN0 45 P30 22 P01/AN1 46 P70/INT0/T0LCP/AN8 23 P02/AN2 47 P71/INT1/T0HCP/AN9 24 P03/AN3 48 P72/INT2/T0IN No.8299-6/23 LC875G32A/24A/16A/08A System Block Diagram Interrupt control IR Standby control PLA ROM RC X’tal Clock generator CF PC MRC SIO0 Bus interface ACC SIO1 Port 0 B register Timer 0 Port 1 C register Timer 1 Port 3 ALU Timer 4 Port 7 Timer 5 ADC PSW Timer 6 INT0-2, INT4,5 INT3(Noise filter) RAR Timer 7 Port 2 RAM Base timer UART1 Stack pointer PWM0 Watchdog timer PWM1 No.8299-7/23 LC875G32A/24A/16A/08A Pin Description Pin Name VSS1 VSS2 I/O Description Option - - Power supply pin No - + Power supply pin No • 8-bit I/O port Yes VSS3 VDD1 VDD2 VDD3 Port 0 I/O • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistors can be turned on and off in 4-bit units • HOLD reset input • Port 0 interrupt input • Shared pins P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output AD converter input port: AN0 (P00) to AN7 (P07) Port 1 I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 2 P20 to P27 I/O Yes • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input Interrupt acknowledge type Rising Falling INT4 enable enable INT5 enable enable Rising & H level L level enable disable disable enable disable disable Falling Continued on next page. No.8299-8/23 LC875G32A/24A/16A/08A Continued from preceding page. Pin Name Port 3 I/O I/O Description Option • 7-bit I/O port Yes • I/O specifiable in 1-bit units P30 to P36 • Pull-up resistors can be turned on and off in 1-bit units Port 7 I/O No • 4-bit I/O port • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistors can be turned on and off in 1-bit units • Shared pins AD converter input port : AN8 (P70), AN9 (P71) P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input Interrupt acknowledge type PWM0, PWM1 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling • PWM0 and PWM1 output ports No • General-purpose I/O available RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin No • Shared pins General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used XT2 I/O • 32.768kHz crystal oscillator output pin No • Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used CF1 Input CF2 Output Ceramic resonator input pin No Ceramic resonator output pin No No.8299-9/23 LC875G32A/24A/16A/08A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type P00 to P07 1-bit 1 P10 to P17 1-bit Output Type Pull-up Resistor CMOS Programmable (Note 1) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable 1-bit 1 CMOS Programmable 2 Nch-open drain Programmable P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable P20 to P27 P30 to P36 1-bit PWM0, PWM1 - No CMOS No XT1 - No Output for 32.768kHz crystal oscillator No (Input only) XT2 - No Input for 32.768kHz crystal oscillator No (Nch-open drain when in general-purpose output mode) Note 1: Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07). Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded. Example 1: During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Example 2: During backup in hold mode, output is not held high and its value in unsettled. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.8299-10/23 LC875G32A/24A/16A/08A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Maximum supply VDD max VDD1, VDD2, VDD3 Input voltage VI XT1, CF1 Input/output VIO Ports 0, 1, 2, voltage voltage VDD1=VDD2=VDD3 Port 3, 7, PWM0, min typ max unit -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 V PWM1, XT2 Peak output IOPH(1) Ports 0, 1, 2, 3 current CMOS output select Per 1 applicable pin IOPH(2) PWM0, PWM1 CMOS output select Per 1 applicable pin High level output current Mean output IOPH(3) Ports P71 to P73 Per 1 applicable pin IOMH(1) Ports 0, 1, 2, 3 CMOS output select current (Note 1-1) Per 1 applicable pin IOMH(2) PWM0, PWM1 CMOS output select Per 1 applicable pin -10 -20 -5 -7.5 -15 IOMH(3) Ports P71 to P73 Per 1 applicable pin Total output ΣIOAH(1) Ports P71 to P73 Total of all applicable pins -10 current ΣIOAH(2) Port 0 Total of all applicable pins -25 ΣIOAH(3) Port 1, Total of all applicable pins PWM0, PWM1 ΣIOAH(4) Ports 0, 1 Total of all applicable pins PWM0, PWM1 Peak output -3 -25 -45 ΣIOAH(5) Ports 2, P35, P36 Total of all applicable pins -25 ΣIOAH(6) Ports P30 to P34 Total of all applicable pins -25 -45 ΣIOAH(7) Ports 2, 3 Total of all applicable pins IOPL(1) Ports P02 to P07 Per 1 applicable pin current mA Ports 1, 2, 3 20 PWM0, PWM1 Low level output current Mean output IOPL(2) Ports P00, P01 Per 1 applicable pin 30 IOPL(3) IOML(1) Port 7, XT2 Per 1 applicable pin 10 Ports P02 to P07 Per 1 applicable pin current Ports 1, 2, 3 (Note 1-1) PWM0, PWM1 IOML(2) 15 Ports P00, P01 Per 1 applicable pin 20 IOML(3) Port 7, XT2 Per 1 applicable pin 7.5 Total output ΣIOAL(1) Port 7, XT2 Total of all applicable pins 15 current ΣIOAL(2) Port 0 Total of all applicable pins 45 ΣIOAL(3) Port 1, Total of all applicable pins 45 PWM0, PWM1 ΣIOAL(4) Ports 0, 1 Total of all applicable pins 80 PWM0, PWM1 Power dissipation ΣIOAL(5) Ports 2, P35, P36 Total of all applicable pins ΣIOAL(6) Ports P30 to P34 Total of all applicable pins ΣIOAL(7) Ports 2, 3 Total of all applicable pins Pd max SQFP48(7×7) Ta= -30 to +70°C 45 45 60 190 QIP48E(14×14) Operating ambient Topr temperature Storage ambient Tstg temperature mW 390 -30 +70 -55 +125 °C Note 1-1: The mean output current is a mean value measured over 100ms. No.8299-11/23 LC875G32A/24A/16A/08A Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] typ max unit 0.294µs ≤ tCYC ≤ 200µs 4.0 5.5 VDD(2) 0.367µs ≤ tCYC ≤ 200µs 3.0 5.5 VDD(3) 0.588µs ≤ tCYC ≤ 200µs 2.5 5.5 2.0 5.5 Operating VDD(1) supply voltage Memory min VHD VDD1=VDD2=VDD3 VDD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. sustaining supply voltage High level input VIH(1) voltage Ports 1, 2, 3 P71 to P73 2.5 to 5.5 P70 port input/ interrupt side 0.3VDD VDD +0.7 PWM0, PWM1 VIH(2) VIH(3) Port 0 2.5 to 5.5 Port 70 watchdog timer 2.5 to 5.5 side VIH(4) Low level input VIL(1) voltage XT1, XT2, CF1, RES 0.3VDD VDD +0.7 0.9VDD VDD 2.5 to 5.5 0.75VDD VDD 4.0 to 5.5 VSS 2.5 to 4.0 VSS 4.0 to 5.5 VSS 2.5 to 4.0 VSS 2.5 to 5.5 VSS 2.5 to 5.5 VSS 0.25VDD Ports 1, 2, 3 P71 to P73 V 0.1VDD +0.4 P70 port input/ interrupt side PWM0, PWM1 VIL(2) VIL(3) Port 0 Port 70 watchdog timer side VIL(4) XT1, XT2, CF1, RES 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 Instruction cycle tCYC 4.0 to 5.5 0.294 200 time (Note 2-1) 3.0 to 5.5 0.367 200 2.5 to 5.5 0.588 200 4.5 to 5.5 0.1 10 2.5 to 5.5 0.1 5 4.5 to 5.5 0.2 20.4 2.5 to 5.5 0.2 10 External system FEXCF CF1 clock frequency µs • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% • CF2 pin open • System clock frequency division ratio=1/2 Oscillation FmCF(1) CF1, CF2 frequency range 10MHz ceramic oscillation See Fig 1. FmCF(2) CF1, CF2 (Note 2-2) 8MHz ceramic oscillation See Fig 1. FmCF(3) CF1, CF2 5MHz ceramic oscillation See Fig 1. FmRC Internal RC oscillation FmMRC Frequency variable RC oscillation source oscillation FsX’tal XT1, XT2 32.768kHz crystal oscillation See Fig 2. 4.0 to 5.5 10 3.0 to 5.5 8 2.5 to 5.5 5 2.5 to 5.5 0.3 1.0 2.5 to 5.5 16 2.5 to 5.5 32.768 MHz 2.0 kHz Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants. No.8299-12/23 LC875G32A/24A/16A/08A Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 2, 3 Output disabled Port 7 RES Pull-up resistor off PWM0, PWM1 VIN=VDD (Including output Tr's off min typ max 2.5 to 5.5 1 2.5 to 5.5 1 2.5 to 5.5 15 unit leakage current) IIH(2) XT1, XT2 For input port specification VIN=VDD Low level input IIH(3) CF1 VIN=VDD IIL(1) Ports 0, 1, 2, 3 Output disabled Port 7 RES Pull-up resistor off current PWM0, PWM1 VIN=VSS (Including output Tr's off 2.5 to 5.5 -1 2.5 to 5.5 -1 µA leakage current) IIL(2) XT1, XT2 For input port specification VIN=VSS IIL(3) CF1 VIN=VSS 2.5 to 5.5 -15 High level output VOH(1) Ports 0, 1, 2, 3 IOH= -1mA 4.5 to 5.5 VDD-1 voltage VOH(2) IOH= -0.1mA 2.5 to 5.5 VDD-0.5 VOH(3) P71 to P73 IOH= -0.4mA 4.5 to 5.5 VDD-1 VOH(4) PWM0, PWM1, IOH= -6mA 4.5 to 5.5 VDD-1 IOH= -1.6mA 4.5 to 5.5 VDD-0.4 2.5 to 5.5 VDD-0.4 VOH(5) P05 (System clock output function V VOH(6) used) IOH= -1mA Low level output VOL(1) Ports 0, 1, 2, 3 IOL=10mA 4.5 to 5.5 1.5 voltage VOL(2) PWM0, PWM1, IOL=1.6mA 4.5 to 5.5 0.4 VOL(3) Pull-up resistance XT2 IOL=1mA 2.5 to 5.5 0.4 IOL=30mA 4.5 to 5.5 1.5 2.5 to 5.5 0.4 VOL(4) P00, P01 VOL(5) Port 7 IOL=1mA Rpu(1) Ports 0, 1, 2, 3 VOH=0.9VDD Port 7 Rpu(2) Ports 0, 1, 2, 3 VOH=0.9VDD Port 7 Hysteresis voltage VHYS RES Ports 1, 2, 7 Pin capacitance CP All pins 4.5 to 5.5 15 35 80 2.5 to 4.5 18 50 150 kΩ 2.5 to 5.5 0.1VDD V 2.5 to 5.5 10 pF For pins other than that under test: VIN=VSS f=1MHz Ta=25°C No.8299-13/23 LC875G32A/24A/16A/08A Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock VDD[V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. tSCKH(1) pulse width tSCKHA(1) 2.5 to 5.5 tCYC 4 • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.5 to 5.5 pulse width tSCKHA(2) 1/2 • Continuous data tSCKH(2) transmission/reception mode • CMOS output selected +2tCYC • See Fig. 6. Data setup time Serial input unit 1 • Continuous data • See Fig. 6. Low level tsDI(1) SB0(P11), SI0(P11) tSCKH(2) +(10/3) tCYC tCYC • Must be specified with respect to rising edge of 2.5 to 5.5 0.03 2.5 to 5.5 0.03 SIOCLK. Data hold time Output clock Input clock Output delay Serial output max 1 transmission/reception mode Serial clock typ 2 pulse width High level min • See Fig. 6. thDI(1) tdD0(1) time SO0(P10), SB0(P11) • Continuous data transmission/reception mode 2.5 to 5.5 • (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode • (Note 4-1-3) tdD0(3) 2.5 to 5.5 (1/3)tCYC +0.05 µs 1tCYC +0.05 (Note 4-1-3) 2.5 to 5.5 (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.8299-14/23 LC875G32A/24A/16A/08A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) See Fig. 6. 2.5 to 5.5 pulse width High level Frequency SCK1(P15) • CMOS output selected tSCKL(4) 2 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time tsDI(2) SB1(P14), SI1(P14) • Must be specified with respect to rising edge of 2.5 to 5.5 0.03 2.5 to 5.5 0.03 SIOCLK. Data hold time Output delay time • See Fig. 6. thDI(2) tdD0(4) SO1(P13), SB1(P14) Serial output unit 1 2.5 to 5.5 pulse width High level max 1 • See Fig. 6. Low level typ tCYC tSCKH(3) tSCK(4) min 2 pulse width Output clock Serial clock VDD[V] • Must be specified with µs respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of 2.5 to 5.5 (1/3)tCYC +0.05 output state change in open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.8299-15/23 LC875G32A/24A/16A/08A Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 are INT2(P72), enabled. min typ 2.5 to 5.5 1 2.5 to 5.5 2 2.5 to 5.5 64 2.5 to 5.5 256 2.5 to 5.5 200 max unit INT4(P20 to P23), INT5(P24 to P27) tPIH(2) INT3(P73) when • Interrupt source flag can be set. tPIL(2) noise filter time • Event inputs for timer 0 are constant is 1/1 tPIH(3) INT3(P73) when • Interrupt source flag can be set. tPIL(3) noise filter time • Event inputs for timer 0 are constant is 1/32 enabled. tPIH(4) INT3(P73) when • Interrupt source flag can be set. tPIL(4) noise filter time • Event inputs for timer 0 are constant is 1/128 tPIL(5) RES tCYC enabled. enabled. Resetting is enabled. µs AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V <12-bits AD Converter Mode / Ta= -10°C to +50°C> Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(P00) to Absolute accuracy ET AN7(P07) Conversion time TCAD AN8(P70) AN9(P71) AN10(XT1) Analog input VAIN min 4.75 to 5.25 (Note 6-1) typ max 12 4.75 to 5.25 unit bit T.B.D LSB See conversion time calculation formulas. 4.75 to 5.25 38.5 90 µs 4.75 to 5.25 VSS VDD V (Note 6-2) AN11(XT2) voltage range Analog port input IAINH VAIN=VDD 4.75 to 5.25 current IAINL VAIN=VSS 4.75 to 5.25 1 -1 µA <8-bits AD Converter Mode / Ta= -30°C to +70°C> Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(P00) to Absolute accuracy ET AN7(P07) Conversion time TCAD AN8(P70) AN9(P71) AN10(XT1) Analog input VAIN AN11(XT2) min 3.0 to 5.5 typ max 8 bit ±1.5 (Note 6-1) 3.0 to 5.5 See conversion time calculation 4.5 to 5.5 22.5 90 3.0 to 5.5 45 90 3.0 to 5.5 VSS VDD formulas. (Note 6-2) voltage range Analog port input IAINH VAIN=VDD 3.0 to 5.5 current IAINL VAIN=VSS 3.0 to 5.5 1 -1 unit LSB µs V µA Conversion time calculation formulas: 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(division ratio))+2) × (1/3) × tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(division ratio))+2) × (1/3) × tCYC Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when : • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.8299-16/23 LC875G32A/24A/16A/08A Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] • FmCF=10MHz consumption VDD1 =VDD2 current =VDD3 • FsX’tal=32.768kHz crystal oscillation Normal mode IDDOP(1) (Note 7-1) min typ max unit ceramic oscillation mode mode • System clock set to 10MHz side 4.0 to 5.5 7 12.5 4.0 to 5.5 8 15 4.5 to 5.5 3.7 6.8 • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(2) • CF1=20MHz external clock • FsX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(3) • FmCF=5MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode mA • System clock set to 5MHz side IDDOP(4) • Internal RC oscillation stopped • Frequency variable RC 2.5 to 4.5 1.9 5.2 4.5 to 5.5 0.6 1.9 2.5 to 4.5 0.3 1.4 4.5 to 5.5 1.3 4.2 2.5 to 4.5 0.7 3.2 4.5 to 5.5 26 85 oscillation stopped • 1/1 frequency division ratio IDDOP(5) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC IDDOP(6) oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(7) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped IDDOP(8) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio IDDOP(9) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side IDDOP(10) µA • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 2.5 to 4.5 11 65 • 1/2 frequency division ratio Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.8299-17/23 LC875G32A/24A/16A/08A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) Pin/ consumption VDD1 =VDD2 current =VDD3 (Note 7-1) Specification Conditions Remarks VDD[V] min typ max unit • HALT mode • FmCF=10MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 10MHz side 4.0 to 5.5 2.4 4.9 4.0 to 5.5 3.4 7.7 4.5 to 5.5 1.5 3.1 • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDHALT(2) • HALT mode • CF1=20MHz external clock • FsX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDHALT(3) • HALT mode • FmCF=5MHz ceramic oscillation mode mA • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 5MHz side IDDHALT(4) • Internal RC oscillation stopped • Frequency variable RC 2.5 to 4.5 0.7 2.2 4.5 to 5.5 0.3 1.1 2.5 to 4.5 0.15 0.8 4.5 to 5.5 1.1 3.6 2.5 to 4.5 0.6 2.7 4.5 to 5.5 18 60 2.5 to 4.5 7 40 oscillation stopped • 1/1 frequency division ratio • HALT mode IDDHALT(5) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation IDDHALT(6) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio • HALT mode IDDHALT(7) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped IDDHALT(8) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio • HALT mode IDDHALT(9) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDHALT(10) • Frequency variable RC oscillation stopped µA • 1/2 frequency division ratio HOLD mode consumption current Timer HOLD IDDHOLD(1) IDDHOLD(3) current HOLD mode (External clock mode) VDD1 Timer HOLD mode • CF1=VDD or open IDDHOLD(4) 4.5 to 5.5 0.015 17 2.5 to 4.5 0.01 12 4.5 to 5.5 16 55 2.5 to 4.5 10 36 • CF1=VDD or open IDDHOLD(2) mode consumption VDD1 (External clock mode) • FsX’tal=32.768kHz crystal oscillation mode Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.8299-18/23 LC875G32A/24A/16A/08A UART (Full duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Transfer rate UBR P20, P21 2.5 to 5.5 min typ 16/3 max unit 8192/3 tCYC Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1-bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Start bit Start of transmission Stop bit End of transmission Transmit data (LSB first) UBR Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Stop bit Start bit Receive data (LSB first) Start of reception End of reception UBR No.8299-19/23 LC875G32A/24A/16A/08A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency 10MHz 8MHz 5MHz Operating Circuit Constant Vendor Name MURATA MURATA MURATA Oscillator Name Oscillation Stabilization Voltage Time Remarks C1 C2 Rf Rd1 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE10M0G52-R0 (10) (10) Open 680 4.0 to 5.5 0.1 0.5 CSTCE10M0G52-B0 (10) (10) Open 680 4.0 to 5.5 0.1 0.5 (SMD type) CSTCE8M00G52-R0 (10) (10) Open 1.0k 3.0 to 5.5 0.1 0.5 Internal C1, C2 CSTCE8M00G52-B0 (10) (10) Open 1.0k 3.0 to 5.5 0.1 0.5 (SMD type) Internal C1, C2 CSTCR5M00G53-R0 (15) (15) Open 2.2k 2.5 to 5.5 0.2 0.6 Internal C1, C2 CSTCR5M00G53-B0 (15) (15) Open 2.2k 2.5 to 5.5 0.2 0.6 (SMD type) The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). It is recommended to insert feedback resister (Rf: 1MΩ) when power supply voltage is used around 2.5V. Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Operating Circuit Constant Vendor Name EPSON 32.768kHz TOYOCOM Oscillator Name Oscillation Stabilization Voltage Time C3 C4 Rf Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 18 Open 510k 2.5 to 5.5 1.1 3.0 MC-306 Remarks Applicable CL value=12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF2 CF1 Rf XT1 XT2 Rf Rd1 C1 C2 C3 Rd2 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.8299-20/23 LC875G32A/24A/16A/08A VDD Operating VDD lower limit 0V Power Supply Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.8299-21/23 LC875G32A/24A/16A/08A VDD (Note) Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC's operating voltage. RRES RES CRES Figure 5 Reset Circuit SIOCLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK : tsDI thDI DATAIN : tdDO DATAOUT : Data RAM transfer period (SIO0 only) tSCKL tSCKHA SIOCLK : tsDI thDI DATAIN : tdDO DATAOUT : Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.8299-22/23 LC875G32A/24A/16A/08A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.8299-23/23