SANYO LV1117N

Ordering number : ENA1046
Bi-CMOS IC
LV1117N/NV
Surround Processor ICs for
Electronic Volume Control
Overview
The LV1117N/NV are sound processor ICs developed for use in TV sets.
They incorporate the surround processing functions including (AViSS), pseudo stereo function, (L+R) output, and the
major functional blocks of an electronic volume control IC.
Features
• Input function SW (4ch stereo inputs [L, R]).
• Line out (through output).
• Input gain control (−6dB, −4dB, 0dB, 4dB, 6dB: 5 positions).
• AViSS (ON/OFF/6-stage level control).
• Tone control (BASS: ±20dB, TREBLE: ±18dB [in 2dB steps]).
• Volume control (0dB to −14dB: 1dB step/−14dB to −80dB: 2dB steps/−∞=−82dB).
• Balance control.
• Through mode/Mute mode.
• Pseudo stereo function (ON/OFF/MONO).
• L+R output with LPF (Mute + 7-stage level control: 8 positions).
• I2C bus control.
• Parallel output ports (4pin).
* Initial gain of L+R AMP can be controlled by the resistance value of external resistor.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
22008 TI IM 20051207-S00008 No.A1046-1/18
LV1117N/1117NV
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VCC max
10.5
V
Allowable power dissipation 1
Pd max1
Ta ≤ 70°C, DIP
700
mW
Allowable power dissipation 2
Pd max2
Ta ≤ 70°C *, SSOP
700
mW
Operating temperature
Topr
-25 to +70
°C
Storage temperature
Tstg
-40 to +125
°C
Note *: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy board
Operating Condtions at Ta = 25°C
Parameter
Recommended supply voltage
Symbol
Conditions
Ratings
Unit
VCC
Operating supply voltage 1
VCC opg1
DIP
Operating supply voltage 2
VCC opg2
SSOP
9.0
V
5.0 to 10.0
V
5.0 to 9.0
V
Control data
“H” level voltage
VIH
2.0 to 5.5
V
“L” level voltage
VIL
0.0 to 1.0
V
μs
Pulse width
tφw
1.0
Hold time
thold
1.0
μs
Operating frequency
fopg
100
kHz
Electrical Characteristics at Ta = 25°C, VCC = 9.0V, fin = 1kHz, VIN = 300mVrms = 0dB, RL = 10kΩ
(Input=L/Rch-A, Output=L/R-VROUT)
Parameter
Quiescent current
Symbol
Conditions
Ratings
min
ICCO
typ
max
48
Unit
mA
Total through (Total through mode, Volume control: 0dB)
Voltage gain
VGT
Maximum output voltage
VOT
THD=1%
-1.6
-0.6
2.0
2.6
+0.6
dB
Vrms
Total harmonic distortion
THDT
DIN AUDIO
0.03
0.1
%
Output noise voltage
VNOT
DIN AUDIO
-93
-85
dBV
CTT
DIN AUDIO
Cross talk
85
93
-1.7
-0.7
1.5
2.0
dB
Matrix through (Matrix mode, Input gain: 0dB, Volume control: 0dB)
Voltage gain
VGF
Maximum output voltage
VOM
THD=1%
+0.7
dB
Vrms
Total harmonic distortion
THDM
DIN AUDIO
0.04
0.1
%
Output noise voltage
VNOM
DIN AUDIO
-92
-83
dBV
CTM
DIN AUDIO
Cross talk
85
91
dB
MONO mode (MONO mode, Input gain: 0dB, Volume control: 0dB)
Maximum output voltage
VOS
Total harmonic distortion
THDS
DIN AUDIO
THD=1%
1.5
0.04
2.0
0.5
Vrms
%
Output noise voltage
VNOS
DIN AUDIO
-92
-82
dBV
Surround (Surround mode-A, Input gain: 0dB, Volume control: 0dB)
Maximum output voltage
VOS
Total harmonic distortion
THDS
DIN AUDIO
THD=1%
1.5
0.2
2.0
0.5
Vrms
%
Output noise voltage
VNOS
DIN AUDIO
-90
-81
dBV
Pseudo stereo (Pseudo stereo mode, Input gain: 0dB, Volume control: 0dB)
Maximum output voltage
VOS
Total harmonic distortion
THDS
DIN AUDIO
THD=1%
1.5
0.07
2.0
0.5
Vrms
%
Output noise voltage
VNOS
DIN AUDIO
-90
-82
dBV
Continued on next page.
No.A1046-2/18
LV1117N/1117NV
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
max
Unit
Bass band EQ (Matrix through mode, Input gain: 0dB, Volume control: 0dB)
Control Range
GeqB
Step resolution
EstepB
Max. Boost/Cut
±17
±20
±23
dB
1.0
2.0
3.0
dB
±15
±18
±21
dB
1.0
2.0
3.0
dB
-2.3
-1.3
-0.3
2.0
2.5
Treble band EQ (Matrix through mode, Input gain: 0dB, Volume control: 0dB)
Control Range
GeqT
Step resolution
EstepT
Max. Boost/Cut
L+R output (Output=L+R-OUT, Step=0dB, L+R_Step=Step4)
Voltage gain
VGF
Maximum output voltage
VOF
Total harmonic distortion
THDF
DIN AUDIO
0.03
0.1
%
Output noise voltage
VNOF
DIN AUDIO
-99
-85
dBV
0.3
V
1.0
mA
THD=1%
dB
Vrms
Port Output (20/21/22/23pin)
Low level output voltage
VOL
Port output sink Current
IO
IO=1mA
Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the
output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or
input signal level.
Package Dimensions
unit : mm (typ)
3025C
[LV1117N]
22
1
21
0.25
13.8
42
15.24
37.7
(4.25)
0.51min
3.8 5.1max
0.95
(1.05)
1.78
0.48
SANYO : DIP42S(600mil)
No.A1046-3/18
LV1117N/1117NV
Package Dimensions
unit : mm (typ)
3277
[LV1117NV]
15.0
0.5
5.6
7.6
23
44
0.22
22
0.2
(1.5)
1.7max
0.65
0.1
1
(0.68)
SANYO : SSOP44(275mil)
No.A1046-4/18
2
Rch-A
1
GND
41
42
Rch-B
3
40
Lch-B
Rch-C
4
39
Lch-C
37
6
+
-
+
-
L Line
out
Rch-D R Line
out
5
38
Lch-D
7
8
ST-1
Stereo
DC
R-DC
35
ST-2
Pseud
DC
36
L-DC
10
LPFC R-TC1
9
Bypass
11
R-BC1
+
-
14
MUTE
MUTE
29
R-BC2 R-OUT R-VRIN
13
TOTAL
Bypass
12
Matrix
TONE CONT
(AViSS)
SURROUND
30
TOTAL
Bypass
Matrix
31
L-BC2 L-OUT L-VRIN
TONE CONT
32
L-BC1
ANALOG
33
L-TC1
Bypass
34
HPFC
+
Lch-A
+
AGND
15
+
-
L+R
16
27
L+R LPF
28
17
VREF
+
-
26
VSS
24
DATA
VCC
18
19
VDD
CONTROL
DATA
CONTROL
25
CLK
OUT2
20
23
OUT0
OUT3
21
22
OUT1
LV1117N/1117NV
Block Diagram [LV1117N]
No.A1046-5/18
2
Rch-A
1
GND
43
44
Rch-B
3
42
Lch-B
Rch-C
4
41
Lch-C
39
6
+
-
+
-
L Line
out
Rch-D R Line
out
5
40
Lch-D
7
8
ST-1
Stereo
DC
R-DC
37
ST-2
Pseud
DC
38
L-DC
10
LPFC R-TC1
9
Bypass
11
R-BC1
13
+
-
14
MUTE
MUTE
31
R-BC2 R-OUT R-VRIN
12
TOTAL
Bypass
Matrix
TONE CONT
(AViSS)
SURROUND
32
TOTAL
Bypass
Matrix
33
L-BC2 L-OUT L-VRIN
TONE CONT
34
L-BC1
ANALOG
35
L-TC1
Bypass
36
HPFC
+
Lch-A
+
AGND
15
+
-
L+R
16
29
L+R LPF
30
17
VREF
+
-
28
VSS
26
NC
VCC
18
NC
19
DATA
CONTROL
27
CONTROL
CLK
VDD
20
25
DATA
OUT2
21
24
OUT0
OUT3
22
23
OUT1
LV1117N/1117NV
Block Diagram [LV1117NV]
No.A1046-6/18
LV1117N/1117NV
I2C BUS Control Signal
tHIGH
tR
tF
SCL
tSU:STA
tHD:STA
tLOW
tHD:DAT
tSU:STO
tSU:DAT
tBUF
SDA
Figure1 I2C BUS Control Signal timing chart
I2C BUS register
1) The explanation of I2C Bus
I2C Bus (Inter IC Bus) is the bus system which the PHILIPS company developed.
It does controls such as the start, the stop by two control signals of SDA (Serial Data) and SCL (Serial Clock).
The output of each signal is open drain and forms out of wired OR.
S: Start condition
P: Stop condition
ACK: Acknowledge
Data is transmitted in the MSB first. 1 unit is composed of 8 bits and ACK is put back from the slave to confirm.
Slave IC reads data with rising edge of SCL. Master IC changes data by falling edge in SCL.
2) The control register
Table1 Slave Address
MSB
LSB
1
1
1
0
1
1
1
0
Note; LV1117N/NV are reception exclusive use. It depends and it uses LSB by the "0" fixation.
Table2 I2C Bus transmission
Sub Address
Function
Data
BINARY
HEX
D7
D6
Input control/Gain control
0000 0001
01
0
0
D5
D4
D3
D2
D1
Volume control
0000 0010
02
Channel
Output/Surround/MODE control
0000 0011
03
Tone control [Bass]
0000 0100
04
0
0
0
Bass
Tone control [TREBLE]
0000 0101
05
0
0
0
TREBLE
Output port control
0000 0110
06
0
0
0
Gain
D0
Input
Volume
L+R out gain
Surround
0
OUT3
MODE
OUT2
OUT1
OUT0
Table3 Input Selection
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
Mute
0
0
*
*
*
0
0
0
In A
0
0
*
*
*
0
0
1
0
0
*
*
*
0
1
0
In C
0
0
*
*
*
0
1
1
In D
0
0
*
*
*
1
0
0
In B
0
A6
0
A5
0
A4
0
A3
Data
0
A2
0
A1
0
A0
1
D0
No.A1046-7/18
LV1117N/1117NV
Table4 Gain control
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
D0
-6dB
0
0
0
1
1
*
*
*
-4dB
0
0
0
1
0
*
*
*
0dB
0
A6
0
A5
0
A4
0
A3
Data
0
A2
0
A1
0
A0
1
0
0
0
0
0
*
*
*
+4dB
0
0
1
1
0
*
*
*
+6dB
0
0
1
1
1
*
*
*
D7
D6
D5
D4
D3
D2
D1
D0
Table5 Mode control
Sub Address
A7
A6
A5
A4
A3
Data
A2
A1
A0
Total
*
*
*
*
*
*
0
0
Matrix
*
*
*
*
*
*
0
1
*
*
*
*
*
*
1
0
*
*
*
*
*
*
1
1
D0
Mono
0
0
0
0
0
0
1
1
Pseudo
Table6 Surround control
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
OFF
*
*
*
0
0
0
*
*
MODE-C
*
*
*
0
1
1
*
*
MODE-B
*
*
*
0
1
0
*
*
*
*
*
*
*
MODE-A
0
A6
0
A5
0
A4
0
A3
Data
0
A2
0
A1
1
A0
1
0
0
1
MODE-F
1
1
1
MODE-E
1
1
0
0
1
*
*
MODE-D
*
*
*
1
D7
D6
D5
D4
D3
D2
D1
D0
MUTE
0
0
0
*
*
*
*
*
Step1
0
0
1
*
*
*
*
*
Step2
0
1
0
*
*
*
*
*
Step3
0
1
1
*
*
*
*
*
Note; At the time of forced mono mode, there is not surround effect.
Note; Output gain = Step1 < Step7
Table7 L+R Output Gain control
Sub Address
A7
Step4
0
A6
0
A5
0
A4
0
A3
0
Data
A2
0
A1
1
A0
1
1
0
0
*
*
*
*
*
Step5
1
0
1
*
*
*
*
*
Step6
1
1
0
*
*
*
*
*
Step7
1
1
1
*
*
*
*
*
Note; Output gain = Step1 < Step7
No.A1046-8/18
LV1117N/1117NV
Table8 Tone control [Bass control]
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
D0
+20dB
0
0
0
0
1
0
1
0
+18dB
0
0
0
0
1
0
0
1
+16dB
0
0
0
0
1
0
0
0
+14dB
0
0
0
0
0
1
1
1
+12dB
0
0
0
0
0
1
1
0
+10dB
0
0
0
0
0
1
0
1
+8dB
0
0
0
0
0
1
0
0
+6dB
0
0
0
0
0
0
1
1
+4dB
0
0
0
0
0
0
1
0
+2dB
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
-2dB
0
0
0
1
0
0
0
1
-4dB
0
0
0
1
0
0
1
0
-6dB
0
0
0
1
0
0
1
1
-8dB
0
0
0
1
0
1
0
0
-10dB
0
0
0
1
0
1
0
1
-12dB
0
0
0
1
0
1
1
0
-14dB
0
0
0
1
0
1
1
1
-16dB
0
0
0
1
1
0
0
0
-18dB
0
0
0
1
1
0
0
1
-20dB
0
0
0
1
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
+18dB
0
0
0
0
1
0
0
1
+16dB
0
0
0
0
1
0
0
0
+14dB
0
0
0
0
0
1
1
1
+12dB
0
0
0
0
0
1
1
0
+10dB
0
0
0
0
0
1
0
1
+8dB
0
0
0
0
0
1
0
0
+6dB
0
0
0
0
0
0
1
1
+4dB
0
0
0
0
0
0
1
0
+2dB
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
-2dB
0
0
0
1
0
0
0
1
-4dB
0
0
0
1
0
0
1
0
-6dB
0
0
0
1
0
0
1
1
0dB
0
A6
0
A5
0
A4
0
A3
Data
0
A2
1
A1
0
A0
0
Table9 Tone control [TREBLE control]
Sub Address
A7
0dB
0
A6
0
A5
0
A4
0
A3
0
Data
A2
1
A1
0
A0
1
-8dB
0
0
0
1
0
1
0
0
-10dB
0
0
0
1
0
1
0
1
-12dB
0
0
0
1
0
1
1
0
-14dB
0
0
0
1
0
1
1
1
-16dB
0
0
0
1
1
0
0
0
-18dB
0
0
0
1
1
0
0
1
No.A1046-9/18
LV1117N/1117NV
Table10 Volume control
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
0dB
*
*
0
0
0
0
0
0
-1dB
*
*
0
0
0
0
0
1
-2dB
*
*
0
0
0
0
1
0
-3dB
*
*
0
0
0
0
1
1
-4dB
*
*
0
0
0
1
0
0
-5dB
*
*
0
0
0
1
0
1
-6dB
*
*
0
0
0
1
1
0
-7dB
*
*
0
0
0
1
1
1
-8dB
*
*
0
0
1
0
0
0
-9dB
*
*
0
0
1
0
0
1
-10dB
*
*
0
0
1
0
1
0
-11dB
*
*
0
0
1
0
1
1
-12dB
*
*
0
0
1
1
0
0
-13dB
*
*
0
0
1
1
0
1
-14dB
*
*
0
0
1
1
1
0
-16dB
*
*
0
0
1
1
1
1
-18dB
*
*
0
1
0
0
0
0
-20dB
*
*
0
1
0
0
0
1
-22dB
*
*
0
1
0
0
1
0
-24dB
*
*
0
1
0
0
1
1
-26dB
*
*
0
1
0
1
0
0
-28dB
*
*
0
1
0
1
0
1
-30dB
*
*
0
1
0
1
1
0
-32dB
*
*
0
1
0
1
1
1
-34dB
0
A6
0
A5
0
A4
0
A3
Data
0
A2
0
A1
1
A0
0
D0
*
*
0
1
1
0
0
0
-36dB
*
*
0
1
1
0
0
1
-38dB
*
*
0
1
1
0
1
0
-40dB
*
*
0
1
1
0
1
1
-42dB
*
*
0
1
1
1
0
0
-44dB
*
*
0
1
1
1
0
1
-46dB
*
*
0
1
1
1
1
0
-48dB
*
*
0
1
1
1
1
1
-50dB
*
*
1
0
0
0
0
0
-52dB
*
*
1
0
0
0
0
1
-54dB
*
*
1
0
0
0
1
0
-56dB
*
*
1
0
0
0
1
1
-58dB
*
*
1
0
0
1
0
0
-60dB
*
*
1
0
0
1
0
1
-62dB
*
*
1
0
0
1
1
0
-64dB
*
*
1
0
0
1
1
1
-66dB
*
*
1
0
1
0
0
0
-68dB
*
*
1
0
1
0
0
1
-70dB
*
*
1
0
1
0
1
0
-72dB
*
*
1
0
1
0
1
1
-74dB
*
*
1
0
1
1
0
0
-76dB
*
*
1
0
1
1
0
1
-78dB
*
*
1
0
1
1
1
0
-80dB
*
*
1
0
1
1
1
1
-∞dB
*
*
1
1
0
0
0
0
No.A1046-10/18
LV1117N/1117NV
Table11 Volume channel control
Sub Address
A7
A6
A5
A4
A3
Data
A2
A1
A0
L-ch
0
R-ch
0
0
0
0
0
1
0
L/R
D7
D6
D5
D4
D3
D2
D1
0
1
*
*
*
*
*
D0
*
1
0
*
*
*
*
*
*
1
1
*
*
*
*
*
*
D0
Table12 Output port control
Sub Address
A7
On (sink)
Off (open)
0
A6
0
A5
0
A4
A3
0
0
Data
A2
A1
1
1
A0
0
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Pin Functions [LV1117N]
Pin No
1
Function
GND
2
INPUT-A(R)
41
INPUT-A(L)
3
INPUT-B(R)
40
INPUT-B(L)
4
INPUT-C(R)
39
INPUT-C(L)
5
INPUT-D(R)
38
INPUT-D(L)
6
LINE-OUT(R)
Voltage
Remarks
Internal equivalent circuit
0
VREF
Input Impedance
ri=50kΩ
VREF
Function SW Output
ro=700Ω
37
LINE-OUT(L)
7
DC Cut(R)
VREF
DC offset cancellation capacitor
connection pin
36
DC Cut(L)
8
ST-1
VREF
Pseudo stereo phase shift capacitor
connection pin
35
ST-2
9
AViSS LPF
VREF
Capacitor connection pin for surround low
pass filter
Continued on next page.
No.A1046-11/18
LV1117N/1117NV
Continued from preceding page.
Pin No
10
Function
TREBLE(R)
Voltage
VREF
Remarks
Internal equivalent circuit
Capacitor connection pin for configuring
treble filter
33
TREBLE(L)
11
BASS-1(R)
VREF
Bass band filter configuration capacitor
and resistor connection pins
32
BASS-1(L)
12
BASS-2(R)
31
BASS-2(L)
13
OUT(R)
VREF
Output Impedance
ro=100Ω
30
OUT(L)
14
EVR-IN(R)
VREF
Input Impedance
ri=50kΩ
29
EVR-IN(L)
15
EVR-OUT(R)
VREF
Output Impedance
ro=100Ω
28
EVR-OUT(L)
16
L+R OUT
VREF
Output Impedance
ro=10kΩ
17
VREF
0.5VCC
Reference voltage
VCC
Continued on next page.
No.A1046-12/18
LV1117N/1117NV
Continued from preceding page.
Pin No
Function
Voltage
18
VCC
VCC
19
VDD
VDD
20
Output 2
21
Output 3
22
Output 1
Remarks
Internal equivalent circuit
Nch open drain port output
23
Output 0
24
I2C-DATA
25
I2C-CLK
26
VSS
27
L+R LPF
VREF
34
AViSS HPF
VREF
42
ANALOG GND
VREF
I2C control data input
0
Internal resistor
No.A1046-13/18
LV1117N/1117NV
Treble / Bass Band Block Equivalent Circuit Diagram
From L-Input Block
SW3
+
-
SW3
+
-
SW2
To L-OUT Block
SW2
SW1
SW4
SW1
SW4
0dB
±2dB
R1=10.633kΩ
±4dB
R2=8.446kΩ
±6dB
R3=6.709kΩ
±8dB
R4=5.329kΩ
±10dB
R5=4.233kΩ
±12dB
R6=3.363kΩ
±14dB
R7=2.671kΩ
±16dB
R8=2.122kΩ
±18dB
R9=1.665kΩ
0dB
Total=51.7kΩ
R10=6.510kΩ
±2dB
R1=15.220kΩ
±4dB
R2=12.089kΩ
±6dB
R3=9.603kΩ
±8dB
R4=7.628kΩ
±10dB
R5=6.059kΩ
±12dB
R6=4.813kΩ
±14dB
R7=3.823kΩ
±16dB
R8=3.037kΩ
±18dB
R9=2.412kΩ
±20dB
R10=1.916kΩ
R12=100Ω
L-TC1
L-BC2
Total=66.7kΩ
R11=100Ω
L-BC1
Same for Right channel
During boost, SW1 and SW3 are ON, during cut, SW2 and SW4 are ON, when 0dB, 0dBSW and SW2 and SW3 are ON.
L+R Block Equivalent Circuit Diagram
From L-VROUT
+
-
R1=50kΩ
Mute
+
-
R4=10kΩ
L+R
R2=50kΩ
From R-VROUT
+
-
Step1
R3=50kΩ
L+R_LPF
Step2
R5=10.284kΩ
Step3
R6=8.169kΩ
Step4
R7=6.489kΩ
Step5
R8=5.154kΩ
Step6
R9=4.094kΩ
Step7
R10=3.252kΩ
Total=50kΩ
R11=12.559kΩ
AGND
ILV00257
No.A1046-14/18
LV1117N/1117NV
Tone Circuit Constant Calculation Examples
Treble Band Circuit: The shelving characteristics can be obtained for the treble band.
The equivalent circuit and calculation formula during boost are indicated below.
• Calculation example 1
Specification Set frequency: f = 10000Hz
Gain during maximum boost: G+18dB = 17.5dB
Let us use R1 = 6.51kΩ and R2 = 45.19kΩ
The above constants are inserted in the following formula
G = 20 × Log10 1+
+
R2
R2
R1
R12+(1/ ω C)2
C
1
C=
2
R2
2πf
-R12
10G/20-1
1
=
45190
2π24000
7.50 - 1
≈2700 (pF)
2
2
- 6510
Bass Band Circuit: The equivalent circuit and the formula for calculating the external RC with a mean frequency of
100Hz are shown below.
• Base band equivalent circuit diagram
+
-
• Calculation example 1
specification
Mean frequency: f0 = 100Hz
Gain during maximum boost: G+20dB = 20dB
Let us use R1 = 0kΩ and R2 = 66.7kΩ, and C1 = C2 = C.
R1
R2
C1
C2
We obtain R2 from G = 20dB
R2
G = 20 × Log10 1+
R3 =
R2
2 (10
R3
2R3
G+20dB/20
- 1)
=
66700
2 (10 - 1)
≈3.6kΩ
We obtain C from mean frequency f0 = 100Hz
f0 =
C=
2π
1
(R3R2C1C2)
1
2πf0
R3R2
=
2π × 100
1
66700 × 3600
≈0.1μF
We obtain Q
Q=
R3R2
2R3
×
1
R3R2
≈2.15
Note item when using
(1) When turning on the power, the setting inside is unsettled.
Before setting control data, it does a mute.
(2) To prevent the digital noise of the high frequency influence a terminal. (SCL, SDA)
It can be protected by a signal line in the ground pattern or by the shielding cable.
(3) To prevent the noise in changing a mode, please set the mute ON.
No.A1046-15/18
LV1117N/1117NV
Volume Control Step Characteristics
Vcc = 9.0V
Vin = 0dBV
Input = VRIN
Output = VROUT
-20
-30
Vcc = 9.0V
Vin = -10dBV
Input = L/R Ch-A
Output = L/R OUT
8
6
Gain Attenetion (dB)
-10
Volume attenuation (dB)
Gain - Frequency
10
0
-40
-50
-60
-70
4
2
0
-2
-4
-6
-80
-8
-90
-90
-80
-70
-60
-50
-40
-30
-20
-10
-10
0
-6
Step Setting (dB)
-15
-20
-25
-30
-35
-10
-15
-20
4
6
-25
-30
-35
-40
-40
-45
-45
10
100
1000
10000
10
100000
100
Frequency (Hz)
-5
10000
100000
L+R Frequency Characteristics
10
Vcc = 9.0V
Vin = -20dBV
Input = L/R Ch-A
Output = L/R OUT
-15
-20
Vcc = 9.0V
Vin = 0dBV
Input = VRIN
Output = VROUT
0
-10
Gain (dBV)
-10
1000
Frequency (Hz)
Surround Mode Frequency Characteristics
Gain (dBV)
0
2
Gain Step (dB)
Vcc = 9.0V
Vin = -20dBV
C = 2700pF
Input = L/R Ch-A
Output = L/R OUT
0
-5
Gain (dBV)
Gain (dBV)
5
Vcc = 9.0V
Vin = -20dBV
C = 0.1uF
R = 3.6kΩ
Input = L/R Ch-A
Output = L/R OUT
-5
-10
-2
Treble Band Frequency Characteristics
Bass Band Frequency Characteristics
5
0
-4
-20
-30
-40
-50
-25
-60
10
100
1000
10000
100000
10
100
Pseud Lch vs Rch Phese Shift vs Frequency
Characteristics
100000
100.0
Vomax (dBV)
Phase Shift (DEG)
10000
Vcc - Vomax Characteristics (1)
Vcc = 9.0V
Vin = -20dBV
Input = L/R Ch-A
Output = L/R OUT
180
1000
Frequency (Hz)
Frequency (Hz)
90
Total
10.0
Matrix
1.0
THD = 1%
Input = L/R Ch-A
Output = L/R OUT
0.1
0
10
100
1000
Frequency (Hz)
10000
100000
5
6
7
8
Vcc (V)
9
10
No.A1046-16/18
LV1117N/1117NV
THD - Vin characteristics
THD - Vin characteristics (Surround)
Total harmonic distotion (%)
Vcc=9.0V
fin=1kHz
0.1
Total
0.01
Matrix
Mono
Psudo
0.001
-40
-30
-20
-10
Total harmonic distotion (%)
1
1
Vcc=9.0V
fin=1kHz
Mode_A
0.1
0.01
0.001
-40
0
-30
-20
Vin (dBV)
THD - Frequency Characteistics
Vcc=9.0V
Vin=-10dBV
0.1
Total
Matrix
Mono
Psudo
Surround
1000
0
THD - Supply Voltage Characteristics
10000
1
Total harmonic distotion (%)
Total harmonic distotion (%)
1
0.01
100
-10
Vin (dBV)
Total
0.1
Matrix
Mono
Psudo
Surround
0.01
4.0
100000
Vin=-10dBV
fin=1kHz
5.0
6.0
7.0
8.0
9.0
10.0
11.0
Supply Voltage (V)
Frequency (Hz)
VCC - VREF
VCC - VDD
3.3
6.0
5.5
3.1
4.5
VDD (V)
VREF (V)
5.0
4.0
3.5
3.0
2.9
2.7
2.5
2.0
1.5
4.0
5.0
6.0
7.0
8.0
9.0
10.0
2.5
4.0
11.0
5.0
6.0
VCC (V)
60.0
5.0
55.0
4.5
50.0
ICCO (mA)
AGND (V)
65.0
5.5
4.0
3.5
3.0
25.0
VCC (V)
9.0
10.0
11.0
35.0
30.0
8.0
11.0
40.0
2.0
7.0
10.0
45.0
2.5
6.0
9.0
VCC - ICCO
6.0
5.0
8.0
VCC (V)
VCC - AGND
1.5
4.0
7.0
9.0
10.0
11.0
20.0
4.0
5.0
6.0
7.0
8.0
VCC (V)
No.A1046-17/18
LV1117N/1117NV
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of February, 2008. Specifications and information herein are subject
to change without notice.
PS No.A1046-18/18