Ordering number : ENA1927 CMOS IC LV51139T 2-Cell Lithium-Ion Secondary Battery Protection IC Overview The LV51139T is a protection IC for 2-cell lithium-ion secondary batteries. Features • Monitoring function for each cell: Detects overcharge and over-discharge conditions and controls the charging and discharging operation of each cell. Over-charge detection accuracy ±25mV Over-discharge detection accuracy ±100mV The hysteresis of over-discharge detection voltage is made small by sensing the connection of a load after overcharging has been detected. Detects over-currents, load shorting, and excessively high voltage of a charger . Normal operation mode typ. 6.0μA Stand by mode max. 0.2μA Charging is enabled even when the cell voltage is 0V by giving a potential difference between the VDD pin and V- pin. • High detection voltage accuracy: • Hysteresis cancel function: • Discharge current monitoring function: • Low current consumption: • 0V cell charging function: Absolute Maximum Ratings at Ta = 25°C Parameter Power supply voltage Symbol Conditions VDD V- Input voltage Ratings Unit -0.3 to +12 V VDD-28 to VDD+0.3 V Charger minus voltage Output voltage Cout pin voltage Vcout VDD-28 to VDD+0.3 V Dout pin voltage Vdout VSS-0.3 to VDD+0.3 V Allowable power dissipation Pd max Independent IC 170 mW Operating ambient temperature Topr -30 to +85 °C Storage temperature Tstg -40 to +125 °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 21611 SY 20110204-S00003 No.A1927-1/7 LV51139T Electrical Characteristics at Ta = 25°C, unless especially specified. Parameter Symbol Conditions Operation input voltage Vcell Between VDD and VSS 0V cell charging minimum operation voltage Vmin Between VDD-VSS =0 and VDD-V- Over-charge detection voltage Vd1 Ratings min typ Unit max 1.5 10 V 1.5 V 4.285 4.310 4.335 V Ta=0°C to 45°C *2 4.275 4.310 4.345 V Ta=0°C to 60°C *2 4.270 4.310 4.350 V VM≤Vd3 4.060 4.110 4.160 V VM>Vd3 4.210 4.320 V Over-charge reset voltage Vh1 Over-charge detection delay time td1 VDD-Vc=3.5V→4.5V, Vc-VSS=3.5V 0.5 1.0 1.5 s Over-charge reset delay time tr1 VDD-Vc=4.5V→3.5V, Vc-VSS=3.5V 20.0 40.0 60.0 ms 2.2 2.3 2.4 V Over-discharge detection voltage Vd2 Over-discharge reset hysteresis voltage Vh2 10.0 20.0 40.0 mV Over-discharge detection delay time td2 VDD-Vc=3.5V→2.2V, Vc-VSS=3.5V 50 100 150 ms Over-discharge reset delay time tr2 VDD-Vc=2.2V→3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 ms Over-current detection voltage Vd3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.11 0.13 0.15 V Over-current reset hysteresis voltage Vh3 VDD-Vc=3.5V, Vc-VSS=3.5V 5.0 10.0 20.0 mV Over-current detection delay time td3 VDD-Vc=3.5V, Vc-VSS=3.5V 10.0 20.0 30.0 ms ms Over-current reset delay time tr3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 Short circuit detection voltage Vd4 VDD-Vc=3.5V, Vc-VSS=3.5V 1.0 1.3 1.6 V Short circuit detection delay time td4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.2 0.5 0.8 ms Excessive charger detection voltage Vd5 VDD-Vc=3.5V, Vc-VSS=3.5V Voltage between (V-)-VSS VDD-Vc=3.5V, Vc-VSS=3.5V -0.275 -0.200 -0.125 10 30 50 VDD×0.4 VDD×0.5 VDD×0.6 V Excessive charger return hysteresis voltage Vh5 Standby reset voltage Vstb VDD-Vc=2.0V, Vc-VSS=2.0V Voltage between (V-)-VSS Excessive charger detection delay time td5 VDD-Vc=3.5V, Vc-VSS=3.5V *1 0.5 1.5 3.0 ms Excessive charger return delay time tr5 VDD-Vc=3.5V, Vc-VSS=3.5V 0.5 1.5 3.0 ms Reset resistance (connected to VDD) RDD 100 200 400 kΩ Reset resistance (connected to VSS) RSS 5 10 18 kΩ Cout Nch ON voltage VOL1 0.5 V Cout Pch ON voltage VOH1 IOL=50μA, VDD-Vc=3.9V, Vc-VSS=3.9V Dout Nch ON voltage VOL2 IOL=50μA, VDD-Vc=Vd2(min), IOL=50μA, VDD-Vc=4.4V, Vc-VSS=4.4V VDD-0.5 mV V V 0.5 V Vc-VSS=Vd2(min) Dout Pch ON voltage VOH2 IOL=50μA, VDD-Vc=3.9V, Vc-VSS=3.9V VDD-0.5 V Vc input current Ivc VDD-Vc=3.5V, Vc-VSS=3.5V 0.0 1.0 μA Current drain IDD VDD-Vc=3.5V, Vc-VSS=3.5V 6.0 13.0 μA Standby current Istb VDD-Vc=2.2V, Vc-VSS=3.5V 0.2 μA Vtest VDD-Vc=3.5V, Vc-VSS=3.5V VDD×0.6 V T pin input ON-voltage VDD×0.4 VDD×0.5 *1: Upon connecting to charger upon over-discharge, the delay time after recovery from over-discharge. *2: The Ratings of the table above is a design targets and are not measured. No.A1927-2/7 LV51139T Package Dimensions unit : mm (typ) 3245B Pd max -- Ta Allowable power dissipation, Pd max -- mW 200 3.0 0.5 3.0 4.9 8 1 (0.53) 2 0.65 0.125 1.1MAX (0.85) 0.25 Independent IC 170 150 100 68 50 0 -30 -20 0 20 40 60 80 100 0.08 Ambient temperature, Ta -- °C SANYO : MSOP8(150mil) Pin Assignment Dout T 8 7 1 2 VDD Cout Pin Functions Pin No. Vc Sense 6 3 V- 5 4 VSS Top view Symbol Description 1 VDD 2 Cout VDD pin Overcharge detection output pin 3 V- Charger minus voltage input pin 4 VSS VSS pin 5 Sense Sense pin 6 Vc Intermediate voltage input pin 7 T Pin to shorten detection time (“H”: Short-circuit mode, “L or OPEN”: Normal mode) 8 Dout + - td5,tr5 Overdischarge detection output pin Block Diagram Sence 5 VDD 1 Level shift + + - Vc 6 2 Cout td1,tr1 Delay control logic + - td2,tr2 8 Dout + + - td3,tr3 + - 4 VSS 3 V- td4 7 T No.A1927-3/7 LV51139T Functional Description Over-charge detection If either of the cell voltage is equal to or more than the over-charge detection voltage, stop further charging by turning “L” the Cout pin and turning off external Nch MOS FET after the over-charge detection delay time. This delay time is set by the internal counter. The over-charge detection comparator has the hysteresis function. Note that this hysteresis can be cancelled by connecting the load after detection of over-charge detection. and it becomes small to hysteresis peculiar to a comparator. Note that short-circuit can be detected. Over-charge return If both cell voltages become equal to or less than the over-charge release voltage（VM≦Vd3） when charger is connected, or if it become equal to or less than the over-charge release voltage（VM>Vd3） when load is connected, the Cout pin returns to “H” after the over-charge release delay time set by the internal counter. When load is connected and either cell or both cell voltages are equal to or more than the over-charge release voltage ([VM>Vd3, the Cout pin does not return to “H”. But the load current flows through the parasitic diode of external Nch MOS FET on Cout, consequently each cell voltage becomes equal to or less than over-charge release voltage （VM>Vd3）, the Cout pin returns to “H.” after the over-charge release delay time. However, excessive voltage charger is connected as mentioned below, Cout pin does not return to “H” because excessive charger detection starts after over-charge release operation. Over-discharge detection When either cell voltage is equal to or less than over-discharge voltage, the IC stops further discharging by turning the Dout pin “L” and turning off external Nch MOS FET after the over-charge detection delay time. The IC goes into stand-by mode after detecting over-discharge and its consumption current is kept at about 0A. After over-discharge detection, the V- pin will be connected to VDD pin via internal resistor (typ 200kΩ). Over-discharge release Release from over-discharge is made by only connecting charger. If the V- pin voltage becomes equal to or lower than the stand-by release voltage by connecting charger after detecting over-discharge, The IC is released from the stand-by state to start cell voltage monitoring. If both cell voltages become equal to or more than the over-discharge detection voltage by charging, the Dout pin returns to “H” after the over-discharge release delay time set by the internal counter. Over-current detection When excessive current flows through the battery, the V- pin voltage rises by the ON resister of external MOS FET and becomes equal to or more than the over-current detection voltage, the Dout pin turns to “L” after the over-current detection delay time and the external Nch MOS FET is turned off to prevent excessive current in the circuit. The detection delay time is set by the internal counter. After detection, the V- pin will be connected to VSS via internal resistor (typ 10kΩ). It will not go into stand-by mode after detecting over-current. Short circuit detection If greater discharging current flows through the battery and the V- pin voltage becomes equal to or more than the short-circuit detection voltage, it will go into short-circuit detection state after the short circuit delay time shorter than the over-current detection delay time. When short-circuit is detected, just like the time of over-current detection, the Dout pin turns to “L” and external Nch MOS FET is turned off to prevent high current in the circuit. The V- pin will be connected to VSS after detection via internal resistor (typ 10kΩ). It will not go into stand-by mode after detecting short circuit. Over-current/short-detection return After detecting over-current or short circuit, the return resistor (typ.10kMΩ) between V- pin and VSS pin becomes effective and if the resistor is opened the V- pin voltage will be pulled by the VSS pin voltage. Thereafter, the IC will return from the over-current/short-circuit detection state when the V- pin voltage becomes equal to or below the overcurrent detection voltage and the Dout pin returns to “H” after over-current return delay time set by the internal counter. No.A1927-4/7 LV51139T Excessive charger detection/release If the voltage between V- pin and VSS pin becomes equal to or less than the excessive charger detection voltage by connecting a charger, no charging can be made by turning the Cout pin “L” after delay time and turning off the external Nch MOS FET. If that voltage returns to equal to or more than the excessive charger detection voltage during detection delay time, the excessive charger detection will be stopped. If the voltage between V- pin and VSS pin becomes equal to or more than the excessive charger detection voltage after excessive charger detection, the Cout returns to “H” after delay time. The detection/return delay time is set internally. If Dout pin is “L”, charging will be made through the parasitic diode of external Nch FET on Dout pin. In that case, the voltage between V- pin and VSS pin is nearly -Vf which is less than the over-charger detection voltage, therefore no excessive charger detection will be made during over-discharge, over-current and short-circuit detection. Furthermore, if excessive voltage charger is connected to the over-discharged battery, no excessive charger detection is made while the Dout pin is “L”. But the battery is continued charging through the parasitic diode. If the battery voltage rises to the over-discharge detection voltage and the voltage between V- pin and VSS pin remains equal to or less than the excessive charger detection voltage, the delay operation will be started after Dout pin turns to “H”. 0V cell charging operation If voltage between VDD and V becomes equal to or more than the 0V cell charging lowest operation voltage when the cell voltage is 0V, the Cout pin turns to “H” and charging is enabled. Shorten the test time By turning T pin to the VDD, the delay times set by the internal counter can be cut. If T pin is “open”, ”L” the delay times are normal. Delay time not set by the counter just like as short circuit detection delay cannot be controlled by this pin. By the substrate layout, the power-supply voltage is lowered due to an excessive current at the load short. Therefore, we recommend that the T pin is connected to the VSS pin because the problem that this IC enters a standby mode might be caused. Operation in case of detection overlap Operation in case of detection overlap Overlap state State after detection When, during over- Over-discharge Over-charge detection is preferred. If over- When over-charge detection is made first, V- is charge detection, detection is made, discharge state continues even after over- released. When over-discharge is detected charge detection, over-discharge detection is after over-charge detection, the standby state is not effectuated. Note that V- is connected to resumed. VDD via 200kΩ. Over-current (*1) Both detections’ can be made in parallel. (*2) When over-current is detected first, V- is detection is made, Over-charge detection continues even when the connected to VSS via 10kΩ. When over-charge detection is made first, V- is released. over-current state occurs. If the over-charge state occurs first, over-current detection is interrupted. During over-discharge Over-charge detection Over-discharge detection is interrupted and The standby state is not effectuated when over- detection, is made, over-charge detection is preferred. When over- discharge detection is made after over-charge detection. Note that V- is connected to VDD via 200kΩ. discharge state continues even after overcharge detection, over-discharge detection is resumed. Over-current (*3) Both detections can be made in parallel. (*4) If over-current state is made first, V- will be detection is made, Over-discharge detection continues even when connected to VSS via 10kΩ. If over-discharge the over-current state is effectuated first. Over- detection is made next, V- will be disconnected current detection is interrupted when the overdischarge state is effectuated first, from VSS and connected to VDD via 200kΩ to get into stand-by mode. If over-discharge state (*1) 200kΩ to get into stand-by mode. (*2) (*3) (*4) is made first, V- will be connected to VDD via When, during overcurrent detection, Over-charge detection is made, Over-discharge detection is made, (Note) Short-circuit detection can be made independently. Excessive charger detection cannot be made during over-discharge, over-current and short-circuit detection. And its delay time starts after the Dout pin returns to “H”. No.A1927-5/7 LV51139T Timing Chart [Cout Output System] Hysteresis cancellation by load connection Charger connection Load connection Load Charger connection connection Charger connection Excessive charger connection Load connection Vd1 Vr1 The charge return is decided by the voltage of the charger in the charger connection VDD Vd2 VDD Discharging via FET parasite Di. Vd4 V- Discharging via FET parasite Di. Vd3 VSS Vd5 VDD td1 Cout tr1 td1 td5 tr1 tr5 VOver-charge detection state Over-charge detection state State of excessive charger detection [Dout Output System] Load connection Charger connection Load connection Load connection Over-current occurrence Load connection Excessive charger connection Load short-circuit occurrence Vd1 Vr1 VDD Vd2 To standby To standby VDD Vd4 V- Vd3 VSS Vd5 Discharging via FET parasite Di. VDD Dout td2 tr2 td3 tr3 td4 tr3 td2 td2 VSS Over-charge detection state Over-charge detection state Short-circuit detection state VDD Cout V- The excessive charger detection when the over-electrical discharge battery is charged operates after the over-electrical discharge returns. td5 No.A1927-6/7 LV51139T Application Circuit Example + R4 R1 C1 R2 C2 VDD Sense C3 T Vc VSS LV51139T V- VSS Dout Cout Components Recommended value max unit R1, R2 100 500 Ω R3 2k 4k Ω R4 100 1k Ω C1, C2, C3 0.1μ 1μ F R3 * These numbers don't mean to guarantee the characteristic of the IC. * In addition to the components in the upper diagram, it is necessary to insert a capacitor with enough capacity between VDD and VSS of the IC as near as possible to stabilize the power supply voltage to the IC. * It is advisable to connect the T pin with the VSS pin. There is no problem even if the T pin is left open. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2011. Specifications and information herein are subject to change without notice. PS No.A1927-7/7