Ordering number : EN*A1693A Bi-CMOS IC LV5233H 24ch LED Driver Overview The LV5233H is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output 24-stage shift register that features a CMOS structure based on Bi-CMOS process technology. The LV5233H also contains an n-channel CMOS construction high-withstand-voltage, large-current drive 24-stage parallel output driver. The protection circuit of the output malfunction is built into. Features • Serial input and serial or parallel output • Enable input for output control • Serial output enables cascade connection • Low supply current (0.45mA typ. during standby ICC≤0.6mA) • Serial input/output levels compatible with typical CMOS devices • High-withstand-voltage LED driver with open drain output High withstand voltage (VDS < 42V) High-current drive (IO max = 100mA) • Operating temperature range Ta = -25 to 75°C • Output malfunction protection circuit Reset input pin Thermal protection circuit VCC decrease voltage confirmation Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max SVCC Output voltage VO max LEDO1 to LEDO24 off Output current IO max Allowable power dissipation Pd max Operating temperature Topr -25 to +75 °C Storage temperature Tstg -40 to +125 °C Ta ≤ 25°C * 6 V 42 V 100 mA 1750 mW * Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board. 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O0610 SY/33110 SY No.A1693-1/8 LV5233H Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended supply voltage VCC SVCC 5.0 Operating supply voltage range VCC op SVCC 3.0 to 5.5 V Output applied voltage VO 42 V Output current IO 100 mA Duty = 45% to 55% V Electrical Characteristics at Ta = 25°C, VCC = 5.0V Parameter Symbol Ratings Conditions min Quiescent current drain ICC1 LEDO driver off (standby) LEDO output on resistance Ron IO = 30mA OFF leak current Ileak VO = 42V Driver output malfunction Vt Unit typ max 0.45 0.6 mA Ω 3 2.58 0 10 μA 2.70 2.82 V prevention voltage Control circuit block H level 1 VINH1 Input H level VCC × 0.8 L level 1 VINL1 Input L level 0 H level 2 VOUTH1 SOUT IO = -1mA L level 2 VOUTL1 SOUT IO = 1mA V VCC × 0.2 V VCC -0.3 V 0 0.3 V Package Dimensions unit : mm (typ) 3235A Pd max -- Ta 2.0 10.5 7.9 (4.9) 36 1 0.25 (0.5) 2.0 0.3 (2.25) 0.8 Specified board : 114.3 × 76.1 × 1.6mm3 glass epoxy Allowable power dissipation, Pd max -- W 0.65 17.8 (6.2) 2.7 1.5 1.0 0.87 0.5 2.45max 0 --25 0 25 50 75 0.1 Ambient temperature, Ta -- C SANYO : HSOP36(375mil) PGND4 LEDO22 LEDO23 LEDO24 SCK SGND LEDO3 LEDO2 LEDO1 SDATAIN XRESET 9 19 PGND1 8 20 LEDO21 LEDO18 7 21 LEDO4 LEDO17 6 22 LEDO20 LEDO16 5 23 LEDO5 PGND3 4 24 LEDO19 LEDO15 3 25 LEDO6 LEDO14 2 26 Heat sink &GND LEDO13 1 27 Heat sink &GND LATCH LEDO7 28 LEDO8 29 LEDO9 30 PGND2 31 LEDO10 32 LEDO11 33 LEDO12 34 SOUT 35 SVCC 36 XEN Pin Assignment 10 11 12 13 14 15 16 17 18 Top view No.A1693-2/8 100 LV5233H Pin Descriptions Pin No. 1 Pin name I/O SVCC Description Power supply 2 SOUT O shift register output (final-stage shift register) 3 LEDO12 O LEDO12 Latch output (LEDO12 of shift register) 4 LEDO11 O LEDO11 Latch output (LEDO11 of shift register) 5 LEDO10 O 6 PGND2 7 LEDO9 O LEDO9 Latch output (LEDO9 of shift register) 8 LEDO8 O LEDO8 Latch output (LEDO8 of shift register) 9 LEDO7 O LEDO7 Latch output (LEDO7 of shift register) 10 LEDO6 O LEDO6 Latch output (LEDO6 of shift register) 11 LEDO5 O LEDO5 Latch output (LEDO5 of shift register) 12 LEDO4 O LEDO4 Latch output (LEDO4 of shift register) 13 PGND1 14 LEDO3 O LEDO3 Latch output (LEDO3 of shift register) 15 LEDO2 O LEDO2 Latch output (LEDO2 of shift register) 16 LEDO1 O LEDO1 Latch output (LEDO1 of shift register) 17 SDATAIN I Serial Input 18 XRESET I Reset input (shift register and latch) 19 SGND 20 SCK I Clock input (for shift register) 21 LEDO24 O LEDO24 Latch output (LEDO24 of shift register) 22 LEDO23 O LEDO23 Latch output (LEDO23 of shift register) 23 LEDO22 O 24 PGND4 25 LEDO21 O LEDO21 Latch output (LEDO21 of shift register) 26 LEDO20 O LEDO20 Latch output (LEDO20 of shift register) 27 LEDO19 O LEDO19 Latch output (LEDO19 of shift register) 28 LEDO18 O LEDO18 Latch output (LEDO18 of shift register) 29 LEDO17 O LEDO17 Latch output (LEDO17 of shift register) 30 LEDO16 O LEDO16 Latch output (LEDO16 of shift register) 31 PGND3 32 LEDO15 O LEDO15 Latch output (LEDO15 of shift register) 33 LEDO14 O LEDO14 Latch output (LEDO14 of shift register) 34 LEDO13 O LEDO13 Latch output (LEDO13 of shift register) 35 LATCH I LEDO10 Latch output (LEDO10 of shift register) GND Heat sink GND GND LEDO22 Latch output (LEDO22 of shift register) GND Heat sink GND Latch input When the latch input is held low, the LED0 output status is retained. When a high-level is input, the LED0 outputs change when the status of the shift register changes. 36 XEN I Enable inputs (LEDO1 to LEDO24) When a high-level is input, all the LED0 outputs are turned off. When a low-level is input, the shift register data is output to LED0. No.A1693-3/8 LV5233H Block Diagram SCK SDATAIN LATCH XEN SVCC SVCC_protection XRESET LEDO1 D Q C Q R D Q C Q R LEDO2 D Q C Q R D Q C Q R D Q C Q R D Q C Q R LEDO3 LEDO4 LEDO21 LEDO22 D Q C Q R D Q C Q R LEDO23 D Q C Q R D Q C Q R LEDO24 D Q C Q R D Q C Q R D Q C Q R SOUT PGND1 PGND3 SGND PGND2 PGND4 Function The LV5233H consists of 1) an 24-stage D-type flip-flop and 2) an 24-stage D-type flip-flop connected to the output of 1). When data is supplied to the serial data input (SDATAIN) and the clock pulse is supplied to the clock input (SCK), the serial data input signal is input to the internal shift register and the data already in the shift register shifted sequentially when the clock changes from low to high. The serial output (SOUT) is used to connect multiple LV5233H to expand the number of bits and is connected to the SDATAIN of the next stage. (Cascade connection supported.) For parallel output, when the output control enable input (XEN) is low, the latch input (LATCH) changes from low to high and the clock pulse input changes from low to high, the serial data input signal is output to LED01, and the output is shifted sequentially. For parallel outputs (LED2 to LED24), the signals whose polarities inverted from those of the serial data input (SDATAIN) are output. When the EN input is high, outputs LED01 through LED01 all turn off. When the reset input is low, outputs LED01 through LED24 and SOUT outputs all turn off. The power must be turned on after checking that the reset input is low. To prevent the malfunction, the output load protection circuit is built into. The output of LEDO1 to LEDO24 is compulsorily turned off when becoming below the voltage with a constant there is VCC. Moreover, a thermal circuit is built into, and the output of LEDO1 to LEDO24 is turned off compulsorily when becoming it at the temperature that exceeds the temperature of the junction in IC. No.A1693-4/8 LV5233H Pin Functions Pin No. Pin Name 17 SDATAIN 20 SCK Pin function Equivalent Circuit Pull-down input SVCC SGND 18 XRESET 35 LATCH 36 XEN Pull-up input SVCC SGND 2 SOUT SOUT output SVCC SOUT SGND 3 LEDO12 4 LEDO11 5 LEDO10 7 LEDO9 8 LEDO8 9 LEDO7 10 LEDO6 11 LEDO5 12 LEDO4 14 LEDO3 15 LEDO2 16 LEDO1 21 LEDO24 22 LEDO23 23 LEDO22 25 LEDO21 26 LEDO20 27 LEDO19 28 LEDO18 29 LEDO17 30 LEDO16 32 LEDO15 33 LEDO14 34 LEDO13 LEDO outputs LEDO1 to LEDO24 SVCC SGND PGND No.A1693-5/8 LV5233H Timing conditions Parameter symbol Conditions min typ max SCK Duty = 50% unit Clock frequency fs1 10 Clock pulse width twck SCK 50 ns Latch pulse width twla LATCH 50 ns Data set up time ts1 SDATAIN setup time relative to the rise of SCK 25 ns Data hold time th1 SDATAIN data hold time relative to the rise of SCK 25 ns Clock latch time tla1 Input conditions 1 ton SCK and SDATAIN rise time 100 ns Input conditions 2 toff SCL and SDATAIN fall time 100 ns 100 MHz ns twck SCK 2.5V 90% 2.5V 90% 10% ts1 10% th1 ton 2.5V SDATAIN toff 2.5V twla tla1 2.5V LATCH 2.5V SOUT output timings Parameter symbol Conditions min typ max unit SOUT delay time 1 tdso1 The time from a SCK falling edge to SOUT rising edge 50 ns SOUT delay time 2 tdso2 The time from a SCK falling edge to SOUT falling edge 50 ns SCK 2.5V 2.5V tdso1 tdso2 2.5V 2.5V SOUT No.A1693-6/8 LV5233H LEDO output timings Parameter symbol LEDO delay time 1 tdled1 Conditions min The time from an XEN rising edge to LEDO rising edge typ max unit 100 ns 100 ns 200 ns 200 ns 200 ns CL = 30pF, IO = 100mA, VO = 42V LEDO delay time 2 tdled2 The time from an XEN falling edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 42V LEDO rise time trled LEDO rise time CL = 30pF, IO = 100mA, VO = 42V LEDO fall time tfled LEDO fall time CL = 30pF, IO = 100mA, VO = 42V LEDO delay time 3 tdled3 The time from a LATCH rising edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 42V XEN 2.5V 2.5V tdled2 tdled1 90% 90% 90% 10% LEDO 10% trled tfled tdled3 2.5V LATCH Application Circuit Example max:42V 5V SVCC SVCC SDATAIN SDATAIN SCK SCK LATCH LATCH XEN XEN XRESET PGND LEDO SOUT SGND PGND LEDO XRESET LEDO SOUT SGND sub CPU LEDO No.A1693-7/8 LV5233H Allowable output current characteristics IO -- LEDO 100 Ta = 25 C 50 C Output current, IO - mA 75 C 90 80 70 duty syscle 100% 60 0 2 4 6 8 10 12 14 16 Number of output ports, LEDO SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2010. Specifications and information herein are subject to change without notice. PS No.A1693-8/8