Ordering number : ENA1277 Bi-CMOS LSI LV5256GP Operating Mode Switching Type Step-Up/Down Converter Overview The LV5256GP is an operating mode switching type step-up/step-down converter that can switch the operating mode by using the external signal. Functions • Built-in Pch gate drive power supply • Output short-circuit detection by monitoring the input side of the error amplifier • OCP timer function • Software start function • Support for tracking function • Built-in thermal protection circuit • Built-in UVLO • ON/OFF function: Off-time input current smaller than 1µA • Oscillation frequency : 300kHz to 1.5MHz Oscillation frequency can be set by an external resistor Specifications Maximum Ratings at Ta = 25°C Parameter Maximum input voltage Symbol Conditions Ratings Unit VIN max 12 VDD max 3.6 V V Maximum output voltage VO max 16 V Maximum output current IO max Between OUT and SW 650 mA Allowable input pin voltage VCONT max RT, FB, IN, OCP, SS, ONOFF, TRAC_IN, VDD V DU_SEL, OPC_SEL pins Allowable power dissipation Pd max 0.8 W Operating temperature Topr Mounted on a specified board * -20 to +85 °C Storage temperature Tstg -40 to +125 °C * Specified board : 50mm × 40mm × 0.8mm, glass epoxy 4-layer circuit board (2S2P). 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 21209 MS PC 20080722-S00003 No.A1277-1/9 LV5256GP Recommended Operating Conditions at Ta = 25°C Parameter Symbol Input voltage range Output voltage range Step-down Step-up Output current Conditions Ratings Unit VIN 4.5 to 10 VDD 2.9 to 3.1 V 1.0 to VIN V V V1 When in normal operation mode V V2 When in tracking operation mode 0 to VIN VOUT1 When in normal operation mode 5.3 to 14 V VOUT2 When in tracking operation mode VIN to V IO 600 mA Electrical Characteristics at Ta = 25°C, VDD = 3.0V, VIN = 6.0V Parameter Symbol Ratings Conditions min typ Unit max Reference voltage Reference voltage for comparison Vref -1% 1.0 -1% V Error amplifier Input voltage range Vrange Open loop voltage gain Av 60 0 110 1.5 Unity-gain bandwidth Ft 2 8 Output source current IfboL IN = 2.0V, FB = 1.0V Output sink current IfboH IN = 0V, FB = 0V IN pin source current IiniL IN = 0V FB pin output range R_fb MHz 2 mA µA 100 100 300 0.1 IN = 0 to Vref V dB nA V TRAC_IN pin source current ItracL TRAC_IN pin input operation range R_trac 0.1 100 300 nA Vref-0.1 V Input voltage H level VoniH 2.8 Input voltage L level VoniL Input current H level IoniH ONOFF = 3.3V 0 µA Input current L level IoniL ONOFF = 0V 0 µA Logic input pin block 1 (ONOFF) V 0.5 V Logic input pin block 2 (DU_SEL) Input voltage H level VduiH Input voltage L level VduiL Input pull-down resistance Rdu 2.8 V 0.5 200 V kΩ Logic input pin block 3 (OCP_SEL) Input voltage H level VocpiH Input voltage L level VocpiL Input pull-down resistance Rocp 2.8 V 0.5 100 V kΩ Soft start 7 10 13 µA Soft start source current IssH SS = 0V Soft start sink current IssL When reset, SS = 1.0V Vsc1 OCP_SEL=GND/OPEN *1 × 0.8 V Vsc2 OCP_SEL=REG_0 *1 × 0.4 V SCP comparator offset voltage SCPosf TRAC_IN = 0.7V, operation starts from 0.9V. OCP pin source current IocpH When in short-circuit protection detection mode OCP pin sink current IocpL When in normal operation mode, OCP = 1.0V OCP timer latch voltage Vocp 1 mA Short-circuit protection, SCP Short-circuit protection detection voltage 1 Short-circuit protection detection voltage 2 -40 40 mV µA 10 0.3 1 3 1.1 1.2 1.3 mA V Continued on next page. No.A1277-2/9 LV5256GP Continued from preceding page. Ratings Parameter Symbol Conditions Unit min typ max Therml protection, UVLO Thermal protection operating Tot Design guarantee value *2 175 °C Dot Design guarantee value *2 20 °C temperature Thermal protection hysteresis UVLO lock release voltage 1 VuvloH REG_O monitored 2.8 V UVLO lock voltage 1 VuvloL REG_O monitored 2.5 V UVLO lock release voltage 2 VuvloH2 VIN pin voltage 3.8 V UVLO lock voltage 2 VuvloL2 VIN pin voltage 3.5 V Oscillation frequency F RT = 100kΩ Oscillation frequency range R_F Triangular wave lower-side VtriL RT = 100kΩ 0.5 V VtriH RT = 100kΩ 1.0 V Ivin1 VIN pin, when converter is in 1MHz operation mode. Oscillator 0.8 1 0.3 1.2 MHz 1.5 MHz threshold value Triangular wave upper-side threshold value Power supply pin block Current drain 2 4 mA Ivin2 VIN pin, when in ONOFF stop mode. 1.0 µA Ivdd1 VDD pin, when in ONOFF stop mode. 1.0 µA Output voltage Voutm5 Vout-5V regulator, VOUT = 10.0V Drooping current Ivoutm5 Vout-5V regulator Output voltage Vreg_o Ireg_o = 2.0mA Drooping current Ireg_o Vreg_o = 2V, VIN = 5V 10 mA Main switch on resistance (Pch) RonH VIN = 5V 0.7 Ω Main switch on resistance (Nch) RonL VIN = 5V 0.7 Ω Through current prevention dead Tdead 25 ns Vout-5V Regulator VOUT-4.5 VOUT-5 VOUT-5.5 20 V mA Internal 3.3V Regulator 3.0 3.3 3.6 V Output characteristics time Maximum on-duty (step-down) DMAX1 RT = 100kΩ 100 % Maximum on-duty (step-up) DMAX2 RT = 100kΩ 85 % Step-down η1 VIN = 5.0V, V = 4.6V, IO = 200mA 93 % Step-up η2 VIN = 5.0V, VOUT1 = 6.6V, IO = 200mA 93 % Step-down ∆V1/VIN VIN = 4.5 to 8.6V, V1 = 4.6V, IO = 200mA 0 % Step-up ∆VOUT1/VIN VIN = 4.5 to 5.5V, VOUT1 = 6.6V, IO = 200mA 0 % Step-down ∆V1/IO VIN = 8.4V, V1 = 4.6V, IO = 0 to 200mA 0 Step-up ∆VOUT1/IO VIN = 5.0, VOUT1 = 6.6V, IO = 200mA 0 Converter characteristics Efficiency Line regulation Load regulation *1 IN pin voltage is the detection point. The lowest voltage among Vref, TRAC_IN, and SS is used. *2 Design guarantee value, and no measurement is performed. No.A1277-3/9 LV5256GP Package Dimensions unit : mm (typ) 3368 TOP VIEW SIDE VIEW Allowable power dissipation, Pd max – W 1.0 BOTTOM VIEW (0.125) (0.13) 3.0 0.4 3.0 (C0.17) 20 2 1 0.25 (0.5) 0.5 SIDE VIEW 0.8 0.6 0.4 0.32 0.2 0 – 20 0.8 (0.035) Pd max -- Ta Mounted on a specified board : 50×40×0.8mm3 Glass epoxy 4-layer circuit board (2S2P) 0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : VCT20(3.0X3.0) FB TRAC_IN SS REG_O OCP Pin Assignment 15 14 13 12 11 10 VOUT-5 IN 16 9 VOUT OCP_SEL 17 LV5256GP RT 18 8 SW Top view VDD 19 7 PGND 1 2 3 4 5 NC ONOFF VIN DU_SEL 6 NC NC LGND 20 No.A1277-4/9 LV5256GP Block Diagrams and Sample Application Circuit 1 (Step-down) 100kΩ at 1MHz 0.1µF REG_O RT BIAS VREF Vref1R2 Vref (1.2V) (1.0V±1%) UVLO 1µF OSC 2.8V/2.5V uvlo VOUT 1.0V 0.5V ot FB V1 or V2 VREG 3.3V TSD disable LDO with OPC L/S Vout-5 pwm Control Logic + 22µH 4.7µF SW VREG du_sel disable 0.01µF at 1.25ms OCP V1 (Normal operation) =1.0V to VIN V2 (Tracking operaton) =0V to VIN Vout-5 IN + 0.022µF VOUT-5 disable ot uvlo tout + + + VIN=4.5 to 10V VIN disable SBD R tout SQ uvlo PGND LGND GND/ OPEN DU_SEL L/S du_sel + + + + 0.1µF VrefR2 ×0.8 disable disable ×0.4 uvlo OPC_SEL + Vref1R2 Vref GND/OPEN: ×0.8 REG_O: ×0.4 VDD=2.9 to 3.1V VDD vdd TRAC_IN SS pin heap 17 pin ONOFF 0.033µF at 3.3ms Sample Application Circuit 2 (Step-up) 100kΩ at 1MHz 0.1µF REG_O RT VREF UVLO Vref1R2 Vref (1.2V) (1.0V±1%) VOUT 1.0V 0.5V ot FB 1µF OSC 2.8V/2.5V uvlo TSD disable VOUT1 or VOUT2 VREG 3.3V disable ot uvlo tout IN + + + + pwm Control Logic LDO with OPC 0.022µF BIAS Vout-5 VOUT-5 L/S Vout-5 VOUT1 (Normal operation) =5.3V to 14V VOUT2 (Tracking operaton) =VIN or more 4.7µF 10µH SW VREG + VIN=4.5~10V VIN disable du_sel disable 0.01µF at 1.25ms OCP uvlo R tout SQ PGND LGND REG_O DU_SEL L/S + + + + VDD=2.9~3.1V 0.1µF disable disable ×0.4 uvlo OPC_SEL + Vref1R2 Vref TRAC_IN VDD vdd VrefR2 ×0.8 GND/OPEN: ×0.8 REG_O: ×0.4 du_sel SS ONOFF pin heap 17 pin 0.033µF at 3.3ms No.A1277-5/9 LV5256GP Pin Functions Pin No. 1 Pin Name NC Description Equivalent Circuit No connection. Must be kept open. 2 6 3 ONOFF ON/OFF signal input pin. VDD Threshold level is TTL level. Maximum withstand voltage is VDD. 3 4 VIN 5 DU_SLE Power supply pin of the IC. Apply the input voltage. Step-up/down switching pin. The IC goes in step-up mode VDD by connecting this pin to REG_O pin, and in step-down mode by connecting this pin to GND or leaving this pin open. An internal pull-down resistor (200kΩ) is provided 5 between DU_SEL and GND pins. 200kΩ 7 PGND Power ground pin. The source of the output transistor (Nch-MOSFET) is connected. 8 SW Switching element. A 0.7Ω (typ) Nch switch is inserted VOUT between this pin and PGND, and a 0.7Ω (typ) Pch switch is connected between this pin and VOUT. In step-down mode, insert an inductor between the switching node and 8 power supply output, and in step-up mode insert an inductor between this pin and power supply input. 9 VOUT Source potential of the internal Pch-MOSFET. In step-down mode, apply the input voltage. In step-up mode, apply the power supply voltage. 10 VOUT-5 Internal Pch-MOSFET gate suplly voltage generation pin. Used to generate a voltage with a level equal to VOUT pin voltage-5V by the internal LDO with OCP. 11 OCP Overcurrent detection timer setup pin. Connect a capacitor between this pin and ground to define the time interval between the beginning of the overcurrent state and the IC latches off. The capacitor is charged by the 10µA internal VIN 10µA constant current source. If the OCP_SEL pin is kept open 10kΩ or connected to GND, the IC identifies a short-circuit and starts the timer counter when the voltage at the IN pin falls REG_O 11 below 0.8 times the voltage of Vref, TRAC_IN or SS, 500Ω 1kΩ whichever is lower. If the OCP_SEL pin is connected to REG_O, the IC compares the voltage at the IN pin with 0.4 times the voltage. When the voltage at this pin goes beyond 1.25V, the IC latches off. The latch-off state is reset by the off signal at the ON/OFF pin or the UVLO lock. 12 REG_O 3.3V regulator output pin. VIN 50Ω 12 32kΩ 20kΩ Continued on next page. No.A1277-6/9 LV5256GP Continued from preceding page. Pin No. 13 Pin Name SS Description Equivalent Circuit Capacitor connection pin for soft start. The capacitor REG_O VIN connected to this pin is charged by the internal 10µA 10µA constant current. The interval during which this voltage 10kΩ reaches Vref is called the soft start period. The voltage is clipped to approx. 2V after the soft start. This pin is pulled 13 500Ω down to the ground level when ONOFF/UVLO lock mode. REG_O 1.25V 14 TRAC_IN Reference voltage input pin for tracking power supply REG_O VIN operating. A voltage from 0V up to Vref applied to this pin serves as the reference voltage for determining the output voltage. This pin must be connected to the SS pin when it 14 is not to be used. 1kΩ REG_O 15 FB Error amplifier output pin. Connect a phase compensation REG_O VIN component between this pin and IN pin. 100µA 400Ω 15 1.25V 1kΩ 16 IN Output voltage input pin. Apply the resistor divided output REG_O VIN voltage to this pin. SS TRAC_IN Vref 1kΩ 16 REG_O 17 OCP_SEL OCP detection voltage switching pin, A 100kΩ pull-down resistor is provided between OCP_SEL and GND. The IC VDD enters the 0.8 times detection mode when this pin is connected to GND or kept open and enters the 0.4 times detection mode when the pin is connected to the REG_O pin. 17 100kΩ Continued on next page. No.A1277-7/9 LV5256GP Continued from preceding page. Pin No. 18 Pin Name RT Description Equivalent Circuit Oscillation frequency setting pin. Connect a resistor between this pin and GND. A 100kΩ resistor causes the VDD 500Ω oscillator to oscillate at 1MHz (typ.). 18 19 VDD 20 LGND 10kΩ Logic system power supply. Apply 3.0V±0.1V to this pin from an external source. Logic system ground pin. All voltages are measured with respect to this voltage level. Startup Sequence VDD ONOFF VIN REG_O ONOFF:H REG_O startup UVLO release VOUT-5 startup VOUT-5 VOUT-5 normal judgment SS start SS SW Power supply operation beginning * Be sure to set the ONOFF to 0V when starts or stops VDD. And apply voltage to VIN after VDD started up. No.A1277-8/9 LV5256GP Output Voltage Setting Method The LV5256GP can produce any arbitrary output voltage. The output voltage is set by the resistor inserted between the IN pin (pin 16) and GND, and IN pin and output voltage. The calculating formula for setting the output voltage by using the output voltage setup lower-side resistor R1 and the output voltage setup upper-side resistor R2 is as follows: Output voltage (Step-down) V1 or V2 (Step-up) VOUT1 or VOUT2 R2 IN R1 R2 R2 Q Vref = 1.00 (typ ) (Output voltage) = 1 + × Vref = 1 + R R1 1 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2009. Specifications and information herein are subject to change without notice. PS No.A1277-9/9