EMIF03-SIM01 ® A.S.D.TM 3 LINES EMI FILTER INCLUDING ESD PROTECTION MAIN APPLICATIONS EMI filtering protection and ESD for : SIM Interface (Subscriber identify Module) ■ DESCRIPTION The EMIF03-SIM01 is a highly integrated array designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF03-SIM01 flip-chip packaging means the package size is equal to the die size. That's why EMIF03-SIM01 is a very small device. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. Flip Chip package PIN CONFIGURATION (Ball side) A3 A2 B3 B2 B1 C3 C2 C1 BENEFITS ■ ■ ■ ■ ■ ■ ■ 3 lines symetrical (I/O) low-pass-filter High efficiency in EMI filtering Very low PCB space consuming: 1.6 x 1.6 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression on both input & output PINS (IEC61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through integration & wafer level packaging. COMPLIES WITH THE FOLLOWING STANDARDS : IEC61000-4-2 15kV (air discharge) 8 kV (contact discharge) on input & output pins. TM : ASD is a trademark of STMicroelectronics. July 2002 - Ed: 6A 1/11 EMIF03-SIM01 Schematic C2 100R A3 A2 47R B3 B1 100R C1 C3 GND B2 is ground pin Aplac model Rseries Port2 50 Port1 50 MODEL = demif03 MODEL = demif03 sub sub DEMIF03 diodes Model - RS = 1.2 - CJO = 17p - M = 0.3333 - VJ = 0.6 - ISR = 100p - BV = 6.8 - IBV = 1m - TT = 100n Vcc 50p 0.05 MODEL = demif03_Vcc 0.08nH Rseries = 47R (CLK line) = 100R (RST & Data lines) 0.1 Filtering behavior Aplac 7.60 User: STMicroelectronics Feb 22 2001 0.00 dB -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 -35.00 -40.00 -45.00 -50.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz B3_B1(CLK) 2/11 A3_A2(RST) C3_C1(DAT) sub DEMIF03_Vcc diode Model - RS = 1.5 - CJO = 20p - M = 0.3333 - VJ = 0.6 - ISR = 100p - BV = 6.8 - IBV = 1m - TT = 100n EMIF03-SIM01 ESD response to IEC61000-4-2 (15kV air discharge) Positive surge Negative surge Capacitance versus reverse applied voltage. C(pF) 35 F=1MHz Vosc =30mV 30 25 20 15 10 0 1 2 3 4 5 6 VR(V) ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Value Unit ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge 15 8 kV Junction temperature 125 °C Top Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C 3/11 EMIF03-SIM01 ELECTRICAL CHARACTERISTICS (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current Symbol Test conditions VBR IR = 1 mA IRM VRM = 3V Min. Typ. Max. Unit 6 V µA 1 Ω 1.5 Rd R1 95 100 105 Ω R2 44.65 47 49.35 Ω R3 95 100 105 Ω 35 pF Cline @ 0V TECHNICAL INFORMATION FREQUENCY BEHAVIOR The EMIF03-SIM01 is firstly designed as an EMI / RFI filter. This low-pass filter is characterized by the following parameters: - Cut-off frequency - Insertion loss - High frequency rejection Fig. A1: Frequency response curve Aplac 7.60 User: STMicroelectronics Feb 22 2001 0.00 dB -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 Figure A1shows that attenuation is better than -20dB at mobile phone frequencies (800MHz to 2.5GHz). -35.00 -40.00 -45.00 -50.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz B3_B1(CLK) 4/11 A3_A2(RST) C3_C1(DAT) EMIF03-SIM01 Fig. A2: Measurements conditions TEST BOARD 50 Ω EMI03 SIM01 50 Ω Vg ESD PROTECTION In addition with the filtering the EMIF03-SIM01 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: Vcl = Vbr + Rd ⋅ Ipp This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. Fig. A3: ESD clamping behavior Rg S1 R = 100Ω or 47Ω Rd S2 Rd R load Vg VBR Vin Vout VBR Device to be protected ESD Surge EMIF03-SIM01 5/11 EMIF03-SIM01 To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and Rload>>Rd, it gives these formulas: Rg ⋅ Vbr + Rd ⋅ Vg Rg R ⋅ Vbr + Rd ⋅ Vin Voutput = R Vinput = The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV, Rg=330Ω ) and Vbr=7V (typ.) give: Vinput = 43.36V Voutput = 7.65V (R = 100Ω) 8.38V (R = 47Ω) This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the series resistance R. LATCH-UP PHENOMENA The early ageing and destruction of IC’s is often due to latch-up phenomena which mainly induced by dV/dt. Thanks to its RC structure, the EMIF03-SIM01 provides a high immunity to latch-up by integration of fast edges. (Please refer to the response of the EMIF03-SIM01 to a 30 ns edge on Fig. A9) The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD protection : - almost no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to Vbr for positive surge and close to ground for negative one Fig. A4: Measurements conditions TEST BOARD V(in) V(out) EMI03 SIM01 6/11 EMIF03-SIM01 Fig. A5: Remaining voltage at both stages S1 (Vin1) and S2 (Vout1) during ESD surge a: Positive Surge b: Negative Surge Please note that the EMIF03-SIM01 is not only acting for positive ESD surges but also for negative ones. For negatives surges, it clamps close to ground voltage as shown in Fig. A5b. Note: Dynamic resistance measurements Fig. A6: Rd measurement current wave I As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd IPP t 2µs 2.5 µs 2.5 µs duration measurement wave 7/11 EMIF03-SIM01 CROSSTALK BEHAVIOR Fig. A7: Crosstalk phenomena RG1 Line 1 VG1 α1VG1 + β12VG2 RL1 RG2 Line 2 VG2 α2VG2 + β21VG1 RL2 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( β12 or β21 ) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 1- Digital crosstalk Fig. A8: Digital crosstalk measurements +3V +3V 74HC04 74HC04 B1 B3 ® Square Pulse Generator +3V Square pulse generator frequency = 3.3MHz 0 - 3.3V Risetime = 30ns ■ ■ ■ 8/11 VG1 C1 EMI35 SIM01 C3 β21 VG1 EMIF03-SIM01 Fig. A9: Digital crosstalk results Digital crosstalk is less than 2 mV peak to peak 2- Analog crosstalk Fig. A10: Analog crosstalk phenomena TEST BOARD 50 Ω EMI35 SIM01 out1 50 Ω in1 Vg 9/11 EMIF03-SIM01 Fig. A11: Analog crosstalk results Aplac 7.60 User: STMicroelectronics Feb 22 2001 0.00 dB -10.00 -20.00 -30.00 -40.00 B3_C1 -50.00 -60.00 -70.00 -80.00 -90.00 -100.0 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz Figure A10 gives the measurement circuit for the analog application. In Figure A11, the curve shows the EMIF03-SIM01 provides a crosstalk immunity better than - 20dB up to 3GHz. ORDER CODE EMIF 03 - SIM 01 Electro Magnetic Interference Filter Version number Nb of lines SIM Card protection PACKAGE MECHANICAL DATA (all dimensions in µm) 500µm ± 50 650µm ± 65 1.57mm ± 50µm 315µm ± 50 1.57mm ± 50µm ■ ■ Bottom side (ball view): Pin A1 missing for die orientation Top side (balls underweath): see the marking . 10/11 EMIF03-SIM01 MARKING and DIE SIZE (typical values) 365 365 200 ® 1570 diam 230 FCT YWW 220 1570 YWW: Date code (year + week code) PACKING Ordering code EMIF03-SIM01 Marking Package Weight Base qty Delivery mode FCT Flip Chip 3.3 mg 5000 Tape & reel 7” Note: More packing information are available in the application note AN1235: “Flip-Chip: Package description and recommendations for use” Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 11/11