STMICROELECTRONICS L6728AH

L6728AH
High frequency single phase PWM controller with Power Good
Features
■
Flexible power supply from 5 V to 12 V
■
Power conversion input as low as 1.5 V
■
0.8 V internal reference
■
0.8% output voltage accuracy
■
High-current integrated drivers
■
Power Good output
■
Sensorless and programmable OCP across
low-side RDS(on)
■
OV / UV protections
■
VSEN disconnection protection
■
Oscillator internally fixed at 600 kHz
■
LS-LESS to manage pre-bias start-up
■
Adjustable output voltage
■
Disable function
■
Internal soft-start
■
VFDFPN 10 package
VFQFPN 10
Description
L6728AH is a single-phase step-down controller
with integrated high-current drivers that provides
complete control logic and protection to realize in
a simple way general DC-DC converters by using
a compact VFDFPN 10 package.
Device flexibility allows managing conversions
with power input VIN as low as 1.5 V and device
supply voltage ranging from 5 V to 12 V.
L6728AH provides simple control loop with
voltage mode EA. The integrated 0.8 V reference
allows regulating output voltages with ±0.8%
accuracy over line and temperature variations.
Oscillator is internally fixed to 600 kHz.
Applications
■
Memory and termination supply
■
Subsystem power supply (MCH, IOCH, PCI)
■
CPU and DSP power supply
■
Distributed power supply
■
General DC / DC converters
L6728AH provides programmable dual level over
current protection as well as over and under
voltage protection. Current information is
monitored across the low-side MOSFET RDS(on)
saving the use of expensive and spaceconsuming sense resistors.
PGOOD output easily provides real-time
information on output voltage status, through
VSEN dedicated output monitor.
Table 1.
Device summary
Order codes
L6728AH
L6728AHTR
May 2009
Package
VFDFPN 10
Doc ID 15726 Rev 1
Packing
Tube
Tape and reel
1/33
www.st.com
33
Contents
L6728AH
Contents
1
2
3
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
6
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1
7
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1
Over-current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8
Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 13
9
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10
2/33
9.1
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9.2
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1
Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2
Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.3
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 15726 Rev 1
L6728AH
11
Contents
20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.1
11.2
12
Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1.1
Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1.2
Output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1.3
Signal input (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1.4
Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Demonstration board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12.1
12.2
Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1.1
Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1.2
Output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1.3
Signal input (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1.4
Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Demonstration board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 15726 Rev 1
3/33
Typical application circuit and block diagram
L6728AH
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical application circuit
VIN = 1.5V to 12V
VCC = 5V to 12V
CDEC
6
RPG
VCC
7
COMP
/ DIS
CF
CP
ROS
BOOT
PGOOD
L6728A
10
PGOOD
UGATE
PHASE
L6728AH
RF
8
RFB
FB
VSEN
LGATE
/ OC
GND
9
CBULK
CHF
3
HS
2
Vout
L
4
COUT
LS
LOAD
ROCSET
5
ROS
1
RFB
L6728A Reference Schematic
1.2
Block diagram
Block diagram
VCC
Figure 2.
VSEN
VOUT MONITOR
PGOOD
VOCTH
OC
CONTROL LOGIC
&
PROTECTIONS
BOOT
ADAPTIVE ANTI
CROSS CONDUCTION
CLOCK
PWM
600 kHz
OSCILLATOR
HS
UGATE
PHASE
VCC
LS
ERROR AMPLIFIER
LGATE
/ OC
GND
+
-
L6728AH
L6728A
FB
IOCSET
COMP
/ DIS
4/33
0.8V
Doc ID 15726 Rev 1
L6728AH
2
Pins description and connection diagrams
Pins description and connection diagrams
Figure 3.
Pins connection (top view)
BOOT
PHASE
UGATE
LGATE / OC
GND
2.1
Pin descriptions
Table 2.
Pin description
1
10
2
9
3
L6728A
L6728AH
8
4
7
5
6
PGOOD
VSEN
FB
COMP / DIS
VCC
Pin #
Name
1
BOOT
HS driver supply.
Connect through a capacitor (100 nF) to the floating node (LS-Drain) pin and provide
necessary bootstrap diode from VCC.
2
PHASE
HS driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS
drain to sense RDS(on) drop to measure the output current. This pin is also used by the
adaptive-dead-time control circuitry to monitor when HS MOSFET is OFF.
3
UGATE
HS driver output. Connect directly to HS MOSFET gate.
4
Function
LGATE. LS driver output. Connect directly to LS MOSFET gate.
OC over-current threshold set. During a short period of time following VCC rising over UVLO
threshold, a 10 μA current is sourced from this pin. Connect to GND with an ROCSET resistor
LGATE / OC greater than 5 kΩ to program OC Threshold. The resulting voltage at this pin is sampled and
held internally as the OC set point. Maximum programmable OC threshold is 0.55 V. A voltage
greater than 0.6 V activates an internal clamp and causes OC threshold to be set at the
maximum value.
5
GND
All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.
6
VCC
Device and drivers power supply.
Operative range from 5 V to 12 V. Filter with at least 1 μF MLCC to GND.
7
COMP. Error amplifier output. Connect with an RF - CF // CP to FB to compensate the device
control loop.
COMP / DIS
DIS. The device can be disabled by pushing this pin lower than 0.75 V (typ). Setting free the
pin, the device enables again.
Error amplifier inverting input.
Connect with a resistor RFB to the output regulated voltage. Output resistor divider may be
used to regulate voltages higher than the reference.
8
FB
9
VSEN
Regulated voltage sense pin for OVP and UVP protections and PGOOD. Connect to the
output regulated voltage, or to the output resistor divider if the regulated voltage is higher than
the reference.
10
PGOOD
Open drain output set free after SS has finished and pulled low when VSEN is outside the
relative window. Pull up to a voltage equal or lower than VCC. If not used it can be left floating.
Doc ID 15726 Rev 1
5/33
Pins description and connection diagrams
2.2
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
RTH(JA)
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67 mm x 69 mm board)
45
°C/W
RTH(JC)
Thermal resistance junction to case
5
°C/W
150
°C
TMAX
Maximum junction temperature
TSTG
Storage temperature range
-40 to 150
°C
TJ
Junction temperature range
-40 to 125
°C
2.25
W
PTOT
6/33
L6728AH
Maximum power dissipation at TA = 25 °C
Doc ID 15726 Rev 1
L6728AH
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol
Parameter
Unit
-0.3 to 15
V
VCC
to GND
VBOOT, VUGATE
to PHASE
to GND
to GND; t < 200 ns
15
33
45
V
VPHASE
to GND
to GND; t < 200 ns
-5 to 18
-8 to 30
V
VLGATE
to GND
-0.3 to VCC+0.3
V
-0.3 to 3.6
V
-0.3 to VCC+0.3
V
FB, COMP, VSEN to GND
PGOOD to GND
3.2
Value
Electrical characteristics
VCC = 5 V to 12 V; TJ = 0 °C to 70 °C unless otherwise specified
Table 5.
Symbol
Electrical characteristics
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply current and power-on
ICC
VCC supply current
UGATE and LGATE = OPEN
IBOOT
BOOT supply current
UGATE = OPEN; PHASE to GND
VCC turn-ON
VCC rising
UVLO
6
mA
0.7
mA
4.1
Hysteresis
0.2
V
V
Oscillator
FSW
Main oscillator accuracy
ΔVOSC
PWM ramp amplitude
dMAX
Maximum duty cycle
540
600
660
1.4
kHz
V
67
%
Reference and error amplifier
Output voltage accuracy
A0
GBWP
-0.8
DC gain (1)
Gain-bandwidth product
(1)
(1)
SR
Slew-rate
DIS
Disable threshold
COMP falling
Doc ID 15726 Rev 1
0.70
-
0.8
%
120
dB
15
MHz
8
V/μs
0.85
V
7/33
Electrical specifications
Table 5.
Symbol
L6728AH
Electrical characteristics (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Gate drivers
IUGATE
HS source current
BOOT - PHASE = 5 V
1.5
A
RUGATE
HS sink resistance
BOOT - PHASE = 5 V
1.1
Ω
ILGATE
LS source current
VCC = 5 V
1.5
A
RLGATE
LS sink resistance
VCC = 5 V
0.65
Ω
Over-current protection
IOCSET
OCSET current source
Sourced from LGATE pin, during OC
setting phase
VOC_SW
OC switch-over threshold
VLGATE/OC rising
9
10
11
600
μA
mV
Over and under-voltage protections
OVP
VSEN rising
0.90
1.00
1.10
V
unlatch, VSEN falling
0.35
0.40
0.45
V
0.50
0.60
0.70
V
OVP threshold
UVP
UVP threshold
VSEN falling
VSEN
VSEN bias current
Sourced from VSEN
Upper threshold
VSEN rising
0.860
0.890
0.920
V
Lower threshold
VSEN falling
0.680
0.710
0.740
V
PGOOD voltage low
IPGOOD = -4 mA
0.4
V
100
nA
PGOOD
PGOOD
VPGOODL
1. Guaranteed by design, not subject to test.
8/33
Doc ID 15726 Rev 1
L6728AH
4
Device description
Device description
L6728AH is a single-phase PWM controller with embedded high-current drivers that
provides complete control logic and protections to realize in an easy and simple way a
general DC-DC step-down converter. Designed to drive N-channel MOSFETs in a
synchronous buck topology, with its high level of integration this 10-pin device allows
reducing cost and size of the power supply solution also providing real-time PGOOD in a
compact VFQFPN10 3x3 mm.
L6728AH is designed to operate from a 5 V or 12 V supply. The output voltage can be
precisely regulated to as low as 0.8 V with ±1% accuracy over line and temperature
variations. The switching frequency is internally set to 600 kHz.
This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15 MHz gain-bandwidth product and 8 V/µs slew rate, allowing high
regulator bandwidth for fast transient response.
To avoid load damages, L6728AH provides over-current protection as well as overvoltage,
under voltage and feedback disconnection protection. The over-current trip threshold is
programmable by a simple resistor connected from Lgate to GND. Output current is
monitored across low-side MOSFET RDS(on), saving the use of expensive and spaceconsuming sense resistor. Output voltage is monitored through dedicated VSEN pin.
L6728AH implements soft-start increasing the internal reference in closed loop regulation.
low-side-less feature allows the device to perform soft-start over pre-biased output avoiding
high current return through the output inductor and dangerous negative spike at the load
side.
L6728AH is available in a compact VFDFN10 3 x 3 mm package with exposed pad.
Doc ID 15726 Rev 1
9/33
Driver section
5
L6728AH
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also
multiple MOSFETs to reduce the equivalent RDS(on)), maintaining fast switching transition.
The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return.
The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return.
The controller embodies an anti-shoot-through and adaptive dead-time control to minimize
low side body diode conduction time, maintaining good efficiency while saving the use of
Schottky diode:
to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin
drops down, the low-side MOSFET gate drive is suddenly applied;
to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has
fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To
allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if
the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so
allowing the negative current of the inductor to recirculate. This mechanism allows the
system to regulate even if the current is negative.
Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See
maximum duty cycle limitations) can be chosen freely.
5.1
Power dissipation
L6728AH embeds high current MOSFET drivers for both high side and low side MOSFETs:
it is then important to consider the power that the device is going to dissipate in driving them
in order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
●
Device bias power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow (assuming to supply HS and LS
drivers with the same VCC of the device):
P DC = V CC ⋅ ( I CC + I BOOT )
●
Drivers power is the power needed by the driver to continuously switch on and off the
external MOSFETs; it is a function of the switching frequency and total gate charge of
the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs (easy calculable) is dissipated by three main
factors: external gate resistance (when present), intrinsic MOSFET resistance and
intrinsic driver resistance. This last term is the important one to be determined to
calculate the device power dissipation. The total power dissipated to switch the
MOSFETs results:
P SW = F SW ⋅ ( Q gHS ⋅ V BOOT + Q gLS ⋅ V CC )
External gate resistors helps the device to dissipate the switching power since the same
power PSW will be shared between the internal driver impedance and the external resistor
resulting in a general cooling of the device.
10/33
Doc ID 15726 Rev 1
L6728AH
6
Soft-start
Soft-start
L6728AH implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required from the input power supply. The device gradually increases the
internal reference from 0 V to 0.8 V in 4.5 msec (typ.), in closed loop regulation, linearly
charging the output capacitors to the final regulation voltage. A pre-charged output voltage
will affect the soft-start duration, resulting in a reduction of this period of time (< 4 msec).
During the soft-start process all the protections but the UVP are active: the UVP becomes
active as soon as the soft-start ends up.
The device begins soft-start phase only when VCC power supply is above UVLO threshold
and over-current threshold setting phase has been completed.
6.1
Low-side-less start up (LSLess)
In order to avoid any kind of negative undershoot and dangerous return from the load during
start-up, L6728AH performs a special sequence in enabling LS driver to switch: during the
soft-start phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This
avoid the dangerous negative spike on the output voltage that can happen if starting over a
pre-biased output.
If the output voltage is pre-biased to a voltage higher than the final one, the HS would never
start to switch. In this case, at the end of soft-start time, LS is enabled and discharge the
output to the final regulation value.
This particular feature of the device masks the LS turn-on only from the control loop point of
view: protections by-pass this turning ON the LS MOSFET in case of need.
Figure 4.
LSLess startup (left) vs. non-LSLess startup (right)
Doc ID 15726 Rev 1
11/33
Over-current protection
7
L6728AH
Over-current protection
The over-current function protects the converter from a shorted output or overload, by
sensing the output current information across the low side MOSFET drain-source onresistance, RDS(on). This method reduces cost and enhances converter efficiency by
avoiding the use of expensive and space-consuming sense resistors.
The low side RDS(on) current sense is implemented by comparing the voltage at the PHASE
node when LS MOSFET is turned on with the programmed OCP thresholds voltages,
internally held. If the monitored voltage is bigger than these thresholds, an over-current
event is detected.
For maximum safety and load protection, L6728AH implements a dual level over-current
protection system:
●
1st level threshold: it is the user externally set threshold. If the monitored voltage on
PHASE exceeds this threshold, a 1st level over-current is detected. If four 1st level OC
events are detected in four consecutive switching cycles, over-current protection will be
triggered.
●
2nd level threshold: it is an internal threshold whose value is equal to 1st level
threshold multiplied by a factor 1.5. If the monitored voltage on PHASE exceeds this
threshold, over-current protection will be triggered immediately.
When over-current protection is triggered, the device turns off both LS and HS MOSFETs in
a latched condition. To recover from over-current protection triggered condition, VCC power
supply must be cycled.
7.1
Over-current threshold setting
L6728AH allows to easily program a 1st level over-current threshold ranging from 50 mV to
550 mV, simply by adding a resistor (ROCSET) between LGATE and GND. 2nd level threshold
will be automatically set accordingly.
During a short period of time (about 5 ms) following VCC rising over UVLO threshold, an
internal 10 µA current (IOCSET) is sourced from LGATE pin, determining a voltage drop
across ROCSET. This voltage drop will be sampled and internally held by the device as 1st
level over-current threshold. The OC setting procedure overall time length is about 5 ms.
Connecting a ROCSET resistor between LGATE and GND, the programmed 1st level
threshold will be:
I OCSET ⋅ R OCSET
I OCth1 = ------------------------------------------R dsON
the programmed 2nd level threshold will be:
I OCSET ⋅ R OCSET
I OCth2 = 1.5 ⋅ -------------------------------------------R dsON
In case ROCSET is not connected, the device sets the OCP thresholds to the maximum
values: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches
600 mV, setting the maximum threshold and suddenly ending OC setting phase.
12/33
Doc ID 15726 Rev 1
L6728AH
8
Output voltage setting and protections
Output voltage setting and protections
L6728AH is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the
device comes with a fixed 0.8 V internal reference that guarantee the output regulated
voltage to be within ±1% tolerance over line and temperature variations (excluding output
resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be easily achieved by adding a resistor ROS between
FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R FB ⎞
V OUT = V REF ⋅ ⎛ 1 + ---------⎝
R OS⎠
where VREF is 0.8 V.
L6728AH monitors the voltage at VSEN pin and compares it to internal reference voltage in
order to provide under voltage and overvoltage protections as well as PGOOD signal.
According to the level of VSEN, different actions are performed from the controller:
●
PGOOD
If the voltage monitored through VSEN exits from the PGOOD window limits, the device
de-asserts the PGOOD signal still continuing switching and regulating. PGOOD is
asserted at the end of the soft-start phase.
●
Under voltage protection
If the voltage at VSEN pin drops below UV threshold, the device turns off both HS and
LS MOSFETs, latching the condition. Cycle VCC to recover.
●
Overvoltage protection
If the voltage at VSEN pin rises over OV threshold (1 V typ), overvoltage protection
turns off HS MOSFET and turns on LS MOSFET. The LS MOSFET will be turned off as
soon as VSEN goes below VREF/2 (0.4 V). The condition is latched, cycle VCC to
recover. Notice that, even if the device is latched, the device still controls the LS
MOSFET and can switch it on whenever VSEN rises above 0.4 V.
●
Feedback disconnection protection
In order to provide load protection even if VSEN pin is not connected, a 100 nA bias
current is always sourced from this pin. If VSEN pin is not connected, this current will
permanently pull it up causing the device to detect an OV: thus LS will be latched on
preventing output voltage from rising out of control.
Doc ID 15726 Rev 1
13/33
Application details
L6728AH
9
Application details
9.1
Compensation network
The control loop showed in Figure 5 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, offset resistor between FB node and GND
can be neglected in control loop calculation).
Error amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with VIN
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and VOUT. This function has a double pole at frequency FLC depending on the L-C output
filter and a zero at FESR depending on the output capacitor ESR. The DC gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage
ΔVOSC.
Figure 5.
PWM control loop
VIN
OSC
ΔV OSC
_
L
+
R
V OUT
COUT
PWM
COMPARATOR
ERROR
AMPLIFIER
+
CF
ESR
VREF
_
RFB
RF
CS
RS
ZFB
CP
ZF
The compensation network closes the loop joining VOUT and EA output with transfer
function ideally equal to -ZF/ZFB.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for
stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain
has to cross 0 dB axis with -20 dB/decade slope.
As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
14/33
Doc ID 15726 Rev 1
L6728AH
Application details
Figure 6.
Example of type III compensation
Gain
[dB]
open loop
EA gain
FZ1 FZ2
FP2
FP1
closed
loop gain
compensation
gain
20log (RF/RFB)
open loop
converter gain
20log (VIN/ΔVOSC )
0dB
F0dB
FLC
●
●
Log (Freq)
FESR
Open loop converter singularities:
a)
1
F LC = --------------------------------2π L ⋅ C OUT
b)
1
F ESR = ------------------------------------------2π ⋅ C OUT ⋅ ESR
Compensation network singularities frequencies:
a)
1
F Z1 = -----------------------------2π ⋅ R F ⋅ C F
b)
1
F Z2 = ----------------------------------------------------2π ⋅ ( R FB + R S ) ⋅ C S
c)
1
F P1 = -------------------------------------------------CF ⋅ CP
2π ⋅ R F ⋅ ⎛⎝ ---------------------⎞⎠
CF + CP
d)
1
F P2 = -----------------------------2π ⋅ R S ⋅ C S
To place the poles and zeroes of the compensation network, the following suggestions may
be followed:
a)
Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth
according to the approximated formula (suggested values for RFB is in the range of
some kΩ):
F 0dB ΔV OSC
RF
= ------------ ⋅ ---------------------------F LC
V IN
R FB
Doc ID 15726 Rev 1
15/33
Application details
b)
L6728AH
Place FZ1 below FLC (typically 0.5*FLC):
1
C F = ----------------------------π ⋅ R F ⋅ F LC
c)
Place FP1 at FESR:
CF
C P = ---------------------------------------------------------2π ⋅ R F ⋅ C F ⋅ F ESR – 1
d)
Place FZ2 at FLC and FP2 at half of the switching frequency:
R FB
R S = -------------------------F SW
------------------ – 1
2 ⋅ F LC
1
C S = -----------------------------π ⋅ R S ⋅ F SW
9.2
e)
Check that compensation network gain is lower than open loop EA gain before
F0dB;
f)
Check phase margin obtained (it should be greater than 45°) and repeat if
necessary.
Layout guidelines
L6728AH provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 7) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
16/33
Doc ID 15726 Rev 1
L6728AH
Application details
Figure 7.
Power connections (heavy lines)
VIN
CIN
UGATE
PHASE
L
L6728A
L6728AH
COUT
LGATE
LOAD
GND
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
recommended to minimize the distance between controller and power section.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC
and Bootstrap capacitor) and feedback compensation components as close to the device as
practical. For over current programmability, place ROCSET close to the device and avoid
leakage current paths on COMP/OC pin, since the internal current source is only 60 μA.
Systems that do not use Schottky diode in parallel to the low-side MOSFET might show big
negative spikes on the phase pin. This spike must be limited within the absolute maximum
ratings (for example, adding a gate resistor in series to HS MOSFET gate), as well as the
positive spike, but has an additional consequence: it causes the bootstrap capacitor to be
over-charged. This extra-charge can cause, in the worst case condition of maximum input
voltage and during particular transients, that boot-to-phase voltage overcomes the absolute
maximum ratings also causing device failures. It is then suggested in this cases to limit this
extra-charge by adding a small resistor in series to the boot capacitor (one resistor in series
to BOOT).
Figure 8.
Drivers turn-on and turn-off paths
LS DRIVER
LS MOSFET
HS DRIVER
VCC
HS MOSFET
BOOT
CGD
RGATE
CGD
RINT
RGATE
LGATE
RINT
UGATE
CGS
CDS
GND
CGS
CDS
PHASE
Doc ID 15726 Rev 1
17/33
Application information
L6728AH
10
Application information
10.1
Inductor design
The inductance value is defined by a compromise between the dynamic response time, the
efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple
current (ΔIL) between 20% and 30% of the maximum output current (typ.). The inductance
value can be calculated with the following relationship:
V IN – V OUT V OUT
L = ------------------------------ ⋅ -------------F SW ⋅ ΔI L
V IN
where FSW is the switching frequency, VIN is the input voltage and VOUT is the output
voltage.
Increasing the value of the inductance reduces the current ripple but, at the same time,
increases the converter response time to a dynamic load change. The response time is the
time required by the inductor to change its current from initial to final value. Until the inductor
has not finished its charging time, the output current is supplied by the output capacitors.
Minimizing the response time can minimize the output capacitance required. If the
compensation network is well designed, during a load variation the device is able to set a
duty cycle value very different (0% or 80%) from steady state one. When this condition is
reached, the response time is limited by the time required to change the inductor current.
18/33
Doc ID 15726 Rev 1
L6728AH
10.2
Application information
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
ΔV OUT_ESR = ΔI L ⋅ ESR
1
ΔV OUT_C = ΔI L ⋅ --------------------------------------8 ⋅ C OUT ⋅ F SW
Where ΔIL is the inductor current ripple. In particular, the expression that defines ΔVOUT_C
takes in consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitors supplies the current to the load or absorb the
current stored into the inductor until the converter reacts. In fact, even if the controller
recognizes immediately the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that also in this case
depends on the ESR and capacitive charge/discharge as follow:
ΔV OUT_ESR = ΔI OUT ⋅ ESR
L ⋅ ΔI OUT
ΔV OUT_C = ΔI OUT ⋅ -------------------------------------2 ⋅ C OUT ⋅ ΔV L
Where ΔVL is the voltage applied to the inductor during the transient response
( D MAX ⋅ VIN – VOUT for the load appliance or VOUT for the load removal).
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation
during load transients while they does not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggested to minimize ripple as well as reducing voltage deviation in dynamic
mode.
10.3
Input capacitors
The input capacitor bank is designed considering mainly the input RMS current that
depends on the output deliverable current (IOUT) and the duty-cycle (D) for the regulation as
follow:
I rms = I OUT ⋅ D ⋅ ( 1 – D )
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depends on the
input capacitor ESR and, in worst case, are:
P = ESR ⋅ ( I OUT ⁄ 2 )
Doc ID 15726 Rev 1
2
19/33
20 A demonstration board
11
L6728AH
20 A demonstration board
L6728AH 20 A demonstration board realizes, in a two-layer PCB, a step-down DC/DC
converter and shows the operation of the device in a general-purpose high-current
application. Different output voltage rails have been considered: 8 V, 5 V, 3.3 V, 2.5 V, 1.25 V
and 0.8 V. The input voltage can range from a bottom value that depends on the chosen rail
up to 15 V buses (absolute maximum). The application can deliver an output current up to
the value fixed by ROCSET (~27 A).
Figure 9.
20 A demonstration board (left) and components placement (right)
Figure 10. 20 A demonstration board’s top (left) and bottom (right) layers
20/33
Doc ID 15726 Rev 1
L6728AH
20 A demonstration board
Figure 11. 20 A demonstration board schematic
Doc ID 15726 Rev 1
21/33
20 A demonstration board
Table 6.
L6728AH
20A demonstration board - bill of material (common components)
Qty
Reference
Description
Package
Capacitors
2
C1, C2
Electrolytic capacitor 1800 μF 16 V
Sanyo P/N 16ME1800WG
1
C10
MLCC, 100 nF, 50 V, X7R
Murata GRM188R71H104K
SMD0603
3
C11 to C13
MLCC, 4.7 μF, 16 V, X7R
Murata GRM31CR71C475K
SMD1206
2
C14, C38
MLCC, 1 μF, 16 V, X7R
Murata GRM21BR71C105K
SMD0805
48
C3 to C9, C15 to C20, C39 to
C59, C36, C37, C21 to C23,
C25 to C29, C31 to C34
Not mounted
1
C30
POSCAP 470 μF, 6.3 V, 10 mΩ
Sanyo P/N 6TPD470M
1
C24
MLCC, 47 nF, 50 V, X7R
Murata GRM188R71H473K
1
C35
MLCC, 100 pF, 50 V, X7R
Murata GRM188R71H101K
Radial 10 x 23 mm
N.A.
SMD1206
SMD0603
Resistors
4
R1, R2, R20, R17
Resistor, 2R2, 1/16W, 1%
SMD0603
5
R3, R5, R11, R12, R16
Resistor, 0R, 1/8W, 1%
SMD0805
5
R4, R10, R14, R15, R21
Not mounted
1
R19
Resistor, 22 K, 1/16W, 1%
1
R18
Resistor, 18 K, 1/16W, 1%
L1
Wurth SMD power inductor
670 nH - 1.75 mΩ - 40 A
P/N 744-315-067
N.A.
SMD0603
Inductor
1
1
L2
N.A.
Not mounted
Active components
1
D1
Diode, 1N4148
5
Q1 to Q4, Q8
Not mounted
1
Q5
STD70NH02L
1
Q7
STD95NH02L
1
U1
Controller, L6728AH
SOT23
N.A.
DPACK
22/33
Doc ID 15726 Rev 1
VFQFPN10,
3x3 mm
L6728AH
20 A demonstration board
11.1
Demonstration board description
11.1.1
Power input (VIN)
This is the input voltage for the power conversion. The high-side drain is connected to this
input. This voltage can range from 1.5 V to 12 V bus.
If the voltage is between 5 V and 12 V it can supply also the device (through the VCC pin)
and in this case the R16 (0 Ω) resistor must be present.
11.1.2
Output (VOUT)
Different output voltage rails have been tested. For each rail a few component need to be
changed: these components are used to program the desiderated output voltage and to
compensate the system. The over-current-protection limit is set to ~27 A but it can be
changed by replacing the resistors R18.
Table 7.
Rail dependent components
Ref.
8 V rail
Q9
5 V rail
3.3 V rail
Mounted
2.5 V rail
1.25 V rail
0.8 V rail
Not mounted
R7
3.6 kΩ
3.6 kΩ
3.6 kΩ
3.6 kΩ
11 kΩ
11 kΩ
R6, R9
3.6 kΩ
3.6 kΩ
4.7 kΩ
4.7 kΩ
22 kΩ
22 kΩ
R8, R13
390 Ω
680 Ω
1.5 kΩ
2.2 kΩ
39 kΩ
Open
Note:
All the previous resistors are SMD 0603 package, 1/16W, 1% tolerance.
11.1.3
Signal input (VCC)
Using the input voltage VIN to supply the controller no power is required at this input.
However the controller can be supplied separately from the power stage through the VCC
input and, in this case, the R16 (0 Ω) resistor must be unsoldered.
11.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing
the device:
–
COMP: The output of the error amplifier;
–
FB: The inverting input of the error amplifier;
–
PGOOD: Signaling the regular functioning (active high);
–
VGDHS: The bootstrap diode anode;
–
PHASE: Phase node;
–
LGATE: Low-side gate pin of the device;
–
HGATE: High-side gate pin of the device.
Doc ID 15726 Rev 1
23/33
20 A demonstration board
11.2
L6728AH
Demonstration board characterization
Figure 12 and Figure 17 show the electrical performances of the tamboured in terms of
accuracy and efficiency.
Figure 12. 20 A demonstration board performances
Input Voltage @ 12 V
0,3%
100%
0,2%
90%
Efficiency [%]
Output Voltage Error [%]
Load / Line Regulation
0,1%
0,0%
-0,1%
-0,2%
0A
5A
10A
15A
80%
70%
60%
50%
20A
5
6
7
8
9
10
11
12
13
14
40%
0,0
15
2,5
5,0
7,5
Input Voltage [V]
90%
90%
80%
70%
40%
0,0
Vout = 0.8 V
Vout = 1.25 V
Vout = 2.5 V
Vout = 3.3 V
12,5
15,0
Vout = 8 V
17,5
20,0
22,5
25,0
80%
70%
60%
50%
Vout = 5 V
Vout = 0.8 V
Vout = 1.25 V
Vout = 2.5 V
Vout = 3.3 V
40%
2,5
5,0
7,5
10,0
12,5
15,0
17,5
20,0
22,5
25,0
Output Current [A]
24/33
10,0
Input Voltage @ 5 V
100%
Efficiency [%]
Efficiency [%]
Input Voltage @ 8 V
50%
Vout = 3.3 V
Output Current [A]
100%
60%
Vout = 1.25 V
Vout = 2.5 V
Vout = 5 V
-0,3%
4
Vout = 0.8 V
0
3
5
8
10
13
15
Output Current [A]
Doc ID 15726 Rev 1
18
20
23
25
L6728AH
12
5 A demonstration board
5 A demonstration board
L6728AH 5 A demonstration board realizes, in a two-layer PCB, a step-down DC/DC
converter and shows the operation of the device in a general-purpose high-current
application. Different output voltage rails have been considered: 8 V, 5 V, 3.3 V, 2.5 V, 1.25 V
and 0.8 V. The input voltage can range from a bottom value that depends on the chosen rail
up to 15 V buses (absolute maximum). The application can deliver an output current up to
the value fixed by ROCSET (~6 A).
Figure 13. 5 A demonstration board (left) and components placement (right)
Figure 14. 5 A demonstration board’s top (left) and bottom (right) layers
Doc ID 15726 Rev 1
25/33
5 A demonstration board
L6728AH
Figure 15. 5 A demonstration board schematic
26/33
Doc ID 15726 Rev 1
L6728AH
5 A demonstration board
Table 8.
5 A demonstration board - bill of material
Qty
Reference
Description
Package
Capacitors
2
C12, C51
MLCC, 10 μF, 16 V, X5R
Murata GRM31CR61C106K
SMD1206
1
C10
MLCC, 100 nF, 50 V, X7R
Murata GRM188R71H104K
SMD0603
2
C14, C38
MLCC, 1 μF, 16 V, X7R
Murata GRM21BR71C105K
SMD0805
2
C39, C40
MLCC, 22 μF, 6.3 V, X5R
Murata GRM31CR60J226K
SMD1206
2
C36
MLCC, 10 nF, 50 V, X7R
Murata GRM188R71H103K
1
C24
MLCC, 47 nF, 50 V, X7R
Murata GRM188R71H223K
1
C35
MLCC, 1 nF, 50 V, X7R
Murata GRM188R71H102K
3
R1, R2, R17
Resistor, 3R3, 1/16 W, 1%
3
R3, R5, R16
Resistor, 0R, 1/8 W, 1%
1
R14
Resistor, 51R, 1/8 W, 1%
2
R6, R9
Resistor, 2K2, 1/16 W, 1%
2
R8, R13
Resistor, 3K9, 1/16 W, 1%
1
R7
Resistor, 270 R, 1/16 W, 1%
1
R19
Resistor, 22 K, 1/16 W, 1%
1
R18
Resistor, 18 K, 1/16 W, 1%
L1
Wurth SMD power inductor
1.8 μH - 3.68 mΩ - 20 A
P/N 744-318-180
SMD0603
Resistors
SMD0603
Inductor
1
N.A.
Active components
1
D1
Diode, BAT54
1
Q5
Dual N-channel MOS,
STS8DNF3LL (the STS8DNH3LL
model can be used as well)
1
U1
Controller, L6728AH
Doc ID 15726 Rev 1
SOT23
SO8
VFQFPN 10
3x3 mm
27/33
5 A demonstration board
L6728AH
12.1
Demonstration board description
12.1.1
Power input (VIN)
This is the input voltage for the power conversion. The high-side drain is connected to this
input. This voltage can range from 1.5 V to 12 V bus.
If the voltage is between 5 V and 12 V it can supply also the device (through the Vcc pin)
and in this case the R16 (0 Ω) resistor must be present.
12.1.2
Output (VOUT)
Different output voltage rails have been tested. For each rail a few component need to be
changed: these components are used to program the desiderate output voltage. The OCP
limit is set to ~6 A but it can be changed by replacing the resistors R18.
Table 9.
Rail dependent components
Ref.
8 V rail
5 V rail
3.3 V rail
2.5 V rail
1.25 V rail
0.8 V rail
R8, R13
240 Ω
430 Ω
680 Ω
1 kΩ
3.9 kΩ
Open
Note:
All the previous resistors are SMD 0603 package, 1/16W, 1% tolerance.
12.1.3
Signal input (VCC)
Using the input voltage VIN to supply the controller no power is required at this input.
However the controller can be supplied separately from the power stage through the VCC
input (5-12 V) and, in this case, the R16 (0 Ω) resistor must be unsoldered.
12.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing
the device:
28/33
–
COMP: The output of the error amplifier;
–
FB: The inverting input of the error amplifier;
–
PGOOD: Signaling the regular functioning (active high);
–
VGDHS: The bootstrap diode anode;
–
PHASE: Phase node;
–
LGATE: Low-Side gate pin of the device;
–
HGATE: High-Side gate pin of the device.
Doc ID 15726 Rev 1
L6728AH
Demonstration board characterization
Figure 16 and Figure 17 show the electrical performances of the demonstration board in
terms of accuracy and efficiency.
Figure 16. 5 A demonstration board performances
Input Voltage @ 12 V
0,3%
100%
0,2%
90%
Efficiency [%]
Output Voltage Error [%]
Load / Line Regulation
0,1%
0,0%
-0,1%
-0,2%
0A
2.5A
80%
70%
60%
50%
5A
-0,3%
4
5
6
7
8
9
10
11
12
13
14
40%
0,0
15
0,5
1,0
1,5
90%
90%
Efficiency [%]
Efficiency [%]
100%
80%
70%
2,0
2,5
3,0
3,5
Vout = 8 V
4,0
4,5
5,0
5,5
Vout = 0.8 V
Vout = 1.25 V
Vout = 2.5 V
Vout = 3.3 V
80%
70%
60%
50%
Vout = 5 V
40%
0,0
Vout = 3.3 V
Input Voltage @ 5 V
Input Voltage @ 8 V
50%
Vout = 1.25 V
Vout = 2.5 V
Output Current [A]
100%
60%
Vout = 0.8 V
Vout = 5 V
Input Voltage [V]
Vout = 0.8 V
Vout = 1.25 V
Vout = 2.5 V
Vout = 3.3 V
40%
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
5,5
0,0
0,5
1,0
1,5
2,0
Output Current [A]
2,5
3,0
3,5
4,0
4,5
5,0
5,5
14
15
Output Current [A]
Figure 17. Demonstration boards power consumption @ 0 A output current
5A Demoboard Power Consumption
20A Demoboard Power Consumption
1,2
1,2
1,0
1,0
0,8
0,8
Power [W]
Power [W]
12.2
5 A demonstration board
0,6
0,4
0,6
0,4
0,2
0,2
0,0
0,0
4
5
6
7
8
9
10
11
12
13
14
15
4
5
6
7
8
9
10
11
12
13
Input Voltage [V]
Input Voltage [V]
Doc ID 15726 Rev 1
29/33
Package mechanical data
13
L6728AH
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
30/33
Doc ID 15726 Rev 1
L6728AH
Package mechanical data
Table 10.
VFDFPN10 3x3 mm mechanical data
mm
mils
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
0.80
0.90
1.00
31.49
35.43
39.37
A1
0.02
0.05
0.787
1.968
A2
0.70
27.55
A3
0.20
7.874
A
b
0.18
D
D2
2.21
7.086
9.055
2.26
1.49
1.64
2.31
87.00
88.97
0.4
90.94
118.1
1.74
58.66
64.56
0.50
0.3
11.81
118.1
3.00
e
L
0.30
3.00
E
E2
0.23
68.50
19.68
0.5
11.81
15.74
M
0.75
29.52
m
0.25
9.842
19.68
Doc ID 15726 Rev 1
M
m
Figure 18. VFDFPN10 3x3 mm package drawing
31/33
Revision history
14
L6728AH
Revision history
Table 11.
32/33
Document revision history
Date
Revision
20-May-2009
1
Changes
Initial release
Doc ID 15726 Rev 1
L6728AH
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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