STMICROELECTRONICS PSD4235G2V

PSD4235G2V
Flash in-system programmable (ISP) peripherals
for 16-bit MCUs (3.3 V supply)
Features
PSD provides an integrated solution to 16-bit
MCU based applications that includes
configurable memories, PLD logic and I/Os:
■
Dual bank Flash memories
– 4 Mbit of Primary Flash memory (8 uniform
sectors, 32K x 16)
– 256 Kbit Secondary Flash memory with 4
sectors
– Concurrent operation: read from one
memory while erasing and writing the other
■
64 Kbit SRAM
■
PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■
■
Seven I/O ports with 52 I/O pins
– 52 individually configurable I/O port pins
that can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function l/Os
– l/O ports may be configured as open-drain
outputs
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
February 2009
LQFP80 (U)
80-lead, Thin, Quad, Flat
■
Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■
Programmable power management
■
High endurance
– 100,000 Erase/write cycles of Flash
memory
– 1,000 Erase/WRITE Cycles of PLD
– 15 Year Data Retention
■
Single supply voltage
– 3.3 V ±10%
■
Memory speed
– 90 ns Flash memory and SRAM access
time
■
Package is ECOPACK®
Rev 2
1/124
www.st.com
1
Contents
PSD4235G2V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1
1.2
1.3
2
In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.1
First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.2
Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 12
1.1.3
Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.1
Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 13
1.2.2
Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.3
Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PSDsoft™ Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5
ISP via JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6
In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.9
Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
PSD register description and address offsets . . . . . . . . . . . . . . . . . . . 22
5
Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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5.1
Data-In registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Data-out registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
Direction registers - ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . 24
5.4
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5
Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6
Drive registers - Ports C and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PSD4235G2V
6
5.7
Enable-Out registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.8
Input macrocells registers- ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9
Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.10
Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.11
Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.12
Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.13
JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.14
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.15
PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.16
PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.17
VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.18
Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.19
Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2
Primary Flash memory and secondary Flash memory description . . . . . 32
6.3
7
8
Contents
6.2.1
Memory block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1
Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2
Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3
Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4
Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.5
Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6
Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.7
Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.8
Toggle flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.9
Error flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.10
Erase timeout flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . 38
Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Contents
9
10
PSD4235G2V
8.1
Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2
Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3
Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1
Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.3
Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12
Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.1
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.2
Memory Select configuration for MCUs with separate
Program and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.3
Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4
Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.5
80C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14
Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
15
PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
16
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
17
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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17.1
Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
17.2
Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17.3
Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 59
PSD4235G2V
18
Contents
17.4
The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
17.5
The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
17.6
Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
17.7
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
18.1
PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
18.2
PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 66
18.3
Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
18.4
MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
18.5
80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
18.6
MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
18.7
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
18.8
H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
18.9
MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
18.10 C16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
19
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
19.1
General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
19.2
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
19.3
MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
19.4
PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
19.5
Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
19.6
Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
19.7
Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
19.8
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
19.9
JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
19.10 MCU Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
19.11 Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
19.12 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
19.13 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
19.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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PSD4235G2V
19.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19.18 Mask macrocell register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
19.21 Ports A, B and C - functionality and structure . . . . . . . . . . . . . . . . . . . . . 84
19.22 Port D - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
19.23 Port E - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
19.24 Port F - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
19.25 Port G - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
20
21
22
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.1
Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 90
20.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
20.3
Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
20.4
PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
20.5
PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
20.6
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
20.7
Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Power-on Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . 94
21.1
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
21.2
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
21.3
I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 94
21.4
Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 94
Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 96
22.1
Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
22.2
JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
22.3
Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
23
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
24
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
25
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Contents
26
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
27
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7/124
List of tables
PSD4235G2V
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/124
Pin names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
JTAG signals on port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 19
Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data-In registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data-Out registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Direction registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Control registers - Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Drive registers - Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Enable-Out registers - Ports A, B, C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input macrocell registers - Port A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output macrocells A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output macrocells B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mask macrocells A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mask macrocells B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory_ID0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status bits for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Output macrocell Port and Data bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
16-bit data bus with BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16-bit data bus with WRH and WRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
16-bit data bus with SIZ0, A0 (Motorola MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
16-bit data bus with LDS, UDS (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port Pin Direction Control, output Enable P.T. not defined. . . . . . . . . . . . . . . . . . . . . . . . . 82
Port Pin Direction Control, output Enable P.T. defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Effect of Power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 91
PSD4235G2V
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
List of tables
APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Status During Power-On Reset, Warm Reset and Power-down mode. . . . . . . . . . . . . . . . 94
JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode on) . . . . . . 102
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode off) . . . . . . 103
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
AC signal letters for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
AC signal behavior symbols for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
CPLD Combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
CPLD macrocell Synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
CPLD macrocell Asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Input macrocell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Program, WRITE and Erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Port F Peripheral Data Mode Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Port F Peripheral Data Mode Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . . . . 119
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PSD4235G2V LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9/124
List of figures
PSD4235G2V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
10/124
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LQFP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PSDsoft Express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8031 memory modules - separate space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8031 memory modules - combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Macrocell and I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
CPLD output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External Chip Select signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
An example of a typical 16-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . 65
An example of a typical 16-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . 66
Interfacing the PSD with an 80C196. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interfacing the PSD with an MC68331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interfacing the PSD with an 80C51XA-G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interfacing the PSD with an H83/2350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interfacing the PSD with an MMC2001. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interfacing the PSD with a C167CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port A, B and C structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Port E, F and G structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Enable Power-down flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PLD ICC /frequency consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Switching waveforms - key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Input to output Disable/Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Synchronous clock mode timing - PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Asynchronous RESET / Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Asynchronous clock mode timing (product term clock). . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Peripheral I/O write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Peripheral I/O read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PSD4235G2V
Figure 49.
List of figures
LQFP80 - 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 119
11/124
Description
1
PSD4235G2V
Description
The PSD family of memory systems for microcontrollers (MCUs) brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and
flexible solution for embedded designs. PSD devices combine many of the peripheral
functions found in MCU based applications.
PSD devices integrate an optimized macrocell logic architecture. The macrocell was created
to address the unique requirements of embedded system designs. It allows direct
connection between the system address/data bus, and the internal PSD registers, to
simplify communication between the MCU and other supporting devices.
The PSD family offers two methods to program the PSD Flash memory while the PSD is
soldered to the circuit board:
1.1
In-system programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG in-system programming (ISP) interface is included on the
PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation, which
means the PSD can be programmed anytime, even when completely blank.
The innovative JTAG interface to Flash memories is an industry first, solving key problems
faced by designers and manufacturing houses, such as:
1.1.1
First time programming
How do I get firmware into the Flash memory the very first time? JTAG is the answer.
Program the blank PSD with no MCU involvement.
1.1.2
Inventory build-up of pre-programmed devices
How do I maintain an accurate count of pre-programmed Flash memory and PLD devices
based on customer demand? How many and what version? JTAG is the answer. Build your
hardware with blank PSDs soldered directly to the board and then custom program just
before they are shipped to the customer. No more labels on chips, and no more wasted
inventory.
1.1.3
Expensive sockets
How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer.
Solder the PSD directly to the circuit board. Program first time and subsequent times with
JTAG. No need to handle devices and bend the fragile leads.
1.2
In-application programming (IAP)
Two independent Flash memory arrays are included so that the MCU can execute code from
one while erasing and programming the other. Robust product firmware updates in the filed
are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this
unique architecture. Designers are relieved of these problems:
12/124
PSD4235G2V
1.2.1
Description
Simultaneous READ and WRITE to Flash memory
How can the MCU program the same memory from which it executing code? It cannot. The
PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code
from one while erasing and programming the other during IAP.
1.2.2
Complex memory mapping
How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is
embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU
address space, segment by segment with extremely high address resolution. As an option,
the secondary Flash memory can be swapped out of the system memory map when IAP is
complete. A built-in page register breaks the MCU address limit.
1.2.3
Separate Program and Data space
How can I write to Flash memory while it resides in Program space during field firmware
updates? My 80C51XA will not allow it. The PSD provides means to reclassify Flash
memory as Data space during IAP, then back to Program space when complete.
1.3
PSDsoft™ Express
PSDsoft Express, a software development tool from ST, guides you through the design
process step-by-step making it possible to complete an embedded MCU design capable of
ISP/IAP in just hours. Select your MCU and PSDsoft Express takes you through the
remainder of the design with point and click entry, covering PSD selection, pin definitions,
programmable logic inputs and outputs, MCU memory map definition, ANSI-C code
generation for your MCU, and merging your MCU firmware with the PSD design. When
complete, two different device programmers are supported directly from PSDsoft Express:
FlashLINK (JTAG) and PSDpro.
13/124
Description
PSD4235G2V
Figure 1.
Logic diagram
VCC
8
PA0-PA7
8
PB0-PB7
3
8
CNTL0CNTL2
PC0-PC7
4
PD0-PD3
PSD4xxxGx
8
16
PE0-PE7
AD0-AD15
8
PF0-PF7
RESET
8
PG0-PG7
VSS
Table 1.
AI04916
Pin names
Pin
14/124
Description
PA0-PA7
Port-A
PB0-PB7
Port-B
PC0-PC7
Port-C
PD0-PD3
Port-D
PE0-PE7
Port-E
PF0-PF7
Port-F
PG0-PG7
Port-G
AD0-AD15
Address/Data
CNTL0-CNTL2
Control
RESET
Reset
PSD4235G2V
Description
Pin names (continued)
Pin
Description
VCC
Supply voltage
VSS
Ground
61 PB0
62 PB1
63 PB2
65 PB4
66 PB5
67 PB6
69 VCC
68 PB7
70 GND
71 PE0
72 PE1
73 PE2
74 PE3
75 PE4
76 PE5
77 PE6
78 PE7
79 PD0
LQFP connections
80 PD1
Figure 2.
64 PB3
Table 1.
PD2 1
60 CNTL1
PD3 2
59 CNTL0
AD0 3
58 PA7
AD1 4
57 PA6
AD2 5
56 PA5
AD3 6
55 PA4
AD4 7
54 PA3
GND 8
53 PA2
VCC 9
AD5 10
52 PA1
AD6 11
50 GND
AD7 12
49 GND
AD8 13
48 PC7
AD9 14
47 PC6
AD10 15
46 PC5
AD11 16
45 PC4
AD12 17
44 PC3
AD13 18
43 PC2
AD14 19
42 PC1
AD15 20
41 PC0
CNTL2 40
RESET 39
PF7 38
PF6 37
PF5 36
PF4 35
PF3 34
PF2 33
PF1 32
PF0 31
VCC 29
GND 30
PG7 28
PG6 27
PG5 26
PG4 25
PG3 24
PG2 23
PG1 22
PG0 21
51 PA0
AI04943
15/124
16/124
1. Additional address lines can be brought in to the device via Port A, B, C, D or F.
PG0 – PG7
PF0 – PF7
CLKIN
PORT
G
PROG.
PORT
PORT
F
PROG.
PORT
ADIO
PORT
PROG.
MCU BUS
INTRF.
CLKIN
82
8
CSIOP
GLOBAL
CONFIG. &
SECURITY
CLKIN
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MACROCELLS
PORT A & B
16 OUTPUT MACROCELLS
8 EXT CS TO PORT C or F
PORT F
64 KBIT SRAM
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
16 SECTORS
4 MBIT PRIMARY
FLASH MEMORY
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
FLASH ISP CPLD
(CPLD)
FLASH DECODE
PLD (DPLD)
SECTOR
SELECTS
EMBEDDED
ALGORITHM
MACROCELL FEEDBACK OR PORT INPUT
82
PAGE
REGISTER
PORT
E
PROG.
PORT
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
PE0 – PE7
PD0 – PD3
PC0 – PC7
PB0 – PB7
PA0 – PA7
Figure 3.
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
PLD
INPUT
BUS
ADDRESS/DATA/CONTROL BUS
Description
PSD4235G2V
PSD block diagram
AI04990b
PSD4235G2V
2
PSD architectural overview
PSD architectural overview
PSD devices contain several major functional blocks. Figure 3 shows the architecture of the
PSD device family. The functions of each block are described briefly in the following
sections. Many of the blocks perform multiple functions and are user configurable.
2.1
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed
discussion can be found in Section 6.1: Memory blocks on page 31.
The 4 Mbit primary Flash memory is the main memory of the PSD. It is divided into 8
equally-sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into 4 equally-sized sectors. Each sector
is individually selectable.
The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the
MCU SRAM.
Each memory block can be located in a different address space as defined by the user. The
access times for all memory types includes the address latching and DPLD decoding time.
2.2
PLDs
The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD
(CPLD), as shown in Table 2, each optimized for a different function. The functional
partitioning of the PLDs reduces power consumption, optimizes cost/performance, and
eases design entry.
The DPLD is used to decode addresses and to generate Sector Select signals for the PSD
internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can
implement more general user-defined logic functions. The CPLD has 16 output macrocells
(OMC) and 8 combinatorial outputs. The PSD also has 24 input macrocells (IMC) that can
be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD input Bus
and are differentiated by their output destinations, number of product terms, and macrocells.
The PLDs consume minimal power. The speed and power consumption of the PLD is
controlled by the Turbo bit in PMMR0 and other bits in PMMR2. These registers are set by
the MCU at run-time. There is a slight penalty to PLD propagation time when not in the
Turbo mode.
2.3
I/O ports
The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O
pin can be individually configured for different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed
address/data buses
The JTAG pins can be enabled on Port E for in-system programming (ISP).
17/124
PSD architectural overview
2.4
PSD4235G2V
MCU bus interface
The PSD easily interfaces easily with most 16-bit MCUs, either with multiplexed or nonmultiplexed address/data buses. The device is configured to respond to the MCU’s control
pins, which are also used as inputs to the PLDs.
2.5
ISP via JTAG port
In-System Programming (ISP) can be performed through the JTAG signals on Port E. This
serial interface allows complete programming of the entire PSD device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port E. Table 3 indicates the JTAG pin assignments.
Table 2.
PLD I/O
Name
Inputs
Outputs
Product Terms
Decode PLD (DPLD)
82
17
43
Complex PLD (CPLD)
82
24
150
Table 3.
JTAG signals on port E
Port E pins
2.6
JTAG signal
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
In-system programming (ISP)
Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can
be programmed or erased without the use of the MCU.
2.7
In-application programming (IAP)
The primary Flash memory can also be programmed, or re-programmed, in-system by the
MCU executing the programming algorithms out of the secondary Flash memory, or SRAM.
The secondary Flash memory can be programmed the same way by executing out of the
primary Flash memory. Table 4 indicates which programming methods can program
different functional blocks of the PSD.
18/124
PSD4235G2V
2.8
PSD architectural overview
Page register
The 8-bit Page register expands the address range of the MCU by up to 256 times. The
paged address can be used as part of the address space to access external memory and
peripherals, or internal memory and I/O. The Page register can also be used to change the
address mapping of the Flash memory blocks into different memory spaces for IAP.
2.9
Power management unit (PMU)
The power management unit (PMU) gives the user control of the power consumption on
selected functional blocks based on system requirements. The PMU includes an Automatic
Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit
has a Power-down mode that helps reduce power consumption.
The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in PMMR0 can be reset to ’0’ and the CPLD latches
its outputs and goes to Standby mode until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. See Section 20: Power management on page 89 for more
details.
Table 4.
Methods of programming different functional blocks of the PSD
JTAG-ISP
Device
programmer
IAP
Primary Flash memory
Yes
Yes
Yes
Secondary Flash memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD configuration
Yes
Yes
No
Functional block
19/124
Development system
3
PSD4235G2V
Development system
The PSD family is supported by PSDsoft Express, a Windows-based software development
tool (Windows-95, Windows-98, Windows-2000, Windows-NT). A PSD design is quickly and
easily produced in a point and click environment. The designer does not need to enter
Hardware Description Language (HDL) equations, unless desired, to define PSD pin
functions and memory map information. The general design flow is shown in Figure 4.
PSDsoft Express is available from our web site (the address is given on the back page of
this data sheet) or other distribution channels.
PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers may be purchased through your local
distributor/representative, or directly from our web site using a credit card. The PSD is also
supported by third party device programmers. See our web site for the current list.
20/124
PSD4235G2V
Figure 4.
Development system
PSDsoft Express development tool
Choose MCU and PSD
Automatically configures MCU
bus interface and other
PSD attributes
Define PSD Pin and
Node Functions
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map
Define General Purpose
Logic in CPLD
C Code Generation
Point and click definition of combinatorial and registered logic in CPLD.
Access HDL is available if needed
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
PSD Programmer
PSDPro, or
FlashLINK (JTAG)
*.OBJ FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
AI04919
21/124
PSD register description and address offsets
4
PSD4235G2V
PSD register description and address offsets
Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD registers. Table 5 provides brief descriptions of the registers in CSIOP space.
The following sections give a more detailed description.
Table 5.
Register address offset
Register name
Data In
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
00
01
10
11
30
40
41
Reads Port pin as input, MCU I/O
input mode
32
42
43
Selects mode between MCU I/O or
Address Out
Control
Port
Other(1)
G
Description
Data Out
04
05
14
15
34
44
45
Stores data for output to Port pins,
MCU I/O output mode
Direction
06
07
16
17
36
46
47
Configures Port pin as input or output
Drive Select
08
09
18
19
38
48
49
Configures Port pins as either CMOS
or Open Drain on some pins, while
selecting high slew rate on other pins.
Input macrocell
0A
0B
Enable Out
0C
0D
Output
macrocells A
20
Output
macrocells B
Mask
macrocells A
Mask
macrocells B
1A
1C
Reads input macrocells
Reads the status of the output enable
to the I/O Port driver
4C
READ - reads output of macrocells A
WRITE - loads macrocell Flip-flops
READ - reads output of macrocells B
WRITE - loads macrocell Flip-flops
21
Blocks writing to the output macrocells
A
22
Blocks writing to the output macrocells
B
23
Flash Memory
Protection
C0
Read only - Primary Flash Sector
Protection
Flash Boot
Protection
C2
Read only - PSD Security and
secondary Flash memory Sector
Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management register 0
PMMR2
B4
Power Management register 2
Page
E0
Page register
VM
E2
Places PSD memory areas in
Program and/or Data space on an
individual basis.
22/124
PSD4235G2V
Table 5.
PSD register description and address offsets
Register address offset (continued)
Register name
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
Port
Other(1)
G
Description
Memory_ID0
F0
Read only - SRAM and primary
memory size
Memory_ID1
F1
Read only - Secondary memory type
and size
1. Other registers that are not part of the I/O ports.
23/124
Register bit definition
5
PSD4235G2V
Register bit definition
All the registers of the PSD are included here, for reference. Detailed descriptions of these
registers can be found in the following sections.
5.1
Data-In registers - port A, B, C, D, E, F, G
Read Port pin status when Port is in MCU I/O input mode.
Read-only registers.
Table 6.
5.2
Data-In registers - Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Data-out registers - port A, B, C, D, E, F, G
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 7.
5.3
Data-Out registers - Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Direction registers - ports A, B, C, D, E, F, G
Table 8.
Direction registers - Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin <i>:
0: Port pin <i> is configured in input mode (default).
1: Port pin <i> is configured in output mode.
5.4
Control registers
Table 9.
Control registers - Ports E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin <i>:
0: Port pin <i> is configured in MCU I/O mode (default).
1: Port pin <i> is configured in Latched Address Out mode.
24/124
PSD4235G2V
5.5
Register bit definition
Drive registers - Ports A, B, D, E, G
Table 10.
Drive registers - Ports A, B, D, E, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin <i>:
0: Port pin <i> is configured for CMOS output driver (default).
1: Port pin <i> is configured for Open Drain output driver.
5.6
Drive registers - Ports C and F
Table 11.
Drive registers - Ports C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin <i>:
0: Port pin <i> is configured for CMOS output driver (default).
1: Port pin <i> is configured in Slew Rate mode.
5.7
Enable-Out registers - Ports A, B, C, F
Read-only registers
Table 12.
Enable-Out registers - Ports A, B, C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin <i>:
0: Port pin <i> is in tri-state driver (default).
1: Port pin <i> is enabled.
5.8
Input macrocells registers- ports A, B, C
Read input macrocell (IMC7-IMC0) status on Ports A, B and C.
Read-only registers
Table 13.
Input macrocell registers - Port A, B, C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
25/124
Register bit definition
5.9
PSD4235G2V
Output macrocells A/B registers
Write register: Load MCellA7-MCellA0/MCellB7-MCellB0 with 0 or 1.
Read register: Read MCellA7-MCellA0/MCellB7-MCellB0 output status.
Table 14.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Table 15.
5.10
Output macrocells A register
Bit 7
Output macrocells B register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Mask macrocells A/B registers
Table 16.
Mask macrocells A register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Table 17.
Mask macrocells B register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
McellA<i>_Prot:
0: Allow MCellA<i>/MCellB<i> flip-flop to be loaded by MCU (default).
1: Prevent MCellA<i>/MCellB<i> flip-flop from being loaded by MCU.
5.11
Flash Memory Protection register
Read-only register
Table 18.
Bit 7
Flash Memory Protection register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Sec<i>_Prot:
1: Primary Flash memory Sector <i> is write protected.
0: Primary Flash memory Sector <i> is not write protected.
26/124
PSD4235G2V
5.12
Register bit definition
Flash Boot Protection register
Table 19.
Flash Boot Protection register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_
Bit
not used
not used
not used
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Sec<i>_Prot:
1: Secondary Flash memory Sector <i> is write protected.
0: Secondary Flash memory Sector <i> is not write protected.
Security_Bit:
0: Security bit in device has not been set.
1: Security bit in device has been set.
5.13
JTAG Enable register
Table 20.
JTAG Enable register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
not used
not used
not used
not used
not used
JTAG
Enable
JTAGEnable:
1: JTAG Port is enabled.
0: JTAG Port is disabled.
5.14
Page register
This register configures the page input to PLD.
Default value is PGR7-PGR0=0.
Table 21.
5.15
Page register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
PMMR0 register
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET)
pulses do not clear the registers.
Table 22.
PMMR0 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
not used
(set to ’0’)
PLD
MCells
CLK
PLD
Array CLK
PLD
Turbo
not used
(set to ’0’)
APD
Enable
not used
(set to ’0’)
27/124
Register bit definition
PSD4235G2V
APD Enable:
0: Automatic Power-down (APD) is disabled.
1: Automatic Power-down (APD) is enabled.
PLD Turbo:
0: PLD Turbo is on.
1: PLD Turbo is off, saving power.
PLD Array CLK:
0: CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD
when Turbo bit is off.
1: CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK:
0: CLKIN to the PLD macrocells is connected.
1: CLKIN to the PLD macrocells is disconnected, saving power.
5.16
PMMR2 register
Table 23.
PMMR2 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
PLD
Array
WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to ’0’)
PLD
Array Addr
For bit 4, bit 3, bit 2: See Table 33 for the signals that are blocked on pins CNTL0-CNTL2.
PLD Array Addr:
0: Address A7-A0 are connected to the PLD array.
1 Address A7-A0 are blocked from the PLD array, saving power.
Note:
In XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4).
PLD Array CNTL2:
0: CNTL2 input to the PLD AND array is connected.
1: CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1
0: CNTL1 input to the PLD AND array is connected.
1: CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0
0: CNTL0 input to the PLD AND array is connected.
1: CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE
0: ALE input to the PLD AND array is connected.
1: ALE input to the PLD AND array is disconnected, saving power.
28/124
PSD4235G2V
Register bit definition
PLD Array WRH
0: WRH/DBE input to the PLD AND array is connected.
1: WRH/DBE input to the PLD AND array is disconnected, saving power.
5.17
VM register
Table 24.
VM register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Peripheral
mode
not used
(set to ’0’)
not used
(set to ’0’)
FL_data
Boot_data
FL_code
Boot_code SR_code
On reset, bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft
Express. bit0 and bit7 are always cleared on reset. bit0-Bit4 are active only when the device
is configured in Philips 80C51XA mode.
SR_code
0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code
0 = PSEN cannot access secondary NVM in 80C51XA modes.
1 = PSEN can access secondary NVM in 80C51XA modes.
FL_code
0 = PSEN cannot access primary Flash memory in 80C51XA modes.
1 = PSEN can access primary Flash memory in 80C51XA modes.
Boot_data
0 = RD cannot access secondary NVM in 80C51XA modes.
1 = RD can access secondary NVM in 80C51XA modes.
FL_data
0 = RD cannot access primary Flash memory in 80C51XA modes.
1 = RD can access primary Flash memory in 80C51XA modes.
Peripheral mode
0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
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Register bit definition
5.18
PSD4235G2V
Memory_ID0 registers
Table 25.
Memory_ID0 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
F_size[3:0]
0h = There is no primary Flash memory
1h: Primary Flash memory size is 256 Kbit
2h: Primary Flash memory size is 512 Kbit
3h = Primary Flash memory size is 1 Mbit
4h = Primary Flash memory size is 2 Mbit
5h = Primary Flash memory size is 4 Mbit
6h = Primary Flash memory size is 8 Mbit
S_size[3:0]
0h = There is no SRAM
1h = SRAM size is 16 Kbit
2h = SRAM size is 32 Kbit
3h = SRAM size is 64 Kbit
4h = SRAM size is 128 Kbit
5h = SRAM size is 256 Kbit
5.19
Memory_ID1 register
Table 26.
Memory_ID1 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
not used
(set to ’0’)
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
B_size[3:0]
0h = There is no secondary NVM
1h = Secondary NVM size is 128 Kbit
2h = Secondary NVM size is 256 Kbit
3h = Secondary NVM size is 512 Kbit
B_type[1:0]
0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
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PSD4235G2V
6
Detailed operation
Detailed operation
As shown in Figure 3, the PSD consists of six major types of functional blocks:
●
Memory blocks
●
PLD blocks
●
MCU bus Interface
●
I/O ports
●
Power management unit (PMU)
●
JTAG-ISP interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
6.1
Memory blocks
The PSD has the following memory blocks:
●
Primary Flash memory
●
Secondary Flash memory
●
SRAM
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft Express.
Table 27 summarizes the sizes and organizations of the memory blocks.
Table 27.
Memory block size and organization
Primary Flash Memory
Sector
number
Secondary Flash Memory
SRAM
Sector size
(x16,
Kbytes)
Sector
Select
signal
Sector size
(x16,
Kbytes)
Sector
Select
signal
SRAM size
(x16,
Kbytes)
SRAM
Select
signal
0
32
FS0
4
CSBOOT0
4
RS0
1
32
FS1
4
CSBOOT1
2
32
FS2
4
CSBOOT2
3
32
FS3
4
CSBOOT3
4
32
FS4
5
32
FS5
6
32
FS6
7
32
FS7
Total
512 Kbytes
8 sectors
32 Kbytes
4 sectors
8 Kbytes
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Detailed operation
6.2
PSD4235G2V
Primary Flash memory and secondary Flash memory
description
The primary Flash memory is divided evenly into 8 sectors. The secondary Flash memory is
divided evenly into 4 sectors. Each sector of either memory block can be separately
protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis, and programmed word-by-word.
Flash sector erasure may be suspended while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory, the status can be output on the
Ready/Busy pin (PE4). This pin is set up using PSDsoft Express.
6.2.1
Memory block Select signals
The DPLD generates the Select signals for all the internal memory blocks (see Section 15:
PLDS). Each of the sectors of the primary Flash memory has a Select signal (FS0-FS7)
which can contain up to three product terms. Each of the sectors of the secondary Flash
memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select signal allows a given sector to be
mapped in different areas of system memory. When using a MCU with separate Program
and Data space (80C51XA), these flexible Select signals allow dynamic re-mapping of
sectors from one memory space to the other before and after IAP. The SRAM block has a
single Select signal (RS0).
6.2.2
Ready/Busy (PE4)
This signal can be used to output the Ready/Busy status of the PSD. The output is a ’0’
(Busy) when a Flash memory block is being written to, or when a Flash memory block is
being erased. The output is a ’1’ (Ready) when no WRITE or Erase cycle is in progress.
6.3
Memory operation
The primary Flash memory and secondary Flash memory are addressed through the MCU
Bus Interface. The MCU can access these memories in one of two ways:
●
The MCU can execute a typical bus WRITE or READ operation just as it would if
accessing a RAM or ROM device using standard bus cycles.
●
The MCU can execute a specific instruction that consists of several WRITE and READ
operations. This involves writing specific data patterns to special addresses within the
Flash memory to invoke an embedded algorithm. These instructions are summarized in
Table 28.
Typically, the MCU can read Flash memory using READ operations, just as it would read a
ROM device. However, Flash memory can only be erased and programmed using specific
instructions. For example, the MCU cannot write a single byte directly to Flash memory as
one would write a byte to RAM. To program a word into Flash memory, the MCU must
execute a Program instruction, then test the status of the Programming event. This status
test is achieved by a READ operation or polling Ready/Busy (PE4).
Flash memory can also be read by using special instructions to retrieve particular Flash
device information (sector protect status and ID).
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PSD4235G2V
Table 28.
Detailed operation
Instructions(1)(2)(3)
FS0-FS7 or
CSBOOT0CSBOOT3(5)
Cycle 1
READ(6)
1
“Read”
RD @ RA
Read Main Flash ID(7)
1
Read Sector
Protection(7)(8)
Instruction(4)
Cycle 2
Cycle 3
AAh@
XAAAh
55h@
X554h
90h@
XAAAh
Read ID
@ XX02h
1
AAh@
XAAAh
55h@
X554h
90h@
XAAAh
Read 00h
or 01h @
XX04h
1
AAh@
XAAAh
55h@
X554h
A0h@
XAAAh
PD@ PA
Flash Sector
Erase(10)(9)
1
AAh@
XAAAh
55h@
X554h
80h@
XAAAh
Flash Bulk Erase(9)
1
AAh@
XAAAh
55h@
X554h
80h@
XAAAh
Suspend Sector
Erase(11)
1
B0h@
XXXXh
Resume Sector
Erase(12)
1
30h@
XXXXh
Reset(7)
1
F0h@
XXXXh
Unlock Bypass
1
AAh@
XAAAh
55h@
X554h
20h@
XAAAh
Unlock Bypass
Program(13)
1
A0h@
XXXXh
PD@ PA
Unlock Bypass
Reset(14)
1
90h@
XXXXh
00h@
XXXXh
(9)
Program a Flash
Word(9)
Cycle 4
Cycle 5
Cycle 6
Cycle 7
AAh@
XAAAh
55h@
X554h
30h@
SA
30h(10)
@ next
SA
AAh@
XAAAh
55h@
X554h
10h@
XAAAh
1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses, RA = Address of the memory
location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR,
CNTL0). PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to
be erased, or verified, must be Active (High).
3. Only address bits A11-A0 are used in instruction decoding.
4. All WRITE bus cycles in an instruction are byte WRITE to an even address (XA4Ah or X554h). A Flash memory Program
bus cycle writes a word to an even address.
5. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express.
6. No Unlock or instruction cycles are required when the device is in the READ mode.
7. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector
Protection Status, or if the Error Flag bit (DQ5/DQ13) goes high.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active,
and (A1,A0)=(1,0)
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Detailed operation
PSD4235G2V
9. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the
instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the
Sector Protection Status of the primary Flash memory.
10. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector
Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a
Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock
Bypass mode.
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7
Instructions
Instructions
An instruction consists of a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard WRITE operation. The
instruction is executed when the correct number of bytes are properly received and the time
between two consecutive bytes is shorter than the timeout period. Some instructions are
structured to include READ operations after the initial WRITE operations.
The instruction must be followed exactly. Any invalid combination of instruction bytes or
timeout between two consecutive bytes while addressing Flash memory resets the device
logic into READ mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in Table 28:
●
Erase memory by chip or sector
●
Suspend or resume sector erase
●
Program a Word
●
Reset to READ mode
●
Read primary Flash Identifier value
●
Read Sector Protection Status
●
Bypass
These instructions are detailed in Table 28. For efficient decoding of the instructions, the first
two bytes of an instruction are the coded cycles and are followed by an instruction byte or
confirmation byte. The coded cycles consist of writing the data AAh to address XAAAh
during the first cycle and data 55h to address X554h during the second cycle (unless the
Bypass instruction feature is used, as described later). Address signals A15-A12 are Don’t
Care during the instruction WRITE cycles. However, the appropriate Sector Select signal
(FS0-FS7, or CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have the same instruction set (except for Read
Primary Flash Identifier). The Sector Select signals determine which Flash memory is to
receive and execute the instruction. The primary Flash memory is selected if any one of its
Sector Select signals (FS0-FS7) is high, and the secondary Flash memory is selected if any
one of its Sector Select signals (CSBOOT0-CSBOOT3) is high.
7.1
Power-up condition
The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7
and CSBOOT0-CSBOOT3) must be held low, and Write Strobe (WR/WRL, CNTL0) high,
during Power-up for maximum security of the data contents and to remove the possibility of
data being written on the first edge of Write Strobe (WR/WRL, CNTL0). Any WRITE cycle
initiation is locked when VCC is below VLKO.
35/124
Instructions
7.2
PSD4235G2V
Reading Flash memory
Under typical conditions, the MCU may read the primary Flash memory, or secondary Flash
memory, using READ operations just as it would a ROM or RAM device. Alternately, the
MCU may use READ operations to obtain status information about a Program or Erase
cycle that is currently in progress. Lastly, the MCU may use instructions to read special data
from these memory blocks. The following sections describe these READ functions.
7.3
Read memory contents
Primary Flash memory and secondary Flash memory are placed in the READ mode after
Power-up, chip reset, or a Reset Flash instruction (see Table 28). The MCU can read the
memory contents of the primary Flash memory, or the secondary Flash memory by using
READ operations any time the READ operation is not part of an instruction.
7.4
Read Primary Flash identifier
The primary Flash memory identifier is read with an instruction composed of 4 operations: 3
specific WRITE operations and a READ operation (see Table 28). The identifier for the
primary Flash memory is E8h. The secondary Flash memory does not support this
instruction.
7.5
Read Memory Sector Protection status
The Flash memory Sector Protection Status is read with an instruction composed of four
operations: three specific WRITE operations and a READ operation (see Table 28). The
READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector
is not protected.
The sector protection status for all NVM blocks (primary Flash memory, or secondary Flash
memory) can be read by the MCU accessing the Flash Protection and Flash Boot Protection
registers in PSD I/O space. See Section 10.1: Flash Memory Sector Protect, for register
definitions.
7.6
Reading the Erase/Program status bits
The PSD provides several status bits to be used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU
spends performing these tasks and are defined in Table 29. The status byte resides in an
even location, and can be read as many times as needed. Also note that DQ15-DQ8 is an
even byte for Motorola MCUs with a 16-bit data bus.
For Flash memory, the MCU can perform a READ operation to obtain these status bits while
an Erase or Program instruction is being executed by the embedded algorithm. See
Section 8: Programming Flash memory, for details.
36/124
PSD4235G2V
Instructions
Table 29.
Status bits
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Data
Polling
Toggle
Flag
Error Flag
X
Erase
timeout
X
X
X
Table 30.
Status bits for Motorola(1)(2)(3)
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Data
Polling
Toggle
Flag
Error Flag
X
Erase
timeout
X
X
X
1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ15-DQ0 represent the Data Bus bits, D15-D0.
3. FS0-FS7/CSBOOT0-CSBOOT3 are active high.
7.7
Data Polling (DQ7) - DQ15 for Motorola
When erasing or programming in Flash memory, the Data Polling bit (DQ7/DQ15) outputs
the complement of the bit being entered for programming/writing on the DQ7/DQ15 bit.
Once the Program instruction or the WRITE operation is completed, the true logic value is
read on the Data Polling bit (DQ7/DQ15, in a READ operation).
7.8
●
Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after
the sixth WRITE pulse (for an Erase instruction). It must be performed at the address
being programmed or at an address within the Flash memory sector being erased.
●
During an Erase cycle, the Data Polling bit (DQ7/DQ15) outputs a '0.' After completion
of the cycle, the Data Polling bit (DQ7/DQ15) outputs the last bit programmed (it is a ’1’
after erasing).
●
If the location to be programmed is in a protected Flash memory sector, the instruction
is ignored.
●
If all the Flash memory sectors to be erased are protected, the Data Polling bit
(DQ7/DQ15) is reset to ’0’ for about 100 µs, and then returns to the value from the
previously addressed location. No erasure is performed.
Toggle flag (DQ6) - DQ14 for Motorola
The PSD offers another way for determining when the Flash memory Program cycle is
completed. During the internal WRITE operation and when either FS0-FS7 or CSBOOT0CSBOOT3 is true, the Toggle Flag bit (DQ6/DQ14) bit toggles from 0 to ’1’ and 1 to ’0’ on
subsequent attempts to read any word of the memory.
When the internal cycle is complete, the toggling stops and the data read on the Data Bus
D0-D7 is the value from the addressed memory location. The device is now accessible for a
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Instructions
PSD4235G2V
new READ or WRITE operation. The cycle is finished when two successive READs yield the
same output data.
7.9
●
The Toggle Flag bit (DQ6/DQ14) is effective after the fourth WRITE pulse (for a
Program instruction) or after the sixth WRITE pulse (for an Erase instruction).
●
If the location to be programmed belongs to a protected Flash memory sector, the
instruction is ignored.
●
If all the Flash memory sectors selected for erasure are protected, the Toggle Flag bit
(DQ6/DQ14) toggles to ’0’ for about 100 µs and then returns to the value from the
previously addressed location.
Error flag (DQ5) - DQ13 for Motorola
During a normal Program or Erase cycle, the Error Flag bit (DQ5/DQ13) is reset to '0.' This
bit is set to ’1’ when there is a failure during a Flash memory Program, Sector Erase, or Bulk
Erase cycle.
In the case of Flash memory programming, the Error Flag bit (DQ5/DQ13) indicates the
attempt to program a Flash memory bit, or bits, from the programmed state, 0, to the erased
state, 1, which is not a valid operation. The Error Flag bit (DQ5/DQ13) may also indicate a
timeout condition while attempting to program a word.
In case of an error in a Flash memory Sector Erase or Word Program cycle, the Flash
memory sector in which the error occurred or to which the programmed location belongs
must no longer be used. Other Flash memory sectors may still be used. The Error Flag bit
(DQ5/DQ13) is reset after a Reset instruction. A Reset instruction is required after detecting
an error on the Error Flag bit (DQ5/DQ13).
7.10
Erase timeout flag (DQ3) - DQ11 for Motorola
The Erase timeout Flag bit (DQ3/DQ11) reflects the timeout period allowed between two
consecutive Sector Erase instructions. The Erase timeout Flag bit (DQ3/DQ11) is reset to ’0’
after a Sector Erase cycle for a period of 100 µs + 20% unless an additional Sector Erase
instruction is decoded. After this period, or when the additional Sector Erase instruction is
decoded, the Erase timeout flag (DQ3/DQ11) bit is set to 1.
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PSD4235G2V
8
Programming Flash memory
Programming Flash memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. Although erasing Flash memory occurs on a sector or
device basis, programming Flash memory occurs on a word basis.
The primary and secondary Flash memories require the MCU to send an instruction to
program a word or to erase sectors (see Table 28).
Once the MCU issues a Flash memory Program or Erase instruction, it must check the
status bits for completion. The embedded algorithms that are invoked inside the PSD
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or Ready/Busy (PE4) signal.
8.1
Data polling
Polling on the Data Polling bit (DQ7/DQ15) is a method of checking whether a Program or
Erase cycle is in progress or has completed. Figure 5 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the word to be programmed in Flash memory to
check the status. The Data Polling bit (DQ7/DQ15) becomes the complement of the
corresponding bit of the original data word to be programmed. The MCU continues to poll
this location, comparing data and monitoring the Error Flag bit (DQ5/DQ13). When the Data
Polling bit (DQ7/DQ15) matches the corresponding bit of the original data, and the Error
Flag bit (DQ5/DQ13) remains 0, the embedded algorithm is complete. If the Error Flag bit
(DQ5/DQ13) is 1, the MCU should test the Data Polling bit (DQ7/DQ15) again since the
Data Polling bit (DQ7/DQ15) may have changed simultaneously with the Error Flag bit
(DQ5/DQ13, see Figure 5).
The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the
embedded algorithm attempted to program the location or if the MCU attempted to program
a ’1’ to a bit that was not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the word that was written to the Flash
memory with the word that was intended to be written.
When using the Data Polling method during an Erase cycle, Figure 5 still applies. However,
the Data Polling bit (DQ7/DQ15) is 0 until the Erase cycle is complete. A '1' on the Error Flag
bit (DQ5/DQ13) indicates a timeout condition on the Erase cycle, a ’0’ indicates no error.
The MCU can read any even location within the sector being erased to get the Data Polling
bit(DQ7/DQ15) and the Error Flag bit (DQ5/DQ13).
PSDsoft Express generates ANSI C code functions that implement these Data Polling
algorithms.
39/124
Programming Flash memory
Figure 5.
PSD4235G2V
Data polling flowchart
START
READ DQ5 and DQ7
(DQ13 and DQ15)
at Valid Even Address
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
No
DQ5
(DQ13)
=1
Yes
READ DQ7
(DQ15)
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
Issue RESET
instruction
AI04920
8.2
Data toggle
Checking the Toggle Flag bit (DQ6/DQ14) is another method of determining whether a
Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Toggle
algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location to be programmed in Flash memory to check the
status. The Toggle Flag bit (DQ6/DQ14) toggles each time the MCU reads this location until
the embedded algorithm is complete. The MCU continues to read this location, checking the
Toggle Flag bit (DQ6/DQ14) and monitoring the Error Flag bit (DQ5/DQ13). When the
Toggle Flag bit (DQ6/DQ14) stops toggling (two consecutive READs yield the same value),
and the Error Flag bit (DQ5/DQ13) remains 0, the embedded algorithm is complete. If the
Error Flag bit (DQ5/DQ13) is 1, the MCU should test the Toggle Flag bit (DQ6/DQ14) again,
40/124
PSD4235G2V
Programming Flash memory
since the Toggle Flag bit (DQ6/DQ14) may have changed simultaneously with the Error Flag
bit (DQ5/DQ13, see Figure 6).
The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the
embedded algorithm attempted to program, or if the MCU attempted to program a ’1’ to a bit
that was not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the word that was written to Flash
memory with the word that was intended to be written.
When using the Data Toggle method after an Erase cycle, Figure 6 still applies. the Toggle
Flag bit (DQ6/DQ14) toggles until the Erase cycle is complete. A '1' on the Error Flag bit
(DQ5/DQ13) indicates a timeout condition on the Erase cycle, a ’0’ indicates no error. The
MCU can read any even location within the sector being erased to get the Toggle Flag bit
(DQ6/DQ14) and the Error Flag bit (DQ5/DQ13).
PSDsoft Express generates ANSI C code functions which implement these Data Toggling
algorithms.
8.3
Unlock Bypass
The Unlock Bypass instruction allows the system to program words to the Flash memories
faster than using the standard Program instruction. The Unlock Bypass mode is entered by
first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the
Unlock Bypass command, 20h (as shown in Table 28). The Flash memory then enters the
Unlock Bypass mode.
A two-cycle Unlock Bypass Program instruction is all that is required to program in this
mode. The first cycle in this instruction contains the Unlock Bypass Program command,
A0h. The second cycle contains the program address and data. Additional data is
programmed in the same manner. This mode dispense with the initial two Unlock cycles
required in the standard Program instruction, resulting in faster total programming time.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
instructions are valid.
To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset
instruction. The first cycle must contain the data 90h; the second cycle the data 00h.
Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode.
41/124
Programming Flash memory
Figure 6.
PSD4235G2V
Data toggle flowchart
START
READ DQ5 and DQ6
(DQ13 and DQ14)
at Valid Even Address
DQ6
(DQ14)
=
Toggle
No
Yes
No
DQ5
(DQ13)
=1
Yes
READ DQ6
(DQ14)
DQ6
(DQ14)
=
Toggle
No
Yes
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
Issue RESET
instruction
AI04921
42/124
PSD4235G2V
9
Erasing Flash memory
9.1
Flash Bulk Erase
Erasing Flash memory
The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation
of the status register, as described in Table 28. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the Read Memory mode.
During a Bulk Erase, the memory status may be checked by reading the Error Flag bit
(DQ5/DQ13), the Toggle Flag bit (DQ6/DQ14), and the Data Polling bit (DQ7/DQ15), as
detailed in Section 8: Programming Flash memory. The Error Flag bit (DQ5/DQ13) returns a
’1’ if there has been an Erase Failure (maximum number of Erase cycles have been
executed).
It is not necessary to program the memory with 00h because the PSD automatically does
this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory does not accept any
instructions.
Flash Sector Erase
The Sector Erase instruction uses six WRITE operations, as described in Table 28.
Additional Flash Sector Erase confirm commands and Flash memory sector addresses can
be written subsequently to erase other Flash memory sectors in parallel, without further
coded cycles, if the additional commands are transmitted in a shorter time than the timeout
period of about 100 µs. The input of a new Sector Erase command restarts the timeout
period.
The status of the internal timer can be monitored through the level of the Erase timeout Flag
bit (DQ3/DQ11). If the Erase timeout Flag bit (DQ3/DQ11) is 0, the Sector Erase instruction
has been received and the timeout period is counting. If the Erase timeout Flag bit
(DQ3/DQ11) is 1, the timeout period has expired and the PSD is busy erasing the Flash
memory sector(s). Before and during Erase timeout, any instruction other than Suspend
Sector Erase and Resume Sector Erase, abort the cycle that is currently in progress, and
reset the device to READ mode. It is not necessary to program the Flash memory sector
with 00h as the PSD does this automatically before erasing.
During a Sector Erase, the memory status may be checked by reading the Error Flag bit
(DQ5/DQ13), the Toggle Flag bit (DQ6/DQ14), and the Data Polling bit (DQ7/DQ15), as
detailed in Section 8: Programming Flash memory.
During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend
Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order
to read data from another Flash memory sector, and then resumed.
43/124
Erasing Flash memory
9.2
PSD4235G2V
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be
used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector
Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 28). This allows reading of
data from another Flash memory sector after the Erase cycle has been suspended.
Suspend Sector Erase is accepted only during the Flash Sector Erase instruction execution
and defaults to READ mode. A Suspend Sector Erase instruction executed during an Erase
timeout period, in addition to suspending the Erase cycle, terminates the time out period.
The Toggle Flag bit (DQ6/DQ14) stops toggling when the PSD internal logic is suspended.
The status of this bit must be monitored at an address within the Flash memory sector being
erased. The Toggle Flag bit (DQ6/DQ14) stops toggling between 0.1µs and 15 µs after the
Suspend Sector Erase instruction has been executed. The PSD is then automatically set to
READ mode.
If an Suspend Sector Erase instruction was executed, the following rules apply:
9.3
●
Attempting to read from a Flash memory sector that was being erased outputs invalid
data.
●
Reading from a Flash memory sector that was not being erased is valid.
●
The Flash memory cannot be programmed, and only responds to Resume Sector
Erase and Reset instructions (READ is an operation and is allowed).
●
If a Reset instruction is received, data in the Flash memory sector that was being
erased is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be
resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h
to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
is high. (See Table 28.)
44/124
PSD4235G2V
Specific features
10
Specific features
10.1
Flash Memory Sector Protect
Each sector of primary or secondary Flash memory can be separately protected against
Program and Erase cycles. Sector Protection provides additional data security because it
disables all Program or Erase cycles. This mode can be activated (or deactivated) through
the JTAG-ISP Port or a device programmer.
Sector protection can be selected for each sector using the PSDsoft Express program. This
automatically protects selected sectors when the device is programmed through the JTAG
Port or a device programmer. Flash memory sectors can be unprotected to allow updating of
their contents using the JTAG Port or a device programmer. The MCU can read (but cannot
change) the sector protection bits.
Any attempt to program or erase a protected Flash memory sector is ignored by the device.
The Verify operation results in a READ of the protected data. This allows a guarantee of the
retention of the Protection status.
The sector protection status can be read by the MCU through the Flash memory protection
and secondary Flash memory protection registers (in the CSIOP block) or use the Read
Sector Protection instruction. See Table 18 to Table 19.
10.2
Reset
The Reset instruction consists of one WRITE cycle (see Table 28). It can also be optionally
preceded by the standard two WRITE decoding cycles (writing AAh to AAAh, and 55h to
554h).
The Reset instruction must be executed after:
●
Reading the Flash Protection Status or Flash ID
●
An Error condition has occurred (and the device has set the Error Flag bit (DQ5/DQ13)
to ’1’) during a Flash memory Program or Erase cycle.
The Reset instruction immediately puts the Flash memory back into normal READ mode.
However, if there is an error condition (with the Error Flag bit (DQ5/DQ13) set to ’1’) the
Flash memory will return to the READ mode in 25 μs after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Program or Bulk Erase cycle of
the Flash memory. The Reset instruction aborts any on-going Sector Erase cycle, and
returns the Flash memory to the normal READ mode in 25 μs.
10.3
Reset (RESET) pin
A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash
memory to the READ mode. When the reset occurs during a Program or Erase cycle, the
Flash memory takes up to 25 μs to return to the READ mode. It is recommended that the
Reset (RESET) pulse (except for Power-on Reset, as described in Section 21.1) be at least
25μs so that the Flash memory is always ready for the MCU to fetch the bootstrap
instructions after the Reset cycle is complete.
45/124
SRAM
11
PSD4235G2V
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select
(RS0) can contain up to three product terms, allowing flexible memory mapping.
SRAM Select (RS0) is configured using PSDsoft Express.
46/124
PSD4235G2V
12
Memory Select signals
Memory Select signals
The Primary Flash Memory Sector Select (FS0-FS7), Secondary Flash Memory Sector
Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD.
They are defined using PSDsoft Express. The following rules apply to the equations for
these signals:
12.1
●
Primary Flash memory and secondary Flash memory Sector Select signals must not
be larger than the physical sector size.
●
Any primary Flash memory sector must not be mapped in the same memory space as
another Flash memory sector.
●
A secondary Flash memory sector must not be mapped in the same memory space as
another secondary Flash memory sector.
●
SRAM, I/O, and Peripheral I/O spaces must not overlap.
●
A secondary Flash memory sector may overlap a primary Flash memory sector. In
case of overlap, priority is given to the secondary Flash memory sector.
●
SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any
address greater than 9FFFh accesses the primary Flash memory segment 0. You can see
that half of the primary Flash memory segment 0 and one-fourth of secondary Flash
memory segment 0 cannot be accessed in this example. Also note that an equation that
defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid.
Figure 7 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must not overlap. level 1 has the highest priority and level 3 has the lowest.
12.2
Memory Select configuration for MCUs with separate
Program and Data spaces
The 80C51XA and compatible family of MCUs, can be configured to have separate address
spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and
Data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the
PSD can reside in either space or both spaces. This is controlled through manipulation of
the VM register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to have an initial value. It can subsequently
be changed by the MCU so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the Data space at
Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the
secondary Flash memory and primary Flash memory. This is easily done with the VM
47/124
Memory Select signals
PSD4235G2V
register by using PSDsoft Express to configure it for Boot-up and having the MCU change it
when desired.
Table 24 describes the VM register.
Figure 7.
Priority level of memory and I/O components
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
Lowest Priority
12.3
AI02867D
Separate space modes
Program space is separated from Data space. For example, Program Select Enable (PSEN,
CNTL2) is used to access the program code from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and
I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 8).
12.4
Combined space modes
The Program and Data spaces are combined into one memory space that allows the
primary Flash memory, secondary Flash memory, and SRAM to be accessed by either
Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are
set to ’1’ (see Figure 9).
48/124
PSD4235G2V
12.5
Memory Select signals
80C51XA memory map example
See the Application notes for examples.
Figure 8.
8031 memory modules - separate space
DPLD
Primary
Flash
Memory
RS0
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI02869C
Figure 9.
8031 memory modules - combined space
DPLD
RD
RS0
Primary
Flash
Memory
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
AI02870C
49/124
Page register
13
PSD4235G2V
Page register
The 8-bit Page register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all eight page register bits are needed for memory
paging, these bits may be used in the CPLD for general logic. See Application Note
AN1154.
Table 5.14 and Figure 10 show the Page register. The eight flip-flops in the register are
connected to the internal data bus (D0-D7). The MCU can write to or read from the Page
register. The Page register can be accessed at address location CSIOP + E0h.
Figure 10. Page register
RESET
D0
D0 - D7
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
PGR0
INTERNAL
SELECTS
AND LOGIC
PGR1
PGR2
PGR3
PGR4
DPLD
AND
CPLD
PGR5
PGR6
PGR7
R/ W
PAGE
REGISTER
50/124
PLD
AI02871B
PSD4235G2V
14
Memory ID registers
Memory ID registers
The 8-bit Read-only Memory Status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0 and
Memory ID1 registers. The content of the registers is defined as shown in Table 25 and
Table 26.
51/124
PLDS
15
PSD4235G2V
PLDS
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for
the PLDs using PSDsoft Express, the logic is programmed into the device and available
upon Power-up.
The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few paragraphs, and in more detail in the following
sections. Figure 11 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory, registers,
and I/O ports Select signals.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The
CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft Express. An input Bus consisting of 82 signals is connected to the PLDs. The
signals are shown in Table 31.
The Turbo bit in PSD
The PLDs in the PSD4235G2V can minimize power consumption by switching to standby
when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit
to ’0’ (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turning the Turbo mode off increases propagation delays while reducing
power consumption. See Section 20: Power management, on how to set the Turbo bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals from
entering the PLDs. This reduces power consumption and can be used only when these
MCU control signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Table 31.
DPLD and CPLD inputs
Input source
52/124
Input name
Number of
signals
MCU address bus(1)
A15-A0
16
MCU control signals
CNTL0-CNTL2
3
Reset
RST
1
Power-down
PDN
1
Port A input macrocells
PA7-PA0
8
Port B input macrocells
PB7-PB0
8
Port C input macrocells
PC7-PC0
8
Port D inputs
PD3-PD0
4
Port F inputs
PF7-PF0
8
PSD4235G2V
Table 31.
PLDS
DPLD and CPLD inputs (continued)
Input source
Input name
Number of
signals
Page register
PGR7-PGR0
8
Macrocell A feedback
MCELLA.FB7-FB0
8
Macrocell B feedback
MCELLB.FB7-FB0
8
Flash memory Program Status bit
Ready/Busy
1
1. The address inputs are A19-A4 in 80C51XA mode.
53/124
54/124
16
1
2
1
3
4
8
CPLD
PT
ALLOC.
OUTPUT MACROCELL FEEDBACK
DECODE PLD
PAGE
REGISTER
24 INPUT MACROCELL
(PORT A,B,C)
INPUT MACROCELL & INPUT PORTS
PORT D and PORT F INPUTS
24
12
MACROCELL
ALLOC.
8
8
MCELLB
TO PORT B
EXTERNAL CHIP SELECTS
TO PORT C or PORT F
8
MCELLA
TO PORT A
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
JTAG SELECT
PERIPHERAL SELECTS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
PRIMARY FLASH MEMORY SELECTS
16 OUTPUT
MACROCELL
DIRECT MACROCELL INPUT TO MCU DATA BUS
82
82
8
I/O PORTS
DATA
BUS
AI05737
PLDS
PSD4235G2V
Figure 11. PLD diagram
PLD INPUT BUS
PSD4235G2V
16
Decode PLD (DPLD)
Decode PLD (DPLD)
The DPLD, shown in Figure 12, is used for decoding the address for internal and external
components. The DPLD can be used to generate the following decode signals:
●
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
●
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
●
1 internal SRAM Select (RS0) signal (three product terms)
●
1 internal CSIOP Select (PSD Configuration register) signal
●
1 JTAG Select signal (enables JTAG-ISP on Port E)
●
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 12. DPLD logic array
(INPUTS)
RT A,B,F)
3
CSBOOT 0
3
CSBOOT 1
3
CSBOOT 2
3
CSBOOT 3
3
FS0
(32)
3
0] (FEEDBACKS)
FS1
(8)
3
0] (FEEDBACKS)
FS2
(8)
3
FS3
(8)
3
FS4
(16)
3
KIN,CSI)
FS5
(4)
3
UT)
FS6
(1)
3
AD/WRITE CONTROL SIGNALS)
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
FS7
(3)
(1)
3
RS0
1
CSIOP
1
PSEL0
1
PSEL1
1
JTAGSEL
(1)
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
AI05738
1. The address inputs are A19-A4 when in 80C51XA mode
2. Additional address lines can be brought into the PSD via Port A, B, C, D, or F.
55/124
Complex PLD (CPLD)
17
PSD4235G2V
Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to
Port C or Port F.
Although External Chip Select (ECS0-ECS7) can be produced by any output macrocell
(OMC), these eight External Chip Select (ECS0-ECS7) on Port C or Port F do not consume
any output macrocells (OMC).
As shown in Figure 11, the CPLD has the following blocks:
●
24 input macrocells (IMC)
●
16 output macrocells (OMC)
●
Product Term Allocator
●
AND Array capable of generating up to 196 product terms
●
Four I/O Ports.
Each of the blocks are described in the sections that follow.
The input macrocells (IMC) and output macrocells (OMC) are connected to the PSD internal
data bus and can be directly accessed by the MCU. This enables the MCU software to load
data into the output macrocells (OMC) or read data from both the input and output
macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
56/124
PSD4235G2V
Complex PLD (CPLD)
Figure 13. Macrocell and I/O port
PLD INPUT BUS
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
CPLD MACROCELLS
PT PRESET
MCU DATA IN
PRODUCT TERM
ALLOCATOR
DATA
LOAD
CONTROL
MCU LOAD
I/O PORTS
LATCHED
ADDRESS OUT
DATA
I/O PIN
D
Q
POLARITY
SELECT
MACROCELL
OUT TO
MCU
CPLD OUTPUT
PR DI LD
D/T
MUX
PT
CLOCK
PLD INPUT BUS
MUX
AND ARRAY
MUX
WR
UP TO 10
PRODUCT TERMS
GLOBAL
CLOCK
SELECT
Q
D/T/JK FF
SELECT
CK
COMB.
/REG
SELECT
PDR
CL
CLOCK
SELECT
INPUT
D
WR
PT CLEAR
Q
DIR
REG.
PT OUTPUT ENABLE (OE)
MUX
INPUT MACROCELLS
I/O PORT INPUT
PT INPUT LATCH GATE/CLOCK
ALE/AS
MUX
MACROCELL FEEDBACK
Q D
Q D
G
AI04945
17.1
Output macrocell (OMC)
Eight of the output macrocells (OMC) are connected to Ports A pins and are named as
McellA0-McellA7. The other eight macrocells are connected to Ports B pins and are named
as McellB0-McellB7.
The output macrocell (OMC) architecture is shown in Figure 14. As shown in the figure,
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other output macrocells (OMC). The polarity of the product term is
controlled by the XOR gate. The output macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the
sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and
has a feedback path to the AND Array inputs.
The flip-flop in the output macrocell (OMC) block can be configured as a D, T, JK, or SR type
in the PSDsoft Express program. The flip-flop’s clock, preset, and clear inputs may be driven
from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be
used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active high inputs. Each clear input can use up to two
product terms.
57/124
Complex PLD (CPLD)
Table 32.
17.2
PSD4235G2V
Output macrocell Port and Data bit Assignments
Assignment
Native
Product
Terms
Maximum
Borrowed
Product
Terms
Data bit for
Loading or
Reading
Motorola 16-Bit
MCU for
Loading or
Reading
McellA0
Port A0
3
6
D0
D8
McellA1
Port A1
3
6
D1
D9
McellA2
Port A2
3
6
D2
D10
McellA3
Port A3
3
6
D3
D11
McellA4
Port A4
3
6
D4
D12
McellA5
Port A5
3
6
D5
D13
McellA6
Port A6
3
6
D6
D14
McellA7
Port A7
3
6
D7
D15
McellB0
Port B0
4
5
D8
D0
McellB1
Port B1
4
5
D9
D1
McellB2
Port B2
4
5
D10
D2
McellB3
Port B3
4
5
D11
D3
McellB4
Port B4
4
6
D12
D4
McellB5
Port B5
4
6
D13
D5
McellB6
Port B6
4
6
D14
D6
McellB7
Port B7
4
6
D15
D7
Output
Port
Macrocell
Product Term Allocator
The CPLD has a Product Term Allocator. PSDsoft Express, uses the Product Term Allocator
to borrow and place product terms from one macrocell to another. The following list
summarizes how product terms are allocated:
●
McellA0-McellA7 all have three native product terms and may borrow up to six more
●
McellB0-McellB3 all have four native product terms and may borrow up to five more
●
McellB4-McellB7 all have four native product terms and may borrow up to six more.
Each macrocell may only borrow product terms from certain other macrocells. Product
terms already in use by one macrocell are not available for another macrocell.
If an equation requires more product terms than are available to it, then “external” product
terms are required, which consume other output macrocells (OMC). If external product
terms are used, extra delay is added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft Express performs this expansion as needed.
58/124
PSD4235G2V
17.3
Complex PLD (CPLD)
Loading and Reading the output macrocells (OMC)
The output macrocells (OMC) block occupies a memory location in the MCU address space,
as defined by the CSIOP (see Section 19: I/O ports). The flip-flops in each of the 16 output
macrocells (OMC) can be loaded from the data bus by a MCU. Loading the output
macrocells (OMC) with data from the MCU takes priority over internal functions. As such,
the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability
to load the flip-flops and read them back is useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking protocols.
Data is loaded to the output macrocells (OMC) on the trailing edge of Write Strobe
(WR/WRL, CNTL0).
17.4
The OMC Mask register
There is one Mask register for each of the two groups of eight output macrocells (OMC). The
Mask registers can be used to block the loading of data to individual output macrocells
(OMC). The default value for the Mask registers is 00h, which allows loading of the output
macrocells (OMC). When a given bit in a Mask register is set to a '1,' the MCU is blocked
from writing to the associated output macrocells (OMC). For example, suppose McellA0McellA3 are being used for a state machine. You would not want an MCU WRITE to McellA
to overwrite the state machine registers. Therefore, you would want to load the Mask
register for McellA (Mask macrocell A) with the value 0Fh.
17.5
The output Enable of the OMC
The output macrocells (OMC) can be connected to an I/O port pin as a PLD output. The
output enable of each port pin driver is controlled by a single product term from the AND
Array, ORed with the Direction register output. The pin is enabled upon Power-up if no
output enable equation is defined and if the pin is declared as a PLD output in PSDsoft
Express.
If the output macrocell (OMC) output is declared as an internal node and not as a port pin
output in the PSDabel file, then the port pin can be used for other I/O functions. The internal
node feedback can be routed as an input to the AND Array.
59/124
Complex PLD (CPLD)
PSD4235G2V
Figure 14. CPLD output macrocell
MASK
REG.
MACROCELL CS
INTERNAL DATA BUS
RD
PT
ALLOCATOR
WR
DIRECTION
REGISTER
ENABLE (.OE)
AND ARRAY
PLD INPUT BUS
PRESET(.PR)
COMB/REG
SELECT
PT
PT
DIN PR
MUX
PT
LD
POLARITY
SELECT
IN
CLEAR (.RE)
CLR
PORT
DRIVER
PROGRAMMABLE
FF (D/T/JK /SR)
PT CLK
CLKIN
I/O PIN
Q
MUX
FEEDBACK (.FB)
PORT INPUT
INPUT
MACROCELL
AI04946
17.6
Input macrocells (IMC)
The CPLD has 24 input macrocells (IMC), one for each pin on Ports A, B, and C. The
architecture of the input macrocells (IMC) is shown in Figure 15. The input macrocells (IMC)
are individually configurable, and can be used as a latch, register, or to pass incoming Port
signals prior to driving them onto the PLD input bus. The outputs of the input macrocells
(IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each
product term output is used to latch or clock four input macrocells (IMC). Port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the input macrocells (IMC) are specified by PSDsoft Express (see
Application Note AN1171). outputs of the input macrocells (IMC) can be read by the MCU
via the IMC buffer (see Section 19: I/O ports).
Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher
than A15. Any latched addresses are routed to the PLDs as inputs.
60/124
PSD4235G2V
Complex PLD (CPLD)
Input macrocells (IMC) are particularly useful with handshaking communication applications
where two processors pass data back and forth through a common mailbox. Figure 17
shows a typical configuration where the Master MCU writes to the Port A Data Out register.
This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output
enable product term.
The Slave can also write to the Port A input macrocells (IMC) and the Master can then read
the input macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from
the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR/WRL, CNTL0), and
Slave_CS.
Figure 15. Input macrocell
INTERNAL DATA BUS
INPUT MACROCELL _ RD
DIRECTION
REGISTER
ENABLE ( .OE )
AND ARRAY
PLD INPUT BUS
PT
OUTPUT
MACROCELLS A
AND
MACROCELLS B
I/O PIN
PT
PORT
DRIVER
MUX
Q
D
PT
MUX
ALE/AS
D FF
FEEDBACK
Q
D
G
LATCH
INPUT MACROCELL
AI04926
61/124
Complex PLD (CPLD)
17.7
PSD4235G2V
External Chip Select
The CPLD also provides eight External Chip Select (ECS0-ECS7) outputs that can be used
to select external devices. Each External Chip Select (ECS0-ECS7) consists of one product
term that can be configured active high or low.
The output enable of the pin is controlled by either the output enable product term or the
Direction register. (See Figure 16.)
Figure 16. External Chip Select signal
CPLD AND ARRAY
PLD INPUT BUS
Port C or Port F
ENABLE (.OE) PT
ECS
To Port C or F
ECS PT
DIRECTION
REGISTER
PORT PIN
POLARITY
BIT
AI04927
62/124
MASTER
MCU
D [ 7:0]
MCU -WR
MCU-RD
PSD
MCU-RD
CPLD
D
Q
Q
D
PORT A
INPUT
MACROCELL
SLAVE – WR
MCU-WR
PORT A
DATA OUT
REGISTER
SLAVE – READ
WR
RD
SLAVE– CS
PORT A
D [ 7:0]
AI02877C
SLAVE
MCU
PSD4235G2V
Complex PLD (CPLD)
Figure 17. Handshaking communication using input macrocells
63/124
MCU bus interface
18
PSD4235G2V
MCU bus interface
The “no-glue logic” MCU Bus Interface block can be directly connected to most popular
MCUs and their control signals. Key 16-bit MCUs, with their bus types and control signals,
are shown in Table 33. The MCU interface type is specified using the PSDsoft Express.
Table 33.
MCUs and their control signals
MCU
CNTL0
CNTL1
CNTL2
PD3
PD0(1)
ADIO0
PF3PF0
68302, 68306, MMC2001
R/W
LDS
UDS
(2)
AS
—
(2)
68330, 68331, 68332,
68340
R/W
DS
SIZ0
(2)
AS
A0
(2)
68LC302, MMC2001
WEL
OE
—
WEH
AS
—
(2)
68HC16
R/W
DS
SIZ0
(2)
AS
A0
(2)
68HC912
R/W
E
LSTRB
DBE
E
A0
(2)
68HC812 3
R/W
E
LSTRB
(2)
(Note 1)
A0
(2)
80196
WR
RD
BHE
(2)
ALE
A0
(2)
80196SP
WRL
RD
(Note 1)
WRH
ALE
A0
(2)
80186
WR
RD
BHE
(2)
ALE
A0
(2)
80C161, 80C164-80C167
WR
RD
BHE
(2)
ALE
A0
(2)
80C51XA
WRL
RD
PSEN
WRH
ALE
A4/D0
A3-A1
H8/300
WRL
RD
(2)
WRH
AS
A0
—
BHE
(2)
ALE
A0
(2)
M37702M2
R/W
E
1. ALE/AS input is optional for MCUs with a non-multiplexed bus
2. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be
configured for other I/O functions.
64/124
PSD4235G2V
18.1
MCU bus interface
PSD interface to a multiplexed bus
Figure 18 shows an example of a system using a MCU with a 16-bit multiplexed bus and a
PSD4235G2V. The ADIO port on the PSD is connected directly to the MCU address/data
bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched
addresses can be brought out to Port E, F or G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and Read Strobe (RD, CNTL1) is active.
Should the system address bus exceed sixteen bits, Ports A, B, C, or F may be used as
additional address inputs.
Figure 18. An example of a typical 16-bit multiplexed bus interface
PSD
MCU
AD [ 7:0]
AD[15:8]
or A[15:8]
ADIO
PORT
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
A [ 7: 0]
PORT
F
(OPTIONAL)
PORT
G
(OPTIONAL)
PORT
A, B,
or C
A [ 15: 8]
A [ 23:16]
(OPTIONAL)
ALE (PD0)
PORT D
RESET
AI04928
65/124
MCU bus interface
18.2
PSD4235G2V
PSD interface to a non-multiplexed 8-bit bus
Figure 19 shows an example of a system using a MCU with a 16-bit non-multiplexed bus
and a PSD4235G2V. The address bus is connected to the ADIO Port, and the data bus is
connected to Ports F and G. Ports F and G are in tri-state mode when the PSD is not
accessed by the MCU. Should the system address bus exceed sixteen bits, Ports A, B, or C
may be used for additional address inputs.
Figure 19. An example of a typical 16-bit non-multiplexed bus interface
PSD
MCU
D [ 15:0]
ADIO
PORT
D [ 7:0]
PORT
F
A [ 15:0]
D[15:8]
PORT
G
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
PORT
A, B
or C
A [ 23:16]
(OPTIONAL)
ALE (PD0)
PORT D
RESET
AI04929
18.3
Data Byte Enable reference
MCUs have different data byte orientations. Table 34 to Table 37 show how the
PSD4235G2V interprets byte/word operations in different bus write configurations. Evenbyte refers to locations with address A0 equal to '0,' and odd byte as locations with A0 equal
to '1.'
Table 34.
66/124
16-bit data bus with BHE
BHE
A0
D15-D8
D7-D0
0
0
Odd Byte
Even Byte
0
1
Odd Byte
—
1
0
—
Even Byte
PSD4235G2V
18.4
MCU bus interface
MCU bus interface examples
Figure 20 to Figure 25 show examples of the basic connections between the PSD4235G2V
and some popular MCUs. The PSD4235G2V Control input pins are labeled as to the MCU
function for which they are configured. The MCU bus interface is specified using PSDsoft
Express.
Table 35.
16-bit data bus with WRH and WRL
WRH
WRL
0
0
Odd Byte
Even Byte
0
1
Odd Byte
—
1
0
—
Even Byte
Table 36.
D15-D8
D7-D0
16-bit data bus with SIZ0, A0 (Motorola MCU)
SIZ0
A0
0
0
Even Byte
Odd Byte
1
0
Even Byte
—
1
1
—
Odd Byte
Table 37.
D15-D8
D7-D0
16-bit data bus with LDS, UDS (Motorola MCU)
WRH
WRL
D15-D8
D7-D0
0
0
Even Byte
Odd Byte
1
0
Even Byte
—
0
1
—
Odd Byte
67/124
MCU bus interface
18.5
PSD4235G2V
80C196 and 80C186
In Figure 20, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is
shown connected to a PSD4235G2V. The Read Strobe (RD, CNTL1), and Write Strobe
(WR/WRL, CNTL0) signals are connected to the CNTL pins. When BHE is not used, the
PSD can be configured to receive WRL and Write Enable high-byte (WRH/DBE, PD3) from
the MCU. higher address inputs (A16-A19) can be routed to Ports A, B, or C as input to the
PLD.
The AMD 80186 family has the same bus connection to the PSD as the 80C196.
Figure 20. Interfacing the PSD with an 80C196
A19-A16
A[ 19:16]
AD15-AD0
AD[ 15:0 ]
VCC
80C196NT
19
18
32
49
6
48
44
45
46
47
58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
57
56
55
54
53
52
51
50
PSD
X1
X2
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
3
4
5
6
7
10
11
12
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
13
14
15
16
17
18
19
20
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
13
14
15
16
17
18
19
20
EP.0/A16
EP.1/A17
EP.2/A18
EP.3/A19
14
13
12
11
9
WR
59
7
RD
60
8
BHE
40
4
ALE
79
80
1
2
NMI
VREF
VPP
ANGND
ACH4/P0.4/PMD.0
ACH5/P0.5/PMD.1
ACH6/P0.6/PMD.2
ACH7/P0.7/PMD.3
P6.0/EPA8
P6.1/EPA9
P6.2/T1CLK
P6.3/T1DIR
P6.4/SC0
P6.5/SD0
P6.6/SC1
P6.7/SD1
WR/WRL/P5.2
RD/P5.3
BHE/WRH/P5.5
P2.0/TX/PVR
P2.1/RXD/PALE
P2.2/EXINT/PROG
P2.3/INTB
P2.4/INTINTOUT
P2.5/HLD
P2.6/HLDA/CPVER
P2.7/CLKOUT/PAC
ALE/ADV/P5.0
EA
31
READY/P5.6
P1.0/EPA0/T2CLK
P1.1/EPA1
P1.2/EPA2/T2DIR
P1.3/EPA3
BUSWIDTH/P5.7
P1.4/EPA4
P1.5/EPA5
P1.6/EPA6
P1.7/EPA7
INST/P5.1
SLPINT/P5.4
2
10
3
1
68/124
69
VCC
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
RESET
39
71
72
73
74
75
76
77
78
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6
PE7
GND
GND
GND
GND
GND
8
RESET
29
VCC
A16
A17
A18
A19
33
RESET
9
VCC
30
49
50
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
70
AI04930b
PSD4235G2V
18.6
MCU bus interface
MC683xx and MC68HC16
Figure 21 shows a MC68331 with a 16-bit non-multiplexed data bus and 24-bit address bus.
The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The
SIZ0 and A0 inputs determine the high/low byte selection. The R/W, DS and SIZ0 signals
are connected to the CNTL0-CNTL2 pins.
The MC68HC16, and other members of the MC683xx family, has the same bus connection
to the PSD as the MC68331 shown in Figure 21.
Figure 21. Interfacing the PSD with an MC68331
D[15:0]
D[15:0]
A[23:0]
A[23:0]
29
9
PSD
69
VCC_BAR
89
88
77
76
75
74
73
72
71
D8
D9
D10
D11
D12
D13
D14
D15
DSACK0
DSACK1
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19_CS6/
A20_CS7/
A21_CS8/
A22_CS9/
A23_CS10/
27
30
31
32
33
35
36
37
38
41
42
121
122
123
124
125
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
79
R_W 85
DS 81
SIZ0
AS
RESET
SIZ1
CLKOUT
CSBOOT/
BR_CS0/
BG_CS1/
BGACK_CS2/
FC0_CS3/
FC1_CS4/
FC2_CS5/
A16
A17
A18
A19
A20
A21
A22
A23
R/W\
DS\
59
60
SIZ0
40
AS
82
68
80
66
112
113
114
115
118
119
120
RESET\
79
80
1
2
39
71
72
73
74
75
76
77
78
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
Vcc
A0
A1
A2
A3
A4
A5
A6
A7
Vcc
A0
A1
A2
A3
A4
A5
A6
A7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0(R/W)
CNTL1(DS)
CNTL2 (SIZ0)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6
PE7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (AS)
PD1 (CLKIN)
PD2 (CSI)
PD3
31
32
33
34
35
36
37
38
D0
D1
D2
D3
D4
D5
D6
D7
21
22
23
24
25
26
27
28
D8
D9
D10
D11
D12
D13
D14
D15
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
GND
GND
GND
GND
GND
D8 100
D9 99
D10 98
D11 97
D12 94
D13 93
D14 92
D15 91
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
10
11
12
8
30
49
50
70
D0
D1
D2
D3
D4
D5
D6
D7
90
20
21
22
23
24
25
26
Vcc
MC68331
111
110
109
108
105
104
103
102
RESET\
AI04951c
69/124
MCU bus interface
18.7
PSD4235G2V
80C51XA
The Philips 80C51XA MCU has a 16-bit multiplexed bus with burst cycles. Address bits (A3A1) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0).
The PSD4235G2V supports the 80C51XA burst mode. The WRH signal is connected to
PD3, and WHL is connected to CNTL0. The RD and PSEN signals are connected to the
CNTL1 and CNTL2 pins. Figure 22 shows the schematic diagram.
The 80C51XA improves bus throughput and performance by issuing burst cycles to fetch
codes from memory. In burst cycles, address A19-A4 are latched internally by the PSD,
while the 80C51XA drives the A3-A1 signals to fetch sequentially up to 16 bytes of code.
The PSD access time is then measured from address A3-A1 valid to data in valid. The PSD
bus timing requirement in a burst cycle is identical to the normal bus cycle, except the
address setup and hold time with respect to Address Strobe (ALE/AS, PD0) is not required.
Figure 22. Interfacing the PSD with an 80C51XA-G3
D[15:0]
D[15:0]
A[3:1]
VCC_BAR
CRYSTAL
20
11
13
6
7
9
8
16
RESET\
10
14
15
35
17
VCC_BAR
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RST
INT0
INT1
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A3
A2
A1
A0/WRH
WRL
RD
PSEN
EA/WAIT
ALE
BUSW
43
42
41
40
39
38
37
36
3
A4D0
4
A5D1
A6D2
5
6
A7D3
A8D4
7
A9D5 10
A10D6 11
A11D7 12
24
25
26
27
28
29
30
31
A12D8 13
A13D9 14
A14D10 15
A15D11 16
A16D12 17
A17D13 18
A18D14 19
A19D15 20
5
4
3
2
18
19
A3
A2
A1
WRH\
WRL\
RD\
59
60
32
PSEN\
40
33
ALE
79
80
1
2
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
69
Vcc
21
U3
Vcc
9
XA-G3
Vcc
PSD
29
A[3:1]
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
39
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6
PE7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
RESET\
31
32
33
34
35
36
37
38
A1
A2
A3
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
8
30
49
50
70
GND
GND
GND
GND
GND
71
72
73
74
75
76
77
78
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
AI04952c
70/124
PSD4235G2V
18.8
MCU bus interface
H8/300
Figure 23 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit
address bus. The H8 data bus is connected to Port F (D0-D7) and Port G (D8-D15).
The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD signal is
connected to CNTL1. The connection to the Address Strobe (AS) signal is optional, and is
required if the addresses are to be latched.
Figure 23. Interfacing the PSD with an H83/2350
D[15:0]
D[15:0]
A[23:0]
A[23:0]
78
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
EXTAL
U3
CRYSTAL
77
29
30
31
32
55
53
57
56
54
58
90
89
91
88
87
86
74
71
70
69
68
67
66
65
64
60
61
62
63
113
114
115
80
RESET\
XTAL
CS7/IRQ3
CS6/IRQ2
IRQ1
IRQ0
RXD0
TXD0
SCK0
RXD1
TXD1
SCK1
RXD2
TXD2
SCK2
PF0/BREQ
PF1/BACK
PF2/LCAS/WAIT/B
NMI
PO0/TIOCA3
PO1/TIOCB3
PO2/TIOCC3/TMRI
PO3/TIOCD3/TMCI
PO4/TIOCA4/TMRI
PO5/TIOCB4/TMRC
PO6/TIOCA5/TMRO
PO7/TIOCB5/TMRO
DREQ/CS4
TEND0/CS5
DREQ1
TEND1
MOD0
MOD1
MOD2
PF0/PHI0
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
LWR
RD
AS
HWR
RESET
WDTOVF
STBY
PO8/TIOCA0/DACK
PO9/TIOCB0/DACK
PO10/TIOCC0/TCL
PO11/TIOCD0/TCL
PO12/TIOCA1
PO13/TIOCB1/TCL
PO14/TIOCA2
PO15/TIOCB2/TCL
AN0
AN1
AN2
AN3
AN4
AN5
AN6/DA0
AN7/DA1
ADTRG
PG0/CAS/OE
PG1/CS3
PG2/CS2
PG3/CS1
PG4/CS0
2
3
4
5
7
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
3
4
5
6
7
10
11
12
11
12
13
14
16
17
18
19
20
21
22
23
25
26
27
28
85
83
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
A16
A17
A18
A19
A20
A21
A22
A23
WRL\
RD\
40
82
AS
84
WRH\
73
72
75
112
111
110
109
108
107
106
105
59
60
RESET\
79
80
1
2
39
71
72
73
74
75
76
77
78
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
9
69
Vcc
43
44
45
46
48
49
50
51
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
Vcc
D8
D9
D10
D11
D12
D13
D14
D15
PE0/D0
PE0/D1
PE0/D2
PE0/D3
PE0/D4
PE0/D5
PE0/D6
PE0/D7
Vcc
34
35
36
37
39
40
41
42
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0(WRL)
CNTL1(RD)
CNTL2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (AS)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
31
32
33
34
35
36
37
38
D0
D1
D2
D3
D4
D5
D6
D7
21
22
23
24
25
26
27
28
D8
D9
D10
D11
D12
D13
D14
D15
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
GND
GND
GND
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
PSD
8
30
49
50
70
H8S/2655
29
VCC_BAR
95
96
97
98
99
100
101
102
92
116
117
118
119
120
AI04953b
71/124
MCU bus interface
18.9
PSD4235G2V
MMC2001
The Motorola MCORE MMC2001 MCU has a MOD input pin that selects internal or external
boot ROM. The PSD can be configured as the external flash boot ROM or as extension to
the internal ROM.
The MMC2001 has a 16-bit external data bus and 20 address lines with external chip select
signals. The Chip Select Control registers allow the user to customize the bus interface and
timing to fit the individual system requirement. A typical interface configuration to the PSD is
shown in Figure 24. The MMC2001’s R/W signal is connected to the CNTL0 pin, while EB0
and EB1 (enable byte-0 and enable byte-1) are connected to the CNTL1 (UDS) and CNTL2
(LDS) pins. The WEN bit in the Chip Select Control register should be set to ’1’ to terminate
the EB0-EB1 earlier to provide the write data hold time for the PSD. The WSC and WWS
bits in the Control register are set to wait states that meet the PSD access time requirement.
Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case, the
PSD control setting will be: OE, WRL, WRH where OE is the READ signal for the
MMC2001.
18.10
C16x family
The PSD supports Infineon’s C16X family of MCUs (C161-C167) in both the multiplexed and
non-multiplexed bus configuration. In Figure 25, the C167CR is shown connected to the
PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE
and ALE, and are routed to the corresponding PSD pins.
The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported
by the PSD.
72/124
PSD4235G2V
MCU bus interface
Figure 24. Interfacing the PSD with an MMC2001
A[19:16]
A[19:16]
AD[15:0]
VCC_BAR
19
20
21
22
23
24
25
26
9
10
11
12
13
14
15
16
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
P5.10/AN10/T6UED
P5.11/AN11/T5UED
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4UED
P5.15/AN15/T2UED
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
EA
P1H7
P1H6
P1H5
P1H4
P1H3
P1H2
P1H1
P1H0
P1L7
P1L6
P1L5
P1L4
P1L3
P1L2
P1L1
P1L0
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
Vref
READY
143
139
127
110
94
RESET\
P4.0/A16
A17
A18
A19
A20
A21
A22
P4.7/A23
WR/WRL
RD
P3.12/BHE/WRH
ALE
P6.0/!CS0
P6.1/!CS1
P6.2/!CS2
P6.3/!CS3
P6.4/!CS4
P6.5/!HOLD
P6.6/!HLDA
P6.7/!BREQ
Vss
Vss
Vss
Vss
Vss
37
97
P3.13/SCLK
P3.15/CLKOUT
RSTIN
RSTOUT
NMI
108
111
112
113
114
115
116
117
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
13
14
15
16
17
18
19
20
85
86
87
88
89
90
91
92
96
95
79
98
69
9
29
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
WR\
RD\
BHE\
ALE
RESET\
59
60
40
79
80
1
2
39
71
72
73
74
75
76
77
78
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
A16
A17
A18
A19
99
135
134
133
132
131
130
129
128
125
124
123
122
121
120
119
118
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
Vcc
3
4
5
6
7
10
11
12
Vcc
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0(WR)
CNTL1(RD)
CNTL2(BHE)
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6
PE7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
GND
GND
GND
GND
GND
1
2
3
4
5
6
7
8
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Agnd
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
100
101
102
103
104
105
106
107
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64
140
141
142
38
80
81
XTAL2
Vss
Vss
Vss
Vss
Vss
65
66
67
68
69
70
73
74
75
76
77
78
83
71
55
45
18
137
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Vcc
82
72
56
46
17
U3
CRYSTAL
ADIO[15:0]
8
30
49
50
70
XTAL1
PSD
Vcc
Vcc
Vcc
Vcc
Vcc
138
Vcc
Vcc
Vcc
Vcc
Vcc
Infineon C167CR
144
136
126
109
93
VCC_BAR
AI04954c
73/124
MCU bus interface
PSD4235G2V
Figure 25. Interfacing the PSD with a C167CR
A19-A16
A[ 19:16]
AD15-AD0
Vcc
144136129109 93 82 72 56 46 17
VccVccVccVccVccVccVccVccVccVcc
138
65
66
67
68
69
70
73
74
75
76
77
78
79
80
100
101
102
103
104
105
106
107
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
108
111
112
113
114
115
116
117
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
13
14
15
16
17
18
19
20
XTAL1
81
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
1
2
3
4
5
6
7
8
19
20
21
22
23
24
25
26
9
10
11
12
13
14
15
16
37
97
XTAL2
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3UED
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
P3.12
P3.13/SCLK
85
86
87
88
89
90
91
92
P5.0/AN0
WR/WRL
P5.1/AN1
P5.2/AN2
RD
P5.3/AN3
P312/BHE/WRH
P5.4/AN4
P5.5/AN5
ALE
P5.6/AN6
P5.7/AN7
EA
P5.8/AN8
P5.9/AN9
P1H7
P5.10/AN10/T6UED
P1H6
P5.11/AN11/T5UED
P1H5
P5.12/AN12/T6IN
P1H4
P5.13/AN13
P1H3
P5.14/AN14/T4UED
P1H2
P5.15/AN15/T2UED
P1H1
P1H0
P6.0/!CS0
P1L7
P6.1/!CS1
P1L6
P6.2/!CS2
P1L5
P6.3/!CS3
P1L4
P6.4/!CS4
P1L3
P6.5/!HOLD
P1L2
P1L1
P6.6/!HLDA
P1L0
P6.7/!BREQ
96
WR
59
95
RD
60
79
BHE
40
98
ALE
79
80
P3.15/CLKOUT
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
Vref
74/124
99
135
134
133
132
131
130
129
128
125
124
123
122
121
120
119
118
9
VCC
29
69
VCC
VCC
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
A16
A17
A18
A19
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
1
2
RESET
39
71
72
73
74
75
76
77
78
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0 (WR)
CNTL1 (RD)
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PD2 (CSI)
PD3 (WRH)
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6
PE7
GND
GND
GND
GND
GND
8
30
49
50
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
70
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
140
RSTIN
RSTOUT
141
NMI
AGND
VssVssVssVssVssVssVssVssVssVss
READY
143139127110 94 83 71 55 45 18
RESET
PSD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
C167CR
137
AD[ 15:0 ]
VCC
142
38
AI04955b
PSD4235G2V
19
I/O ports
I/O ports
There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each port pin is
individually user configurable, thus allowing multiple functions per port. The ports are
configured using PSDsoft Express or by the MCU writing to on-chip registers in the CSIOP
space.
The topics discussed in this section are:
19.1
●
General Port architecture
●
Port operating modes
●
Port Configuration registers (PCR)
●
Port Data registers
●
Individual Port functionality.
General port architecture
The general architecture of the I/O Port block is shown in Figure 26. Individual Port
architectures are shown in Figure 28 to Figure 30. In general, once the purpose for a port
pin has been defined, that pin is no longer available for other purposes. Exceptions are
noted.
As shown in Figure 26, the ports contain an output multiplexer whose select signals are
driven by the configuration bits in the Control registers (Ports E, F and G only) and PSDsoft
Express Configuration. inputs to the multiplexer include the following:
●
Output data from the Data Out register
●
Latched address outputs
●
CPLD macrocell output
●
External Chip Select from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and
can be read by the MCU. The Data Out and macrocell outputs, Direction register and
Control register, and port pin input are all connected to the Port Data Buffer (PDB).
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND Array enable product term and the Direction register. If the
enable product term of any of the Array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, the Direction register has sole control of the
buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB)
feedback path allows the MCU to check the contents of the registers.
Ports A, B, and C have embedded input macrocells (IMC). The input macrocells (IMC) can
be configured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array.
The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the
MCU (see Figure 15: Input macrocell).
75/124
I/O ports
19.2
PSD4235G2V
Port operating modes
The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft
Express, some by the MCU writing to the registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft Express must be programmed into the
device and cannot be changed unless the device is reprogrammed. The modes that can be
changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port,
Address input, Peripheral I/O and MCU Reset modes are the only modes that must be
defined before programming the device. All other modes can be changed by the MCU at
run-time. See Application Note AN1171 for more detail.
Table 38 summarizes which modes are available on each port. Table 39 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following sections.
Figure 26. General I/O port architecture
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT PIN
OUTPUT
MUX
G
MACROCELL OUTPUTS
EXT CS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD-INPUT
AI02885
76/124
PSD4235G2V
19.3
I/O ports
MCU I/O mode
In the MCU I/O mode, the MCU uses the PSD Ports to expand its own I/O ports. By setting
up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The
addresses of the ports are listed in Table 5.
A port pin can be put into MCU I/O mode by writing a ’0’ to the corresponding bit in the
Control register (for Ports E, F and G). The MCU I/O direction may be changed by writing to
the corresponding bit in the Direction register, or by the output enable product term (see
Section 19.2: Port operating modes). When the pin is configured as an output, the content of
the Data Out register drives the pin. When configured as an input, the MCU can read the
port input through the Data In buffer (see Figure 26).
Ports A, B and C do not have Control registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if they are specified in PSDsoft Express.
19.4
PLD I/O mode
The PLD I/O Mode uses a port as an input to the CPLD’s input macrocells (IMC), and/or as
an output from the CPLD’s output macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the Direction register to ’0’. The corresponding
bit in the Direction register must not be set to ’1’ if the pin is defined for a PLD input signal in
PSDsoft Express. The PLD I/O mode is specified in PSDsoft Express by declaring the port
pins, and then specifying an equation in PSDsoft Express.
19.5
Address Out mode
For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive
latched addresses onto the port pins. These port pins can, in turn, drive external devices.
Either the output enable or the corresponding bits of both the Direction register and Control
register must be set to a ’1’ for pins to use Address Out mode. This must be done by the
MCU at run-time. See Table 40 for the address output pin assignments on Ports E, F and G
for various MCUs.
Note:
Do not drive address signals with Address Out Mode to an external memory device if it is
intended for the MCU to Boot from the external device. The MCU must first Boot from PSD
memory so the Direction and Control register bits can be set.
Table 38.
Port operating modes
Port Mode
Port A
Port B
Port C
Port D
Port E
Port F
Port G
MCU I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PLD I/O
McellA outputs
McellB outputs
Additional Ext. CS outputs
PLD inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out
No
No
No
No
Yes (A7 - 0) Yes (A7 - 0)
Yes (A7 - 0)
or (A15 - 8)
77/124
I/O ports
PSD4235G2V
Table 38.
Port operating modes (continued)
Port Mode
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Address In
Yes
Yes
Yes
Yes
No
Yes
No
Data Port
No
No
No
No
No
Yes
Yes
Peripheral I/O
Yes
No
No
Yes
No
Yes
No
No
No
Yes
Yes
JTAG ISP
MCU Reset
mode(2)
No
No
No
No
No
No
No
No
(1)
Yes
No
1. Can be multiplexed with other I/O functions.
2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.
Table 39.
Port operating mode settings(1)
Mode
MCU I/O
Defined in PSDsoft
Express
Control
register
setting
Direction
register
setting
Declare pins only
0(2)
1 = output,
0 = input
VM register
setting
JTAG Enable
N/A
N/A
(3)
Declare pins and
Logic equations
N/A
(3)
N/A
N/A
Selected for MCU
with non-multiplexed
bus
N/A
N/A
N/A
N/A
Declare pins only
1
1(3)
N/A
N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for input
macrocells
N/A
N/A
N/A
N/A
Peripheral I/O
(Port F)
Logic equations
(PSEL0 and PSEL1)
N/A
N/A
PIO bit = 1
N/A
JTAG ISP(4)
Declare pins only
N/A
N/A
N/A
JTAG_Enable
MCU Reset mode
Specific pin logic
level
N/A
N/A
N/A
N/A
PLD I/O
Data Port (Port F, G)
Address Out
(Port E, F, G)
1. N/A = Not Applicable
2. Control register setting is not applicable to Ports A, B and C.
3. The direction of the Port A,B,C, and F pins are controlled by the Direction register ORed with the individual output enable
product term (.oe) from the CPLD AND Array.
4. Any of these three methods enables the JTAG pins on Port E.
78/124
PSD4235G2V
Table 40.
I/O ports
I/O port latched address output assignments(1)
MCU
80C51XA
All other MCU with
multiplexed bus
Port E
Port E
Port F
Port F
Port G
Port G
(PE3-PE0)
(PE7-PE4)
(PF3-PF0)
(PF7-PF4)
(PG3-PG0)
(PG7-PG4)
N/A
Address
a7-a4
N/A
Address
a7-a4
Address
a11-a8
Address
a15-a12
Address
a3-a0
Address
a7-a4
Address
a3-a0
Address
a7-a4
Address
a11-a8
Address
a15-a12
1. N/A = Not Applicable.
19.6
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can be
latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is
included in the DPLD equations for the primary Flash memory, secondary Flash memory or
SRAM is considered to be an address input.
19.7
Data Port mode
Ports F and G can be used as a data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O
functions are disabled in Ports F and G if the ports are configured as a Data Port. Data Port
mode is automatically configured in PSDsoft Express when a non-multiplexed bus MCU is
selected.
19.8
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all
of Port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting bit 7 of the VM register to a '1.' Figure 27 shows how Port A acts as a bidirectional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be specified in PSDsoft Express. The buffer is tri-stated when
PSEL0 or PSEL1 is not active.
79/124
I/O ports
PSD4235G2V
Figure 27. Peripheral I/O mode
RD
PSEL0
PSEL
PSEL1
VM REGISTER BIT 7
D0 - D7
DATA BUS
PA0 - PA7
WR
AI02886
19.9
JTAG in-system programming (ISP)
Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port E because In-System Programming
(ISP) is not performed during normal system operation. For more information on the JTAG
Port, see Figure 33: Reset (RESET) timing.
19.10
MCU Reset mode
Ports F and G can be configured to operate in MCU Reset mode. This mode is available
when PSD is configured for the Motorola 16-bit 683xx and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU reads the logic level on the data bus (D15D0) pins. The MCU then configures some of its I/O pin functions according to the logic level
input on the data bus lines. Two dedicated buffers are usually enabled during reset to drive
the data bus lines to the desired logic level.
The PSD can replace the two buffers by configuring Ports F and G to operate in MCU Reset
mode. In this mode, the PSD will drive the pre-defined logic level or data pattern on to the
MCU data bus when Reset is active and there is no ongoing bus cycle. After reset, Ports F
and G return to the normal Data Port mode.
The MCU Reset mode is enabled and configured in PSDsoft Express. The user defines the
logic level (data pattern) that will be drive out from Ports F and G during reset.
80/124
PSD4235G2V
19.11
I/O ports
Port Configuration registers (PCR)
Each Port has a set of Port Configuration registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
cycles at the addresses given in Table 5. The addresses in Table 5 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, bit 0 in a register refers to bit 0 of its port. The three Port
Configuration registers (PCR), shown in Table 41, are used for setting the Port
configurations. The default Power-up state for each register in Table 41 is 00h.
19.12
Control register
Any bit reset to ’0’ in the Control register sets the corresponding port pin to MCU I/O mode,
and a ’1’ sets it to Address Out mode. The default mode is MCU I/O. Only Ports E, F and G
have an associated Control register.
Table 41.
Port Configuration registers (PCR)
Register name
Control
Direction
Drive Select
(1)
Port
MCU access
E, F, G
WRITE/READ
A, B, C, D, E, F, G
WRITE/READ
A, B, C, D, E, F, G
WRITE/READ
1. See Table 45 for Drive register bit definition.
19.13
Direction register
The Direction register controls the direction of data flow in the I/O Ports. Any bit set to ’1’ in
the Direction register causes the corresponding pin to be an output, and any bit set to ’0’
causes it to be an input. The default mode for all port pins is input.
Figure 28 and Figure 30 show the Port Architecture diagrams for Ports A/B/C and E/F/G,
respectively. The direction of data flow for Ports A, B, C and F are controlled not only by the
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction register has sole control of a given
pin’s direction.
An example of a configuration for a Port with the three least significant bits set to output and
the remainder set to input is shown in Table 44. Since Port D only contains four pins, the
Direction register for Port D has only the four least significant bits active.
Drive Select register
The Drive Select register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is
set to a '1.' The default pin drive is CMOS.
81/124
I/O ports
PSD4235G2V
(The slew rate is a measurement of the rise and fall times of an output. A higher slew rate
means a faster output response and may create more electrical noise. A pin operates in a
high slew rate when the corresponding bit in the Drive register is set to '1.' The default rate is
slow slew.)
Table 45 shows the Drive register for Ports A, B, C, D, E, F and G. It summarizes which pins
can be configured as Open Drain outputs and which pins the slew rate can be set for.
Table 42.
Table 43.
Port Pin Direction Control, output Enable P.T. not defined
Direction register bit
Port pin mode
0
Input
1
Output
Port Pin Direction Control, output Enable P.T. defined
Direction register bit
Output Enable P.T.
Port pin mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Table 44.
Port direction assignment example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 45.
Drive
register
Drive register pin assignment(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port C
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port D
NA
NA
NA
NA
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port E
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port F
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port G
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
1. NA = Not Applicable.
82/124
PSD4235G2V
19.14
I/O ports
Port Data registers
The Port Data registers, shown in Table 46, are used by the MCU to write data to or read
data from the ports. Table 46 shows the register name, the ports having each register type,
and MCU access for each register type. The registers are described next.
19.15
Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is
read through the Data In buffer.
19.16
Data Out register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
register are driven out to the pins if the Direction register or the output enable product term
is set to '1.' The contents of the register can also be read back by the MCU.
19.17
Output macrocells (OMC)
The CPLD output macrocells (OMC) occupy a location in the MCU’s address space. The
MCU can read the output of the output macrocells (OMC). If the Mask macrocell register bits
are not set, writing to the macrocell loads data to the macrocell flip-flops (see Figure 13:
Macrocell and I/O port).
19.18
Mask macrocell register
Each Mask macrocell register bit corresponds to an output macrocell (OMC) flip-flop. When
the Mask macrocell register bit is set to a '1,' loading data into the output macrocell (OMC)
flip-flop is blocked. The default value is 0, or unblocked.
19.19
Input macrocells (IMC)
The input macrocells (IMC) can be used to latch or store external inputs. The outputs of the
input macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU (see
Section 17.6: Input macrocells (IMC)).
Table 46.
Port Data registers
Register Name
Port
MCU Access
Data In
A, B, C, D, E, F,
READ - input on pin
G
Data Out
A, B, C, D, E, F,
WRITE/READ
G
Output macrocell
A, B
READ - outputs of macrocells
WRITE - loading macrocells Flip-flop
83/124
I/O ports
PSD4235G2V
Table 46.
Port Data registers
Register Name
19.20
Port
MCU Access
Mask macrocell
A, B
WRITE/READ - prevents loading into a given
Macrocell
Input macrocell
A, B, C
READ - outputs of the input macrocells
Enable Out
A, B, C, F
READ - the output enable control of the port driver
Enable Out
The Enable Out register can be read by the MCU. It contains the output enable values for a
given port. A '1' indicates the driver is in output mode. A '0' indicates the driver is in tri-state
and the pin is in input mode.
19.21
Ports A, B and C - functionality and structure
Ports A, B and C have similar functionality and structure, as shown in Figure 28. The ports
can be configured to perform one or more of the following functions:
84/124
●
MCU I/O mode
●
CPLD output - macrocells McellA7-McellA0 can be connected to Port A. McellB7McellB0 can be connected to Port B. External Chip Select (ECS7-ECS0) can be
connected to Port C or Port F.
●
CPLD input - Via the input macrocells (IMC).
●
Address In - Additional high address inputs using the input macrocells (IMC).
●
Open Drain/Slew Rate - pins PC7-PC0 can be configured to fast slew rate. Pins PA7PA0 can be configured to Open Drain mode.
PSD4235G2V
I/O ports
Figure 28. Port A, B and C structure
DATA OUT
Register
D
DATA OUT
Q
WR
PORT Pin
OUTPUT
MUX
MCELLA7-MCELLA0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
ENABLE OUT
DIR Register
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD-INPUT
AI04936
19.22
Port D - functionality and structure
Port D has four I/O pins. See Figure 29. Port D can be configured to perform one or more of
the following functions:
●
MCU I/O mode
●
CPLD input - direct input to the CPLD, no input macrocells (IMC)
Port D pins can be configured in PSDsoft Express as input pins for other dedicated
functions:
●
Address Strobe (ALE/AS, PD0)
●
CLKIN (PD1) as input to the macrocells Flip-flops and APD counter
●
PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory,
SRAM and CSIOP.
●
Write Enable high-byte (WRH, PD3) input, or as DBE input from a MC68HC912.
85/124
I/O ports
PSD4235G2V
Figure 29. Port D structure
DATA OUT
Register
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
INTERNAL DATA BUS
READ MUX
OUTPUT
SELECT
P
D
DATA IN
B
DIR Register
D
WR
Q
CPLD-INPUT
AI04937
19.23
Port E - functionality and structure
Port E can be configured to perform one or more of the following functions (see Figure 30):
86/124
●
MCU I/O Mode
●
In-System Programming (ISP) - JTAG port can be enabled for programming/erase of
the PSD device. See Figure 33: Reset (RESET) timing for more information on JTAG
programming.
●
Open Drain - pins can be configured in Open Drain mode
●
Latched Address output - Provide latched address output.
PSD4235G2V
19.24
I/O ports
Port F - functionality and structure
Port F can be configured to perform one or more of the following functions:
19.25
●
MCU I/O Mode
●
CPLD output - External Chip Select (ECS7-ECS0) can be connected to Port F or Port
C.
●
CPLD input - direct input to the CPLD, no input macrocells (IMC)
●
Latched Address output - Provide latched address output as per Table 40.
●
Slew Rate - pins can be configured for fast Slew Rate
●
Data Port - connected to D7-D0 when Port F is configured as Data Port for a nonmultiplexed bus
●
Peripheral Mode
●
MCU Reset Mode - for 16-bit Motorola 683xx and HC16 MCUs
Port G - functionality and structure
Port G can be configured to perform one or more of the following functions:
●
MCU I/O Mode
●
Latched Address output - Provide latched address output as per Table 40.
●
Open Drain - pins can be configured in Open Drain Mode
●
Data Port - connected to D15-D8 when Port G is configured as Data Port for a nonmultiplexed bus
●
MCU Reset Mode - for 16-bit Motorola 683xx and hc16 mcus
87/124
I/O ports
PSD4235G2V
Figure 30. Port E, F and G structure
DATA OUT
Register
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
A[ 7:0] OR A[15:8]
G
PORT Pin
OUTPUT
MUX
Ext. CS (Port F)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL Register
D
ENABLE OUT
Q
WR
DIR Register
D
Q
WR
ENABLE PRODUCT TERM (.OE)
CPLD-INPUT (Port F)
ISP (Port E)
Configuration Bit
AI04938b
88/124
PSD4235G2V
20
Power management
Power management
The PSD device offers configurable power saving options. These options may be used
individually or in combinations, as follows:
●
All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and
SRAM) are built with power management technology. In addition to using special silicon
design methodology, power management technology puts the memories into standby
mode when address/data inputs are not changing (zero DC current). As soon as a
transition occurs on an input, the affected memory “wakes up”, changes and latches its
outputs, then goes back to standby. The designer does not have to do anything special
to achieve memory Standby mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Standby mode when its inputs are not changing, as
described for the Power Management Mode registers (PMMR), later.
●
The Automatic Power Down (APD) block allows the PSD to reduce to standby current
automatically. The APD Unit also blocks MCU address/data signals from reaching the
memories and PLDs. This feature is available on all PSD devices. The APD Unit is
described in more detail in Figure 31: APD unit.
Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity
for a certain period (the MCU is asleep), the APD Unit initiates Power-down mode (if
enabled). Once in Power-down mode, all address/data signals are blocked from
reaching the PSD memories and PLDs, and the memories are deselected internally.
This allows the memories and PLDs to remain in Standby mode even if the
address/data signals are changing state externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states
keeps the PLD out of Standby mode, but not the memories.
●
PSD Chip Select input (CSI, PD2) can be used to disable the internal memories,
placing them in Standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
Unit, especially if your MCU has a chip select output. There is a slight penalty in
memory access time when PSD Chip Select input (CSI, PD2) makes its initial transition
from deselected to selected.
●
The Power Management Mode registers (PMMR) can be written by the MCU at runtime to manage power. All PSD devices support “blocking bits” in these registers that
are set to block designated signals from reaching both PLDs. Current consumption of
the PLDs is directly related to the composite frequency of the changes on their inputs
(see Figure 34).
Significant power savings can be achieved by blocking signals that are not used in
DPLD or CPLD logic equations at run-time. PSDsoft Express creates a fuse map that
automatically blocks the low address byte (A7-A0) or the control signals (CNTL0CNTL2, ALE and Write Enable high-byte (WRH/DBE, PD3)) if none of these signals
are used in PLD logic equations.
PSD devices have a Turbo bit in PMMR0. This bit can be set to turn the Turbo mode off
(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs are changing (zero DC current). Even
when inputs do change, significant power can be saved at lower frequencies (AC
current), compared to when Turbo mode is on. When the Turbo mode is on, there is a
significant DC current component, and the AC component is higher.
89/124
Power management
20.1
PSD4235G2V
Automatic Power-down (APD) Unit and Power-down mode
The APD Unit, shown in Figure 31, puts the PSD into Power-down mode by monitoring the
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four-bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes high, and the PSD enters Power-down mode, as discussed next.
20.2
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
●
If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
operation. The PSD also returns to normal operation if either PSD Chip Select input
(CSI, PD2) is low or the Reset (RESET) input is high.
●
The MCU address/data bus is blocked from all memory and PLDs.
●
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the Power Management Mode registers (PMMR). The
blocked signals include MCU control signals and the common CLKIN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit.
●
All PSD memories enter Standby mode and are drawing standby current. However, the
PLDs and I/O ports blocks do not go into Standby mode because you do not want to
have to wait for the logic and I/O to “wakeup” before their outputs can change. See
Table 47 for Power-down mode effects on PSD ports.
●
Typical standby current is or the order of µA. This standby current value assumes that
there are no transitions on any PLD input.
Table 47.
Effect of Power-down mode on ports
Port function
90/124
Pin level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data port
Tri-State
Peripheral I/O
Tri-State
PSD4235G2V
Power management
Figure 31. APD unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
CLR
RESET
CSI
PD
Secondary Flash
Memory Select
Primary Flash
Memory Select
APD
COUNTER
EDGE
DETECT
PD
PLD
CLKIN
SRAM Select
POWER DOWN
(PDN) Select
DISABLE Primary and Secondary
FLASH Memory and SRAM
AI04939
Table 48.
Mode
Powerdown
PSD timing and standby current during Power-down mode(1)
PLD propagation
delay
Normal tPD
Memory
access time
No Access
Access recovery time to Typical standby
normal access
current
tLVDV
ISB(2)
1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the
Turbo bit.
2. Typical current consumption, see Table 60, assuming no PLD inputs are changing state and the PLD
Turbo bit is 0.
20.3
Other power saving options
The PSD offers other reduced power saving options that are independent of the Powerdown mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2 (as summarized in Section 5.15 and Table 23).
20.4
PLD power management
The power and speed of the PLDs are controlled by the Turbo bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time is increased after the Turbo bit is set to ’1’ (turned off) when the inputs change at
a composite frequency of less than 15 MHz. When the Turbo bit is reset to ’0’ (turned on),
the PLDs run at full power and speed. The Turbo bit affects the PLD’s DC power, AC power,
and propagation delay. See the AC and DC characteristics tables for PLD timing values
(seeTable 68).
Blocking MCU control signals with the PMMR2 bits can further reduce PLD AC power
consumption.
91/124
Power management
20.5
PSD4235G2V
PSD Chip Select input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When
low, the signal selects and enables the internal primary Flash memory, secondary Flash
memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on
PSD Chip Select input (CSI, PD2) disables the primary Flash memory, secondary Flash
memory, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O
signals remain operational when PSD Chip Select input (CSI, PD2) is high.
There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 68.
20.6
Input clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the output macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the macrocells block by setting bits 4 or 5 to a ’1’ in PMMR0.
Figure 32. Enable Power-down flowchart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0 to 6.
No
ALE/AS idle
for 15 CLKIN
clocks?
Yes
PSD in Power
Down Mode
AI04940
92/124
PSD4235G2V
20.7
Power management
Input control signals
The PSD provides the option to turn off the address input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and Write Enable high-byte
(WRH/DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to
the PLD AND Array. During Power-down mode, or, if any of them are not being used as part
of the PLD logic equation, these control signals should be disabled to save AC power. They
are disconnected from the PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6 to a ’1’ in
PMMR2.
Table 49.
APD counter operation
APD Enable
bit
ALE PD
polarity
ALE level
APD counter
0
X
X
Not counting
1
X
Pulsing
Not counting
1
1
1
Counting (Generates PDN after 15 clocks)
1
0
0
Counting (Generates PDN after 15 clocks)
93/124
Power-on Reset, Warm Reset and Power-down
PSD4235G2V
21
Power-on Reset, Warm Reset and Power-down
21.1
Power-on Reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO (minimum
1 ms) after VCC is steady. During this period, the device loads internal configurations, clears
some of the registers and sets the Flash memory into Operating mode. After the rising edge
of Reset (RESET), the PSD remains in the Reset mode for an additional period, tOPR
(maximum 120 ns), before the first memory access is allowed.
The PSD Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0FS7 and CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR/WRL, CNTL0) high,
during Power-on Reset for maximum security of the data contents and to remove the
possibility of data being written on the first edge of Write Strobe (WR/WRL, CNTL0). Any
Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO.
21.2
Warm Reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, tNLNH (minimum 150 ns). The same tOPR period is needed before the device is
operational after warm reset. Figure 33 shows the timing of the Power-up and warm reset.
21.3
I/O pin, register and PLD status at Reset
Table 50 shows the I/O pin, register and PLD status during Power-on reset, warm reset and
Power-down mode. PLD outputs are always valid during warm reset, and they are valid in
Power-on Reset once the internal PSD Configuration bits are loaded. This loading of PSD is
completed typically long before the VCC ramps up to operating level. Once the PLD is active,
the state of the outputs are determined by equations specified in PSDsoft Express.
21.4
Reset of Flash Memory Erase and Program cycles
An external Reset (RESET) also resets the internal Flash memory state machine. During a
Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the
Flash memory to the READ mode within a period of tNLNH-A (minimum 25 μs).
Table 50.
Status During Power-On Reset, Warm Reset and Power-down mode
Port configuration
Power-On Reset
Warm Reset
Power-down mode
MCU I/O
Input mode
Input mode
Unchanged
PLD output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
PMMR0 and PMMR2
Cleared to ’0’
Unchanged
Unchanged
94/124
PSD4235G2V
Table 50.
Power-on Reset, Warm Reset and Power-down
Status During Power-On Reset, Warm Reset and Power-down mode (continued)
Port configuration
Power-On Reset
Warm Reset
Power-down mode
Macrocells Flip-flop status
Cleared to ’0’ by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM register(1)
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Unchanged
All other registers
Cleared to ’0’
Cleared to ’0’
Unchanged
1. The SR_code and Peripheral Mode bits in the VM register are always cleared to ’0’ on Power-On Reset or Warm Reset.
Figure 33. Reset (RESET) timing
VCC
VCC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
tOPR
Warm Reset
RESET
AI02866b
95/124
Programming in-circuit using the JTAG serial interface
22
PSD4235G2V
Programming in-circuit using the JTAG serial
interface
The JTAG Serial Interface on the PSD can be enabled on Port E (see Table 51). All memory
blocks (primary Flash memory and secondary Flash memory), PLD logic, and PSD
Configuration bits may be programmed through the JTAG-ISC Serial Interface. A blank
device can be mounted on a printed circuit board and programmed using JTAG In-System
Programming (ISP).
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and
Erase cycles.
Note:
By default, on a blank PSD (as shipped from the factory, or after erasure), four pins on Port
E are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note AN1153 for more details on JTAG In-System Programming (ISP).
22.1
Standard JTAG signals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a serial command from an external JTAG controller device (such as
FlashLINK or Automated Test Equipment). When the enabling command is received from
the external JTAG controller device, TDO becomes an output and the JTAG channel is fully
functional inside the PSD. The same command that enables the JTAG channel may
optionally enable the two additional JTAG pins, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic JTAG
pins (TMS, TCK, TDI, and TDO) on their respective Port E pins. For purposes of discussion,
the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are enabled for
JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O.
JTAG_ON = PSDsoft Express_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Express Configuration utility. This dedicates the
pins for JTAG at all times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address CSIOP
+ offset C7h. Setting the JTAG_ENABLE bit in this register will
enable the pins for JTAG use. This bit is cleared by a PSD reset or
the microcontroller. See Table 20 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name JTAGSEL. Once
defined as a node in PSDabel, the designer can write an equation for
JTAGSEL. This method is used when the Port E JTAG pins are
multiplexed with other I/O signals. It is recommended to tie
logically the node JTAGSEL to the JEN\ signal on the Flashlink cable
when multiplexing JTAG signals. See Application Note 1153 for
details. */
96/124
PSD4235G2V
Programming in-circuit using the JTAG serial interface
The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations
if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However,
Reset (RESET) will prevent or interrupt JTAG operations if the JTAG Enable register (as
shown in Table 20) is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary
Scan. ST’s PSDsoft Express software tool and FlashLINK JTAG programming cable
implement the JTAG In-System-Programmability (ISP) commands.
22.2
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received
over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed
Program and Erase cycles by indicating status on PSD pins instead of having to scan the
status out serially using the standard JTAG channel. See Application Note AN1153.
TERR indicates if an error has occurred when erasing a sector or programming in Flash
memory. This signal goes low (active) when an Error condition occurs, and stays low until a
specific JTAG command is executed or a Reset (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4) described in Section 6.2.2: Ready/Busy
(PE4). TSTAT is high when the PSD4235G2V device is in READ mode (primary Flash
memory and secondary Flash memory contents can be read). TSTAT is low when Flash
memory Program or Erase cycles are in progress, and also when data is being written to the
secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
Note:
The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG
signals are dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset
(Reset) prevents or interrupts JTAG operations if the JTAG Enable register (as shown in
Table 20) is used to enable the JTAG signals.
22.3
Security and Flash memory protection
When the Security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the
device to a non-secured blank state. The Security bit can be set in PSDsoft Express.
All primary Flash memory and secondary Flash memory sectors can individually be sector
protected against erasure. The sector protect bits can be set in PSDsoft Express.
Table 51.
JTAG port signals
Port E pin
JTAG signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
97/124
Programming in-circuit using the JTAG serial interface
Table 51.
98/124
PSD4235G2V
JTAG port signals (continued)
Port E pin
JTAG signals
Description
PE4
TSTAT
Status
PE5
TERR
Error Flag
PSD4235G2V
23
Initial delivery state
Initial delivery state
When delivered from ST, the PSD device has all bits in the memory and PLDs set to '1.' The
PSD Configuration register bits are set to '0.' The code, configuration, and PLD logic are
loaded using the programming procedure. Information for programming the device is
available directly from ST. Please contact your local sales representative.
99/124
Maximum rating
24
PSD4235G2V
Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 52.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during Soldering (20 seconds
max.)(1)
Max.
Unit
–65
150
°C
235
°C
VIO
Input and output voltage (Q = VOH or Hi-Z)
–0.6
4.0
V
VCC
Supply voltage
–0.6
4.0
V
VPP
Device programmer supply voltage
–0.6
13.5
V
VESD
Electrostatic discharge voltage (Human Body
model)(2)
–2000
2000
V
1. IPC/JEDEC J-STD-020A.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
100/124
Min.
PSD4235G2V
DC and AC parameters
These tables describe the AD and DC parameters of the PSD4235G2V:
●
DC Electrical Specification
●
AC timing Specification
–
PLD timing
Combinatorial timing
Synchronous clock mode
Asynchronous clock mode
Input macrocell timing
–
MCU timing
READ timing
WRITE timing
Peripheral mode timing
Power-down and Reset timing
The parameters in the DC and AC Characteristic tables that follow are derived from tests
performed under the Measurement Conditions summarized in the relevant tables. Designers
should check that the operating conditions in their circuit match the measurement conditions
when relying on the quoted parameters.
The following are issues concerning the parameters presented:
●
In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD is in each mode. Also, the supply power is considerably different if the Turbo
bit is 0.
●
The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figure 34 show the PLD mA/MHz as a function of the number of Product
Terms (PT) used.
●
In the PLD timing parameters, add the required delay when Turbo bit is 0.
Figure 34. PLD ICC /frequency consumption
60
VCC = 3V
)
100%
N(
O O
50
B
TUR
40
O
FF
30
TU
RB
O
ICC – (mA)
25
DC and AC parameters
20
O
TURB
10
PT 100%
PT 25%
F
O
RB
TU
5%)
ON (2
OF
0
0
5
10
15
20
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
25
AI03100
101/124
DC and AC parameters
Table 53.
PSD4235G2V
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode on)(1)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
= 8 MHz
MCU ALE frequency (Freq ALE)
= 4 MHz
% Flash memory Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down mode
= 90%
Number of product terms used
(from fitter report)
= 54 PT
% of total product terms
= 54/127 = 25%
Turbo Mode
= ON
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x 1.1 mA/MHz x Freq PLD
+ #PT x 200 µA/PT)
= 50 µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 1.1 mA/MHz x 8 MHz
+ 54 x 0.2 mA/PT)
= 45 µA + 0.1 x (3.84 + 0.48 + 8.8 + 10.8 mA)
= 45 µA + 0.1 x 23.92
= 45 µA + 2.39 mA
= 2.43 mA
1. This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on
IOUT=0 mA.
102/124
PSD4235G2V
Table 54.
DC and AC parameters
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode off)(1)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
(from fitter report)
= 54 PT
% of total product terms
= 54/127 = 25%
Turbo Mode
= Off
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 15 mA)
= 45µA + 0.1 x (3.84 + 0.48 + 15)
= 45µA + 0.1 x 18.84
= 45µA + 1.94 mA
= 1.98 mA
1. This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT = 0
mA.
103/124
DC and AC parameters
Table 55.
PSD4235G2V
Operating conditions
Symbol
Parameter
VCC
TA
Table 56.
Min.
Max.
Unit
Supply voltage
3.0
3.6
V
Ambient operating temperature (industrial)
–40
85
°C
0
70
°C
Ambient operating temperature (commercial)
AC signal letters for PLD timings(1)
Letter
Description
A
Address input
C
CEout output
D
Input data
E
E input
G
Internal WDOG_ON signal
I
Interrupt input
L
ALE input
N
Reset input or output
P
Port signal output
Q
Output data
R
WR, UDS, LDS, DS, IORD, PSEN inputs
S
Chip Select input
T
R/W input
W
Internal PDN Signal
B
VSTBY output
M
Output macrocell
1. Example: tAVLX = time from Address Valid to ALE Invalid.
Table 57.
AC signal behavior symbols for PLD timings
Letter
104/124
Description
t
Time
L
Logic level low or ALE
H
Logic level high
V
Valid
X
No Longer a Valid Logic level
Z
Float
PSD4235G2V
Table 58.
DC and AC parameters
AC measurement conditions(1)
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
30
Unit
pF
1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 59.
Capacitance(1)
Symbol
Parameter
Test condition
Typ(2)
Max.
Unit
CIN
Input capacitance (for input pins)
VIN = 0V
4
6
pF
COUT
Output capacitance (for
input/output pins)
VOUT = 0V
8
12
CVPP
Capacitance (for CNTL2/VPP)
VPP = 0V
18
25
pF
pF
1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
Figure 35. AC measurement I/O waveform
0.9VCC
Test Point
1.5V
0V
AI04947
Figure 36. AC measurement load circuit
2.0 V
400 Ω
Device
Under Test
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI04948
105/124
DC and AC parameters
PSD4235G2V
Figure 37. Switching waveforms - key
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
Table 60.
DC characteristics
Test Condition
Symbol
Parameter
(in addition to those in
Table 55)
Min.
Typ.
Max.
Unit
VIH
input high voltage
3.0 V < VCC < 3.6 V
0.7VCC
VCC +0.5
V
VIL
input low voltage
3.0 V < VCC < 3.6 V
–0.5
0.8
V
VIH1
RESET high level input
voltage
(1)
0.8VCC
VCC +0.5
V
VIL1
RESET low level input voltage
(1)
–0.5
0.2VCC –0.1
V
VHYS
RESET pin hysteresis
0.3
VLKO
VCC (min) for Flash Erase and
Program
1.5
VOL
Output low voltage
VOH
Output high voltage
ISB
Standby supply current
for Power-down mode
CSI >VCC –0.3V(2)(3)
ILI
input Leakage Current
VSS < VIN < VCC
ILO
output Leakage Current
0.45 < VOUT < VCC
106/124
V
2.3
V
IOL = 20 µA, VCC = 4.5V
0.01
0.1
V
IOL = 8 mA, VCC = 4.5V
0.15
0.45
V
IOH = –20µA, VCC = 4.5V
2.9
2.99
V
IOH = –2 mA, VCC = 4.5V
2.7
2.8
V
50
100
µA
–1
±0.1
1
µA
–10
±5
10
µA
PSD4235G2V
Table 60.
DC and AC parameters
DC characteristics (continued)
Test Condition
Symbol
Parameter
Min.
(in addition to those in
Table 55)
Typ.
Max.
Unit
PLD_TURBO = Off,
f = 0 MHz (Note 5)
0
PLD_TURBO = On,
f = 0 MHz
200
400
µA/PT
During Flash memory
WRITE/Erase Only
10
25
mA
Read Only, f = 0 MHz
0
0
mA
0
0
mA
µA/PT
PLD Only
Operating
ICC (DC)
Supply
5
(Note )
Current
Flash memory
SRAM
ICC (AC)
f = 0 MHz
PLD AC Adder
(4)
Flash memory AC Adder
1.5
2.0
mA/
MHz
SRAM AC Adder
0.8
1.5
mA/
MHz
1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 34 for the PLD current calculation.
Figure 38. Input to output Disable/Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 61.
CPLD Combinatorial timing
-90
Symbol
Parameter
-12
Conditions
Min
Max
Min
Max
tPD
CPLD input
Pin/Feedback to CPLD
Combinatorial output
38
43
tEA
CPLD input to CPLD
output Enable
43
tER
CPLD input to CPLD
output Disable
tARP
CPLD register Clear or
Preset Delay
Slew
Fast
Turbo
PT
rate
Off
(1)
Aloc
+4
Unit
+ 20
–6
ns
45
+ 20
–6
ns
43
45
+ 20
–6
ns
38
43
+ 20
–6
ns
107/124
DC and AC parameters
Table 61.
PSD4235G2V
CPLD Combinatorial timing (continued)
-90
Symbol
Parameter
Min
tARPW
CPLD register Clear or
Preset Pulse Width
tARD
CPLD Array Delay
-12
Conditions
Max
28
Min
Max
Slew
Fast
Turbo
PT
rate
Off
(1)
Aloc
Unit
+ 20
ns
30
Any
macrocell
23
27
+4
ns
1. Fast Slew Rate output available on Port C and Port F.
Table 62.
CPLD macrocell Synchronous clock mode timing
-90
Symbol
Parameter
Min
Maximum frequency
External Feedback
fMAX
-12
Conditions
1/(tS+tCO)
Max
Min
Max
Fast
Turbo Slew
PT
rate
Off
(1)
Aloc
Unit
24.3
20.4
MHz
Maximum frequency
1/(tS+tCO–10)
Internal Feedback (fCNT)
32.2
25.6
MHz
Maximum frequency
Pipelined Data
45.0
35.7
MHz
1/(tCH+tCL)
tS
Input setup time
18
23
tH
Input Hold time
0
0
ns
tCH
Clock high time
Clock input
11
14
ns
tCL
Clock low time
Clock input
11
14
ns
tCO
Clock to output Delay
Clock input
23
26
tARD
CPLD Array Delay
Any macrocell
23
27
tMIN
Minimum Clock
Period(2)
tCH+tCL
1. Fast Slew Rate output available on Port C and Port F.
2. CLKIN (PD1) tCLCL = tCH + tCL.
108/124
22
28
+4
+ 20
ns
–6
+4
ns
ns
ns
PSD4235G2V
Table 63.
DC and AC parameters
CPLD macrocell Asynchronous clock mode timing
-90
Symbol
Parameter
Min
fMAXA
-12
Conditions
Max
Min
Max
PT Turbo Slew
Aloc
Off
rate
Unit
Maximum
frequency
External
Feedback
1/(tSA+tCOA)
23.8
20.8
MHz
Maximum
frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10)
31.25
26.3
MHz
1/(tCHA+tCLA)
38.4
30.3
MHz
Maximum
frequency
Pipelined Data
tSA
Input setup time
8
10
tHA
Input Hold time
10
12
tCHA
Clock input high
time
15
18
+ 20
ns
tCLA
Clock input low
time
12
15
+ 20
ns
tCOA
Clock to output
Delay
tARDA
CPLD Array
Delay
tMINA
Minimum Clock
Period
Any macrocell
+ 20
ns
ns
34
38
23
27
32
1/fCNTA
+4
+ 20
+4
38
–6
ns
ns
ns
Figure 39. Synchronous clock mode timing - PLD
tCH
tCL
CLKIN
tS
tH
INPUT
tCO
REGISTERED
OUTPUT
AI02860
109/124
DC and AC parameters
PSD4235G2V
Figure 40. Asynchronous RESET / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 41. Asynchronous clock mode timing (product term clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
AI02859
Figure 42. Input macrocell timing (product term clock)
t INH
t INL
PT CLOCK
t IS
t IH
INPUT
OUTPUT
t INO
AI03101
Table 64.
Input macrocell timing
-90
Symbol
Parameter
-12
Conditions
Min
Max
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input setup time
0
0
tIH
Input Hold time
20
23
tINH
NIB input high time
13
13
ns
tINL
NIB input low time
12
13
ns
tINO
NIB input to combinatorial
delay
(1)
46
ns
+ 20
62
+4
+ 20
1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
110/124
ns
ns
PSD4235G2V
Table 65.
DC and AC parameters
Program, WRITE and Erase times
Symbol
Parameter
Min.
Flash Program
Flash Bulk Erase
Typ.
Max.
Unit
8.5
(1)
(pre-programmed)
s
3
Flash Bulk Erase (not pre-programmed)
10
tWHQV3
Sector Erase (pre-programmed)
1
tWHQV2
Sector Erase (not pre-programmed)
2.2
tWHQV1
Byte Program
14
Program / Erase Cycles (per Sector)
30
s
30
Sector Erase timeout
tQ7VQV
DQ7 Valid to output (DQ7-DQ0) Valid (Data
Polling)(2)(3)
s
s
1200
100,000
tWHWLO
s
µs
cycles
100
µs
30
ns
1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus.
Figure 43. Peripheral I/O write timing
ALE /AS
A / D BUS
ADDRESS
DATA OUT
tWLQV
tWHQZ (PF)
(PF)
WR
tDVQV (PF)
PORT F
DATA OUT
AI05741
111/124
DC and AC parameters
PSD4235G2V
Figure 44. READ timing
tAVLX
tLXAX
1
ALE/AS
tLVLX
A /D
MULTIPLEXED
BUS
DATA
VALID
ADDRESS
VALID
tAVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLQV
CSI
tRLQV
tRHQX
tRLRH
RD
(PSEN, DS)
tRHQZ
tEHEL
E
tTHEH
tELTL
R /W
tAVPV
ADDRESS OUT
AI02895
1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
Table 66.
READ timing
-90
Symbol
Parameter
-12
Conditions
Min
Max
Min
Max
Turbo
Off
Unit
tLVLX
ALE or AS Pulse Width
22
24
ns
tAVLX
Address setup time
7
9
ns
tLXAX
Address Hold time
8
10
ns
tAVQV
Address Valid to Data Valid
tSLQV
CS Valid to Data Valid
(1)
90
120
+ 20
ns
90
120
ns
RD to Data Valid 8-bit Bus
(2)
35
35
ns
tRLQV
RD or PSEN to Data Valid
8-bit Bus, 8031, 80251
(3)
45
48
ns
tRHQX
RD Data Hold time
(4)
0
0
ns
36
40
ns
tRLRH
RD Pulse Width
tRHQZ
RD to Data high-Z
tEHEL
E Pulse Width
38
42
ns
tTHEH
R/W setup time to Enable
10
16
ns
112/124
38
40
ns
PSD4235G2V
DC and AC parameters
Table 66.
READ timing (continued)
Symbol
Parameter
-90
Min
tELTL
R/W Hold time After Enable
tAVPV
Address input Valid to
Address output Delay
-12
Conditions
Max
0
(5)
Min
Max
0
30
Turbo
Off
Unit
ns
35
ns
1. Any input used to select an internal PSD function.
2. RD timing has the same timing as DS, LDS, and UDS signals.
3. RD and PSEN have the same timing.
4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
113/124
DC and AC parameters
PSD4235G2V
Figure 45. WRITE timing
tAVLX
t LXAX
ALE/AS
t LVLX
A /D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLWL
CSI
tDVWH
t WLWH
WR
(DS)
t WHDX
t WHAX
t EHEL
E
t THEH
t ELTL
R/ W
t WLMV
tAVPV
t WHPV
STANDARD
MCU I/O OUT
ADDRESS OUT
AI02896
Table 67.
WRITE timing
-90
Symbol
Parameter
Unit
Min
tLVLX
-12
Conditions
Min
Max
22
24
ns
Address setup time
(1)
7
9
ns
tLXAX
Address Hold time
(1)
8
10
ns
tAVWL
Address Valid to Leading
Edge of WR
(1)(2)
15
18
ns
tSLWL
CS Valid to Leading edge of WR
(2)
15
18
ns
tDVWH
WR Data setup time
(2)
40
45
ns
tWHDX
WR Data Hold time
(2)(3)
5
8
ns
WR Pulse Width
(2)
40
45
ns
tWHAX1
Trailing edge of WR to Address Invalid
(2)
8
10
ns
tWHAX2
Trailing edge of WR to DPLD Address
Invalid
(2)(4)
0
0
ns
tAVLX
tWLWH
114/124
ALE or AS Pulse Width
Max
PSD4235G2V
Table 67.
DC and AC parameters
WRITE timing
-90
Symbol
Parameter
Unit
Min
tWHPV
Trailing edge of WR to Port output
Valid Using I/O Port Data register
tDVMV
-12
Conditions
Max
Min
Max
(2)
33
33
ns
Data Valid to Port output Valid
Using macrocell register
Preset/Clear
(2)(5)
65
68
ns
tAVPV
Address input Valid to Address
Output Delay
(6)
30
35
ns
tWLMV
WR Valid to Port output Valid Using
Macrocell register Preset/Clear
(2)(7)
65
70
ns
1. Any input used to select an internal PSD function.
2. WR has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
3. tWHAX is 6 ns when writing to the output macrocell registers AB and BC.
4. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
5. Assuming WRITE is active before data becomes valid.
6. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
7. Assuming data is stable before active WRITE signal.
Figure 46. Peripheral I/O read timing
ALE/AS
A /D BUS
ADDRESS
DATA VALID
tAVQV (PF)
tSLQV (PF)
CSI
tRLQV (PF)
RD
tQXRH (PF)
tRHQZ (PF)
tRLRH (PF)
tDVQV (PF)
DATA ON PORT F
AI05740
115/124
DC and AC parameters
Table 68.
PSD4235G2V
Port F Peripheral Data Mode Read timing
-90
Symbol
Parameter
-12
Turbo
Conditions
Unit
Max
Off
50
50
+ 20
ns
35
40
+ 20
ns
35
40
ns
RD to Data Valid 8031 Mode
45
45
ns
tDVQV–PF
Data In to Data Out Valid
34
38
ns
tQXRH–PF
RD Data Hold time
tRLRH–PF
RD Pulse Width
tRHQZ–PF
RD to Data high-Z
Min
tAVQV–PF
Address Valid to Data Valid
tSLQV–PF
CSI Valid to Data Valid
(1)
(2)(3)
RD to Data Valid
tRLQV–PF
(4)
Max
Min
0
0
ns
35
36
ns
38
40
ns
1. Any input used to select Port F Data Peripheral mode.
2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3. Data is already stable on Port F.
4. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
Table 69.
Port F Peripheral Data Mode Write timing
-90
Symbol
Parameter
-12
Conditions
Unit
Min
Max
Min
Max
WR to Data Propagation Delay
(1)
40
43
ns
tDVQV–PF
Data to Port F Data Propagation Delay
(2)
35
38
ns
tWHQZ–PF
WR Invalid to Port F Tri-state
(1)
35
33
ns
tWLQV–PF
1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Data stable on ADIO pins to data on Port F.
Figure 47. Reset (RESET) timing
VCC
VCC(min)
tNLNH-PO
tNLNH
tNLNH-A
tOPR
Power-On Reset
tOPR
Warm Reset
RESET
AI02866b
Table 70.
Symbol
Reset (RESET) timing
Parameter
tNLNH
RESET Active low time(1)
tNLNH–PO
Power-on Reset Active low time
116/124
Conditions
Min
Max
Unit
300
ns
1
ms
PSD4235G2V
Table 70.
DC and AC parameters
Reset (RESET) timing
Symbol
Parameter
Conditions
Min
(2)
tNLNH–A
Warm Reset
tOPR
RESET high to Operational Device
Max
Unit
μs
25
300
ns
1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode.
Table 71.
Power-down timing
-90
Symbol
Parameter
Unit
Min
tLVDV
ALE Access time from Power-down
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
-12
Conditions
Max
Min
128
Using CLKIN
(PD1)
Max
135
15 * tCLCL(1)
ns
µs
1. tCLCL is the period of CLKIN (PD1).
Figure 48. ISC timing
t ISCCH
TCK
t ISCCL
t ISCPSU
t ISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
117/124
DC and AC parameters
Table 72.
PSD4235G2V
ISC timing
-90
Symbol
Parameter
Unit
Min
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
tISCCFP
Clock (TCK, PC1) frequency (PLD only)
tISCCHP
Clock (TCK, PC1) high time (PLD only)
tISCCLP
-12
Conditions
Max
Min
15
(1)
12
MHz
30
40
ns
30
40
ns
2
(2)
Max
2
MHz
240
240
ns
Clock (TCK, PC1) low time (PLD only)
240
240
ns
tISCPSU
ISC Port Setup time
11
12
ns
tISCPH
ISC Port Hold Up time
5
5
ns
tISCPCO
ISC Port Clock to output
26
32
ns
tISCPZV
ISC Port high-Impedance to Valid output
26
32
ns
tISCPVZ
ISC Port Valid output to
High-Impedance
26
32
ns
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
118/124
PSD4235G2V
26
Package mechanical
Package mechanical
In order to meet environmental requirements, ST offers this device in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 49. LQFP80 - 80-lead plastic thin, quad, flat package outline
D
D1
D3
A2
41
60
40
61
e
E3 E1 E
b
21
80
Pin 1
identification
1
20
A
ccc
L1
c
A1
k
L
9X_ME
1. Drawing is not to scale.
Table 73.
LQFP80 - 80-lead plastic thin, quad, flat package mechanical data(1)
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
–
1.600
–
–
0.0630
A1
–
0.050
0.150
–
0.0020
0.0060
A2
1.400
1.350
1.450
0.0550
0.0530
0.0570
b
0.220
0.170
0.270
0.0090
0.0070
0.0110
c
–
0.090
0.200
–
0.0040
0.0080
D
14.000
–
–
0.5510
–
–
D1
12.000
–
–
0.4720
–
–
D3
9.500
–
–
0.3740
–
–
E
14.000
–
–
0.5510
–
–
E1
12.000
–
–
0.4720
–
–
E3
9.500
–
–
0.3740
–
–
e
0.500
–
–
0.0200
–
–
L
0.600
0.450
0.750
0.0240
0.0180
0.0300
119/124
Package mechanical
Table 73.
PSD4235G2V
LQFP80 - 80-lead plastic thin, quad, flat package mechanical data(1)
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
1.000
–
–
0.0390
–
–
k
0°
7°
3.5
0°
7°
ccc
0.080
–
–
0.003
L1
1. Values in inches are converted from mm and rounded to 4 decimal digits.
120/124
PSD4235G2V
Part numbering
27
Part numbering
Table 74.
Ordering information scheme
Example:
PSD42
3
5
G
2
V
– 90
U
1
T
Device Type
PSD42 = Flash PSD with CPLD
SRAM Size
3 = 64 Kbit
Flash Memory Size
5 = 4 Mbit
I/O Count
G = 52 I/O
2nd Non-Volatile Memory
2 = 256 Kbit Flash memory
Operating voltage
blank(1) = VCC = 4.5 to 5.5V
V = VCC = 3.0 to 3.6V
Speed
90 = 90ns
12 = 120ns
Package
U = ECOPACK LQFP80
Temperature Range
blank = 0 to 70°C (Commercial)
I = –40 to 85°C (Industrial)
Option
T = Tape & Reel Packing
1. The 5.0V±10% devices are not covered by this datasheet, but by the PSD4235G2 datasheet.
For a list of available options (e.g., Speed, Package) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
121/124
Pin assignments
Appendix A
Table 75.
PSD4235G2V
Pin assignments
PSD4235G2V LQFP80
Pin
num.
Pin assignments
Pin
num.
Pin assignments
Pin
num.
Pin assignments
Pin
num.
Pin assignments
1
PD2
21
PG0
41
PC0
61
PB0
2
PD3
22
PG1
42
PC1
62
PB1
3
AD0
23
PG2
43
PC2
63
PB2
4
AD1
24
PG3
44
PC3
64
PB3
5
AD2
25
PG4
45
PC4
65
PB4
6
AD3
26
PG5
46
PC5
66
PB5
7
AD4
27
PG6
47
PC6
67
PB6
8
GND
28
PG7
48
PC7
68
PB7
9
VCC
29
VCC
49
GND
69
VCC
10
AD5
30
GND
50
GND
70
GND
11
AD6
31
PF0
51
PA0
71
PE0
12
AD7
32
PF1
52
PA1
72
PE1
13
AD8
33
PF2
53
PA2
73
PE2
14
AD9
34
PF3
54
PA3
74
PE3
15
AD10
35
PF4
55
PA4
75
PE4
16
AD11
36
PF5
56
PA5
76
PE5
17
AD12
37
PF6
57
PA6
77
PE6
18
AD13
38
PF7
58
PA7
78
PE7
19
AD14
39
RESET
59
CNTL0
79
PD0
20
AD15
40
CNTL2
60
CNTL1
80
PD1
122/124
PSD4235G2V
28
Revision history
Revision history
Table 76.
Document revision history
Date
Revision
14-Dec-2001
1
Document for the 3.3V±10% range separated out from the data
sheet on the 5V±10% range
2
Document reformatted.
Updated datasheet status to “Full Datasheet”.
Changed TQFP80 to LQFP80, updated Figure 49: LQFP80 - 80-lead
plastic thin, quad, flat package outline, Figure 73: LQFP80 - 80-lead
plastic thin, quad, flat package mechanical data and ECOPACK text
in Section 26: Package mechanical.
Removed SRAM battery backup and related parameters.
12-Feb-2009
Changes
123/124
PSD4235G2V
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124/124