FAIRCHILD 74VHCT573ASJ_07

74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
tm
Features
General Description
■ High speed: tPD = 7.7ns (Typ.) at TA = 25°C
■ High Noise Immunity: VIH = 2.0V, VIL = 0.8V
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a Latch Enable input (LE)
and an Output Enable input (OE). When the OE input is
HIGH, the eight outputs are in a high impedance state.
■ Power Down Protection is provided on all inputs and
outputs
Low
Noise: VOLP = 1.6V (Max.)
■
■ Low Power Dissipation: ICC = 4µA (Max.) @ TA = 25°C
■ Pin and function compatible with 74HCT573
Protection circuits ensure that 0V to 7V can be applied to
the input and output(1) pins without regard to the supply
voltage. This device can be used to interface 3V to 5V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mismatched supply and input voltages.
Note:
1. Outputs in OFF-State
Ordering Information
Order Number
74VHCT573AM
74VHCT573ASJ
74VHCT573AMTC
Package
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Description
Pin Names
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
Description
D0–D7
Data Inputs
LE
Latch Enable Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
www.fairchildsemi.com
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
May 2007
Functional Description
IEEE/IEC
The VHCT573A contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW the latches store the information that
was present on the D inputs, a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode, but, this does
not interfere with entering new data into the latches.
Truth Table
Inputs
Outputs
OE
LE
D
On
L
H
H
H
L
H
L
L
L
L
X
O0
H
X
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
2
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
Logic Symbol
Symbol
Parameter
Rating
VCC
Supply Voltage
–0.5V to +7.0V
VIN
DC Input Voltage
–0.5V to +7.0V
VOUT
DC Output Voltage
Note 2
–0.5V to VCC + 0.5V
Note 3
–0.5V to +7.0V
IIK
Input Diode Current
–20mA
IOK
Output Diode Current(4)
±20mA
IOUT
DC Output Current
±25mA
ICC
DC VCC / GND Current
TSTG
Storage Temperature
TL
±75mA
–65°C to +150°C
Lead Temperature (Soldering, 10 seconds)
260°C
Recommended Operating Conditions(5)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VIN
VOUT
Parameter
Rating
Supply Voltage
4.5V to +5.5V
Input Voltage
0V to +5.5V
Output Voltage
Note 2
0V to VCC
Note 3
0V to 5.5V
TOPR
Operating Temperature
–40°C to +85°C
tr , tf
Input Rise and Fall Time, VCC = 5.0V ± 0.5V
0ns/V ~ 20ns/V
Notes:
2. HIGH or LOW state. IOUT absolute maximum rating must be observed.
3. When outputs are in OFF-State or when VCC = 0V.
4. VOUT < GND, VOUT > VCC (Outputs Active).
5. Unused inputs must be held HIGH or LOW. They may not float.
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
3
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
TA = –40°C
to +85°C
TA = 25°C
Symbol
Parameter
VCC (V)
Conditions
Min.
Typ.
Max.
Min.
Max. Units
VIH
HIGH Level Input
Voltage
4.5
2.0
5.5
2.0
VIL
LOW Level Input
Voltage
4.5
0.8
0.8
5.5
0.8
0.8
HIGH Level Output
Voltage
4.5
LOW Level Output
Voltage
4.5
IOZ
3-STATE Output
Off-State Current
5.5
IIN
Input Leakage
Current
ICC
VOH
VOL
VIN = VIH IOH = –50µA
or VIL
IOH = –8mA
4.40
2.0
2.0
4.50
V
4.40
3.94
VIN = VIH IOL = 50µA
or VIL
IOL = 8mA
V
V
3.80
0.0
0.1
0.1
0.36
0.44
V
VIN = VIH or VIL,
VOUT = VCC or GND
±0.25
±2.5
µA
0–5.5
VIN = 5.5V or GND
±0.1
±1.0
µA
Quiescent Supply
Current
5.5
VIN = VCC or GND
4.0
40.0
µA
ICCT
Maximum ICC /Input
5.5
VIN = 3.4V, Other
Inputs = VCC or GND
1.35
1.50
mA
IOFF
Output Leakage
Current (Power
Down State)
0.0
VOUT = 5.5V
0.5
5.0
µA
Noise Characteristics
TA = 25°C
Symbol
Parameter
VCC (V)
Conditions
Typ.
Limits
Units
Quiet Output Maximum
Dynamic VOL
5.0
CL = 50pF
1.2
1.6
V
VOLV(6)
Quiet Output Minimum
Dynamic VOL
5.0
CL = 50pF
–1.2
–1.6
V
VIHD(6)
Minimum HIGH Level
Dynamic Input Voltage
5.0
CL = 50pF
2.0
V
VILD(6)
Maximum LOW Level
Dynamic Input Voltage
5.0
CL = 50pF
0.8
V
VOLP
(6)
Note:
6. Parameter guaranteed by design.
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
4
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
DC Electrical Characteristics
TA = –40°C
to +85°C
TA = +25°C
Symbol
tPLH, tPHL
tPLH, tPHL
tPZL, tPZH
tPLZ, tPHZ
Parameter
VCC (V)
Min.
Typ. Max. Min. Max. Units
CL = 15pF
7.7
12.3
1.0
13.5
CL = 50pF
8.5
13.3
1.0
14.5
CL = 15pF
5.1
8.5
1.0
9.5
CL = 50pF
5.9
9.5
1.0
10.5
5.0 ± 0.5 RL = 1kΩ CL = 15pF
6.3
10.9
1.0
12.5
CL = 50pF
7.1
11.9
1.0
13.5
5.0 ± 0.5 RL = 1kΩ CL = 50pF
8.8
11.2
1.0
12.0
ns
1.0
1.0
ns
10
10
Propagation Delay
Time (LE to On)
5.0 ± 0.5
Propagation Delay
Time (D to On)
5.0 ± 0.5
3-STATE Output
Enable Time
3-STATE Output
Disable Time
tOSLH, tOSHL Output to Output
Skew
Conditions
5.0 ± 0.5 (7)
ns
ns
ns
Input Capacitance
VCC = Open
4
COUT
Output Capacitance
VCC = 5.0V
6
pF
CPD
Power Dissipation
Capacitance
(8)
25
pF
CIN
pF
Notes:
7. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min|
8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the Latch operates can be
calculated by the equation: CPD(total) = 14 + 13n.
AC Operating Requirements
TA = +25°C
Symbol
VCC (V)
Min.
Minimum Pulse Width (LE)
5.0 ± 0.5
6.5
8.5
ns
tS
Minimum Set-Up Time
5.0 ± 0.5
1.5
1.5
ns
tH
Minimum Hold Time
5.0 ± 0.5
3.5
3.5
ns
tW(H)
Parameter
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
Typ.
Max.
TA = –40°C to +85°C
Min.
Max.
Units
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5
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
AC Electrical Characteristics
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
6
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
7
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
8
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I27
©1997 Fairchild Semiconductor Corporation
74VHCT573A Rev. 1.3
www.fairchildsemi.com
9
74VHCT573A Octal D-Type Latch with 3-STATE Outputs
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