STLC4550 Single chip 802.11b/g WLAN radio DATA BRIEF Features ■ ■ ■ ■ ■ ■ ■ ■ Extremely small footprint Ultra Low Power consumption Fully compliant with the IEEE 802.11b and 802.11g WLAN standards Support for 54, 48, 36, 24, 18, 12, 9, and 6Mbps OFDM, 11 and 5.5Mbps CCK and legacy 2 and 1Mbps data rates Single Chip 802.11b/g WLAN solution with Fully integrated: – Zero IF (ZIF) transceiver, – Voltage Controlled Oscillator (VCO), – High-Speed A/ D and D/A Converters, – Radio Power Management Unit (PMU), – OFDM and CCK baseband processor, – ARM9 Media Access Controller (MAC), – SPI serial host interface – SDIO (4-bit) serial host interface – Passive components integration – PA bias control – Flexible integrated Power Management Unit – Glueless FEM interface Intelligent Power Control, Including 802.11 Power Save Mode Fully integrated Bluetooth coexistence LFBGA240 (8.5x8x1.4mm) Description The STLC4550 is a single chip 802.11b/g WLAN radio for embedded, low-power and very small form factor mobile applications. The product conforms to the IEEE 802.11b and 802.11g protocols operating in the 2.45GHz ISM frequency band supporting OFDM data rates of 54, 48, 36, 24, 18, 12, 9, and 6Mbps as well as CCK data rates of 11 and 5.5Mbps and legacy data rates of 2 and 1Mbps. The STLC4550 is a fully integrated wireless radio including a ZIF transceiver, RDocRev1F Synthesizer/VCO, high-speed data converters, an OFDM/CCK digital baseband processor, an ARM9-based MAC and a complete Power Management Unit with integrated PA bias control. In addition some passive components are integrated further reducing the overall reference design cost and size. An external FEM completes a highly integrated chip set solution. Applications ■ ■ ■ ■ ■ ■ ■ Host control is provided by a flexible SPI or SDIO serial interface. The SPI interface supports a maximum clock rate of 48MHz whereas the SDIO supports a maximum clock rate of xxMHz. For maximum flexibility, the STLC4550 accepts system reference clock frequencies of 19.2, 26, 38.4 and 40MHz. A reference design evaluation platform of hardware and software is provided to system integrators to rapidly enable wireless connectivity to mobile platforms. Cellular Phones Personal Digital Assistants (PDA) Portable Computers Hand-held Data Transfer Devices Cameras Computer Peripherals Cable Replacement Order codes Part number Temp range, °C Package Packing STLC4550 -30 to 85°C LFBGA240- (8.5x8x1.4mm) Tray February 2006 DocRev1 For further information contact your local STMicroelectronics sales office. 1/5 www.st.com 5 2/5 BPF Antenna 7.0pF DocRev1 A 4.7uF Switch Control 6x D 6 OFDM/CCK Modulation Baseband Processor (BBP) D 4 ARM9 WEP Media Access Controller (MAC) 4x D 6 DGND VBATT D LOOP44 FREQ STATUS 3.6V 1.2K 82pF RF_ACTIVE TX_CONF 1000pF REF_CLK OSC_EN SLEEP_CLK POWER_UP VIO HOST_IRQ SPI_DOUT SPI_DIN SPI_CLK SPI_CSX D D 1000pF 1 Block diagram & Application circuit Figure 1. Block Diagram and Application Circuit (Standard Front End Module) 4.7uF Note: Refer to evaluation platform schematics for optimized component values. TRSW+/- ANTSEL+/- A Bluetooth Device A A PA_RREF High-Speed Data Converters 4 1.2V VDD_CORE Host CPU 20K PA_BIAS PA_DET RF VCO RX Downconverter TX Upconverter Baseband Filters RF ZIF Section: 4x A Power Management Unit (PMU) A 1.8V VDDD 0.1uF TX_OUT VCO_LOOP 68pF 4700pF VDD_VCO VCO_CAP LNA_IN- LNA_IN+ 0.1uF 6.49K 0.1uF 3.3pF 3.3pF 4.7uF 7.0pF Balun 2 0.1uF PMU_CREF 2x A 1.8V VDDA 4.7uF 1uF 0.1uF PMU_RSET A VDD_VCO VDD_QLO 1.8V 0.1uF 7.0pF 7.0pF A 1M A 2.8V VDD_BIAS 22uF RF FEM (PA Swiches) A 7.0pF Block diagram & Application circuit STLC4550 4.7uH STLC4550 2 Package Information Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LFBGA240 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A A1 MAX. MIN. TYP. 1.4 0.15 MAX. 0.055 0.006 A2 1.065 0.042 A3 0.28 0.011 A4 0.8 0.031 b 0.25 0.3 0.35 0.010 0.012 0.014 D 8.35 8.5 8.65 0.329 0.335 0.341 D1 E 7.5 7.85 OUTLINE AND MECHANICAL DATA 8 0.295 8.15 0.309 0.315 E1 7 0.276 e 0.5 0.020 F 0.5 0.020 0.321 Body: 8.5 x 8 x 1.4mm ddd 0.08 0.003 eee 0.15 0.006 fff 0.05 0.002 LFBGA240 Low Profile Ball Grid Array 7870466 A DocRev1 3/5 Revision history 3 STLC4550 Revision history Table 1. 4/5 Document revision history Date Revision 06-Feb-2006 1 Changes Initial release. DocRev1 STLC4550 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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