STMICROELECTRONICS STTS2002_11

STTS2002
2.3 V memory module temperature sensor
with a 2 Kb SPD EEPROM
Features
■
2.3 V memory module temperature sensor with
integrated 2 Kb SPD EEPROM
■
Forward compatible with JEDEC TSE 2002a2
and backward compatible with STTS424E02
■
Operating temperature range:
– –40 °C to +125 °C
■
Single supply voltage: 2.3 V to 3.6 V
■
2 mm x 3 mm TDFN8, height: 0.80 mm (max)
– JEDEC MO-229, WCED-3 compliant
■
RoHS compliant, halogen-free
TDFN8
2 mm x 3 mm
(max height 0.80 mm)
Temperature sensor
2 Kb SPD EEPROM
■
Temperature sensor resolution:
programmable (9-12 bits)
0.25 °C (typ)/LSB - (10-bit) default
■
Functionality identical to ST’s M34E02 SPD
EEPROM
■
■
Temperature sensor accuracy (max):
– ± 1 °C from +75 °C to +95 °C
– ± 2 °C from +40 °C to +125 °C
– ± 3 °C from –40 °C to +125 °C
Permanent and reversible software data
protection for the lower 128 bytes
■
Byte and page write (up to 16 bytes)
■
Self-time WRITE cycle (5 ms, max)
■
Automatic address incrementing
■
ADC conversion time: 125 ms (max) at default
resolution (10-bit)
■
Typical operating supply current: 160 µA
(EEPROM standby)
■
■
Two-wire bus
■
Temperature hysteresis selectable set points
from: 0, 1.5, 3, 6.0 °C
Two-wire SMBus/I2C - compatible serial
interface
■
Supports up to 400 kHz transfer rate
Supports SMBus timeout 25 ms - 35 ms
■
Does not initiate clock stretching
March 2011
Doc ID 15389 Rev 5
1/52
www.st.com
1
Contents
STTS2002
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
2.1
Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1
A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3
SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.4
SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.5
EVENT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.6
VDD (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
SMBus/I2C communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
SMBus/I2C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
SMBus/I2C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
4.2.1
Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2
Interrupt mode
4.2.3
Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.4
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.5
Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1
4.4
2/52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Temperature trip point registers (read/write) . . . . . . . . . . . . . . . . . . . . . . 25
4.4.1
Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.2
Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5
Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6
Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . . 28
4.7
Temperature resolution register (read/write) . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 15389 Rev 5
STTS2002
Contents
4.8
5
SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
2 Kb SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2
Internal device reset - SPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4
Software write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5
5.6
5.7
6
SMBus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4.1
SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.2
PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.2
Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5.3
Write cycle polling using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read operations - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6.1
Random address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6.2
Current address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6.3
Sequential read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6.4
Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Initial delivery state - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1
Programming the SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.1
DIMM isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.2
DIMM inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 39
7
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 15389 Rev 5
3/52
List of tables
STTS2002
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
4/52
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC characteristics of STTS2002 for SMBus and I2C compatibility timings. . . . . . . . . . . . . 15
Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17
Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Legend for Figure 9: Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Temperature register coding examples (for 10 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Manufacturer ID register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device ID and device revision ID register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Temperature resolution register (TRES) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TRES details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Acknowledge when writing data or defining the write-protection (instructions with R/W bit =
0)37
Acknowledge when reading the write protection (instructions with R/W bit=1). . . . . . . . . . 38
DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC/AC characteristics - temperature sensor component with EEPROM . . . . . . . . . . . . . . 41
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 44
Parameters for landing pattern - TDFN8 package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Carrier tape dimensions TDFN8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reel dimensions for 8 mm carrier tape - TDFN8 package . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 15389 Rev 5
STTS2002
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SMBus/I2C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SMBus/I2C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12
SMBus/I2C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13
SMBus/I2C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Write mode sequences in a non write-protected area of SPD . . . . . . . . . . . . . . . . . . . . . . 34
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read mode sequences - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 44
DN package topside marking information (TDFN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Landing pattern - TDFN8 package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Carrier tape for TDFN8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Doc ID 15389 Rev 5
5/52
Description
1
STTS2002
Description
The STTS2002 is targeted for DIMM modules in mobile personal computing platforms
(laptops), servers and other industrial applications. The thermal sensor (TS) in the
STTS2002 is compliant with the JEDEC specification TSE2002a2, which defines memory
module thermal sensors requirements for mobile platforms. The 2 Kb serial presence detect
(SPD) I2C-compatible electrically erasable programmable memory (EEPROM) in the
STTS2002 is organized as 256 x8 bits and is functionally identical to the industry standard
M34E02.
The TS-SPD EEPROM combination provides space as well as cost savings for mobile and
server platform dual inline memory modules (DIMM) manufacturers, as it is packaged in the
compact 2 mm x 3 mm 8-lead TDFN package with a thinner maximum height of 0.80 mm.
The DN package is compliant to JEDEC MO-229, variation WCED-3.
The digital temperature sensor has a programmable 9-12 bit analog-to-digital converter
(ADC) which monitors and digitizes the temperature to a resolution of up to 0.0625 °C. The
default resolution is 0.25 °C/LSB (10-bit). The typical accuracies over these temperature
ranges are:
±2 °C over the full temperature measurement range of –40 °C to 125 °C
±1 °C in the +40 °C to +125 °C active temperature range, and
±0.5 °C in the +75 °C to +95 °C monitor temperature range
The temperature sensor in the STTS2002 is specified for operating at supply voltages from
2.3 V to 3.6 V. Operating at 3.3 V, the typical supply current is 160 µA (includes SMBus
communication current).
The on-board sigma delta ADC converts the measured temperature to a digital value that is
calibrated in °C. For Fahrenheit applications, a lookup table or conversion routine is
required. The STTS2002 is factory-calibrated and requires no external components to
measure temperature.
The digital temperature sensor component has user-programmable registers that provide
the capabilities for DIMM temperature-sensing applications. The open drain event output pin
is active when the monitoring temperature exceeds a programmable limit, or it falls above or
below an alarm window. The user has the option to set the event output as a critical
temperature output. This pin can be configured to operate in either a comparator mode for
thermostat operation or in interrupt mode.
The 2 Kb serial EEPROM memory in the STTS2002 has the ability to permanently lock the
data in its first half (upper) 128 bytes (locations 00h to 7Fh). This feature has been designed
specifically for use in DRAM DIMMs with SPD. All of the information concerning the DRAM
module configuration (e.g. access speed, size, and organization) can be kept write
protected in the first half of the memory. The second half (lower) 128 bytes of the memory
can be write protected using two different software write protection mechanisms.
By sending the device a specific sequence, the first 128 bytes of the memory become write
protected: permanently or resettable. In the STTS2002 the write protection of the memory
array is dependent on whether the software protection has been set.
6/52
Doc ID 15389 Rev 5
STTS2002
2
Serial communications
Serial communications
The STTS2002 has a simple 2-wire SMBus/I2C-compatible digital serial interface which
allows the user to access both the 2 Kb serial EEPROM and the data in the temperature
register at any time. It communicates via the serial interface with a master controller which
operates at speeds of up to 400 kHz. It also gives the user easy access to all of the
STTS2002 registers in order to customize device operation.
2.1
Device type identifier (DTI) code
The JEDEC temperature sensor and EEPROM each have their own unique I2C address,
which ensures that there are no compatibility or data translation issues. This is due to the
fact that each of the devices have their own 4-bit DTI code, while the remaining three bits
are configurable. This enables the EEPROM and thermal sensors to provide their own
individual data via their unique addresses and still not interfere with each other’s operation
in any way. The DTI codes are:
●
'0011' for the TS, and
●
'1010' for addressing the EEPROM memory array, and
●
‘0110’ to access the software write protection settings of the EEPROM.
Doc ID 15389 Rev 5
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Serial communications
Figure 1.
STTS2002
Logic diagram
VDD
SDA(1)
EVENT(1)
SCL
A2
A1
A0
STTS2002
VSS
AI12261
1. SDA and EVENT are open drain.
Table 1.
Signal names
Pin
Symbol
Description
1
A0
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
2
A1
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
3
A2
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
4
VSS
Supply ground
5
(1)
SDA
6
SCL
7
EVENT(1)
8
VDD
Direction
Serial data
Input/output
Serial clock
Input
Event output pin. Open drain and active-low.
Output
Supply power (2.3 V to 3.6 V)
1. SDA and EVENT are open drain.
Note:
See Section 2.2: Pin descriptions on page 10 for details.
Figure 2.
TDFN8 connections (top view)
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VDD
EVENT(1)
SCL
SDA(1)
AI12262
1. SDA and EVENT are open drain.
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Doc ID 15389 Rev 5
STTS2002
Figure 3.
Serial communications
Block diagram
8
VDD
2 Kb SPD EEPROM
Temperature
Sensor
Logic Control
Comparator
Timing
EVENT
7
ADC
Standard array
(80h - FFh)
Capability
Register
Configuration
Register
Temperature
Register
Software
write-protected array
(00h - 7Fh)
Address Pointer
Register
Upper
Register
Lower
Register
Critical
Register
Manufacturer
ID
Device ID/
Revision
1
2
3
SCL
A0
A1
A2
6
SMBus/I2C
Interface
SDA
5
VSS
4
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Serial communications
2.2
Pin descriptions
2.2.1
A0, A1, A2
STTS2002
A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2C interface address.
They can be set to VDD or GND to provide 8 unique address selections. These pins are
internally connected to the E2, E1, E0 (chip selects) of EEPROM.
2.2.2
VSS (ground)
This is the reference for the power supply. It must be connected to system ground.
2.2.3
SDA (open drain)
This is the serial data input/output pin.
2.2.4
SCL
This is the serial clock input pin.
2.2.5
EVENT (open drain)
This output pin is open drain and active-low.
2.2.6
VDD (power)
This is the supply voltage pin, and ranges from 2.3 V to 3.6 V.
10/52
Doc ID 15389 Rev 5
STTS2002
3
Temperature sensor operation
Temperature sensor operation
The temperature sensor continuously monitors the ambient temperature and updates the
temperature data register. Temperature data is latched internally by the device and may be
read by software from the bus host at any time.
The SMBus/I2C slave address selection pins allow up to 8 such devices to co-exist on the
same bus. This means that up to 8 memory modules can be supported, given that each
module has one such slave device address slot.
After initial power-on, the configuration registers are set to the default values. The software
can write to the configuration register to set bits per the bit definitions in Section 3.1:
SMBus/I2C communications.
For details of operation and usage of 2 Kb SPD EEPROM, refer to Section 5: SPD
EEPROM operation.
3.1
SMBus/I2C communications
The registers in this device are selected by the pointer register. At power-up, the pointer
register is set to “00”, which is the capability register location. The pointer register latches
the last location it was set to. Each data register falls into one of three types of user
accessibility:
1.
Read-only
2.
Write-only, and
3.
WRITE/READ same address
A WRITE to this device will always include the address byte and the pointer byte. A WRITE
to any register other than the pointer register, requires two data bytes.
Reading this device is achieved in one of two ways:
●
If the location latched in the pointer register is correct (most of the time it is expected
that the pointer register will point to one of the read temperature registers because that
will be the data most frequently read), then the READ can simply consist of an address
byte, followed by retrieval of the two data bytes.
●
If the pointer register needs to be set, then an address byte, pointer byte, repeat start,
and another address byte will accomplish a READ.
The data byte transfers the MSB first. At the end of a READ, this device can accept either an
acknowledge (ACK) or no acknowledge (No ACK) status from the master. The No ACK
status is typically used as a signal for the slave that the master has read its last byte. This
device subsequently takes up to 125 ms to measure the temperature for the default
temperature resolution.
Note:
STTS2002 does not initiate clock stretching which is an optional I2C bus feature.
Doc ID 15389 Rev 5
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Temperature sensor operation
Figure 4.
STTS2002
SMBus/I2C write to pointer register
1
SCL
9
1
9
SDA
0
0
Start
by
Master
1
1
A2 A1 A0 R/W
0
0
0
0
0
D2 D1 D0
Pointer Byte
Address Byte
ACK
by
STTS2002
ACK
by
STTS2002
AI12264
Figure 5.
SMBus/I2C write to pointer register, followed by a read data word
1
SCL
9
1
9
SDA
0
0
Start
by
Master
1
SDA
(continued)
0
1
0
0
0
0
0
D2 D1 D0
Pointer Byte
ACK
by
STTS2002
ACK
by
STTS2002
9
0
Repeat
Start
by
Master
A2 A1 A0 R/W
Address Byte
1
SCL
(continued)
1
1
A2 A1 A0 R/W
1
D15
Address Byte
9
D14
D13
D12 D11 D10
D9
1
D8
MSB Data Byte
ACK
by
STTS2002
D7
9
D6
D5
D4
D3
D2
LSB Data Byte
ACK
by
Master
D1
D0
Stop
Cond.
No ACK
by
by
Master
Master
AI12265
12/52
Doc ID 15389 Rev 5
STTS2002
Temperature sensor operation
Figure 6.
SMBus/I2C write to pointer register, followed by a write data word
1
SCL
9
1
9
SDA
0
0
Start
by
Master
SCL
(continued)
SDA
(continued)
1
1
A2 A1 A0 R/W
0
0
0
0
0
D2 D1 D0
Pointer Byte
Address Byte
ACK
by
STTS2002
ACK
by
STTS2002
1
D15
9
D14
D13
D12 D11 D10
D9
D8
1
D7
MSB Data Byte
9
D6
D5
D4
D3
D2
LSB Data Byte
ACK
by
STTS2002
D1
D0
Stop
Cond.
No ACK
by
by
Master
STTS2002
AI14012
3.2
SMBus/I2C slave sub-address decoding
The physical address for the TS is different than that used by the EEPROM. The TS physical
address is binary 0 0 1 1 A2 A1 A0 RW, where A2, A1, and A0 are the three slave subaddress pins, and the LSB “RW” is the READ/WRITE flag.
The EEPROM physical address is binary 1 0 1 0 A2 A1 A0 RW for the memory array and is
0 1 1 0 A2 A1 A0 RW for permanently set write protection mode.
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Temperature sensor operation
STTS2002
SMBus/I2C AC timing consideration
3.3
In order for this device to be both SMBus- and I2C-compatible, it complies to a subset of
each specification. The requirements which enable this device to co-exist with devices on
either an SMBus or an I2C bus include:
●
The SMBus minimum clock frequency is required.
●
The SMBus timeout is maximum 35 ms (temperature sensor only).
SMBus/I2C timing diagram
Figure 7.
t
LOW
t
t
R
F
VIH
SCL
VIL
t
BUF
HD:STA
t
HD:DI
t
t
t
HIGH
SU:STA
t
SU:STO
t
t
HD:DAT
SU:DAT
V
IH
VIL
SDA
P
S
S
P
NOTE: P stands for STOP and S stands for START
VIH
SCL
V
IL
t
SU:STO
t
SU:STA
VIH
SDA
VIL
t
W
STOP
CONDITION
WRITE
CYCLE
START
CONDITION
ai12266a
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Doc ID 15389 Rev 5
STTS2002
Temperature sensor operation
AC characteristics of STTS2002 for SMBus and I2C compatibility timings
Table 2.
Symbol
Parameter
Min
Max
Units
fSCL
SMBUS/I2C clock frequency
10
400
kHz
tHIGH
Clock high period
600
–
ns
Clock low period
1300
–
ns
tLOW
(1)
tR(2)
Clock/data rise time
–
300
ns
tF(2)
Clock/data fall time
20
300
ns
tSU:DAT
Data in setup time
100
–
ns
tHD:DI
Data in hold time
0
–
ns
Data out hold time
200
900
ns
Repeated start condition setup time
600
–
ns
tHD:STA
Hold time after (repeated) start condition. After this
period, the first clock cycle is generated.
600
–
ns
tSU:STO
Stop condition setup time
600
–
ns
tBUF
Bus free time between stop (P) and start (S) conditions
1300
–
ns
tW(4)
WRITE time for EEPROM
–
10
ms
25
35
ms
tHD:DAT
tSU:STA(3)
ttimeout(5)
Bus timeout (temperature sensor only)
1. STTS2002 will not initiate clock stretching which is an
I 2C
bus optional feature.
2. Guaranteed by design and characterization, not necessarily tested.
3. For a restart condition, or following a WRITE cycle.
4. This parameter reflects maximum WRITE time for EEPROM.
5. Bus timeout value supported depends on setting of TMOUT bit 6 in capability register.
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Temperature sensor registers
4
STTS2002
Temperature sensor registers
The temperature sensor component is comprised of various user-programmable registers.
These registers are required to write their corresponding addresses to the pointer register.
They can be accessed by writing to their respective addresses (see Table 3). Pointer
register bits 7 - 4 must always be written to '0' (see Table 4). This must be maintained, as not
setting these bits to '0' may keep the device from performing to specifications.
The main registers include:
●
Capability register (read-only)
●
Configuration register (read/write)
●
Temperature register (read-only)
●
Temperature trip point registers (read/write), including
–
Alarm temperature upper boundary,
–
Alarm temperature lower boundary, and
–
Critical temperature.
●
Manufacturer ID register (read-only)
●
Device ID and device revision ID register (read-only)
●
Temperature resolution register (TRES) (read/write)
See Table 5 on page 17 for pointer register selection bit details.
Table 3.
Temperature sensor registers summary
Address (hex)
Not applicable
Note:
16/52
Register name
Power-on default
Address pointer
Undefined
00
Capability
B-grade
0x006F
01
Configuration
0x0000
02
Alarm temperature upper boundary trip
0x0000
03
Alarm temperature lower boundary trip
0x0000
04
Critical temperature trip
0x0000
05
Temperature
06
Manufacturer’s ID
0x104A
07
Device ID/revision
0x0300
08
Temperature resolution register
0x0001
Undefined
Registers beyond the specified (00-08) are reserved for STMicroelectronics internal use
only, for device test modes in product manufacturing. The registers must NOT be accessed
by the user (customer) in the system application or the device may not perform according to
specifications.
Doc ID 15389 Rev 5
STTS2002
Temperature sensor registers
Table 4.
Pointer register format
MSB
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
P3
P2
P1
P0
Pointer/register select bits
Table 5.
Pointer register select bits (type, width, and default values)
P3
P2
P1
P0
Name
0
0
0
0
CAPA
Thermal sensor capabilities
0
0
0
1
CONF
0
0
1
0
0
0
1
0
1
0
Width
(bits)
Register description
16
R
00 6F
Configuration
16
R/W
00 00
UPPER
Alarm temperature upper boundary
16
R/W
00 00
1
LOWER
Alarm temperature lower boundary
16
R/W
00 00
0
0
CRITICAL Critical temperature
16
R/W
00 00
1
0
1
TEMP
Temperature
16
R
00 00
0
1
1
0
MANU
Manufacturer ID
16
R
10 4A
0
1
1
1
ID
Device ID/revision
16
R
03 00
1
0
0
0
TRES
Temperature resolution register
8
R/W
01
4.1
B-grade only
Type Default state
(R/W)
(POR)
Capability register (read-only)
This 16-bit register is read-only, and provides the TS capabilities which comply with the
minimum JEDEC TSE2002a2 specifications (see Table 6 and Table 7 on page 18). The
STTS2002 resolution is programmable via writing to pointer 08 register. The power-on
default value is 0.25 °C/LSB (10-bit).
Table 6.
Capability register format
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EVSD
TMOUT
VHV
TRES1
TRES0
Wider
range
Higher
precision
Alarm and
critical trips
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Temperature sensor registers
Table 7.
STTS2002
Capability register bit definitions
Bit
0
Basic capability
– 0 = Alarm and critical trips turned OFF.
– 1 = Alarm and critical trips turned ON.
1
Accuracy
– 0 = Accuracy ±2 °C over the active range and ±3 °C over the monitoring range
(C-grade).
– 1 = High accuracy ±1 °C over the active range and ±2 °C over the monitoring range
(B-grade) (default).
2
Range width
– 0 = Values lower than 0 °C will be clamped and represented as binary value '0'.
– 1 = Temperatures below 0 °C can be read and the Sign bit will be set accordingly.
4:3
Temperature resolution
– 00 = 9 bit, 0.5 °C/LSB
– 01 = 10 bit, 0.25 °C/LSB - default resolution
– 10 = 11 bit, 0.125 °C/LSB
– 11 = 12 bit, 0.0625 °C/LSB
5
(VHV) high voltage support for A0 (pin 1)
– 1 = STTS2002 supports a voltage up to 10 volts on the A0 pin - (default)
6
TMOUT - bus timeout support (for temperature sensor only)
– 0 = ttimeout is supported in the range of 10 to 60 ms
– 1 = Default for STTS2002-SMBus compatible 25 ms - 35 ms
Note: Timeout is not required for EEPROM component
7
EVSD - EVENT behavior upon shutdown
– 0 = Default for STTS2002. The EVENT output freezes in its current state when
entering shutdown. Upon entering shutdown, the EVENT output remains in the
previous state until the next thermal data conversion or possibly sooner if EVENT is
programmed for comparator mode.
– 1 = EVENT output is deasserted (not driven) when entering shutdown and remains
deasserted upon exit from shutdown until the next thermal sample is taken or possibly
sooner if EVENT is programmed for comparator mode.
15:8
18/52
Definition
Reserved
These values must be set to '0'.
Doc ID 15389 Rev 5
STTS2002
4.2
Temperature sensor registers
Configuration register (read/write)
The 16-bit configuration register stores various configuration modes that are used to set up
the sensor registers and configure according to application and JEDEC requirements (see
Table 8 on page 19 and Table 9 on page 20).
4.2.1
Event thresholds
All event thresholds use hysteresis as programmed in register address 0x01 (bits 10 through
9) to be set when they de-assert.
4.2.2
Interrupt mode
The interrupt mode allows an event to occur where software may write a '1' to the clear
event bit (bit 5) to de-assert the event Interrupt output until the next trigger condition occurs.
4.2.3
Comparator mode
Comparator mode enables the device to be used as a thermostat. READs and WRITEs on
the device registers will not affect the event output in comparator mode. The event signal will
remain asserted until temperature drops outside the range or is re-programmed to make the
current temperature “out of range”.
4.2.4
Shutdown mode
The STTS2002 features a shutdown mode which disables all power-consuming activities
(e.g. temperature sampling operations), and leaves the serial interface active. This is
selected by setting shutdown bit (bit 8) to '1'. In this mode, the devices consume the
minimum current (ISHDN), as shown in Table 30 on page 41.
Note:
Bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'.
The device may be enabled for continuous operation by clearing bit 8 to '0'. In shutdown
mode, all registers may be read or written to. Power recycling will also clear this bit and
return the device to continuous mode as well.
Table 8.
Configuration register format
Bit15
Bit14
Bit13
Bit12
Bit11
RFU
RFU
RFU
RFU
RFU
Bit7
Bit6
Bit5
Bit4
Bit3
Critical
lock bit
Alarm lock
bit
Clear
event
Bit10
Hysteresis Hysteresis
Bit2
Event output Event output
Critical
status
control
event only
Doc ID 15389 Rev 5
Bit9
Bit8
Shutdown
mode
Bit1
Bit0
Event
polarity
Event
mode
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Temperature sensor registers
Table 9.
Bit
STTS2002
Configuration register bit definitions
Definition
0
Event mode
– 0 = Comparator output mode (this is the default).
– 1 = Interrupt mode; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it is
unlocked.
1
Event polarity(1)
The event polarity bit controls the active state of the EVENT pin. The EVENT pin is driven to this state
when it is asserted.
– 0 = Active-low (this is the default). Requires a pull-up resistor to set the inactive state of the opendrain output. The power to the pull-up resistor should not be greater than VDD + 0.2 V. Active state
is logical “0”.
– 1 = Active-high. The active state of the pin is then logical “1”.
2
Critical event only
– 0 = Event output on alarm or critical temperature event (this is the default).
– 1 = Event only if the temperature is above the value in the critical temperature register (TA > TCRIT); when
the alarm window lock bit (bit6) is set, this bit cannot be altered until it is unlocked.
3
Event output control
– 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it
is unlocked.
4
Event status (read-only)(2)
– 0 = Event output condition is not being asserted by this device.
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
5
Clear event (write-only)(3)
– 0 = No effect.
– 1 = Clears the active event in interrupt mode. The pin is released and will not assert until a new interrupt
condition occurs.
6
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
7
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
8
Shutdown mode
– 0 = TS is enabled, continuous conversion (this is the default).
– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No
event conditions will be asserted; when either of the lock bits (bit6 or bit7) is set, then this bit cannot be
altered until it is unlocked. It can be cleared at any time.
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Doc ID 15389 Rev 5
STTS2002
Table 9.
Temperature sensor registers
Configuration register bit definitions (continued)
Bit
Definition
10:9
Hysteresis enable (see Figure 8 and Table 10)
– 00 = Hysteresis is disabled (default)
– 01 = Hysteresis is enabled at 1.5 °C
– 10 = Hysteresis is enabled at 3 °C
– 11 = Hysteresis is enabled at 6 °C
Hysteresis applies to all limits when the temperature is dropping below the threshold so that once the
temperature is above a given threshold, it must drop below the threshold minus the hysteresis in order to be
flagged as an interrupt event. Note that hysteresis is also applied to the EVENT pin functionality. When
either of the lock bits is set, these bits cannot be altered.
15:11
Reserved for future use. These bits will always read ‘0’ and writing to them will have no effect. For
future compatibility, all RFU bits must be programmed as ‘0’.
1. As this device is used in DIMM (memory modules) applications, it is strongly recommended that only the active-low polarity
(default) is used. This will provide full compatibility with the STTS424E02. This is the recommended configuration for the
STTS2002.
2. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be
cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning).
3. Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always
return a logic '0' result.
Figure 8.
Hysteresis
TH
TH - HYS
TL
TL - HYS
Below Window bit
Above Window bit
AI12270
1. TH = Value stored in the alarm temperature upper boundary trip register
2. TL = Value stored in the alarm temperature lower boundary trip register
3. HYS = Absolute value of selected hysteresis
Table 10.
Hysteresis as applied to temperature movement
Below alarm window bit
Above alarm window bit
Temperature slope
Temperature
threshold
Temperature slope
Temperature
threshold
Sets
Falling
TL - HYS
Rising
TH
Clears
Rising
TL
Falling
TH - HYS
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Temperature sensor registers
4.2.5
STTS2002
Event output pin functionality
The STTS2002 EVENT pin is an open drain output that requires a pull-up to VDD on the
system motherboard or integrated into the master controller. EVENT has three operating
modes, depending on configuration settings and any current out-of-limit conditions. These
modes are interrupt, comparator or critical.
In interrupt mode the EVENT pin will remain asserted until it is released by writing a ‘1’ to
the “Clear Event” bit in the status register. The value to write is independent of the EVENT
polarity bit.
In comparator mode the EVENT pin will clear itself when the error condition that caused the
pin to be asserted is removed.
In the critical mode the EVENT pin will only be asserted if the measured temperature
exceeds the critical limit. Once the pin has been asserted, it will remain asserted until the
temperature drops below the critical limit minus hysteresis. Figure 9 on page 23 illustrates
the operation of the different modes over time and temperature.
When the hysteresis bits (bits 10 and 9) are enabled, hysteresis may be used to sense
temperature movement around trigger points. For example, when using the “above alarm
window” bit (temperature register bit 14, see Table 12 on page 24) and hysteresis is set to
3 °C, as the temperature rises, bit 14 is set (bit 14 = 1). The temperature is above the alarm
window and the temperature register contains a value that is greater than the value set in
the alarm temperature upper boundary register (see Table 16 on page 26).
If the temperature decreases, bit 14 will remain set until the measured temperature is less
than or equal to the value in the alarm temperature upper boundary register minus 3 °C (see
Figure 8 on page 21 and Table 10 on page 21 for details.
Similarly, when using the “below alarm window” bit (temperature register bit 13, see Table 12
on page 24) will be set to '0'. The temperature is equal to or greater than the value set in the
alarm temperature lower boundary register (see Table 17 on page 26). As the temperature
decreases, bit 13 will be set to '1' when the value in the temperature register is less than the
value in the alarm temperature lower boundary register minus 3 °C (see Figure 8 on
page 21 and Table 10 on page 21 for details.
The device will retain the previous state when entering the shutdown mode. If the device
enters the shutdown mode while the EVENT pin is low, the shutdown current will increase
due to the additional event output pull-down current.
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Doc ID 15389 Rev 5
STTS2002
Temperature sensor registers
Figure 9.
Event output boundary timings
TCRIT - THYS
TCRIT
TUPPER - THYS
TUPPER - THYS
TUPPER
TA
TLOWER - THYS
TLOWER
Event output (active low)
TLOWER - THYS
Comparator
Interrupt
S/W Int. Clear
Critical
Note:
1
2
1 3
4
35 7 6 4
2
AI12271
Table 11.
Legend for Figure 9: Event output boundary timings
Event output
Note
TA bits
Event output boundary conditions
Comparator Interrupt Critical
15
14
13
1
TA ≥ TLOWER
H
L
H
0
0
0
2
TA < TLOWER - THYS
L
L
H
0
0
1
3
TA > TUPPER
L
L
H
0
1
0
4
TA ≤ TUPPER - THYS
H
L
H
0
0
0
5
TA ≥ TCRIT
L
L
L
1
0
0
6
TA < TCRIT - THYS
L
H
H
0
1
0
7
When TA ≥ TCRIT and TA < TCRIT - THYS, the event output is in comparator mode and bit 0 of
the configuration register (interrupt mode) is ignored.
Systems that use the active high mode for Event output must be wired point-to-point
between the STTS2002 and the sensing controller. Wire-OR configurations should not be
used with active high Event output since any device pulling the Event output signal low will
mask the other devices on the bus. Also note that the normal state of Event output in active
high mode is a ‘0’ which will constantly draw power through the pull-up resistor.
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Temperature sensor registers
4.3
STTS2002
Temperature register (read-only)
This 16-bit, read-only register stores the temperature measured by the internal band gap TS
as shown inTable 12. When reading this register, the MSBs (bit 15 to bit 8) are read first, and
then the LSBs (bit 7 to bit 0) are read. The result is the current-sensed temperature. The
data format is 2s complement with one LSB = 0.25 °C for the default resolution. The MSB
has a 128 °C resolution.
The trip status bits represent the internal temperature trip detection, and are not affected by
the status of the event or configuration bits (e.g. event output control or clear event). If
neither of the above or below values are set (i.e. both are 0), then the temperature is exactly
within the user-defined alarm window boundaries.
4.3.1
Temperature format
The 16-bit value used in the trip point set and temperature read-back registers is 2s
complement, with the LSB equal to 0.0625 °C (see Table 12). For example:
1.
a value of 019C h represents 25.75 °C,
2.
a value of 07C0 h represents 124 °C, and
3.
a value of 1E74 h represents –24.75 °C
All unused resolution bits are set to zero. The MSB will have a resolution of 128 °C. The
STTS2002 supports programmable resolutions (9-12 bits) which is 0.5 to 0.0625 °C/LSB.
The default is 0.25 °C/LSB (10 bits) programmable.
The upper 3 bits indicate trip status based on the current temperature, and are not affected
by the event output status.
Table 12.
Temperature register format
Sign
MSB
Bit
15
Bit
14
Bit
13
Flag bit
Flag bit
Flag bit
Bit
12
LSB(1)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
11 10 9
8
7
6
5
4
3
Sign 128 64 32 16
Above
Below
Above
alarm
alarm
critical
input(4) window(4) window(4)
0
0
2
1
0
0
0
1
1
1
1
1
0
0
0.25
Bit
0(3)
0.125 0.0625 °C/LSB
0
0
0
0
0
0
07C0 h
Example hex value of 1D80 corresponds to –40 °C (10-bit)
0
1
1
1
0
1
1
0
0
0
1. Bit 2 is LSB for default 10-bit mode.
2. Depending on status of the resolution register, bit 1 may display 0.125 °C value.
3. Depending on status of the resolution register, bit 0 may display 0.0625 °C value.
4. See Table 14 for explanation.
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0.5
Bit
1(2)
Example hex value of 07C0 corresponds to 124 °C (10-bit)
Flag bits
0
4
Temperature (default - 10 bit)
Flag bits
0
8
Bit
2
Doc ID 15389 Rev 5
0
0
0
0
1D80 h
STTS2002
Temperature sensor registers
A 0.25 °C minimum granularity is supported in all registers. Examples of valid settings and
interpretation of temperature register bits for 10-bit (0.25 °C) default resolution are provided
in Table 13.
Table 13.
Table 14.
Bit
4.4
Temperature register coding examples (for 10 bits)
B15:B0 (binary)
Value
Units
xxx0 0000 0010 11xx
+2.75
°C
xxx0 0000 0001 00xx
+1.00
°C
xxx0 0000 0000 01xx
+0.25
°C
xxx0 0000 0000 00xx
0
°C
xxx1 1111 1111 11xx
–0.25
°C
xxx1 1111 1110 00xx
–1.00
°C
xxx1 1111 1101 11xx
–2.25
°C
Temperature register bit definitions
Definition with hysteresis = 0
13
Below (temperature) alarm window
– 0 = Temperature is equal to or above the alarm window lower boundary temperature.
– 1 = Temperature is below the alarm window.
14
Above (temperature) alarm window.
– 0 = Temperature is equal to or below the alarm window upper boundary temperature.
– 1 = Temperature is above the alarm window.
15
Above critical trip
– 0 = Temperature is below the critical temperature setting.
– 1 = Temperature is equal to or above the critical temperature setting.
Temperature trip point registers (read/write)
The STTS2002 alarm mode registers provide for 11-bit data in 2s compliment format. The
data provides for one LSB = 0.25 °C. All unused bits in these registers are read as '0'.
The STTS2002 has three temperature trip point registers (see Table 15):
Note:
●
Alarm temperature upper boundary threshold (Table 16),
●
Alarm temperature lower boundary threshold (Table 17), and
●
Critical temperature trip point value (Table 18).
If the upper or lower boundary threshold values are being altered in-system, all interrupts
should be turned off until a known state can be obtained to avoid superfluous interrupt
activity.
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Temperature sensor registers
Table 15.
Temperature trip point register format
Width
(bits)
Type
(R/W)
Default state
(POR)
Alarm temperature upper boundary
16
R/W
00 00
LOWER
Alarm temperature lower boundary
16
R/W
00 00
CRITICAL
Critical temperature
16
R/W
00 00
P3
P2
P1
P0
0
0
1
0
UPPER
0
0
1
1
0
1
0
0
4.4.1
STTS2002
Name
Register description
Alarm window trip
The device provides a comparison window with an upper temperature trip point in the alarm
upper boundary register, and a lower trip point in the alarm lower boundary register. When
enabled, the event output will be triggered whenever entering or exiting (crossing above or
below) the alarm window.
4.4.2
Critical trip
The device can be programmed in such a way that the event output is only triggered when
the temperature exceeds the critical trip point. The critical temperature setting is
programmed in the critical temperature register. When the temperature sensor reaches the
critical temperature value in this register, the device is automatically placed in comparator
mode, which means that the critical event output cannot be cleared by using software to set
the clear event bit.
Table 16.
Alarm temperature upper boundary register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
Bit
12
LSB(1)
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Alarm window upper boundary temperature
Bit(2)
1
Bit(3)
0
0
0
1. Bit 2 is LSB for default 10-bit mode.
2. Depending on status of the resolution register, bit 1 may display 0.125 °C value.
3. Depending on status of the resolution register, bit 0 may display 0.0625 °C value.
Table 17.
Alarm temperature lower boundary register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
Bit
12
LSB(1)
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Alarm window lower boundary temperature
1. Bit 2 is LSB for default 10-bit mode.
2. Depending on status of the resolution register, bit 1 may display 0.125 °C value.
3. Depending on status of the resolution register, bit 0 may display 0.0625 °C value.
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Bit
4
Doc ID 15389 Rev 5
Bit
3
Bit
2
Bit(2) Bit(3)
1
0
0
0
STTS2002
Table 18.
Temperature sensor registers
Critical temperature register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
Bit
12
LSB(1)
Bit
11
Bit
10
Bit
9
Bit
8
Bit(2)
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Critical temperature trip point
Bit(3) Bit(4)
1
0
0
0
1. Bit 2 is LSB for default 10-bit mode.
2. If critical trip lockout bit (bit 7 of configuration register in Table 9) is set, then this register becomes read-only.
3. Depending on status of the resolution register, bit 1 may display 0.125 °C value.
4. Depending on status of the resolution register, bit 0 may display 0.0625 °C value.
Note:
In all temperature register formats bits 0 and bits 1 are used when the resolution is more
than 10 bits. These registers show temperature data for the default 10 bits.
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Temperature sensor registers
4.5
STTS2002
Manufacturer ID register (read-only)
The manufacturer’s ID (programmed value 104Ah) in this register is the STMicroelectronics
Identification provided by the Peripheral Component Interconnect Special Interest Group
(PCiSIG).
Table 19.
4.6
Manufacturer ID register (read-only)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
1
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
1
0
0
1
0
1
0
Device ID and device revision ID register (read-only)
The device IDs and device revision IDs are maintained in this register. The register format is
shown in Table 20. The device IDs and device revision IDs are currently '0' and will be
incremented whenever an update of the device is made.
Table 20.
Device ID and device revision ID register (read-only)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
1
1
Device ID
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
Device revision ID
The current device ID and revision ID value is 0300 h.
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STTS2002
4.7
Temperature sensor registers
Temperature resolution register (read/write)
With this register a user can program the temperature sensor resolution from 9-12 bits as
shown below. The power-on default is always 10 bit (0.25 °C/LSB). The selected resolution
is also reflected in bits (4:3) (TRES1:TRES0) of the capability register.
Table 21.
Temperature resolution register (TRES) (read/write)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
1
Resolution section register
Table 22.
Resolution bits
TRES details
Resolution register bits
Bit1
Bit0
°C/LSB
Bits
Conversion time (max)
0
0
0.5
9
65 ms
0
1
0.25
10
125 ms (default)
1
0
0.125
11
250 ms
1
1
0.0625
12
500 ms
The default value is 01 for TRES register.
4.8
SMBus timeout
The STTS2002 supports the SMBus timeout feature which is turned on by default. If the
host holds SCL low for more than ttimeout (max), the STTS2002 resets itself and releases the
bus. This feature is supported even when the device is in shutdown mode and when the
device is driving SDA low.
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SPD EEPROM operation
STTS2002
5
SPD EEPROM operation
5.1
2 Kb SPD EEPROM operation
The 2 Kb serial EEPROM is able to lock permanently the data in its first half (from location
00h to 7Fh). This feature has been designed specifically for use in DRAM DIMMs (dual in
line memory modules) with serial presence detect. All the information concerning the DRAM
module configuration (such as its access speed, its size, its organization) can be kept write
protected in the first half of the memory.
The first half of the memory area can be write-protected using two different software write
protection mechanisms. By sending the device a specific sequence, the first 128 bytes of
the memory become write protected: permanently or resetable.
These I2C-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 256x8 bits.
I2C uses a two wire serial interface, comprising a bidirectional data line and a clock line. The
device carries a built-in 4-bit device type identifier code (1010) in accordance with the I2C
bus definition to access the memory area and a second device type identifier code (0110) to
define the protection. These codes are used together with the voltage level applied on the
three chip enable inputs (A2, A1, A0). These input signals are used to set the value that is to
be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. In
the end application, A0, A1 and A2 must be directly (not through a pull-up or pull-down
resistor) connected to VDD or VSS to establish the device select code. When these inputs
are not connected, an internal pull-down circuitry makes (A0, A1, A2) = (0,0,0).
The A0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction
(refer to Table 23: Device select code).
The device behaves as a slave device in the I2C protocol, with all memory operations
synchronized by the serial clock. Read and Write operations are initiated by a START
condition, generated by the bus master. The START condition is followed by a Device Select
Code and RW bit (as described in Table 23: Device select code), terminated by an
acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
5.2
Internal device reset - SPD EEPROM
In order to prevent inadvertent Write operations during power-up, a Power On Reset (POR)
circuit is included.
At power-up (phase during which VDD is lower than VDDmin but increases continuously), the
device will not respond to any instruction until VDD has reached the Power On Reset
threshold voltage (this threshold is lower than the minimum VDD operating voltage defined in
Table 2: AC characteristics of STTS2002 for SMBus and I2C compatibility timings). Once
VDD has passed the POR threshold, the device is reset.
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STTS2002
SPD EEPROM operation
Prior to selecting the memory and issuing instructions, a valid and stable VDD voltage must
be applied. This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
At power-down (phase during which VDD decreases continuously), as soon as VDD drops
from the normal operating voltage below the Power On Reset threshold voltage, the device
stops responding to any instruction sent to it.
Table 23.
Device select code
Chip enable
signals
Device type identifier
Chip enable bits
RW
b7(1)
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
A2
A1
A0
RW
Memory area select code
(two arrays)(2)
A2
A1
A0
Set write protection
(SWP)
VSS
VSS
VHV
0
0
1
0
Clear write protection
(CWP)
VSS
VDD
VHV
0
1
1
0
Permanently set write
protection (PSWP)(2)
A2
A1
A0
A2
A1
A0
0
Read SWP
VSS
VSS
VHV
0
0
1
1
Read CWP
VSS
VDD
VHV
0
1
1
1
Read PSWP(2)
A2
A1
A0
A2
A1
A0
1
0
1
1
0
1. The most significant bit, b7, is sent first.
2. A0, A1 and A2 are compared against the respective external pins on the memory device.
5.3
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 23: Device select code (on serial data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit chip enable
“Address” (A2, A1, A0). To address the memory array, the 4-bit device type identifier is
1010b; to access the write-protection settings, it is 0110b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the chip enable (A0, A1, A2) inputs. When the device select code is
received, the device only responds if the chip enable address is the same as the value on
the chip enable (A0, A1, A2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into standby mode. The
operating modes are detailed in Table 24.
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SPD EEPROM operation
Table 24.
STTS2002
Operating modes
Mode
Current address read
RW bit
Bytes
1
1
0
START, device select, RW = 1
START, device select, RW = 0, address
Random address read
1
reSTART, device select, RW = 1
1
5.4
Initial sequence
Sequential read
1
≥1
Byte write
0
1
START, device select, RW = 0
Page write
0
≤ 16
START, device select, RW = 0
TS write
0
2
START, device select, R/W = 0, pointer data, stop
TS read
1
2
START, device select, R/W = 1, pointer data, stop
Similar to current or random address read
Software write protect
Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh)
to be temporarily or permanently write protected.
Software write-protection is handled by three instructions:
●
SWP: set write protection
●
CWP: clear write protection
●
PSWP: permanently set write protection
The level of write-protection (set or cleared) that has been defined using these instructions,
remains defined even after a power cycle.
Figure 10. Result of setting the write protection
FFh
Standard
Array
Memory
Area
FFh
Standard
Array
80h
7Fh
Standard
Array
00h
Default EEPROM memory area
state before write access
to the Protect Register
Write
Protected
Array
80h
7Fh
00h
State of the EEPROM memory
area after write access
to the Protect Register
AI01936c
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STTS2002
5.4.1
SPD EEPROM operation
SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared
again with a CWP instruction.
The two instructions (SWP and CWP) have the same format as a byte write instruction, but
with a different device type identifier (as shown in Table 23). Like the byte write instruction, it
is followed by an address byte and a data byte, but in this case the contents are all “Don’t
Care” (Figure 11). Another difference is that the voltage, VHV, must be applied on the A0 pin,
and specific logical levels must be applied on the other two (A1 and A2, as shown in
Table 23).
PSWP
If the software write-protection has been set with the PSWP instruction, the first 128 bytes of
the memory are permanently write-protected. This write-protection cannot be cleared by
any instruction, or by power-cycling the device. Also, once the PSWP instruction has been
successfully executed, the STTS2002 SPD no longer acknowledges any instruction (with a
device type identifier of 0110) to access the write-protection settings.
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
STOP
Figure 11. Setting the write protection
START
5.4.2
DATA
SDA LINE
BUS ACTIVITY
ACK
ACK
ACK
VALUE
VALUE
(DON'T CARE) (DON'T CARE)
AI01935b
Reading write-protection status
The status of software write protection can be determined using these instructions:
●
Read SWP: Read Write Protection status
●
Read PSWP: Read Permanently Set Write Protection status
Read SWP
The controller issues a Read SWP command. If Software Write Protection has not been set,
the device replies to the data byte with an Ack. If Software Write Protection has been set,
the device replies to the data byte with a NoAck.
Read PSWP
The controller issues a Read PSWP command. If Permanent Software Write Protection has
not been set, the device replies to the data byte with an Ack. If Permanent Software Write
Protection has been set, the device replies to the data byte with a NoAck.
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SPD EEPROM operation
5.5
STTS2002
Write operations
Following a start condition the bus master sends a device select code with the RW bit reset
to 0. The device acknowledges this, as shown in Figure 12, and waits for an address byte.
The device responds to the address byte with an acknowledge bit, and then waits for the
data byte.
When the bus master generates a stop condition immediately after the ack bit (in the “10th
bit” time slot), either at the end of a byte write or a page write, the internal memory write
cycle is triggered. A stop condition at any other time slot does not trigger the internal write
cycle.
During the internal write cycle, serial data (SDA) and serial clock (SCL) are ignored, and the
device does not respond to any requests.
5.5.1
Byte write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoAck, and the location is not modified. If, instead, the addressed location is not writeprotected, the device replies with Ack. The bus master terminates the transfer by generating
a stop condition, as shown in Figure 12.
5.5.2
Page write
The page write mode allows up to 16 bytes to be written in a single write cycle, provided that
they are all located in the same page in the memory: that is, the most significant memory
address bits are the same. If more bytes are sent than will fit up to the end of the page, a
condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become
overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device. After each byte is transferred, the internal byte address counter (the 4 least
significant address bits only) is incremented. The transfer is terminated by the bus master
generating a stop condition.
Figure 12. Write mode sequences in a non write-protected area of SPD
ACK
BYTE ADDR
DATA IN
R/W
ACK
DEV SEL
START
PAGE WRITE
ACK
STOP
DEV SEL
START
BYTE WRITE
ACK
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
ACK
ACK
STOP
DATA IN N
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AI01941
STTS2002
5.5.3
SPD EEPROM operation
Write cycle polling using ACK
During the internal write cycle, the device disconnects itself from the bus and writes a copy
of the data from its internal latches to the memory cells. The maximum write time (tw) is
shown inTable 2 on page 15 , but the typical time is shorter. To make use of this, a polling
sequence can be used by the bus master.
The sequence, as shown in Figure 13, is:
●
Initial condition: a write cycle is in progress.
●
Step 1: the bus master issues a start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal write cycle, no Ack will be returned and the
bus master goes back to step 1. If the device has terminated the internal write cycle, it
responds with an Ack, indicating that the device is ready to receive the second part of
the instruction (the first byte of this instruction having been sent during step 1).
Figure 13. Write cycle polling flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send Address
and Receive ACK
ReSTART
NO
STOP
START
Condition
YES
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
AI01847c
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SPD EEPROM operation
5.6
STTS2002
Read operations - SPD
Read operations are performed independently of whether hardware or software protection
has been set.
The device has an internal address counter which is incremented each time a byte is read.
Figure 14. Read mode sequences - SPD
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
(1)
START
DEV SEL
R/W
DEV SEL
NO ACK
DATA OUT
R/W
ACK
ACK
DATA OUT 1
NO ACK
DATA OUT N
STOP
START
DEV SEL
R/W
ACK
(1)
START
DEV SEL
ACK
R/W
ACK
ACK
(1)
BYTE ADDR
DEV SEL
START
SEQUENTIAL
RANDOM
READ
(1)
BYTE ADDR
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
ACK
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01942
1. The seven most significant bits of the device select code of a random read (in the 1st and 3rd bytes) must
be identical.
5.6.1
Random address read - SPD
A dummy write is first performed to load the address into this address counter (as shown in
Figure 14) but without sending a stop condition. Then, the bus master sends another start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a stop condition.
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5.6.2
SPD EEPROM operation
Current address read - SPD
For the current address read operation, following a start condition, the bus master only
sends a device select code with the RW bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a stop condition, as shown in
Figure 14, without acknowledging the byte.
5.6.3
Sequential read - SPD
This operation can be used after a current address read or a random address read. The bus
master does acknowledge the data byte output, and sends additional clock pulses so that
the device continues to output the next byte in sequence. To terminate the stream of bytes,
the bus master must not acknowledge the last byte, and must generate a stop condition, as
shown in Figure 14.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
5.6.4
Acknowledge in read mode
For all read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive serial data (SDA) low during this
time, the device terminates the data transfer and switches to its standby mode.
Table 25 and Table 26 on page 38 show how the Ack bits can be used to identify the writeprotection status.
Table 25.
Status
Acknowledge when writing data or defining the write-protection
(instructions with R/W bit = 0)
Instruction
Ack
PSWP, SWP or
CWP
Permanently
protected
Page or byte write in
lower 128 bytes
NoAck
Ack
Ack
Write
cycle(tW)
Not
significant
NoAck
No
Data
NoAck
No
Not
NoAck
significant
Not
significant
NoAck
No
Ack
Not
NoAck
significant
Address
Ack
SWP
NoAck
CWP
Ack
Not
significant
Ack
Not
significant
Ack
Yes
PSWP
Ack
Not
significant
Ack
Not
significant
Ack
Yes
Page or byte write in
lower 128 bytes
Ack
Address
Ack
Data
NoAck
No
PSWP, SWP or
CWP
Ack
Not
significant
Ack
Not
significant
Ack
Yes
Page or byte write
Ack
Address
Ack
Data
Ack
Yes
Protected
with SWP
Not
Protected
Data byte
Address
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SPD EEPROM operation
Table 26.
Acknowledge when reading the write protection (instructions with R/W
bit=1)
Status
Instruction
Ack
Address
Ack
Data byte
Ack
Permanently
protected
PSWP, SWP or CWP
NoAck
Not significant
NoAck
Not significant
NoAck
SWP
NoAck
Not significant
NoAck
Not significant
NoAck
CWP
Ack
Not significant
NoAck
Not significant
NoAck
PSWP
Ack
Not significant
NoAck
Not significant
NoAck
PSWP, SWP or CWP
Ack
Not significant
NoAck
Not significant
NoAck
Protected with
SWP
Not protected
5.7
STTS2002
Initial delivery state - SPD
The device is delivered with all bits in the memory array set to ‘1’ (each byte contains FFh).
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6
Use in a memory module
Use in a memory module
In the Dual In line Memory Module (DIMM) application, the SPD is soldered directly on to
the printed circuit module. The three chip enable inputs (A0, A1, A2) must be connected to
VSS or VDD directly (that is without using a pull-up or pull-down resistor) through the DIMM
socket (see Table 27).
Table 27.
6.1
DRAM DIMM connections
DIMM position
A2
A1
A0
0
VSS (0)
VSS (0)
VSS (0)
1
VSS(0)
VSS (0)
VDD (1)
2
VSS (0)
VDD (1)
VSS (0)
3
VSS (0)
VDD (1)
VDD(1)
4
VDD (1)
VSS (0)
VSS (0)
5
VDD (1)
VSS (0)
VDD (1)
6
VDD (1)
VDD (1)
VSS (0)
7
VDD (1)
VDD (1)
VDD (1)
Programming the SPD
The situations in which the SPD EEPROM is programmed can be considered under two
headings:
6.1.1
●
when the DIMM is isolated (not inserted on the PCB motherboard)
●
when the DIMM is inserted on the PCB motherboard
DIMM isolated
With specific programming equipment, it is possible to define the SPD EEPROM content,
using byte and page write instructions, and its write-protection using the SWP and CWP
instructions. To issue the SWP and CWP instructions, the DIMM must be inserted in the
application-specific slot where the A0 signal can be driven to VHV during the whole
instruction. This programming step is mainly intended for use by DIMM makers, whose end
application manufacturers will want to clear this write-protection with the CWP on their own
specific programming equipment, to modify the lower 128 bytes, and finally to set
permanently the write-protection with the PSWP instruction.
6.1.2
DIMM inserted in the application motherboard
As the final application cannot drive the A0 pin to VHV, the only possible action is to freeze
the write-protection with the PSWP instruction.
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Maximum ratings
7
STTS2002
Maximum ratings
Stressing the device above the ratings listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 28.
Absolute maximum ratings
Symbol
TSTG
TSLD(1)
Parameter
Value
Unit
–65 to 150
°C
260
°C
A0
VSS – 0.3 to 10.0
V
others
VSS – 0.3 to 6.5
V
Storage temperature
Lead solder temperature for 10 seconds
VIO
Input or output voltage
VDD
Supply voltage
VSS – 0.3 to 6.5
V
IO
Output current
10
mA
PD
Power dissipation
320
mW
θJA
Thermal resistance
87.4
°C/W
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
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STTS2002
8
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 29. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 29.
Operating and AC measurement conditions
Parameter
Conditions
Unit
VDD supply voltage
2.3 to 3.6
V
Operating temperature
–40 to 125
°C
Input rise and fall times
≤ 50
ns
Load capacitance
100
pf
Input pulse voltages
0.2VDD to 0.8VDD
V
Input and output timing reference voltages
0.3VDD to 0.7VDD
V
Figure 15. AC measurement I/O waveform
Input and output timing
reference levels
Input levels
0.8 * VDD
0.7 * VDD
0.3 * VDD
0.2 * VDD
ai14011
Table 30.
Sym
VDD
DC/AC characteristics - temperature sensor component with EEPROM
Description
Test condition(1)
Min
Typ(2)
Max
Unit
2.3
3.3
3.6
V
EEPROM
F = 400 kHz
0.4
2.0
mA
EEPROM standby,
F = 400 kHz
160
300
µA
EEPROM standby,
TS shutdown
3.0
5
µA
VIN = VSS or VDD
±5
µA
VOUT = VSS or VDD,
SDA in Hi-Z
±5
µA
Supply voltage
active(3)
IDD
IDD1
VDD supply current (no load)
Shutdown mode supply current
IILI
Input leakage current (SCL, SDA)
IILO
Output leakage current
VPOR
Power on Reset (POR) threshold
VDD falling edge:
DN package
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V
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DC and AC parameters
Table 30.
STTS2002
DC/AC characteristics - temperature sensor component with EEPROM (continued)
Sym
Test condition(1)
Description
Accuracy for corresponding
B-grade range
2.3 V ≤ VDD ≤ 3.6 V
Typ(2)
Max
Unit
+75 °C < TA < +95
±0.5
±1.0
°C
+40 °C < TA <+ 125
±1.0
±2.0
°C
–40 °C < TA < +125
±2.0
±3.0
°C
Min
0.5
0.25
9
10
0.0625 °C/LSB
Resolution
tCONV
SMBus/I2
Conversion time
10-bit - default
12
bits
125
ms
C interface
VIH
Input logic high
SCL, SDA, A0-A2
0.7VDD
VDD + 1
V
VIL
Input logic low
SCL, SDA, A0-A2
–0.5
0.3VDD
V
CIN(4)
fSCL
SMBus/I2C input capacitance
5
SMBus/I2C clock frequency
pF
10
400
kHz
ttimeout
SMBus timeout
Temperature sensor only
25
35
ms
VHV
A0 high voltage
VHV ≥ VDD + 4.8 V
7
10
V
VOL1
Low level voltage, EVENT
IOL = 2.1 mA
0.4
V
V
Low level voltage, SDA
IOL = 2.1 mA
0.4
VOL2
IOL = 6 mA
0.6
V
(4)
(A0, A1, A2) input impedance
VIN < 0.3 VDD
30
kΩ
ZAIH(4)
(A0, A1, A2) input Impedance
VIN > 0.7 VDD
800
kΩ
tSP(4)
Spike suppression
Pulse width of spikes that must
be suppressed by the input filter
ZAIL
Input filter on SCL and SDA
VHYST(5) Input hysteresis (SCL, SDA)
TS only
50
0.05VDD
1. Guaranteed operating temperature for combined module: TA = –40 °C to 125 °C; VDD = 2.3 V to 3.6 V (except where
noted).
2. Typical numbers taken at VDD = 3.3 V, TA = 25 °C.
3. Read current only
4. Verified by design and characterization, not necessarily tested on all devices
5. VHYST parameter is optional in the JEDEC TSE2002a2 specifications
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V
STTS2002
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Package mechanical data
STTS2002
Figure 16. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN)
8089094_A
Note:
JEDEC MO-229, variation WCED-3 proposal
Table 31.
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN)
mm
inches
Sym
Min
Typ
Max
Min
Typ
Max
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.00
0.05
0.000
0.000
0.002
A3
0.20
b
0.20
0.25
0.30
0.008
0.010
0.012
D
1.95
2.00
2.05
0.077
0.079
0.081
D2
1.35
1.40
1.45
0.053
0.055
0.057
E
2.95
3.00
3.05
0.116
0.118
0.120
E2
1.25
1.30
1.35
0.049
0.051
0.053
e
L
ddd
Note:
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0.008
0.50
0.30
0.35
0.020
0.40
0.08
JEDEC MO-229, variation WCED-3 proposal
Doc ID 15389 Rev 5
0.012
0.014
0.016
0.003
STTS2002
Package mechanical data
Figure 17. DN package topside marking information (TDFN8)
(1)
B2DN
(2)
TSE2
(3)
xxxx
ai13907b
1. Temperature grade and package
B = B-grade, stacked
2 = Minimum operating voltage of 2.3 V
DN = 0.80 mm TDFN package
2. Device name
TSE2 = STTS2002
3. Traceability codes
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Package mechanical data
STTS2002
The landing pattern recommendations per the JEDEC proposal for the TDFN package (DN)
are shown in Figure 18.
The preferred implementation with wide corner pads enhances device centering during
assembly, but a narrower option is defined for modules with tight routing requirements.
Figure 18. Landing pattern - TDFN8 package (DN)
e4
e2
e/2
e
e/2
L
K
D2
E3
D2/2
D2/2
E2/2
E2
E2/2
E3
K
L
b2
b
b
K2
K2
K2
b4
ai14000
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Package mechanical data
Table 32 lists variations of landing pattern implementations, ranked as “Preferred” and
Minimum Acceptable” based on the JEDEC proposal.
Table 32.
Parameters for landing pattern - TDFN8 package (DN)
Dimension
Parameter
Description
Min
Nom
Max
D2
Heat paddle width
1.40
-
1.60
E2
Heat paddle height
1.40
-
1.60
E3
Heat paddle centerline to contact inner locus
1.00
-
-
L
Contact length
0.70
-
0.80
K
Heat paddle to contact keepout
0.20
-
-
K2
Contact to contact keepout
0.20
-
-
-
0.50
-
0.25
-
0.30
-
0.50
-
0.25
-
0.30
-
0.60
-
0.45
-
0.50
e
Contact centerline to contact centerline pitch for inner contacts
b
Contact width for inner contacts
e2
Landing pattern centerline to outer contact centerline, “minimum
acceptable” option(1)
b2
Corner contact width, “minimum acceptable option”(1)
e4
Landing pattern centerline to outer contact centerline, “preferred”
option(2)
b4
Corner contact width, “preferred” option(2)
1. Minimum acceptable option to be used when routing prevents preferred width contact.
2. Preferred option to be used when possible.
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Package mechanical data
STTS2002
Figure 19. Carrier tape for TDFN8 package
P0
E
P2
D
T
A0
F
TOP COVER
TAPE
W
B0
P1
CENTER LINES
OF CAVITY
K0
USER DIRECTION OF FEED
AM03073v1
Table 33.
Carrier tape dimensions TDFN8 package
Package
W
D
TDFN8
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
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E
P0
P2
F
1.75
4.00
2.00
3.50
±0.10 ±0.10 ±0.10 ±0.05
A0
B0
K0
P1
T
2.30
±0.10
3.20
±0.10
1.10
±0.10
4.00
±0.10
0.30
±0.05
Doc ID 15389 Rev 5
Unit
Bulk
Qty
mm 3000
STTS2002
Package mechanical data
Figure 20. Reel schematic
T
40mm min.
Access hole
At slot location
B
D
C
N
A
G measured
Tape slot
In core for
Full radius
Tape start
2.5mm min.width
At hub
AM04928v1
Table 34.
Reel dimensions for 8 mm carrier tape - TDFN8 package
A
B
(max)
(min)
180 mm
(7-inch)
1.5 mm
Note:
C
13 mm
± 0.2 mm
D
N
(min)
(min)
20.2 mm
60 mm
G
8.4 mm
+ 2/–0 mm
T
(max)
14.4 mm
The dimensions given in Table 34 incorporate tolerances that cover all variations on critical
parameters.
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Part numbering
10
STTS2002
Part numbering
Table 35.
Ordering information scheme
Example:
STTS2002
B
2
DN
3
F
Device
STTS2002
Accuracy grade
B: Maximum accuracy 75 °C to 95 °C = ± 1 °C
Voltage
2 = 2.3 V - 3.6 V
Package
DN = TDFN8
Temperature range
3 = –40 °C to 125 °C
Shipping method
F = ECOPACK® package, tape & reel packing
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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STTS2002
11
Revision history
Revision history
Table 36.
Document revision history
Date
Revision
Changes
11-Feb-2009
1
Initial release.
08-Oct-2009
2
Updated Features, Section 1, Section 2.1, Section 2.2.5,
Section 3.3, Section 4.1, Section 4.8, Section 5.4, Section 5.4.2,
Section 5.5.2, Section 5.5.3, Section 6, Figure 3, 7, 19, Table 2, 3, 5,
6, 7, 9, 12, 13, 24, 25, 28, 29, and 30; moved Figure 14, Section 5.7,
Table 25 and 26; added Table 33; removed section on “Alert reponse
address (ARA)”; reformatted document.
19-Oct-2009
3
Updated Figure 17.
13-Sep-2010
4
Document updated to full datasheet; updated Figure 3, Table 35;
Section 4.8: SMBus timeout; minor textual changes; added
Figure 20, Table 34, note to Table 3.
21-Mar-2011
5
Updated Figure 17: DN package topside marking information
(TDFN8) and document status.
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STTS2002
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