STMICROELECTRONICS STW24NK55Z

STW24NK55Z
N-channel 550 V - 0.18 Ω - 23 A - TO-247
Zener-protected SuperMESH™ Power MOSFET
Features
Type
VDSS
RDS(on)
ID
Pw
STW24NK55Z
550 V
<0.22 Ω
23 A
285 W
■
Extremely high dv/dt capability
■
100% avalanche tested
■
Gate charge minimized
■
Very low intrinsic capacitances
■
Very good manufacturing repeatability
2
3
1
TO-247
Application
■
Switching applications
Description
Figure 1.
Internal schematic diagram
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs.
Table 1.
Device summary
Order code
Marking
Package
Packaging
STW24NK55Z
24NK55Z
TO-247
Tube
January 2008
Rev 1
1/12
www.st.com
12
Contents
STW24NK55Z
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
.......................... 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
.............................................. 8
STW24NK55Z
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
550
V
VGS
Gate-source voltage
± 30
V
ID
Drain current (continuous) at TC = 25 °C
23
A
ID
Drain current (continuous) at TC=100 °C
10.35
A
IDM(1)
Drain current (pulsed)
92
A
PTOT
Total dissipation at TC = 25 °C
285
W
Derating factor
2.27
W/°C
Peak diode recovery voltage slope
4.5
V/ns
-55 to 150°C
°C
150
°C
Value
Unit
0.44
°C/W
Thermal resistance junction-ambient max
50
°C/W
Maximum lead temperature for soldering purpose
300
°C
Value
Unit
dv/dt(2)
Tstg
TJ
Storage temperature
Max. perating junction temperature
1. Pulse width limited by safe operating area
2. ISD ≤ 23 A, di/dt ≤ 200 A/µs,VDD= 80% V(BR)DSS
Table 3.
Symbol
Rthj-case
Rthj-a
Tl
Table 4.
Symbol
Thermal data
Parameter
Thermal resistance junction-case max
Avalanche characteristics
Parameter
IAR
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj Max)
23
A
EAS
Single pulse avalanche energy
(starting Tj=25 °C, ID=IAR, VDD=50 V)
400
mJ
3/12
Electrical characteristics
2
STW24NK55Z
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5.
Symbol
V(BR)DSS
On/off states
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 1 mA, VGS= 0
Min.
Typ.
Max.
Unit
550
V
VDS = Max rating,
VDS = Max rating @125 °C
1
50
µA
µA
Gate body leakage current
(VDS = 0)
VGS = ±20 V
±10
µA
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 100 µA
3.75
4.5
V
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 11.5 A
0.18
0.22
Ω
Typ.
Max.
Unit
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
Table 6.
Symbol
gfs (1)
Ciss
Coss
Crss
3
Dynamic
Parameter
Test conditions
Forward transconductance
VDS =15 V, ID = 11.5 A
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25 V, f=1 MHz,
VGS=0
Coss eq(2). Equivalent output
capacitance
Min.
20
S
4397.5
480.5
116
pF
pF
pF
VGS=0, VDS =0 to 480 V
250
pF
RG
Intrinsic gate resistance
f=1 MHz, open drain
2.3
Ω
Qg
Total gate charge
Gate-source charge
Gate-drain charge
VDD= 440 V, ID = 23 A
130
25
76
nC
nC
nC
30
35
136
88
ns
ns
ns
ns
Qgs
Qgd
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VGS =10 V
(see Figure 15)
VDD= 275 V, ID=11.5 A,
RG= 4.7 Ω, VGS=10 V
(see Figure 14)
1. Pulsed: pulse duration=300 µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
4/12
STW24NK55Z
Electrical characteristics
Table 7.
Symbol
Source drain diode
Max
Unit
Source-drain current
23
A
ISDM(1)
Source-drain current (pulsed)
92
A
VSD(2)
Forward on voltage
ISD= 23 A, VGS=0
1.6
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 23 A, VDD= 50 V
ISD
trr
Qrr
IRRM
trr
Qrr
IRRM
Parameter
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
Min
di/dt = 100 A/µs,
(see Figure 18)
ISD= 23 A,
di/dt = 100 A/µs,
VDD= 50 V, Tj=150 °C
(see Figure 18)
Typ.
508
7.4
29
ns
µC
A
608
9.7
31.8
ns
µC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300 µs, duty cycle 1.5%
Table 8.
Symbol
Gate-source Zener diode
Parameter
BVGSO(1) Gate-source breakdown voltage
Test conditions
Igs=±1 mA
(open drain)
Min.
Typ.
Max.
Unit
30
V
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
5/12
Electrical characteristics
STW24NK55Z
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
HV41790
ID(A)
HV41795
ID(A)
70
70
VGS =10V
VDS = 20V
60
60
7V
50
50
40
40
30
30
6V
20
20
10
10
5V
0
0
Figure 6.
5
10
15
20
25
30
VDS(V)
Normalized BVDSS vs temperature
0
0
Figure 7.
2
4
6
8
10
VGS(V)
Static drain-source on resistance
HV41880
RDS(on)
(Ω)
0.18
0.15
0.14
0.12
6/12
5
10
15
20
ID(A)
STW24NK55Z
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
HV41800
VGS
(V)
12
VDD=440V
ID=23A
VGS=10V
10
8
6
4
2
0
0
50
100
150
Qg (nC)
Figure 10. Normalized gate threshold voltage
vs temperature
Figure 11. Normalized on resistance vs
temperature
Figure 12. Maximum avalanche energy vs
temperature
Figure 13. Source-drain diode forward
characteristics
HV41780
450
EAS
(mJ)
HV41850
VSD
1.199997
(V)
400
1.0
0.999997
350
Tj = -50˚C
0.8
0.799998
300
250
25˚C
0.6
0.599998
200
150˚C
0.4
0.399999
150
100
0.2
0.199999
50
0
0
30
60
90
120
150
0
0.000000
TJ (˚C)
0
5
10
15
20
ID(A)
7/12
Test circuits
3
STW24NK55Z
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
Figure 16. Test circuit for inductive load
Figure 17. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 18. Unclamped inductive waveform
8/12
Figure 19. Switching time waveform
STW24NK55Z
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STW24NK55Z
TO-247 MECHANICAL DATA
DIM.
mm.
MIN.
inch
MAX.
MIN.
TYP.
MAX.
A
4.85
5.15
0.19
0.20
A1
2.20
2.60
0.086
0.102
b
1.0
1.40
0.039
0.055
b1
2.0
2.40
0.079
0.094
0.134
b2
3.0
3.40
0.118
c
0.40
0.80
0.015
0.03
D
19.85
20.15
0.781
0.793
E
15.45
15.75
0.608
e
5.45
0.620
0.214
L
14.20
14.80
0.560
L1
3.70
4.30
0.14
L2
18.50
0.582
0.17
0.728
øP
3.55
3.65
0.140
0.143
øR
4.50
5.50
0.177
0.216
S
10/12
TYP
5.50
0.216
STW24NK55Z
5
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
04-Jan-2008
1
Changes
First release
11/12
STW24NK55Z
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