STMICROELECTRONICS STW4810BRA

STw4810
Power Management for Multimedia Processors
PRELIMINARY DATA
Features
■
2 Step-down converters
– 1 to 1.5V with 15 steps at 600mA
– 1.8V at 600mA for general purpose usage
■
3 Low-drop output regulators for different uses
– PLL analog supplies:
1.05V, 1.2V, 1.3V 1.8V - 10mA
– Processor analogue functions:
2.5V - 10mA
– Auxiliary device:
1.5V, 1.8V, 2.5V, 2.8V - 150 mA
■
USB OTG module
– Full and low speed USB OTG transceiver
– Charge-pump (5V, 100mA) for USB cable
■
Mass memory cards (SD/MMC/SDIO)
– 1 linear regulator: 1.8V, 2.85V, 3V - 150mA
– Level shifter
■
Miscellaneous
– 32 kHz control for multimedia processor
– Processor supply monitoring
– Processor reset control
– 2 Serial I2C interfaces
STw4810BHD
TFBGA 84
6x6x1.2mm
0.5mm pitch
STw4810BRA
VFBGA 84
4.6x4.6x1.0mm
0.4mm pitch
Description
STw4810 is a power management companion
chip for multimedia processors used in portable
applications. It supplies the multimedia processor
including its memories and peripherals. STw4810
supports the main mass memory standard cards.
SDIOTM is also supported and allows to connect
multimedia peripherals like cameras.
Application
■
ST NOMADIKTM STn88xx
■
Multimedia processor
■
Mobile phones, PDA, Videophone
Order codes
Part number
Package
Packing
STw4810BHD/LF
TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch
Tray
STw4810BRA/LF
VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch
Tray
February 2006
Rev3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/72
www.st.com
1
STw4810
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
3.1
Ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Digital control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
4.4
4.5
2/72
4.2.1
State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2
POWER OFF / VDDOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.3
SLEEP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.4
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.5
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.6
IT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.7
Clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.1
Bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.2
VCORE regulator: DC/DC STEP- DOWN regulator . . . . . . . . . . . . . . . . . . . 30
4.3.3
VIO_VMEM regulator: DC/DC step- down regulator . . . . . . . . . . . . . . . . . . . 31
4.3.4
VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.5
VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.6
VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.7
Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.8
Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.9
Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
USB OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.2
Modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.3
USB enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SD/MMC/SDIO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Rev3
STw4810
5
Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2
Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4
6
7
8
5.3.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.2
VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.3
VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.4
VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.5
LDO regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.6
Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4.1
CMOS input/output static characteristics: I2C interface . . . . . . . . . . . . . . . . 53
5.4.2
CMOS input/output dynamic characteristics: I2C interface . . . . . . . . . . . . . . 53
5.4.3
CMOS input/output static characteristics: VIO level . . . . . . . . . . . . . . . . . . . 54
5.4.4
CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . . . . . 56
5.4.5
CMOS input/output static characteristics: VMMC level . . . . . . . . . . . . . . . . . 57
5.5
USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6
SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1
Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.1
TFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2
VFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Rev3
3/72
STw4810
1 Overview
1
Overview
●
●
●
●
Figure 1.
4/72
Power management module
–
1 Step-down converter for processor core (1 to 1.5 V with 15 steps at 600 mA)
–
1 Step-down converter (1.8 V at 600 mA) for general purpose usage such as
processor input/output supply, external memory, DDR and SDRAM and peripherals
–
1 Low-drop output regulator for analog supplies, such as PLL (1.05 V, 1.2 V, 1.3 V,
1.8 V at 10 mA)
–
1 Low-drop Output regulator for processor analogue functions (2.5 V at 10 mA)
–
1 Low-drop output regulator for auxiliary devices (1.5 V, 1.8 V, 2.5 V, 2.8 V at 150 mA)
USB OTG module
–
Full and low speed USB OTG transceiver
–
1 Linear regulators (3.1 V at 40 mA) supplying transceiver
–
1 Charge-pump (5 V at 100 mA) supplying VBUS line of the USB cable
Mass memory cards (SD/MMC/SDIO)
–
1 Linear regulator (1.8 V, 2.85 V, 3 V at 150 mA)
–
Level shifter
Miscellaneous
–
32 kHz control for multimedia processor
–
Processor supply monitoring
–
Processor reset control
–
2 Serial I2C interfaces
Typical mobile multimedia system
Rev3
STw4810
Functional block diagram
MASTER_CLK
CLK32K_IN
CLK32K
1.8V- 600mA
VMINUS_DIG
Internal
oscillator
clock
switching
and
control
VBAT_ANA
VMINUS_ANA
SOFT_START
VREF_VIO_VMEM
GPO1
BG
VREF_VCORE
VREF_VPLL
VREF_VAUX
GPO2
USBINTn
SDA
SCL
Buffer
VREF_18
BIAS
Control
registers
VBAT_VPLL_ANA
Thermal
shutdown
TCXO_EN
REQUEST_MC
PON
VDDOK
PORn
PWREN
SW_RESETn
VCORE
1V=>1.5V- 600mA
VBAT_DIG
VMINUS_VCORE
VLX_VCORE
VBAT_VCORE
VIO_VMEM
VMINUS_VIO_VMEM
STw4810 block diagram
VBAT_VIO_VMEM
Figure 2.
VLX_VIO_VMEM
2
2 Functional block diagram
VPLL_LDO
1.05V,1.2V,1.3V,1.8V,
10mA
Monitoring
VPLL
VANA_LDO
2.5V, 10mA
General
PORn_VBAT
control
VANA
VBAT_VAUX
VAUX_LDO
1.5V,1.8V2.5V,2.8V,
150mA
I2C
interface
VAUX
VBAT_USB
USB OTG transceiver interface
USBSDA
USBSCL
I2C
Mux
USB
control
Control
Charge
pump
5V - 100mA
CP
CN
VBUS
3.1V - 40mA
VUSB
IT_WAKE_UP
SD/MMC/
SDIO control
USBOEn
USBVP
USBVM
USBRCV
VMINUS_USB
MCCMDDIR
MCDAT0DIR
MCDAT2DIR
MCDAT31DIR
MCCLK
MCFBCLK
MCCMD
MCDATA0
MCDATA[3:1]
Driver
Level
shifter
ID
Pull
up &
down
DP
DN
VBAT_MMC
SD/ MMC/SDIO interface
1.8/2.85/3V-150mA
Level
shifter
Driver
Rev3
VMMC
LATCHCLK
CLKOUT
CMDOUT
DATAOUT0
DATAOUT[3:1]
5/72
STw4810
3 Ball information
3
Ball information
3.1
Ball connections
Table 1.
STw4810 ball connections
1
2
3
5
VBAT_VIO_
VIO_VMEM
VMEM
6
7
8
9
10
VAUX
VANA
VPLL
VREF_18
VCORE
A
CLK32K_IN
VMINUS_
VIO_VMEM
B
“Reserved”
REQUEST_ VMINUS_ VBAT_VIO_
MC
VIO_VMEM
VMEM
VMINUS_
ANA
VBAT_
VAUX
“Reserved”
“Reserved”
“Reserved”
VMINUS_
VCORE
C
TCXO_EN
IT_WAKE_
UP
VMINUS_
DIG
“Reserved”
VBAT_ANA
VBAT_
VPLL_ANA
PON
VMINUS_
VCORE
VLX_
VCORE
D
VBAT_DIG
MASTER_
CLK
“reserved”
VLX_
VCORE
VBAT_
VCORE
VBAT_
VCORE
E
DATAOUT0
DATAOUT
<1>
DATAOUT
<2>
ID
DP
DN
F
DATAOUT
<3>
CMDOUT
LATCHCLK
“Reserved”
VBAT_USB
VUSB
G
CLKOUT
MCCLK
MCCMD
DIR
“Reserved”
USBSCL
VBUS
H
MCCMD
MCDATA
<3>
MCDATA
<1>
MCDATA31
DIR
MCFBCLK
PWREN
SDA
USBINTn
USBSDA
CP
J
MCDATA
<2>
VDDOK
PORN
VBAT_
MMC
GPO1
SCL
USBVP
USBVM
VMINUS_
USB
CN
K
MCDATA0
MCDAT0
DIR
CLK32K
SW_
RESET
VMMC
GPO2
USBRCV
USBOEn
MCDAT2
DIR
“Reserved”
3.2
VLX_VIO_
VMEM
4
VLX_VIO_
VMEM
Ball functions
STw4810 includes the following ball types
●
VDDD/VDDA: digital/analog power supply
●
VSSD/VSSA: digital/analog ground supply
●
DO/DI/DIO: Digital Output / Digital Input / Digital Input Output
●
DOz: Digital Output with high impedance capability
●
AO/AI/AIO: Analog Output / Analog Input / Analog Input-Output
●
G: to be connected to ground
●
O: to be left open
●
Int-Ref: Associated to internal reference
Table 2 details the ballout.
6/72
Rev3
STw4810
3 Ball information
Table 2.
STw4810 balls function
Ball
Ball name
Ball type
Description
General supplies
D1
VBAT_DIG
VDDD-VBAT
Battery supply for digital/oscillator
C3
VMINUS_DIG
VSSD
Ground for digital and oscillator
C6
VBAT_ANA
VDDA-VBAT
Battery supply for analog
B5
VMINUS_ANA
VSSA
Ground for analog
F9
VBAT_USB
VDDA-VBAT
Battery supply for USB block
J9
VMINUS_USB
VSSA
Ground for USB block
A9
VREF_18
Int-Ref
Internal reference
Control balls
C8
PON
DI(VBAT)
Pull Down 1.5MΩ
Power-on and reset
K4
SW_RESETn
DI(VIO_VMEM)
Pull Up 1.5MΩ
Software reset, reset all applications when
SW_RESETn = 0
J2
VDDOK
DO(VIO_VMEM)
Supply monitoring for multimedia
processors. Interruption for high
temperature warning
J3
PORn
DO(VIO_VMEM)
Multimedia processor Resetn
H6
PWREN
DI(VIO_VMEM)
Pull Up 1.5MΩ
Sleep mode from multimedia processor
C1
TCXO_EN
DI(VIO_VMEM)
Pull Down 1.5MΩ
Request of master clock from modem part
B2
REQUEST_MC
DO(VIO_VMEM)
Request to master clock oscillator
J6
SCL
DI(VIO_VMEM)
Clock for Main I2C interface
H7
SDA
DIO(VIO_VMEM)
SDA for Main I2C interface
D2
MASTER_CLK
AI
Pull Down 1.5MΩ
26 MHz, 13 MHz or 19.2 MHz from modem
A1
CLK32K_IN
DI(VIO_VMEM)
Pull Down 1.5MΩ
32 kHz input
K3
CLK32K
DO(VIO_VMEM)
32 kHz to multimedia processor
Rev3
7/72
STw4810
3 Ball information
Table 2.
STw4810 balls function
Ball
Ball name
Ball type
Description
Regulator balls
A4
B4
VBAT_VIO_VMEM
VDDA-VBAT
Battery power supply for step down
VIO_VMEM
A2
B3
VMINUS_VIO_VMEM
VSSA
Ground for step down VIO_VMEM
A3
C4
VLX_VIO_VMEM
AIO
BUCK of step down VIO_VMEM
A5
VIO_VMEM
AI
VIO_VMEM Feed back input
D9
D10
VBAT_VCORE
VDDA-VBAT
Battery power supply for step down
VCORE
B10
C9
VMINUS_VCORE
VSSA
Ground for step down VCORE
C10
D8
VLX_VCORE
AIO
BUCK of step-down VCORE
A10
VCORE
AI
VCORE sense
C7
VBAT_VPLL_ANA
VDDA-VBAT
Battery supply for VPLL, VANA
A7
VANA
AO
VANA output
A8
VPLL
AO
VPLL output
A6
VAUX
AO
VAUX output
B6
VBAT_VAUX
VDDA-VBAT
Battery supply for VAUX
C2
IT_WAKE_UP
DO(VBAT-DIG)
Interrupt to modem for wake-up due to
USB plug
K8
USBOEn
DIO(VIO_VMEM)
Pull Down 1.5MΩ
Output enable of the differential driver in
the USB mode
J7
USBVP
DIO(VIO_VMEM)
Pull Down 1.5MΩ
Data input in the USB transmit mode,
positive data input the single-ended
transmit mode, or TXD in UART mode
J8
USBVM
DIO(VIO_VMEM)
Pull Down 1.5MΩ
Single-ended zero input in the USB
transmit mode, negative data input in the
single-ended transmit mode, or RXD in the
UART mode
K7
USBRCV
DO(VIO_VMEM)
Differential receiver output
E9
DP
AIO(VUSB)
Positive data line in the USB mode, or
serial data input in the UART mode
E10
DN
AIO(VUSB)
Negative data line in the USB mode, or
serial data output in the UART mode.
E8
ID
AI(VBAT-USB)
ID ball of the USB detector used for
protocol identification.
USB balls
8/72
Rev3
STw4810
3 Ball information
Table 2.
STw4810 balls function
Ball
Ball name
Ball type
Description
H10
CP
AIO(VBUS)
C plus flying capacitor
(VBUS level 4.4 to 5.25)
J10
CN
AIO(VBUS)
C minus flying capacitor (VBUS Level)
G10
VBUS
AIO(VBUS)
USB cable supply (VBUS Level)
F10
VUSB
AIO
Decoupling capacitor for USB internal
regulator
G9
USBSCL
DI(VIO_VMEM)
Clock for dedicated USB I2C
H9
USBSDA
DIO(VIO_VMEM)
SDA for dedicated USB I2C
H8
USBINTn
DO(VIO_VMEM)
Interrupt to multimedia processor for USB
or accessory plug
DI(VIO_VMEM)
Pull Down 1.5MΩ
CMD direction.
- “high”: CMD signal from processor to
card
- “Low”: CMD signal from card to
processor
DI(VIO_VMEM)
Pull Down 1.5MΩ
DATA0 direction
- “high”: DATA0 signal from processor to
card
- “Low”: DATA0 signal from card to
processor
DI(VIO_VMEM)
Pull Down 1.5MΩ
DATA2 direction
- “high”: DATA2 signal from processor to
card
- “Low”: DATA2 signal from card to
processor
SD MMC balls
G3
K2
K9
MCCMDDIR
MCDAT0DIR
MCDAT2DIR
H4
MCDAT31DIR
DI(VIO_VMEM)
Pull Down 1.5MΩ
DATA(3,1) direction
- “high”: DATA(3,1) signal from processor
to card
- “Low”: DATA(3,1) signal from card to
processor
G2
MCCLK
DI(VIO_VMEM)
Pull Down 1.5MΩ
Host clock, between processor and
STw4810, to the card (processor clock).
H5
MCFBCLK
DO(VIO_VMEM)
Host feedback clock between STw4810
and processor, to re-synchronize data in
processor.
H1
MCCMD
DIO(VIO_VMEM)
Pull Up 1.5MΩ
Bidirectional command/response signal
between processor and STw4810.
K1
MCDATA0
DIO(VIO_VMEM)
Pull Up1.5MΩ
Bidirectional data0 between processor and
STw4810
H2
H3
J1
MCDATA[3:1]
DIO(VIO_VMEM)
Pull Up 1.5MΩ
Bidirectional data [3:1] between processor
and STw4810.
Rev3
9/72
STw4810
3 Ball information
Table 2.
STw4810 balls function
Ball
Ball name
Ball type
Description
F3
LATCHCLK
DI(VMMC)
Pull Down 1.5MΩ
Host feedback clock to STw4810, to resynchronize data in processor.
G1
CLKOUT
DO(VMMC)
Host clock, between STw4810 and card
(processor clock).
F2
CMDOUT
DIO(VMMC)
Pull Up 1.5MΩ
Bidirectional command/response signal
between STw4810 and processor.
E1
DATAOUT0
DIO(VMMC)
Pull Up 1.5MΩ
Bidirectional data0 between STw4810 and
card
F1
E3
E2
DATAOUT[3:1]
DIO(VMMC)
Pull Up 1.5MΩ
Bidirectional data[3:1] between STw4810
and card.
J4
VBAT_MMC
VDDA-VBAT
Battery supply for VMMC
K5
VMMC
AIO
VMMC supply output
Other balls
10/72
J5
GPO1
AO
General purpose output
K6
GPO2
AO
General purpose output
B9
D3
“Reserved”
G
To be connected to ground
B1
B7
B8
C5
F8
G8
K10
“Reserved”
O
To be left open
Rev3
STw4810
4 Functional description
4
Functional description
4.1
Introduction
The STw4810 integrates all the power supplies for a multimedia processor as well as memories
and peripherals:
4.2
●
Two switched mode power supply regulators: one for the multimedia processor core, one
for multimedia processor I/Os and memories
●
Three low-drop output regulators for multimedia processor analog supplies (PLL and
others) and auxiliary components
●
USB OTG FS/LS physical interface
●
MMC card power supplies and level shifters
●
Multimedia processor supply monitoring / power-on reset and power supply alarms /
interrupt management
●
Two serial I2C communication interfaces; one to control the devices (SDA, SCL) and one
to control the USB (USBSDA, USBSCL).
Digital control module
This module describes the interfaces used to program the device and the related registers.
4.2.1
State machine
Description of each states: (Figure 3.)
OFF: In this mode the STw4810 is switched off. Off is when PON=0, when battery level is under
2.4 V or when thermal shutdown is activated. There is no multimedia processor power supply.
The only active cell is the USB cable detection and VBAT level detection.
OSC_START: Oscillator is enabled and the power up module is waiting for the rising edge of
the internal signal OSC_OK to start power up sequence. This state duration is 300 µs.
START_BIAS: Bias, reference and thermal shut-down are enabled, a counter is activated to
wait for rising edge of internal signals PDN_regulators. This state duration has a typical value of
7.77 ms and a worst case value of 9.46 ms.
START_PM: after a 1 ms wait, multimedia processor power supplies are available
(VIO_VMEM, VCORE, VPLL, and VANA). The device can allow I2C communication, output
power supply monitoring and application (USB,SD/MMC).
OFF2: STw4810 is waiting for the 32 kHz multimedia processor signal. This state has an
indeterminate duration. If 32kHz is present during the states describes above, it has no effect.
The 32 kHz signal is taken into account by STw4810 only when the ‘VDDOK’ ball is high, that is
at the end of START_PM state.
RESET: STw4810 forces a reset during 10*32 kHz period before setting PORn high.
INT_OSC: The STw4810 can work without MASTER_CLK via its internal oscillator. The device
waits for an external clock detection before switching to the external clock. When receiving a
rising edge on PWREN ball (coming from multimedia processor) or on TCXO_EN ball (coming
from modem), STw4810 answers by asserting to “1” the REQUEST_MC ball. STw4810 remains
in internal oscillator mode until it receives the external clock signal on MASTER_CLK ball.
Rev3
11/72
STw4810
4 Functional description
EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as reference and
switches off its internal oscillator to save quiescent. MASTERCLK should remain connected up
to SLEEP mode.
SLEEP: SLEEP mode is required by multimedia processor by setting a PWREN at low level.
Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and wait
for PWREN at high level (Figure 4).
WAKE-UP: From SLEEP mode, the multimedia processor requests to switch back to Normal
mode. Thus the device restarts its internal oscillator and then switches regulators from sleep to
normal mode and informs multimedia processor with VDDOK at high level (Figure 4).
Note:
By default VAUX is in stand by mode, pdn_vaux = 0 (Table 17). It can be programmed in normal
mode only by asserted pdn_vaux bit to “1”.
Figure 3.
Start-up timing
OFF
VBAT
PON ball
9.38mS (11mS wc)
300µs
PDN__OSC
START_BIAS START_PM
7.77ms (9.46ms wc)
1mS
PDN_regulators
VDDOK ball
10*(1/32KHz)
CLK32K_IN ball
(*)
RESET
PORn ball
PWREN ball
Internal_OSC
MASTER_CLK ball
TCXO_EN ball
“or”
REQUEST_MC ball
OFF2
RESET
VPLL / VIO_VMEM
VCORE
Voutput(s) ball
CLK32K ball
Delays are worst case maximum delays
(*) If 32 Khz available before VDDOK signal rising edge, OFF2 state duration is null
12/72
Rev3
INT_OSC
STw4810
4 Functional description
All regulators are started with PDN_regulators but can be switched off from the beginning or
during application by software (Table 26)
.
Figure 4.
Switching POWER to sleep timing
HPM
HPM
SLEEP
~100µs
PWREN
Sleep regulators
VDDOK
PDN_regulators
CLK32K
PDN_intOSC
int_OSC _detect
REQUEST_MC
Internal_OSC
MASTER_CLK
Registers reset
In the event of a hardware reset coming from the modem, PON ball set to “0”, all registers are
reset at initial value when PON ball goes back to “1” level.
A software reset from multimedia processor of STw4810, through SW_RESETn ball set to “0”,
reset all registers except power control register (at address 1E & 1F).
Main clock oscillator control
REQUEST_MC is an OR output gate between PWREN (coming from multimedia processor)
and TCXO_EN (coming from modem supply), it is synchronized on 32 kHz, except during
power-up where PWREN is masked and considered as high.
REQUEST_MC enabled or disabled the master clock oscillator device.
Rev3
13/72
STw4810
4 Functional description
4.2.2
POWER OFF / VDDOK
●
In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detected,
or ‘it_twarn’ bit set to “1” (Table 17), then multimedia processor is reset (PORn low during
a minimum time of 312.5 µs) and restarted with no time-out. (see Figure 5). In case of
VDDOK falling edge because PWREN balls equals “0”, there is no reset (PORn still high).
●
In case of PON falling edge (STw4810 switched off from modem) multimedia processor is
also reset with no time-out. We consider that clean switch off between modem and
multimedia processor is done by software directly.
Figure 5.
VDDOK block diagram
PWREN
vcore_monitor
vio_monitor
Digital block
&
&
VDDOK
it_twarn
mask_twarn
register reset after
read operation
or PON falling edge
or PORN_VBAT.
Reg status
Under voltage detection
VDDOK
Operating voltage threshold value reached
PORn
312.5 µs
(10* 32 Khz)
4.2.3
SLEEP mode
STw4810 goes into SLEEP mode by different ways.
Whether VCORE, VIO_VMEM and VAUX are programmed to SLEEP mode or not is indicated
in Table 26.
Taking in account the bit programming from Table 26, SLEEP mode is summarized with the
following formula:
SLEEP = (Vxxx_SLEEP x PWREN) + (Vxxx_FORCE_SLEEP) = 1,
(Vxxx = VCORE or VIO_VMEM or VAUX)
14/72
Rev3
STw4810
I2C Interface
The device supports two I2C bus interfaces. One main interface (SDA,SCL) controls power
management and all programmable functions, the second interface (USBSDA, USBSCL) is
dedicated to USB control. STw4810 allows to work with only the main I2C interface to control all
the functions, including the USB, via USB_I2C_CTRL bit of power control register (Table 26).
I2C Interface is used to read status information from inside the device.
Flags, interrupt and write registers are used to configure the device functions (threshold, clock
division, output voltage, etc....). By default, the main I2C interface (SCL,SDA) controls the main
registers and USB I2C interface (USBSCL, USBSDA) controls USB registers.
Figure 6.
I2C interface block diagram
SCL
SDA
usb_i2c_ctrl
Main registers
SCL
SDA
USBSCL
MUX
4.2.4
4 Functional description
USBSDA
SCL or USBSCL
SDA or USBSDA
USB registers
Both I2C are configured as slave serial interface compatible with I2C registered trademark of
Phillips Inc. (version 2.1).
I2C interface description
STw4810 I2C is a slave serial interface with a serial data line (SDA or USBSDA) and a serial
clock line (SCL or USBSCL):
–
SCL / USBSCL: input clock used to shift data
–
SDA / USBSDA: input/output bidirectional data transfers
It is composed of:
–
One filter to reject spikes on the bus data line and preserve data integrity
–
Bidirectional data transfers up to 400kbit/s (Fast-mode) via SDA or USBSDA signal
The SDA or USBSDA signal contains the input/output control and data signals that are shifted
in the device, MSB first. The first bit must be high (START) followed by the Device ID (7 bits)
and Read/Write bit control (1 indicates read access, a logical 0 indicates a write access).
–
Device ID in write mode: 5Ah (01011010)
–
Device ID in read mode: 5Bh (01011011)
Then STw4810 sends an acknowledge at the end of an 8 bits transfer. The next 8 bits
correspond to the register address followed by another acknowledge. The 8 bits data field is
sent last, followed by a last acknowledge.
Rev3
15/72
STw4810
4 Functional description
Table 3.
Device ID
b7
b6
b5
b4
b3
b2
b1
b0
AdrID6
AdrID5
AdrID4
AdrID3
AdrID2
AdrID1
AdrID0
R/W
Table 4.
Register address
b7
b6
b5
b4
b3
b2
b1
b0
RegADR7
RegADR6
RegADR5
RegADR4
RegADR3
RegADR2
RegADR1
RegADR0
Table 5.
Register data
b7
b6
b5
b4
b3
b2
b1
b0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
I2C interface modes
Figure 7.
Control interface: I2C format
DEVICE ADDRESS
WRITE
SINGLE BYTE
ACK
ACK
REGn ADDRESS
REGn Data In
ACK
01011010
START
RANDOM ADDR
READ
SINGLE BYTE
STOP
DEVICE ADDRESS
ACK
ACK
REGn ADDRESS
01011010
DEVICE ADDRESS
ACK
REGn Data Out
NO ACK
01011011
START
START
RANDOM ADDR
READ
MULTI BYTE
DEVICE ADDRESS
ACK
ACK
REGn ADDRESS
01011010
ACK
ACK
ACK
DEVICE ADDRESS
Reg n Data Out
01011011
START
NO ACK
Reg n + m Data Out
START
STOP
m+1 data bytes
Figure 8.
Control interface: I2C timing
tbuf
SDA
USBSDA
tsu_sta
thd_sta
tf
SCL
USBSCL
tlow
Stop
16/72
thd_dat
tr
tsu_dat
thd_sta
tsu_sto
thigh
Start
Start repeated
Rev3
Stop
STw4810
4.2.5
4 Functional description
Control registers
Control registers have the following functions:
–
Select level of regulation for multimedia processor supply
–
Control the USB interface
–
Control the SD/MMC/SDIO interface
–
Control the state machine
Table 6.
Register general information
Address
Comment
I2C control
00h to 10h
USB Registers (Table 8 to Table 16)
USBSDA / USBSCL or
SDA / SCL (1)
11h
SD MMC Control register (Table 17)
SDA / SCL
12h to 1Dh
Test registers
1Eh to 1Fh
Power control registers (Table 18 to Table 26)
SDA / SCL
20h
twarning register (Table 27)
SDA / SCL
1. Controlled by USB_I2C_CTRL bit of Power control register (Table 26)
Table 7.
Register summary
Register
Addr.
7
6
5
4
3
2
1
0
00h
1
0
0
0
0
0
1
1
01h
0
0
0
0
0
1
0
0
02h
0
0
0
1
0
0
0
0
03h
0
1
0
0
0
0
0
0
Vendor ID
Product ID
USB control
register 1
04h
05h
Not used uart_en
oe_int_
en
bdis_
not used dat_se0
acon_en
USB control
register 2
06h
07h
vbus_
chrg
vbus_
dischrg
vbus_
drv
id_gnd
dn_
dp_
dn_
pulldown pulldown pullup
USB interrupt
source
08h
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
sess_vld vbus_vld
USB interrupt latch
0Ah
0Bh
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
sess_vld vbus_vld
USB interrupt mask 0Ch
false
0Dh
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
sess_vld vbus_vld
USB interrupt mask 0Eh
true
0Fh
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
sess_vld vbus_vld
USB EN
10h
Not used
SD MMC control
11h
pdn_
vaux
Twarning
20h
Not used
suspend speed
usb_en
it_warn
monitori
ng_vio_
vmem_
vcore
gpo2
gpo1
sel_vmmc<1:0>
dp_
pullup
not used
pdn_
vmmc
mask_
twarn
Rev3
17/72
STw4810
4 Functional description
Register
Addr.
Power control
15
14
13
1Fh
Register
Addr.
Power control
1 Eh
12
11
10
9
Not used
7
6
5
8
reg address 2 bits
4
reg address 3 bits
3
2
1
data din/dout 4 bits
0
ena write
REGISTERS CONTROLLED BY I2C USB BUS
The registers described in this chapter are controlled through the USB serial I2C interface,
USBSCL and USBSDA balls.
These registers could also be controlled through the main I2C interface, SCL and SDA balls by
setting to “1” USB-I2C_CTRL bit in Power control register (Table 22).
Table 8.
USB register address
Address
Note:
Register
Type
00h - 01h
Vendor ID
R
02h - 03h
Product ID
R
04h set
USB Control Register 1
R/W
05h clearh
USB Control Register 1
R/W
06h set
USB Control Register 2
R/W
07h clearh
USB Control Register 2
R/W
08h
USB Interrupt Source
R
09h
Not used
0Ah set
USB Interrupt Latch
R/W
0Bh clearh
USB Interrupt Latch
R/W
0Ch set
USB Interrupt Mask False
R/W
0Dh clearh
USB Interrupt Mask False
R/W
0Eh set
USB Interrupt Mask True
R/W
0Fh clearh
USB Interrupt Mask True
R/W
10h
USB_EN
R/W
A bit of register 1 is set at “1” by writing a “1” at address 04h, is reset at “0” by writing a “1” at
address 05h. This is also applicable for USB Control Register 2 (06h, 07h), USB Interrupt
register (0Ah,0Bh), USB Interrupt Mask False register (0Ch, 0Dh) and USB Interrupt Mask True
register (0Eh, 0Fh). Writing “0” at any address has not effect on the content of any register.
Table 9.
Vendor ID and Product ID: Read only
Name
Address
Register Value
00h
83h
01h
04h
02h
10h
03h
40h
Vendor ID
Product ID
18/72
Rev3
STw4810
4 Functional description
USB control register 1
Table 10.
USB control register 1 (address = 04h set and 05h clearh)
Register
Bit name
7
6
5
Not used
uart_en
oe_int_
en
-
R/W
R/W
Type
Bits
Name
4
3
bdis_
not used
acon_en
R/W
Value
-
2
1
0
dat_se0
suspend
speed
R/W
R/W
R/W
Settings
Default
6
uart_en
0
1
Inactive
UART logic buffers are enabled
0
5
oe_int_en
0
1
Inactive
Allow to send interruption through USBOEn
0
4
bdis_acon_en
0
1
Inactive (default)
Enable A-device to connect if B-device disconnect
detected:
0
2
dat_se0
0
1
VP_VM USB mode
DAT_SE0 USB mode
0
1
suspend
0
1
Inactive (default)
Put transceiver in low power mode
0
0
speed
0
1
Set rise and fall times of transmit
Low Speed
Full Speed
0
Rev3
19/72
STw4810
4 Functional description
USB control register 2
Table 11.
USB Control Register 2 (Address = 06h set and 07h clearh)
Register
Bit name
Type
Bits
20/72
Name
7
6
5
4
vbus_
chrg
vbus_
dischrg
vbus_
drv
id_gnd
R/W
R/W
R/W
R/W
Value
3
2
dn_
dp_
pulldown pulldown
R/W
R/W
Settings
1
0
dn_
pullup
dp_
pullup
R/W
R/W
Default
7
vbus_chrg
0
1
Inactive
Charge VBUS through a resistor
0
6
vbus_dischrg
0
1
Inactive
Discharge VBUS through a resistor to ground.
0
5
vbus_drv
0
1
Inactive
Provide power to VBUS
0
4
id_gnd
0
1
Inactive
Connect ID ball to ground
0
3
dn_pulldown
0
1
Inactive
Connect DN pull-down
0
2
dp_pulldown
0
1
Inactive
Connect DP pull-down
0
1
dn_pullup
0
1
Inactive
Connect DN pull-up
0
0
dp_pullup
0
1
Inactive
Connect DP pull-up
0
Rev3
STw4810
4 Functional description
USB interrupt source register
Table 12.
USB Interrupt source register (address = 08h)
Register
Bit name
7
6
5
4
3
2
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
R
R
R
R
R
R
Type
Bits
Name
Value
1
0
sess_vld vbus_vld
R
Settings
R
Default
0
1
Inactive
DP ball is above the carkit interrupt threshold
0
0
1
Inactive
Set when bdis_acon_en is set, and transceiver asserts
dp_pullup after detecting B-device disconnect.
0
id_float
0
1
Inactive
ID ball floating
0
4
dn_hi
0
1
Inactive
DN ball is high
0
3
id_gnd_forced
0
1
Inactive
ID ball grounded
0
2
dp_hi
0
1
Inactive
DP asserted during SRP,
0
1
sess_vld
0
1
Session valid comparator threshold <0.8V or >4.4V
0.8V < Session valid comparator threshold < 4.4V
0
0
vbus_vld
0
1
A-device VBUS valid comparator threshold <4.4V
A-device VBUS valid comparator threshold >4.4V
0
7
cr_int
6
bdis_acon
5
USB latch register
Table 13.
USB interrupt latch registers (address = 0Ah set and 0Bh clearh)
Register
Bit name
Default
Type
7
6
5
4
3
2
1
0
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
sess_vld vbus_vld
USB interrupt latch register bits indicate which sources have generate an interrupt.
Rev3
21/72
STw4810
4 Functional description
USB interrupt mask false register
Table 14.
USB interrupt mask false register (address = 0Ch and 0Dh)
Register
Bit name
Default
Type
7
6
5
4
3
2
1
0
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
sess_vld vbus_vld
USB interrupt mask false register bits enable transition from true to false.
USB interrupt mask true register
Table 15.
USB interrupt mask true register (address = 0Eh and 0Fh)
Register
7
6
5
4
3
2
Bit name
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
Type
R/W
R/W
R/W
R/W
R/W
R/W
sess_vld vbus_vld
R/W
R/W
USB interrupt mask true register bits enable interrupts on transition from false to true.
USB EN register
Table 16.
USB EN register (address = 10h)
Register
7
6
5
Bit name
1
22/72
3
2
Not used
Type
Bits
4
-
Name
usb_en
-
-
Value
0
1
-
-
Settings
Inactive
Enable USB PHY
Rev3
-
1
0
usb_en
not used
R/W
-
Default
0
STw4810
4 Functional description
REGISTERS CONTROLLED BY MAIN I2C BUS
I²C controlled registers are controlled through the main serial I2C interface, SCL and SDA balls.
SD MMC control register
Table 17.
SD MMC control register (11h)
Register
7
6
5
4
3
2
1
0
Bit name
pdn_
vaux
it_warn
monitori
ng_vio_
vmem_
vcore
gpo2
gpo1
sel_vmmc<1:0>
pdn_
vmmc
Type
R/W
R(1)
R(1)
R/W
R/W
R/W
R/W
1. These bits are reset (0) after reading
Bits
Name
Value
Settings
Default
7
pdn_vaux
0
1
Inactive
Enable LDO vaux
0
6
it_warn
0
1
Below temperature threshold
Above temperature threshold
0
5
monitoring_vio_
vmem_vcore
0
1
Outputs in the good range
Outputs lower than expected on vio_vmem or vcore
0
4
gpo2
0
1
Output GPO2 HZ
Output GPO2 Low
0
3
gpo1
0
1
Output GPO1 HZ
Output GPO1 low
0
00
01
10
11
1.8V selection
1.8V selection
2.85V selection
3V selection
00
0
1
Inactive
Enable SD/MMC or SDIO function.
0
[2:1] sel_vmmc<1:0>
0
pdn_vmmc
In Flash OTP two registers allow to program STw4810 energy management part.
These two registers are at address 1E and 1F and must be programmed with 1F register first
followed by 1E register.
Rev3
23/72
STw4810
4 Functional description
Power control register at address 1Eh
Table 18.
Power control register - General information (Address = 1Eh)
Register
Bit name
7
6
2
1
0
EN
R/W
R/W
R/W
Value
Settings
[7:5] reg address 3 bits
data din/
dout 4 bits
0
1
EN
0
3
data din/dout 4 bits
Name
[4:1]
4
reg address 3 bits LSB’s
Type
Bits
5
Default
See Table 20 “Address” column (LSB’s).
0
See Table 20 control register
0
Read enabled
Write enabled
0
Power control register at address 1Fh
Table 19.
Power control register - General information (Address = 1Fh)
Register
15
14
13
Bit name
12
11
10
9
8
reg address 2 bits
MSB’s
Not used
Type
R/W
Bits
Name
[9:8]
reg address 2 bits
MSB’s
Value
Settings
Default
See Table 20 “Address” column (MSB’s).
0
Power control register mapping
Table 20.
Power control register mapping
Address 1Fh
Address 1Eh
reg address
Not used
15 14 13 12 11 10
2 bits
MSB’s
9
8
Comment
3 bits
LSB’s
7
6
data din/dout
4 bits
5
4
3
2
00h to 04h
0
Test purpose
05h to 0Ah
Setting
0Bh to 1E
24/72
1
EN
See Table 21 to Table 26
Test purpose
Rev3
STw4810
4 Functional description
Caution: Only the latest value written in register at address 1E/1F can be read.
Power control register at address 05h
Table 21.
Power control register at address 05h
Address 1Fh
15
Bits
[4:1]
14
13
12
11
Address 1Eh
9
8
7
6
5
Not used
0
0
1
0
1
Name
Value
vcore_sel [3:0]
10
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
3
vcore_sel [3:0]
Settings
= 1.00V
= 1.05V
= 1.10V
= 1.15V
= 1.20V (default)
= 1.22V
= 1.24V
= 1.26V
= 1.28V
= 1.30V
= 1.32V
= 1.34V
= 1.36V
= 1.38V
= 1.40V
= 1.50V
Rev3
2
1
0
EN
Default
0100
25/72
STw4810
4 Functional description
Power control register at address 06h
Table 22.
Power control register at address 06h
Address 1Fh
15
14
Bits
4
13
12
11
Address 1Eh
10
9
8
7
6
5
4
Not used
0
0
1
1
0
vpll_sel
[0]
Name
Value
vpll_sel[1:0]
on 06h and 07h
address
[3:2] vaux_sel[1:0]
1
usb_i2c_ctrl
3
2
vaux_sel
<1:0>
1
0
usb_
i2c_ctrl
EN
Settings
Default
00
01
10
11
= 1.05V
= 1.2V
= 1.3V
= 1.8V
11
00
01
10
11
= 1.5V
= 1.8V
= 2.5V
= 2.8V
00
0
1
USB I2C interface controls USB registers
Main I2C interface controls USB registers
0
Power control register at address 07h
Table 23.
Power control register at address 07h
Address 1Fh
15
Bits
14
13
12
11
Address 1Eh
10
9
8
7
6
5
4
3
2
1
0
Not used
0
0
1
1
1
en_vpll
not
used
en_
vcore
vpll_sel
[1]
EN
Name
Value
Settings
4
en_vpll
0
1
Disabled / VPLL = OFF
2
en_vcore
0
1
Disabled / VCORE = OFF
1
vpll_sel[1]
-
See Table 22
Enabled / VPLL = ON(1)
Enabled / VCORE = ON(1)
1. No soft start feature at supply enabled after a disabled/enabled sequence
26/72
Rev3
Default
1
1
-
STw4810
4 Functional description
Power control register at address 08h
Table 24.
Power control register at address 08h
Address 1Fh
15
14
13
12
11
Address 1Eh
10
9
8
7
6
5
4
3
Not used
0
1
0
0
0
Bits
Name
Value
4
en_clock_squarer
0
1
Disabled
Enabled (sine wave signal input)
0
3
en_monitoring
0
1
Disabled / MONITORING = OFF
Enabled / VCORE & VIO_VMEM monitoring = ON
1
2
en_vana
0
1
Disabled / VANA = OFF
Enabled / VANA = ON
1
en_clk en_mo
squarer nitoring
2
1
0
en_
vana
not
used
EN
Settings
Default
Power control register at address 09h
Table 25.
Power control register at address 09h
Address 1Fh
15
Bits
14
13
12
11
Address 1Eh
10
9
8
7
6
5
4
3
Not used
0
1
0
0
1
vaux_
sleep
not
used
Name
Value
Settings
2
1
vio_
vcore_
vmem_
sleep
sleep
0
EN
Default
4
vaux_sleep
0
1
When PWREN is low:
VAUX stays in normal mode
VAUX goes in sleep mode (default)
1
2
vio_vmem_sleep
0
1
When PWREN is low:
VIO_VMEM stays in normal mode
VIO_VMEM goes in sleep mode
1
1
vcore_sleep
0
1
When PWREN is low:
VCORE stays in normal mode
VCORE goes in sleep mode
1
Rev3
27/72
STw4810
4 Functional description
Power control register at address 0Ah
Table 26.
Power control register at address 0Ah
Address 1Fh
15
14
13
12
11
Address 1Eh
10
9
Not used
0
8
1
7
0
6
1
5
4
3
0
vaux_
force_
sleep
not
used
2
1
vio_
vcore_
vmem_
force_
force_
sleep
sleep
Settings
0
EN
Bits
Name
Value
Default
4
vaux_force_sleep
0
1
0: VAUX in normal mode
1: VAUX goes in sleep mode (for any PWREN level)
0
2
vio_vmem_force_
sleep
0
1
0: VIO_VMEM in normal mode
1: VIO_VMEM goes in sleep mode (for any PWREN
level)
0
1
vcore_force_slee
p
0
1
0: VCORE stays in normal mode
1: VCORE goes in sleep mode (for any PWREN level)
0
Twarning register
Table 27.
Twarning register (Address = 20h)
Register
7
6
5
Bit name
Type
28/72
Bits
Name
Value
0
mask_twarn
0
1
4
3
2
0
Not used
mask_
twarn
-
R/W
Settings
Inactive
Mask TWARN interruption (it_twarn bit) through
VDDOK
Rev3
1
Default
0
STw4810
4.2.6
4 Functional description
IT generation
STw4810 has three interrupt balls:
IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged
this interrupt is activated to wake up the host or the modem, depends of application (active low).
USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor
VDDOK: This ball has two functions:
- When high, it indicates that VIO_VMEM and VCORE output voltages are within the right
range and that the device internal temperature is below the maximum allowed temperature.
- When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated
properly or PWREN = “0”, or that the temperature is above the allowed threshold (see Thermal
shut-down section). The interruption source in the application register (address 11h) needs to
be checked.
4.2.7
Clock switching and control
This block generates the clock used by the DC/DC converter (USB charge pump, step-down
VIO_VMEM and step-down VCORE). STw4810 is able to sustain the master clock frequencies
of 26 MHz, 19.2MHz and 13 MHz. It can also sustain dedicated MASTER_CLK signal in the
frequency range of 750KHz to 1MHz. If the clock is not detected the internal oscillator is
automatically selected.
Note:
When present the Master clock should remain connected up to Sleep mode.
Figure 9.
Clock switching between master and internal clock (1)
* Phase delay is less than 90 between int and ext clock
internal clock
transition
external clock
PON
INT_OSC
INT_OSC_OK
MASTER_CLK_OK
Third rising edge after switching
PDN_INT_OSC
CONTROL_SWITCH
MASTER_DIV_CLK
STEP_DOWN_CLK
Rev3
29/72
STw4810
4 Functional description
4.3
Power management module
STw4810 includes several regulators that supply the multimedia processor and its peripherals.
All regulators can work in different modes depending on the processor needs.
When the STw4810 is in ‘Low Current Mode’”, the output current is reduced to save energy via
the lower quiescent current. The nominal mode is called high power mode (HPM). The mode is
selected by PWREN signal according to both multimedia processor and STw4810 state.
When PWREN = “0”, sleep mode is selected. HPM is selected as default when PWREN = “1”.
Each regulator has a dedicated battery power supply. It can be powered down by a signal
called PDN_regulator_name as shown in the Figure 2: STw4810 block diagram. In this mode,
the regulator is switched off and only a leakage current is present (max. 1µA). VCORE, VAUX
and VPLL output voltages are programmable, through main I2C interface, using the
“Regulator”_SEL[x:0] bits of the POWER CONTROL registers (Table 21 to Table 26).
In addition, an output current limitation prevents high current delivery in case of output short
circuit.
All multimedia processor power supplies have the same soft start to prevent leakage in the
multimedia processor device during the start-up phase. There is an exception with VAUX which
can be started independently.
4.3.1
Bandgap, biasing and references
Figure 10. Block diagram of biasing and references of the device
BG
VREF_18
VOLTAGE REFERENCE
CONTROL
All internal
references
All internal
biasing
BIAS GENERATOR
4.3.2
VCORE regulator: DC/DC STEP- DOWN regulator
This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down
regulator that generates the regulated power supply with very high efficiency. The 15 voltage
levels enable dynamic voltage and frequency scaling suitable for any supply voltage of CMOS
process, they also follow the processor process roadmap. The regulated output voltage levels
are adjustable by the power control registers (Table 21), via the main I2C interface (SDA, SCL).
The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to
generate the switching clock of the SMPS. When this clock is not available, regulators run the
internal RC oscillator.
30/72
Rev3
STw4810
4 Functional description
Main features:
●
Programmable output voltage, 15 levels from 1.0 V to 1.5 V (VCORE_SEL [3:0] bits of
Power control register - Table 21)
●
3 power domains:
–
‘Normal mode’ when multimedia processor is in run mode, 600 mA full load
–
‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current
capability.
Fast switching from low current to normal mode.
The regulator is in ‘low current mode’ when multimedia processor is in sleep mode.
PWREN signal indicates that the multimedia processor is about to switch to run
mode. VDDOK signal indicates to the multimedia processor that all supplies are in the
specified range.
Note:
The definition of SLEEP mode is given in section 4.2.3: SLEEP mode.
●
‘Power Down mode’ or ‘Standby Mode’ when regulator is switched off, no consumption
(EN_VCORE bit of Power control register - Table 27)
●
Soft start circuitry at start up, from power off to normal mode, when PON ball changes
from “0” to “1”.
●
Default setting defined by start-up configuration.
4.3.3
VIO_VMEM regulator: DC/DC step- down regulator
VIO_VMEM step-down regulator has the same structure than VCORE.
The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals.
This regulator can be used to supply the memories working with the multimedia processor,
such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to
generate the 1.8 V regulated power supply with very high efficiency.
The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to
generate the SMPS switching clock. When this clock is not available, regulators can run the
internal RC oscillator.
Main features
Note:
●
Fixed 1.8 V output voltage
●
Two power domains:
–
‘Normal mode’ when multimedia processor is in run mode - 600 mA full load
–
‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current
capability.
Fast switching from low current to normal mode.
The regulator is in ‘low current mode’ when multimedia processor is in sleep mode.
PWREN signal indicates that the multimedia processor is about to switch to run
mode. VDDOK signal indicates to the multimedia processor that all supplies are in the
specified range.
The definition of SLEEP mode is given in 4.2.3: SLEEP mode section.
●
Soft start circuitry at start up, from power off to normal mode, when PON ball changes
from “0” to “1”.
●
Default setting defined by start-up configuration.
Rev3
31/72
STw4810
4 Functional description
4.3.4
VPLL
This LDO is dedicated to the multimedia processor PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V) power
supply with 10 mA max full load (Power Control Registers - Table 26 and Table 27).
Main features
4.3.5
●
Programmable output voltage, (VPLL_SEL[1:0] bits of power control register - Table 26
and Table 27)
●
Two power domains:
–
‘Normal mode’ 10 mA full load
–
‘Power Down mode’ or ‘Standby Mode’ when regulators are switched off and there is
no power consumption (EN_VPLL bit of power control register - Table 27)
●
Soft start circuitry at start up, from power off to normal mode, when PON ball changes
from “0” to “1”.
●
Default setting defined by start-up configuration.
VANA
This LDO is dedicated to the multimedia processor analogue function (2.5 V) power supply with
10 mA full load.
Main features:
●
2.5 V output voltage,
●
Two power domains
●
4.3.6
–
‘Normal mode’ 10 mA full load
–
‘Power Down mode’ or ‘Standby Mode’ when regulators are switched off and there is
no power consumption (EN_VANA bit of Power control register - Table 28),
Default setting defined by start-up configuration.
VAUX
This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliary
devices. Power supply values are 1.5 V,1.8 V, 2.5 V, 2.8 V with 150 mA full load and 0.5 mA in
SLEEP mode. In case of 1.5 V on the output, this LDO can be supplied by using VIO_VMEM
DC/DC converter (1.8 V). One pad feed-back is used.
Main features:
Note:
32/72
●
Programmable output voltage, 4 levels
(VAUX_SEL[1:0] bits of Power control register - Table 26)
●
Three power domains:
–
‘Normal mode’ when multimedia processor is in run mode, 150 mA full load
–
‘Low current mode’ when multimedia processor is in sleep mode, 0.5 mA current
capability.
Fast switching from low current to normal mode.
Definition of SLEEP mode is given in 4.2.3: SLEEP mode section.
–
‘Power down mode’ or ‘standby mode’ when regulator is switched off, no power
consumption (PDN_VAUX bit of SD MMC control register - Table 17)
●
Default setting defined by start-up configuration
Rev3
STw4810
4.3.7
4 Functional description
Power supply monitoring
This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drop
below the threshold, the multimedia processor is reset.
This feature can be desactivated by setting EN_MONITORING bit of Power control register
(Table 28) to “0”.
4.3.8
Power supply domains
Table 28 lists the register bits that control the different STw4810 supply domains for each
supply.
Table 28.
Power supply domains
Supply domains
Supply
name
Description
Normal
Sleep
Power down
VCORE
STEP-DOWN
15 values
VCORE_SEL[3:0]
VCORE_SLEEP
VCORE_FORCE_SLEEP
VIO_VMEM
STEP-DOWN
1.8 V
VIO_VMEM_SLEEP
VIO_VMEM_FORCE_SLEEP
VPLL
LDO
4 values
VPLL_SEL[1:0]
EN_VPLL
VANA
LDO
2.5 V
EN_VANA
VAUX
LDO
4 values
VAUX_SEL[1:0]
VMMC
LDO
3 values
SEL_VMMC[1:0]
VAUX_SLEEP
VAUX_FORCE_SLEEP
Note:
More details on VMMC supply are given in Section 4.5
4.3.9
Thermal shut-down
EN_VCORE
PDN_VAUX
PDN_VMMC
A thermal sensor is used to monitor the die temperature.
●
As soon as the die temperature exceeds the thermal warning rising threshold 1, VDDOK
ball goes to “0” and ‘it_warn’ bit is set to “1” (SD MMC control register - Table 17). The IC
turns back VDDOK ball to “1” and ‘it_warn’ bit to “0” when the device temperature drops
below the thermal warning falling threshold 1 of the thermal sensor.
●
A second thermal detection level, thermal shutdown rising threshold 2, puts all STw4810
supplies OFF, the supplies goes back to ON state when the temperature reaches the
thermal shutdown falling threshold 2.
Table 29.
Thermal threshold values
Description
Min
Typ
Max
Unit
Rising threshold
134
140
149
°C
Falling threshold
117
123
131
°C
Thermal Warning Threshold 1
Rev3
33/72
STw4810
4 Functional description
Table 29.
Thermal threshold values
Description
Min
Typ
Max
Unit
Rising threshold
149
155
164
°C
Falling threshold
129
135
143
°C
Thermal Shutdown Threshold 2
Figure 11. Thermal threshold temperatures for ‘it_warn’ bit and VDDOK ball
‘it_warn’ bit
All supplies
are turn “OFF”
VDDOK ball
Rising Warning
Threshold 1
4.4
Rising Shutdown Temperature
Threshold 2
USB OTG module
This transceiver complies with the USB specification:
●
Universal Serial Bus Specification Rev 2.0
●
On the Go supplement to the USB specification Rev 1.0-a
●
Car kit Interface Specification (see: OTG transceiver specification rev0.92)
The USB OTG Transceiver has two modes: USB mode and UART mode.
It includes:
34/72
●
Full and low speed transceiver (12 Mbit/s and 1.5 Mbit/s data rate)
●
Support data line and VBUS pulsing session request
●
Contains Host Negotiation Protocol (HNP) command and status register
●
Charge pump regulator (5 V at 100 mA) to supply VBUS line of the USB cable
●
VBUS Pull-up and pull-down resistors as defined by Session Request Protocol (SRP)
●
VBUS threshold comparators
●
VUSB LDO internal regulator which provides power supply for the bus driver and receiver.
●
ID line detector and interrupt generator
●
Dedicated I²C serial control interface
Rev3
STw4810
Block diagram
Figure 12. USB OTG transceiver block diagram
VBAT_USB
CP
CN
VBAT_DIG
USB_INTn
vbus_vld
sess_vld
dn_hi
Interrupt dp_hi
Control bdis_acon
Register id_gnd_forced
id_float
cr_int
usb_en
CHARGE
PUMP
5V - 100mA
REF
vbus_drv
VBUS
VBUS_MONITOR
VBUS > 4.4 V
vbus_vld
sess_vld
USBSDA
SCL
SDA
SW_RESETn
vbus_chrg
VBAT_USB
VBUS < 0.8V
Gnd
VUSB_LDO
vbus_dischrg
vbus_drv
bdis_acon_en
dn_pullup
dp_pullup
Control dn_pulldown
Registers dp_pulldown
id_gnd
vbus_chrg
vbus_dischrg
speed
uart_en
dat_se0
oe_int_en
suspend
RA_BUS_IN
2V < VBUS < 4.4 V
usb_i2c_ctrl
USBSCL
100 mA
R_VBUS_SRP
CLK
VMINUS_DIG
R_VBUS_PD
vbus_session_end
VUSB
DP_MONITOR
5.7 R
DP
cr_int
RXD
TRANCEIVER
RXD
dp_pullup
dn_pullup
RPU_DP
DAT_VP
USBVP
Diff Tx
SEO_VM
USBVM
R
DP < [0.4 to 0.6] V
RPU_DN
OE_TP_INT
USBOEn
DP
out_diff_Rx
Diff Rx
DN
USBRCV
SINGLE
ENDED
RCV
SE_DP
RPD_DP
suspend
RPD_DN
4.4.1
4 Functional description
VP
dn_pulldown
DECODER
SE_DN
VM
dp_pulldown
VBAT_DIG
VBAT_USB
R
Plug detect
Management
IT_WAKE_UP
id_float
sess_vld
ID
4.7 R
id_gnd
0.15*ID
OR
ID Detector
Rev3
RID_PU
0.85*ID
id_gnd
R
35/72
STw4810
4 Functional description
VBUS monitoring
These comparators monitor the VBUS voltage. They detect the current status of the VBUS line:
●
VBUS > 4.4 V means VBUS_VALID
●
2 V<VBUS<4.4 V means SESSION_VALID
●
VBUS<0.8 V means SESSION_END
These three bits generate an interrupt when active (see USB interrupt registers).
VUSB LDO: Internal regulator which provides power supply for the bus driver and receiver.
ID detector: This block detects the status of the ID line. It is capable of detecting three different
states of line: ball is floating ID_FLOAT high, ball is tied to ground ID_GND high and ball ID is
grounded via resistor. This detection generates interrupts (see USB interrupt registers).
Transceiver: The driver can operate in several different modes. It can act as a classical lowspeed and full-speed differential driver, as two independent single-ended drivers or as a singleended driver in UART mode. This block contains one differential receiver for the USB mode of
operation and two single-ended receivers for USB signaling and UART mode.
DP monitor: This block is used to detect car kit peripheral (0.6 V on DP).
Pull up and pull down resistor: Configurable integrated pull-up and pull-down resistor of data
line and VBUS.
4.4.2
Modes and operations
Power modes
The transceiver power modes are:
●
Active power mode
●
Suspended power mode
●
Power down mode
In suspended power mode the differential transmitter and receiver are turned off to save power
but the USB interface is still active (pull-up and pull-down on, VBUS on). In power down mode,
only the serial interface is active and the transceiver is able to detect SRP. In power down
mode, ID ball sensing can be turned on/off via a control bit in the control registers.
USB modes
The two transceiver modes are:
36/72
●
DAT_SEO mode (dat_se0 = 1 in USB control register 1 - Table 10)
●
VP_VM mode (dat_se0 = 0 in USB control register 1 - Table 10)
Rev3
STw4810
4 Functional description
Data transmission The transceiver transmits USB data in the following conditions for USB
control register 1 (Table 30, Table 31):
uart_en=0; oe_int_en=0
Table 30.
Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0
USB mode
(DAT_SE0)
Inputs
Outputs
Comments
USBVP
USBVM
DP
DN
1 (DAT_SE0 mode)
0
0
0
1
Not used
Single ended data (zero sent)
1 (DAT_SE0 mode)
1
0
1
0
Not used
Single ended data (1 sent)
1 (DAT_SE0 mode)
x
1
0
0
Not used
Force single ended zero
0 (VP_VM mode)
0
0
0
0
DIFF_RX
0 (VP_VM mode)
1
0
1
0
DIFF_RX
0 (VP_VM mode)
0
1
0
1
DIFF_RX
0 (VP_VM mode)
1
1
1
1
DIFF_RX
Table 31.
USBRCV
DAT_VP drives the level of DP
SE0_VM drives the level of DN
Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1
USB mode
(dat_se0)
Inputs
Outputs
Comments
USBVP
USBVM
DP
DN
USBRCV
1 (DAT_SE0 mode)
0
0
0
1
not used
single ended data (zero sent)
1 (DAT_SE0 mode)
1
0
1
0
not used
single ended data (1 sent)
1 (DAT_SE0 mode)
x
1
0
0
not used
Force single ended zero
0 (VP_VM mode)
0
0
0
0
0 (off)
0 (VP_VM mode)
1
0
1
0
0 (off)
0 (VP_VM mode)
0
1
0
1
0 (off)
0 (VP_VM mode)
1
1
1
1
0 (off)
Driver are suspended
If oe_int_en = 1 and suspend=1 (USB control register 1 - Table 10), the USBOEn ball becomes
an output used to generate an IT to multimedia processor.
Rev3
37/72
STw4810
4 Functional description
The transceiver receives USB data in the following conditions:
uart_en = 0 (USB control register 1); oe_int_en = 1
Table 32.
Data receiver via USB control register 1
Inputs
USB mode
(dat_se0)
Suspend
1 (DAT_SE0 mode)
Outputs
Comments
DP
DN
USBVP
USBVM
USBRCV
0
0
0
Diff rcv 1
1
not used
1 (DAT_SE0 mode)
0
1
0
1
0
not used
1 (DAT_SE0 mode)
0
0
1
0
0
not used
1 (DAT_SE0 mode)
0
1
1
Diff rcv 1
0
not used
1 (DAT_SE0 mode)
1
0
0
0
1
not used
1 (DAT_SE0 mode)
1
1
0
1
0
not used
1 (DAT_SE0 mode)
1
0
1
0
0
not used
1 (DAT_SE0 mode)
1
1
1
1
0
not used
0 (VP_VM mode)
0
0
0
0
0
diff rcv 1
0 (VP_VM mode)
0
1
0
1
0
1
0 (VP_VM mode)
0
0
1
0
1
0
0 (VP_VM mode)
0
1
1
1
1
diff rcv 1
0 (VP_VM mode)
1
0
0
0
0
not used
0 (VP_VM mode)
1
1
0
1
0
not used
0 (VP_VM mode)
1
0
1
0
1
not used
0 (VP_VM mode)
1
1
1
1
1
not used
UART mode
UART mode is entered by setting the ‘uart_en’ bit to 1 (USB control register 1 - Table 10). The
transceiver contains two digital logic level translators between the following balls:
●
TXD signal: from USBVM to DN
●
RXD signal: from DP to USBVP
When not in UART mode the level translators are disabled.
38/72
Rev3
STw4810
4 Functional description
VBUS monitoring and control
The monitoring is made of three comparators that determine if the VBUS voltage is at a valid
level for operation:
●
VBUS VALID: It corresponds to the minimum level on VBUS. Any voltage on VBUS below
the threshold is considered to be a fault. During power-up, it is expected that this
comparator output is ignored.
●
VBUS SESSION VALID: This threshold is necessary for session request protocol to detect
the VBUS pulsing.
●
VBUS SESSION END: Session is ended. In this USB block, a B-device Session End
threshold is defined within the range [0.2; 0.8] V. The reason for a low 0.2 V limit is that the
leakage current could charge the VBUS up to 0.2 V (maximum).
When the A-device (default master) is power supplied and does not supply VBUS, it presents
an input impedance RA_BUS_IN on VBUS of no more than 100 kΩ. If the A-device responds to
the VBUS pulsing method of SRP, then the input impedance RA_BUS_IN may not be lower
than 40 kΩ.
When the A-device supplies power, the rise time TA_VBUS_RISE on VBUS to go from 0 to
4.4 V is less than 100 ms when driving 100 mA and with an external load capacitance of 10 µF
(in addition to VBUS decoupling capacitance). If VBUS does not reach this voltage within
TA_VBUS_RISE maximum time, it indicates that the B-device is drawing more current that the
A-device is capable of providing and an over-current condition exists. In this case, the A-device
turns VBUS off and terminates the session.
VBUS capacitance
A dual-role device must have a VBUS capacitance CDRD_VBUS value comprised between
1 µF and 6.5 µF (see charge pump specification). The limit on the decoupling capacitance
allows a B-device to differentiate between a powered-down dual-role device and a powereddown standard host. The capacitance on a host is higher than 96 µF.
Data line pull-down resistance
When an A-device is idle or acting as host, it activates the pull-down resistors RPD on both DP
and DN lines.
When an A-device is acting as peripheral, it disables RPD on DP, not DN.
The A-device can disable both pull-down resistors during the interval of a packet transmission
when acting as either host or peripheral.
The two bits of USB control register, dn_pulldown and dp_pulldown (Table 11) are used to
connect/disconnect the pull-down resistors.
When the line is not used, the pull-down is activated and the maximum level on this ball should
not exceed 0.342 V.
Data line pull-up resistance
Full-speed and low-speed devices are differentiated by the position of the pull-up resistor from
the peripheral device. A pull-up resistor is connected to DP line for a full-speed device and a
pull-up resistor is connected to DN line for a low-speed device. The pull-up resistor value is in
the range of 900 Ω to 1600 Ω when the bus is idle and 1425 Ω to 3100 Ω when the upstream
device is transmitting.
Rev3
39/72
STw4810
4 Functional description
The two bits of USB control register dp_pullup and dn_pullup (Table 11) are used to connect/
disconnect pull-up resistors.
Session Request Protocol (SRP)
To save power, the OTG supplement allows an A-device to leave the VBUS turned off when the
bus is not being used. If the B-device wants to use the bus when VBUS is turned off, then it
requires the A-device to supply power on VBUS using the Session Request Protocol (SRP).
●
Initial conditions
The B-device does not attempt to start a new session until it has determined if the A-device has
detected the end of the previous session. The B-device must ensure that VBUS is below
VBUS_SESSION_END before requesting a new session.
Additionally, the B-device switches a pull-down resistor (R_VBUS_PD) from VBUS to ground in
order to quicken the discharge process as long as the B-device does not draw more than 8 mA
from VBUS. R_VBUS_PD is activated by bit ‘vbus_dischrg’ of USB control register 2,
(Table 11).
When the B-device detects that VBUS is below the VBUS_SESSION_END and that both DP
and DN have been low (SEO) for at least 2 ms, then any previous session on the A-device is
over and a new session can start.
●
Data-line pulsing
To indicate a request for a new session using the data line pulsing, the B-device turns on the
DP pull-up resistor for 5 ms to 10 ms (only at full speed, no DN pulsing). The DP pull-up resistor
is connected to VUSB (regulator output voltage). Timing is controlled by the USB digital control.
●
VBUS pulsing
To indicate a request for a new session using the VBUS pulsing method, the B-device waits for
the initial conditions and then drives VBUS. VBUS is driven for a long enough period for a
capacitance on VBUS that is smaller than 2x6.5 µF to be charged to 2.1 V while a capacitance
on VBUS higher than 97 µF is not charged above 2.0 V. In this USB block, the
VBUS_SESSION_VALID threshold is used to determine if an A-device is DRD (dual role
device) or a standard host.
The B-device VBUS pulsing block is designed so that the maximum drawn current does not
exceed 8 mA. In this USB block, the pull-up is 600 Ω +/- 30%.
If a B-device is attached to a standard device, the pull-up must be disconnected after the
defined timing to prevent damage of standard hosts not designed to withstand a voltage
externally applied to VBUS.
●
Session Request Protocol (SRP)
If the B-device is in correct condition to start a new session, it first performs data line pulsing,
followed by VBUS pulsing. When VBUS next crosses the SESSION VALID threshold, the Bdevice considers a session to be in progress and asserts the DP or DN data line within 100 ms.
After SRP initialization, the B- device is set up to wait for at least 5 seconds for the A-device to
respond before informing the user that the consumption attempt has failed.
●
Host Negotiation Protocol (HNP)
At the start of a session, the A-device has the role of host as default. During a session, the host
role can be transferred back and forth between the A-device and the B-device any number of
times using the Host Negotiation Protocol (HNP). The process for this exchange of host role is
described in the “On the Go Supplement to the USB 2.0 Specification” (rev 1.0).
40/72
Rev3
STw4810
4 Functional description
ID detector
In either active or suspended power mode, the ID detector detects the condition of the ID line
and differentiates between the following three conditions:
–
ID ball floating: (e.g. with USB B-device connected)
–
ID ball shorted to ground: (e.g. with USB A-device connected)
–
ID ball connected to ground through resistor RACC_ID: (e.g.with an accessory).
The transceiver pulls the ID ball to VID_HI (VBAT) through a resistance of RID_PU when an
accessory is plugged in. In this case, the ID ball is externally connected to ground via Racc_ID
resistor.
Two comparators are used to detect the ID voltage: VID_GND and VID_FLOAT.
The ID detector also has a switch that can be used to ground the ID ball. This switch is
controlled by id_gnd bit of USB control register 2 (Table 11); This pull-down is used for
CEA_KARKIT purposes.
Car kit interrupt detector
The transceiver is able to detect when the DP line is below the Carkit Interrupt threshold ‘cr_int’,
(see USB interrupt register) (refer to OTG specifications, Rev 0.92, §2.7, p13).
Charge pump
From VBAT_USB, the charge pump supplies VBUS, ‘vbus_drv’ bit of USB control register 2
(Table 11) is used to enable/disable the charge pump.
LDO USB
From VBAT_USB, a LDO provides VUSB supply, ‘usb_en’ bit of USB_EN register (Table 16) is
used to enable/disable the VUSB LDO.
Rev3
41/72
STw4810
4 Functional description
4.4.3
USB enable control
STw4810 OFF
In this state, the overall system is able to detect USB connection through IT_WAKE_UP ball
and with VBUS session valid comparator and ID detection ON.
IT_WAKE_UP is activated (low level) in either of the two following cases:
–
When Mini A connector cable is connected and ID goes low
–
When activity on VBUS, i.e. a mini B is connected and is able to communicate.
This mode is used to wake-up the modem platform. In this configuration, USBINTn
ball is not enabled.
STw4810 ON, USB driver not enabled
The USBINTn is now enabled.
If the USB cable is already connected while STw4810 is starting, the USB driver will be enabled
when power management is ready.
●
●
●
42/72
Wake-up USB driver conditions
–
A plug-in on a mini A-device and active ID detector
–
B device is connected and ready to start data transfer, VBUS is driven high (session
valid high)
–
Activity on USB registers (00h to 0Fh - Table 8 to Table 15). Multimedia processor
ready to wake-up and set-up USB PHY.
–
Possibility to force PHY high (enable) when writing usb_en = 1 in USB EN register
(Table 16)
Set condition: one among the following possibilities
–
External it_wake_up =0
–
usb_en = 1 by writing to I²C USB interface
–
Access to any other USB register (00h to 0Fh)
Power down USB driver conditions in order to set the USB driver to power down mode:
–
it_wake_up = 1, and only then
–
Set usb_en bit of USB EN register (Table 16) to “0”
Rev3
STw4810
4.5
4 Functional description
SD/MMC/SDIO module
This block provides the power supply (1.8 V, 2.85 V or 3 V) and signal shifting functions
required to connect any of the following peripherals to the multimedia processor:
–
SD card
–
MMC cards, low and 52 MHz high speed
–
SDIO cards (except SDIO card version 1.0 / Vsupply range: [3.1; 3.6] V
Cards detection is automatically done by the multimedia processor system. Following a card
detection, the multimedia processor starts the SD/MMC application by writing in the SD MMC
control register (Table 17) to start LDO VMMC and then starts the protocol initialization.
The module includes:
–
1.8 V, 2.85 V or 3 V voltage regulators (150 mA)
–
Five bidirectional level shifter channels compatible with 1.8 V, 2.85 V or 3 V
–
Two unidirectional lines for clock: multimedia processor to card and feedback clock to
multimedia processor for synchronization.
–
Four control signals for channel direction
Figure 13. SD MMC block diagram
SD/ MMC/SDIO INTERFACE
VBAT_VMMC
MCCMDDIR
MCDATA0DIR
MCDATA2DIR
MCDATA31DIR
VMMC
1.8V,2.85V,3V
150mA
CLKOUT
MCCLK
DRIVER
3 * RA
SD, MMC
SDIO OR
CARDS
Level
5 * RB
Vsdc2
EMIF
RC
3 * RA
Rs
Shifter
CMDOUT
MCCMD
MCDATA0
MCDATA[3:1]
MCFBCLK
Dz
Dz
DATAOUT0
DATAOUT[3:1]
LATCHCLK
Rev3
43/72
STw4810
5 Electrical and timing characteristics
5
Electrical and timing characteristics
Otherwise specified parameters are defined for T = 25°C. / VBAT = 3.6 V
5.1
Absolute maximum rating
Table 33.
Stw4810 absolute maximum ratings
Symbol
Description
Min.
Typ.
Max.
Units
Maximum power supply
-0.5
7
V
Ta
Maximum operating ambient temperature
-30
85
°C
Tj
Maximum junction temperature
-30
125
°C
0.92
W
Maximum power dissipation
ESD performance(1)
2
kV
1. : HBM Mil-Std-883 Method 3015
5.2
Package dissipation
Table 34.
Package dissipation
Symbol
Description
Min.
Typ.
Max.
Units
TFBGA 84 6x6x1.2mm 0.5mm ball pitch
RTHJ-A
Thermal resistance Junction to Ambient
70
°C/W
76
°C/W
VFBGA84 4.6x4.6x1.0mm 0.4mm ball pitch
RTHJ-A
Thermal resistance Junction to Ambient
5.3
Power supply
Note:
STw4810 has different ways to go in SLEEP mode.
The different possibilities for VCORE, VIO_VMEM and VAUX to be programmed to SLEEP
mode are given in Table 29 and Table 26.
Taking into account the bit programming of Table 29 and Table 26 related to SLEEP mode,
SLEEP mode is summarized with the following formula:
SLEEP = (Vxxx_SLEEP x PWREN) + (Vxxx_FORCE_SLEEP) = 1
(Vxxx = VCORE or VIO_VMEM or VAUX)
In all the following tables:
–
“Normal mode” is defined as “SLEEP = ‘0’”
–
“SLEEP mode” is defined as “SLEEP = ‘1’”
Use Table 26 to refer to each Vxxx supply (VCORE or VIO_VMEM or VAUX).
44/72
Rev3
STw4810
5.3.1
5 Electrical and timing characteristics
Operating conditions
Table 35.
Symbol
VBAT
IQSLEEP
Operating conditions (Temp range: -30 to +85 °C)
Description
Power supply
Min.
Typ.
2.7
Sleep mode
170
Max.
Units
5.5
V
250
µA
4
µA
Max.
Units
4.8
V
1.84
V
Quiescent Current
IQSTDBY
5.3.2
Test conditions
Off mode
VREF18
Table 36.
Symbol
VREF18
Description
Test conditions
Min.
Typ.
VBAT
Supply voltage
2.7
VREF_18
Output voltage
1.78
PSRR
Power supply
rejection ratio
Vpp = 0.3 V
f ≤100 kHz
60
dB
Noise
100 Hz ≤f ≤100 kHz
30
µV
tS
Settling time
1.8
7.77
Rev3
9.46
ms
45/72
STw4810
5 Electrical and timing characteristics
5.3.3
VCORE DC/DC step-down converter
Table 37.
Symbol
VCORE DC/DC step-down converter
Description
Test conditions
Min.
Typ.
Max.
Units
VCORE Regulator in Normal Mode (SLEEP = ‘0’) / Otherwise specified; VCORE = 1.2 V
VBAT
Input power supply
VRIPPLE
Output voltage
ripple
VOUT
46/72
Programmable
output voltage
Battery voltage
2.7
3.6
4.8
10
VCORE_SEL[3:0]
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100 (default)
0011
0010
0001
0000
-3.7%
-4.25%
-5%
1.50
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.15
1.10
1.05
1.00
V
mVpp
+3.7%
V
+4.25%
+5%
IOUT
Output current
PEFF
Power efficiency
VBAT = 3.6 V
IOUT = 200 mA
LIR
Line regulation
VBAT: [2.7; 4.8]V
10
mV
LDR(1)
Load regulation
IOUT: [0.1; 600] mA
10
mV
ISHORT
Short circuit current
limitation
1.2
1.4
A
IQ
Quiescent current
IOUT = 0 mA
130
250
µA
ILKG
Power-down
current
‘en_vcore’ = 0
1
µA
PSRR(1)
Power supply
rejection
Vpp = 0.3 V
[0; 20] kHz
LIRT
Transient line
regulation
∆VBAT = 300 mV
tR = tF = 10 µs
7
mV
LDRT
Transient load
regulation
IOUT = [1; 600] mA
tR = tF = 100 ns
70
mV
600
86
0.9
Rev3
40
mA
%
dB
STw4810
5 Electrical and timing characteristics
Table 37.
Symbol
VCORE DC/DC step-down converter
Description
Test conditions
Min.
Typ.
Max.
Units
2.7
3.6
4.8
V
VCORE Regulator in Sleep Mode (SLEEP= ‘1’)
VBAT
Input power supply
VRIPPLE
VCORE output
voltage ripple
LIR
Line regulation
VBAT: [2.7; 4.8]V
10
mV
LDR
Load regulation
IOUT: [0.1; 5] mA
10
mV
IOUT
VCORE output
current
5
mA
PEFF
Power efficiency
IQ
Quiescent current
LIRT
Transient line
regulation
Battery voltage
10
mVpp
VBAT= 3.6 V
IOUT: [0.1; 5] mA
85
IOUT = 0 mA
20
∆ VBAT= 300 mV
%
30
7
tR = tF = 10 µs
µA
mV
1. Guaranteed by design
5.3.4
VIO_VMEM DC/DC step-down converter
Table 38.
Symbol
VIO_VMEM DC/DC step-down converter
Description
Test conditions
Min.
Typ.
Max.
Units
2.7
3.6
4.8
V
-3%
1.8
+3%
V
VIO_VMEM Regulator in Normal Mode (SLEEP = ‘0’)
VBAT
Input power supply
VOUT
Output voltage (1)
VRIPPLE
Output ripple
LIR
Line regulation
VBAT: [2.7; 4.8]V
10
mV
LDR(2)
Load regulation
IOUT: [0.1; 600] mA
10
mV
IOUT
Output current
600
mA
PEFF
Power efficiency
Battery voltage
10
VBAT = 3.6 V,
VIO = 1.8 V
IOUT= 100 mA
ISHORT
Short circuit current
limitation
IQ
Quiescent current
IOUT = 0 mA
PSRR(2)
Power supply
rejection
Vpp = 0.3 V
[0; 20] kHz
LIRT
Transient line
regulation
∆VBAT = 300 mV
tR = tF = 10 µs
90
0.9
Rev3
mVpp
%
1.2
1.4
A
130
250
µA
40
dB
7
mV
47/72
STw4810
5 Electrical and timing characteristics
Table 38.
Symbol
LDRT
VIO_VMEM DC/DC step-down converter
Description
Transient load
regulation
Test conditions
Min.
IOUT= [1; 600] mA
tR = tF = 100 ns
Typ.
Max.
Units
70
mV
VIO_VMEM Regulator in Sleep Mode (SLEEP=’1’)
VBAT
Input power supply
VRIPPLE
Output ripple
LIR
Line regulation
VBAT: [2.7; 4.8]V
10
mV
LDR
Load regulation
IOUT: [0.1; 5] mA
10
mV
IOUT
Output current
5
mA
PEFF
Power efficiency
IQ
Quiescent current
IOUT = 0 mA
LIRT
Transient line
regulation
∆VBAT = 300 mV
tR = tF = 10 µs
Battery voltage
2.7
3.6
4.8
10
V
mVpp
VBAT = 3.6 V
IOUT = [0.1; 5] mA
85
%
15
7
1. Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy,
industrial manufacturing tolerances and ripple voltage due to switching
2. Guaranteed by design
48/72
Rev3
µA
mV
STw4810
5.3.5
5 Electrical and timing characteristics
LDO regulators
VPLL
Table 39.
Symbol
LDO regulators - VPLL
Description
Test conditions
Min.
Typ.
Max.
Units
4.8
V
+3%
V
3.5
10
mA
130
165
mA
30
40
µA
1
µA
VPLL Regulator in Normal Mode / Otherwise specified, VPLL = 1.8 V
VBAT
Input power supply
Battery voltage
2.7
VOUT
Output voltage
VPLL_SEL[1:0]
11 (default)
10
01
00
-3%
IOUT
Output current
ISHORT
Short-circuit
limitation
IQ
Quiescent current
IOUT = 0 mA
ILKG
Power-down
current
EN_VPLL = 0
PSRR(1)
Power supply
rejection
Vpp = 0.3 V
f < 10 kHz
10 kHz < f <100 kHz
LIR
Line regulation
VBAT: [2.7; 4.8]V
5
mV
LDR
Load regulation
IOUT: [0.1; 10] mA
10
mV
LIRT
Transient line
regulation
LDRT
Transient load
regulation
IOUT = [0.1; 10] mA
tR = tF = 1 µs
En(1)
Noise density
at 1 KHz
BW = 100 Hz
95
∆VBAT = 300 mV
tR = tF = 10 µs
3.6
1.8
1.3
1.2
1.05
55
45
dB
dB
1
mV
1
mV
nV
250
rms
-----------Hz
1. Guaranteed by design
Rev3
49/72
STw4810
5 Electrical and timing characteristics
VANA
Table 40.
Symbol
LDO regulators - VANA
Description
Test conditions
Min.
Typ.
Max.
Units
2.7
3.6
4.8
V
-5%
2.5
+5%
V
10
mA
64
mA
VANA regulator in normal mode
VBAT
Input power supply
VOUT
Output voltage
IOUT
Output current
ISHORT
Short-circuit
limitation
IQ
Quiescent current
IOUT = 0 mA
30
µA
ILKG
Power-down
current
EN_VANA = 0
1
µA
PSRR(1)
Power supply
rejection
Vpp = 0.3 V
f < 10 kHz
LIR
Line regulation
VBAT: [2.7; 4.8] V
5
mV
LDR
Load regulation
IOUT: [0.1; 10] mA
5
mV
LIRT
Transient line
regulation
LDRT
Transient load
regulation
Battery voltage
39
51
45
∆VBAT = 300 mV
tR = tF = 10 µs
IOUT = [0.1; 10] mA
tR = tF = 1 µs
dB
3
mV
15
mV
1. Guaranteed by design
VAUX
Table 41.
Symbol
LDO regulators - VAUX
Description
Test conditions
Min.
Typ.
Max.
Units
4.8
V
V
VAUX Regulator in Normal Mode (PDN_VAUX= 1, SLEEP= ‘0’)
VBAT
Input power supply
VOUT = 1.5V
1.7
VOUT = 1.8/2.5 V
2.7
3.6
4.8
3
3.6
4.8
-3%
1.5
1.8
2.5
2.8
+3%
VOUT = 2.8 V
50/72
VOUT
Output voltage
IOUT
Output current
ISHORT
Short-circuit
limitation
IQ
Quiescent current
VAUX_SEL[1:0]
00 (default)
01
10
11
500
IOUT = 0 mA
Rev3
700
V
150
mA
900
mA
30
µA
STw4810
5 Electrical and timing characteristics
Table 41.
Symbol
LDO regulators - VAUX
Description
Test conditions
Min.
Typ.
Max.
Units
1
µA
Power-down
current
PDN_VAUX = 0
PSRR
Power supply
rejection
VOUT=1.5 V
Vpp = 0.3 V
f < 10 kHz
LIR
Line regulation
VOUT=1.5 V
VBAT: [2.7; 4.8]V
5
mV
LDR(1)
Load regulation
VOUT=1.5 V
IOUT= [0.1; 150] mA
10
mV
LIRT
Transient line
regulation
∆VBAT = 300 mV
tR = tF = 10 µs
2
mV
LDRT
Transient load
regulation
IOUT = [10; 90%] mA
tR = tF = 1 µs
35
mV
tS
Settling time
100
µs
ILKG
(1)
32
dB
VAUX Regulator in Sleep Mode (PDN_VAUX= 1, SLEEP=’1’)
VBAT
Input power supply
VOUT = 1.5V
VIO_VMEM supply
1.7
VOUT = 1.8/2.5 V
2.7
VOUT = 2.8 V
VAUX_SEL[1:0]
00 (default)
01
10
11
4.8
V
3.6
4.8
V
3
3.6
4.8
-3%
1.5
1.8
2.5
2.8
+3%
VOUT
Output voltage
IOUT
Output current
IQ
Quiescent current
IOUT = 0 mA
PSRR(1)
Power supply
rejection
VOUT=1.5 V
Vpp = 0.3 V
f < 10 kHz
LIR
Line regulation
VOUT=1.5 V
VBAT: [2.7; 4.8]V
5
mV
LDR
Load regulation
VOUT=1.5 V
IOUT= [10; 90%] µA
10
mV
LIRT
Transient line
regulation
∆VBAT = 300 mV
tR = tF = 10 µs
2
mV
LDRT
Transient load
regulation
IOUT = [10; 90%] µA
tR = tF = 1 µs
35
mV
V
500
µA
15
µA
38
dB
1. Guaranteed by design
Rev3
51/72
STw4810
5 Electrical and timing characteristics
5.3.6
Power supply monitoring
This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM
drops below the threshold, the multimedia processor is reset.
Table 42.
Power supply monitoring
Symbol
Description
Test conditions
Min.
Typ.
Max.
Units
Threshold
THCORE(1)
Threshold VCORE
-3%
VCORE-150
+3%
mV
THVIO(1)
Threshold
VIO_VMEM
-3%
1.65
+3%
V
2.7
3.6
4.8
V
Comparators
VBAT
Supply voltage
tRES
Response time
100
ns
HYFALL
Hysteresis (input
voltage falling)
26
mV
HYRIS
Hysteresis (input
voltage rising)
+4
mV
1. Guaranteed by design
52/72
Rev3
STw4810
5 Electrical and timing characteristics
5.4
Digital specifications
5.4.1
CMOS input/output static characteristics: I2C interface
Table 43.
CMOS input/output static characteristics: I²C interface
Symbol
Description
Test conditions
Min.
Typ.
Max.
Units
0.3*VIO
V
I²C interface(1)
VIL
Low level input
voltage
VIH
High level input
voltage
0.7*VIO
IIL
Low level input
current
-1.0
1.0
µA
IIH
High level input
current
-1.0
1.0
µA
VOL
Low level output
voltage
IOL = 3mA
(with open drain or
open collector)
0.2*VIO
V
VOH
High level output
voltage
IOL = 3mA
(with open drain or
open collector)
V
0.8*VIO
V
1. Vio is for VIO_VMEM
5.4.2
CMOS input/output dynamic characteristics: I2C interface
Table 44.
CMOS input/output dynamic characteristics: I²C interface
Symbol
Description
Min.
Typ.
Max.
Units
400
Khz
I²C interface (Figure 8)
Fscl
Clock frequency
thigh
Clock pulse width high
600
ns
tlow
Clock pulse width low
1300
ns
tr
SDA, SCL, USBSDA, USBSCL rise time
20+0.1*Cb (1)
300
ns
tf
SDA, SCL, USBSDA, USBSCL fall time
20+0.1*Cb
300
ns
thd_sta
Start condition hold time
600
ns
tsu_sta
Start condition set up time
600
ns
thd_dat
Data input hold time
0
ns
tsu_dat
Data input set up time
250
ns
tsu_sto
Stop condition set up time
600
ns
tbuf
Bus free time
1300
ns
Cb
Capacitive load for each bus line
1.
400
pF
Cb = total capacitance of one bus line in pF
Rev3
53/72
STw4810
5 Electrical and timing characteristics
5.4.3
CMOS input/output static characteristics: VIO level
USB and control I/Os
Table 45.
Symbol
VIO level: USB and control I/Os
Description
Test conditions
Min.
Typ.
Max.
Units
SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN,
USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK
VIL(1)
Low level input
voltage
VIH
High level input
voltage
0.7*Vio
IIL
Low level input
current
-1.0
1.5
µA
IIH
High level input
current
-1.0
1.5
µA
CIN
Input capacitance
10
pF
VOL
Low level output
voltage
IOL = TBD
0.2*Vio
V
VOH
High level output
voltage
IOL = TBD
tOF
Output fall time
Capacitance 10pF
TBD
ns
tOR
Output rise time
Capacitance 10pF
TBD
ns
CI/O
Driving capability
100
pF
0.3*Vio
1. Vio for VIO_VMEM
54/72
Rev3
V
V
0.8*Vio
V
STw4810
5 Electrical and timing characteristics
MMC Interface
Table 46.
Symbol
VIO level: MMC interface
Description
Test conditions
Min.
Typ.
Max.
Units
MMC Interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR,
MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1
VIL(1)
Low level input
voltage
VIH
High level input
voltage
0.7*Vio
IIL
Low level input
current
-1.0
1.5
µA
IIH
High level input
current
-1.0
1.5
µA
CIN
Input capacitance
10
pF
VOL
Low level output
voltage
IOL = TBD
0.2*Vio
V
VOH
High level output
voltage
IOL = TBD
CI/O
Driving capability at
52 MHz
0.3*Vio
V
V
0.8*Vio
V
30
pF
1. Vio for VIO_VMEM
Rev3
55/72
STw4810
5 Electrical and timing characteristics
5.4.4
CMOS input/output static characteristics: VBAT level
Table 47.
Symbol
CMOS input/output static characteristics: VBAT level
Description
Test conditions
Min.
Typ.
Max.
Units
0.3*Vbat
V
IT_WAKE_UP, PON, GPO1, GPO2
56/72
VIL
Low level input
voltage
PON
VIH
High level input
voltage
PON
0.7*Vbat
IIL
Low level input
current
PON
-1.0
1.5
µA
IIH
High level input
current
PON
-1.0
1.5
µA
CIN
Input capacitance
10
pF
VOL
Low level output
voltage
IT_WAKE_UP,
GPO1, GPO2
IOL = TBD
0.2*Vbat
V
VOH
High level output
voltage
IT_WAKE_UP,
GPO1, GPO2
IOL = TBD
tOF
Output fall time
Capacitance 10pF
TBD
ns
tOR
Output rise time
Capacitance 10pF
TBD
ns
CI/O
Driving capability
100
pF
Rev3
V
0.8*Vbat
V
STw4810
5.4.5
5 Electrical and timing characteristics
CMOS input/output static characteristics: VMMC level
Table 48.
Symbol
CMOS input/output static characteristics VMMC level
Description
Test conditions
Min.
Typ.
Max.
Units
DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT
VIL
Low level input
voltage
VIH
High level input
voltage
0.7*VMMC
IIL
Low level input
current
-1.0
1.5
µA
IIH
High level input
current
-1.0
1.5
µA
CIN
Input capacitance
10
pF
VOL
Low level output
voltage
IOL = TBD
VOH
High level output
voltage
IOL = TBD
CI/O
Driving capability
0.3*VMMC
0.2*VMMC
0.8*VMMC
40
Rev3
pF
57/72
STw4810
5 Electrical and timing characteristics
5.5
USB OTG transceiver
Table 49.
Symbol
USB OTG transceiver
Description
Test conditions
Min.
Typ.
Max.
Units
UART Mode
tR
Rise time
CLOAD= [50;100] pF
[10; 90] % of
VOH-VOL
100
ns
tF
Fall time
CLOAD= [50;100] pF
10......90% of
VOH-VOL
100
ns
tPLH
Drive propagation
delay low => high
CLOAD= [50;100] pF
50% of |VOH-VOL|
100
ns
tPHL
Drive propagation
delay high => low
CLOAD= [50;100] pF
50% of |VOH-VOL|
100
ns
USB Full Speed Mode (DP & DN signals)
tR
Rise time
4
20
ns
tF
Fall time
4
20
ns
DRFM
Differential rise an
fall time matching
90
111
%
OSCV
Output signal
crossover voltage
1.3
2
V
PDEL
Propagation delay
18
ns
USBVP & USBVM :
- Trise & Tfall < 1 ns
- Skew < 0.66 ns
USB Low Speed Mode (DP & DN signals)
tR
Rise time
75
300
ns
tF
Fall time
75
300
ns
DRFM
Differential rise an
fall time matching
80
125
%
OSCV
Output signal
crossover voltage
1.3
2
V
4.8
V
VBUS Comparators
VBAT
Input power supply
tRR
Rising reacting time
1.7
µs
tFR
Fall reacting time
2.1
µs
Battery voltage
3.1
3.6
Threshold VBUS Monitoring
VBval
VBses
58/72
VBUS valid
4.4
VBUS session valid
1.8
Rev3
4.5
4.6
V
2
V
STw4810
5 Electrical and timing characteristics
Table 49.
Symbol
USB OTG transceiver
Description
Test conditions
Min.
Typ.
Max.
Units
100
KΩ
100
ms
VBUS
RA_BUS_
40
IN
VBUS = [0; 4.4] V
ILOAD = 100mA
External cap 10µF
TA_VBUS_
RISE
Data Line Pull-down Resistance
RPD_DPDN
14
19
25
KΩ
Data Line Pull-up Resistance
RPU_DP
Bus idle
Bus driven
900
1425
1200
2300
1600
3100
Ω
RPU_DN
Bus idle
Bus driven
900
1425
1200
2300
1600
3100
Ω
650
925
1200
Ω
420
600
780
Ω
PULL-DOWN on VBUS
RVBUS_PD
PULL-UP on VBUS
RVBUS_SRP
ID
VID_GND
ID_GND
comparator
threshold
VID_HI
(VBAT)
Battery level
VID_FLOAT
ID_FLOAT
comparator
threshold
2.7 V < VBAT < 4.8 V
0.15*VBAT
2.7
3.6
V
4.8
0.85*VBAT
RPU_ID
70
RPD_ID
Rev3
100
V
V
130
KΩ
10
KΩ
59/72
STw4810
5 Electrical and timing characteristics
Table 49.
USB OTG transceiver
Symbol
Description
Test conditions
Min.
Typ.
Max.
Units
Carkit Threshold Detection
Carkit interrupt
threshold
0.4
0.6
V
VOH_TXD_
DAT
TXD output high on
ISOURCE = 500 µA
DN
2.4
3.6
V
VOL_TXD_
DAT
TXD output low on
DN
0.4
V
VIH_RXD
RXD input high on
DP
cR_INT
Transceiver
_DAT
VIL_RXD_
DAT
ISINK = 2mA
2
V
RXD input low on
DP
0.8
V
Charge Pump
VBAT
Input power supply
Battery voltage
VBUS
Output voltage
Current load up to
100 mA
tS
Settling time
[0;4.8] V)
Ext. load: 100 mA +
External cap = 10µF
1.2
ms
IQ
Quiescent current
No Load
2.7
mA
VRipple
Amplitude output
ripple on VBUS
Current load 8 mA
Current load 100mA
25
40
mV
mV
IOUT
Output current
Eff
Efficiency
VUSB+0.1
3.6
4.8
V
4.75
5
5.25
V
100
mA
VBAT = 3.0V
IOUT =100mA
85
%
VBAT= 3.6V.
IOUT = 8 mA.
60
%
VUSB regulator
60/72
VBAT(1)
Input voltage
Battery voltage:
VBAT min =
VOUT + 0.1V
VOUT
Output voltage
VBAT min=
VOUT + 0.1V
ISHORT
Short circuit current
limitation
IQ
Quiescent current
No load
PSRR(2)
Power supply
rejection
VBAT= VOUT+0.2V
f < 20 kHz
Rev3
VUSB+0.1
3.6
5.5
V
3.0
3.1
3.2
V
320
mA
70
µA
45
dB
STw4810
5 Electrical and timing characteristics
Table 49.
Symbol
USB OTG transceiver
Description
Test conditions
NVOUT
Output noise
voltage
VBAT= VOUT+0.2V
10Hz <f< 100kHz
LIRT
Transient line
regulation
tS
tD
Min.
Typ.
Max.
Units
100
µVrms
∆VBAT = 300 mV
tR = tF = 10µs.
5
mV
Settling time
OFF->ON
IOUT = 0mA
25
µs
Discharge time
ON>OFF
IOUT = 0mA
400
µs
1. From 4.8 V to 5.5 V, charge pump is “Off” and no OTG feature is provided
2. Guaranteed by design
Rev3
61/72
STw4810
5 Electrical and timing characteristics
5.6
SD/MMC card interface
Table 50.
Symbol
SD/MMC card interface
Description
Test conditions
Min.
Typ.
Max.
Units
3.25
3.1
2.7
3.6
4.8
V
-3%
3
2.85
1.8
+3%
V
150
mA
600
mA
VMMC regulator specifications (PDN_VMMC = 1)
VOUT = 3 V
VOUT = 2.85 V
VOUT = 1.8 V
VBAT
Input voltage
VOUT
Output voltage
IOUT
Output current
ISHORT
Short circuit current
limitation
IQ
Quiescent current
IOUT = 0 mA
30
µA
ILKG
Power-down
current
PDN_VMMC = 0
1
µA
PSRR(1)
Power supply
rejection
LIR(1)
Line regulation
VOUT=2.85 V
VBAT: [3.1; 4.8]V
5
mV
LDR(1)
Load regulation
VOUT=2.85 V
IOUT= [1; 150] mA
10
mV
LIRT
Transient line
regulation
VOUT=2.85 V
VBAT: 3.1 to 3.4V
tR = tF = 10 µs.
2
mV
LDRT
Transient load
regulation
IOUT = [1; 150] mA
tR = tF = 1 µs
25
mV
tS
Settling time
OFF->ON
IOUT = 0 mA
100
µs
tD
Discharge time
ON>OFF
IOUT = 0 mA
1
ms
240
360
IOUT = 150 mA
Vpp = 0.3 V
f < 20 kHz
45
dB
Bus line specifications
62/72
RA(2)
Pull-up resistor
To prevent bus
floating
1.5
MΩ
RB
Pull-down resistor
To prevent bus
floating
1.5
MΩ
fDT
Clock frequency
With CL = 30pF
data transfert mode
52
MHz
fID
Clock frequency
identification mode
400
KHz
With CL = 30pF
Rev3
STw4810
5 Electrical and timing characteristics
Table 50.
Symbol
SD/MMC card interface
Description
Test conditions
Min.
Typ.
Max.
Units
TPHC
Propagation time
from Host to card
Figure 14
7
ns
TPCH
Propagation time
from card to host
Figure 14
7
ns
TSHC
Clock /data skew
time from host to
card
Figure 14
Reference is
CLKOUT
+/- 0.5
ns
TSCH
Clock /data skew
time from card to
host
Figure 14
Reference is
MMCLK
+/- 0.5
ns
TR
Rise time
3
ns
TF
Fall time
3
ns
C1LINE
Between
multimedia
processor &
STw4810
Bus line
capacitance
f < 52 Mhz
20(3)
pF
C2LINE
Between STw4810
& MMC card
Bus line
capacitance
f < 52 MHz
20 + 20(4)
pF
1. Guaranteed by design
2. MMC interface pull up resistors are in EMIF06-HCM01F2 device (7 KΩ for CMD; 75 KΩ for Data wires)
3. 20 pF for equivalent board parasitic capacitance.
4. 20 pF for EMIF06 protection + 20 pF for board parasitic capacitance.
Figure 14. Propagation and clock/data skew times
2 ns
2 ns
2 ns
MCCLK
MCCMD
MCDATA[3:0]
MCFBCLK
90%
90%
50%
10%
10%
TPHC
CLKOUT
MCCLK 10%
50%
DATAOUT[3:0]
MCDATA[3:0]
t
TPHC
2 ns
2 ns
MCCLK
MCCMD
MCDATA[3:0]
MCFBCLK
50%
t
CLKOUT
CMDOUT
DATAOUT[3:0]
LATCHCLK
CLKOUT
CMDOUT
DATAOUT[3:0]
LATCHCLK
TSHC
90%
2 ns
90%
10%
90%
50%
TSCH
90%
50%
10%
TPCH
t
CLKOUT 10%
MCCLK
50%
DATAOUT[3:0]
TPCH
MCDATA[3:0]
t
Rev3
63/72
STw4810
6 Application information
6
Application information
6.1
Components list
Table 51.
Name
Components list
Typical
value
Comments
Function
VIO_VMEM output filter
C1
22µF
C4
VCORE output filter
C2
VBAT_VIOVMEM decoupling
C3
10µF
C5
C6
C7
C8
1µF
C10
C13
VBAT_ANA decoupling
In the complete system application, the
sum of the capacitors connected on each
STw4810 ball must never be less than
30% of the value indicated in the typical
value column of this table. This includes
all capacitor parameters:
– production dispersion
– DC bias voltage applied
– temperature range of the complete
system application
– aging
VPLL output filter
VANA output filter
VREF output filter
VUSB output filter
VAUX output filter
C9
470nF
C11
4.7µF
C12
2.2µF
VSD_MMC output filter
C13, C14,
C15, C16,
C17
1 µF
Vbattery input voltage decoupling
capacitors
L1
Flying capacitor for charge pump
VBUS output filter (tank charge
pump capacitor)
Coil VIOVMEM DC/DC
4.7µH
See Table 52. for recommended coils
L2
Coil VCORE DC/DC
Table 52.
Supplier
TDK
Coilcraft
List of 4.7 µH coils
DCR (Ω)
Irms(1) (A)
L x l x h (mm * mm * mm)
VLF3010AT-4R7MR70
0.28
0.7
2.8 * 2.6 * 1.0
VLF3012AT-4R7MR74
0.16
0.74
2.8 * 2.6 * 1.2
VLF4012AT-4R7M1R1
0.14
1.1
3.7 * 3.5 * 1.2
DO1605T-472MX
0.15
1.1
5.5 * 4.2 * 1.8
DO3314-472ML
0.32
1.1
3.3 * 3.3 * 1.4
ME3320-472MX
0.19
1.1
3.2 * 2.5 * 2.0
Part Number
1. Irms: 30% decrease of initial value
64/72
VBAT_VCORE decoupling
Rev3
STw4810
Table 53.
6 Application information
Other ST components
Name
Order code
Function
EMIF02
EMIF02USB05
USB ESD/EMI Protection
EMIF06
EMIF06-HMC01F2
MMC Interface ESD/EMI Protection
Rev3
65/72
STw4810
6 Application information
6.2
Application schematics
Figure 15. STw4810 application schematics
C4
VLX_VCORE
VBAT_VCORE
VMINUS_ANA
VBAT_ANA
PON
CLK32Kin
MASTER_CLK
VIOVMEM_FB
VMINUS_DIG
VLX_VIOVMEM
VMINUS_VIOVMEM
VBAT_DIG
VBAT_VIOVMEM
MODEM & SYSTEM CLOCK
C13(*)
L2
C5
C3
VCORE
L1
C2
VMINUS_VCORE
C1
C14(*)
VBAT_VPLL_VANA
C6
IT_WAKE_UP
VPLL
REQUEST_MC
TCXO_EN
C7
VANA
C8
B9
VREF
C15(*)
VBAT_VAUX
D3
C13
VAUX
C16(*)
VBAT_USB
PWREN
VDDOK
PORn
CLK32K
SW_RESETn
CN
STw4810
Multimedia processor
SDA
C10
VUSB
C11
VBUS
USBVP
USBOEn
USBVM
USBRCV
ID
ESD
USBINTn
DP
USBSCL
DN
USBSDA
R1
R1
EMI
filter
MCCLK
MCFBCLK
VBAT_MMC
MCCMDDIR
MCCMD
3
C9
CP
EMIF02
C17(*)
C12
VMMC
MCDAT0DIR
MCDAT0
MCDAT31DIR
MCDAT[3,1]
DATOUT[3:1]
DATAOUT0
CMDOUT
MCDAT2DIR
MCDAT2
SD
MMC
3
EMI
Filter
CLKOUT
LATCHCLK
EMIF06-HMC01F2
GPO1
GPO2
(*) The usefulness of these capacitors depend of PCB layout
66/72
USB
SCL
VMINUS_USB
Rev3
SDIO
CARD
STw4810
7 Package mechanical data
7
Package mechanical data
7.1
TFBGA 84 balls
See Figure 16: TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing.
Table 54.
TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing dimensions(1)
Drawing dimensions (mm)
Min.
Typ.
A
A1
Max.
1.16
0.20
A2
0.25
0.30
0.82
b
0.25
0.30
0.35
D
5.90
6.00
6.10
D1
E
4.50
5.90
E1
6.00
6.10
4.50
e
0.45
0.50
0.55
f
0.65
0.75
0.85
ddd
0.08
1. These measurements conform to JEDEC standards
Rev3
67/72
STw4810
7 Package mechanical data
Figure 16. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing
Note:
68/72
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or
metallized markings, or other feature of package body or integral heatslug. A distinguishing
feature is allowable on the bottom surface of the package to identify the terminal A1 corner.
Exact shape of each corner is optional.
Rev3
STw4810
7.2
7 Package mechanical data
VFBGA 84 balls
See Figure 17: VFBGA 84 balls 4.6x4.6x1.0 mm body size / mm ball pitch drawing.
Table 55.
VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch(1)
Drawing dimensions (mm)
Min.
Typ.
A
A1
Max.
0.864
0.15
0.19
A2
0.615
A3
0.18
A4
0.435
0.23
b
0.21
0.25
0.29
D
4.55
4.60
4.65
D1
E
3.60
4.55
4.60
E1
3.60
e
0.40
f
0.50
4.65
ddd
0.08
eee
0.13
fff
0.04
1. These measurements conform to JEDEC standards
Rev3
69/72
STw4810
7 Package mechanical data
Figure 17. VFBGA 84 balls 4.6x4.6x1.0 mm body size / mm ball pitch drawing
Note:
70/72
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or
metallized markings, or other feature of package body or integral heatslug. A distinguishing
feature is allowable on the bottom surface of the package to identify the terminal A1 corner.
Exact shape of each corner is optional.
Rev3
STw4810
8
8 Revision history
Revision history
Date
Revision
Changes
24-Jan-06
1
Initial release.
7-Feb-06
2
Modified document title.
Reviewed list of applications on cover page.
Replaced APE with multimedia processor.
Replaced fuse with analogue function.
Renamed VFUSE as VANA.
Modified figure 6 - Control interface - I2C format
9-Feb-06
3
Correction of Figure 13: SD MMC block diagram.
Correction of Figure 15: STw4810 application schematics.
Rev3
71/72
STw4810
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Rev3