73M2901CL V.22bis Single Chip Modem ® TDK SEMICONDUCTOR CORP. May 2002 DESCRIPTION FEATURES The 73M2901CL is a single-chip modem that combines all the controller (DTE) and data pump functions necessary to implement an intelligent V.22bis data modem. • • It is adequately suited for embedded applications where a data return channel is needed through the telephone network such as Set top Box, Point of Sale Terminal, Automatic Teller machine, Hand Held Communication Device and Smart Card Reader. This device is based on TDK Semiconductor’s implementation of the industry standard 8032 microcontroller core with a proprietary Multiply/ ACcumulate (MAC) coprocessor; Sigma-Delta A/D and D/A converters (CODEC); and an analog DAA drivers. The ROM and RAM necessary to operate the modem are contained on the device. Additionally, the 73M2901CL provides an on-chip oscillator and hybrid. • • • • • • • • • • BLOCK DIAGRAM True one chip solution for embedded systems Low power As low as 9.5mA operating with standby and power down mode available Power supply operation from 3.6V to 2.7V Data speed: V.22bis – 2400bps V.22/Bell212 – 1200bps V.21/Bell103 – 300bps V.23 – 1200/75bps (with PAVI turnaround) Bell202 – 1200bps Bell202/V23 4-wire operations International Call Progress support FCC68, CTR21, JATE, etc. Worldwide Caller ID capability Type I and II support EIA 716 compliant DTMF generation and detection On chip hybrid driver Blacklisting capability Line-In-Use and Parallel Pick-Up (911) detection capability Manufacturing Self Test capability Packaging: 32 pin PLCC / 32 pin TQFP / 44 pin LQFP 73M2901CL V.22bis Single Chip Modem but no clocks will be supplied to the CPU. Instruction processing and activity on the internal busses is halted. Normal operation is resumed when an interruption such as assertion of '75 or 5,1*, a character is sent to the 73M2901CL TXD input, or a reset occurs. HARDWARE DESCRIPTION The 73M2901CL is designed to operate from a +3.6 to +2.7 volt supply with low power consumption (~30mW @ 3.0 volts). The modem supports automatic standby idle mode. The modem will also accept a request to power down from the DTE via hardware control. No additional major components are required to complete the modem core logic. The modem provides direct firmware LED support via port pins. ANALOG LINE / HYBRID INTERFACE The 73M2901CL provides a differential analog output (TXAP and TXAN) and a single-ended analog input (RXA) with internal A/D and D/A converters. A driver is provided for an internal hybrid function. HARDWARE FEATURES • Fully self-contained. “AT” Command interpreter and data pump • User pins available • Synchronous serial data I/O available • Asynchronous serial port • On-chip hybrid and line driver. • Autobaud capability from 300bps to 9600bps The internal hybrid driver is capable of driving an external load matching impedance and a linecoupling transformer. The internal hybrid/line driver senses the load and adapts itself to its requirements. The 73M2901CL provides firmware control for a hook relay driver (5(/$<) as well as interrupt support for a ring detect opto-coupler (5,1*). INTERRUPT PINS POWER SUPPLY The external interrupt sources, '75 and 5,1*, come from dedicated input pins of the same name. Power is supplied to the 73M2901CL via the VPD and VPA pins. The 73M2901CL is designed for a single +3.6 to +2.7 volt supply and for low power consumption (~30mW @ 3.0 volts). Ground is supplied to the 73M2901CL via VND and VNA pins. DTR informs the 73M2901CL that the host has requested the 73M2901CL perform a specific function. The function of '75 can be changed by “AT” commands (described in full in the TDK 73M2901CL User’s Guide). The 73M2901CL has been designed with separated analog and digital supplies to insure the best performance of the part by using different filtered power supplies. It is recommended that separate locally bypassed traces be used to apply power to the analog supply VPA and the digital supply VPD. RING is used to inform the 73M2901CL that the external DAA circuitry has detected a ring signal. In addition, sending any character on the TXD line also generates an internal interrupt. CRYSTAL OSCILLATOR The TDK 73M2901CL single chip modem can use an external 11.0592 MHz reference clock or can generate a clock using only a crystal and two capacitors. If an external clock is used, it should be applied to OSCIN. LOW POWER MODE The TDK 73M2901CL supports a low power standby mode. If the low power standby option is enabled the 73M2901CL will go into a power saving mode when idle. The oscillator will be running, clocks will be supplied to the UART, timers and interrupt blocks; 2 73M2901CL V.22bis Single Chip Modem SPECIFYING A CRYSTAL Crystals with low ESRs may oscillate at higher than specified voltage levels. The manufacturer of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure that the same frequency is obtained in the application, the circuit conditions must be the same. The TDK 73M2901CL modem requires a parallel mode (anti-resonant) crystal, the important specifications of which are as follows: Mode: RESET A reset is accomplished by holding the RESET pin high. To ensure a proper power-on reset, the reset pin must be held high for a minimum of 3µs. At power on, the voltage at VPD, VPA, and RESET must come up at the same time for a proper reset. The signals '&', &76 and '65 will be held inactive for 25ms, acknowledging the reset operation, within a 250ms time window after the reset-triggering event. The 73M2901CL is ready for operation after that 250ms window and/or after the signals '&', &76 and '65 become active. Parallel (anti-resonant) Frequency: 11.0592 MHz Frequency tolerance: ±50 ppm at initial temperature. Temperature drift: An additional ±50 ppm over full range. Load capacitance: ASYNCHRONOUS AND SYNCHRONOUS SERIAL DATA INTERFACE 18pF or 20pF ESR: 75Ω max. Drive level: The serial data interface consists of the TXD and RXD data paths (LSB shifted in and out first, respectively); and the TXCLK and RXCLK serial clock outputs associated with the data pins; &76/576 flow control; '&', '65 and '75. In synchronous mode, the data is passed at the bit rate (tolerance is +1%, -2.5%). Less than 1mW. The peak voltage level of the oscillator should be checked to assure it will not violate the maximum voltage levels allowed on the oscillator pins. A resistor in series with the crystal can be used, if necessary, to reduce the oscillator’s peak voltage levels. PIN DESCRIPTIONS POWER PIN DESCRIPTION PIN NAME 32 pin PLCC 32 pin TQFP 44 pin LQFP TYPE DESCRIPTION VPA 15 10 16 I Positive analog voltage (Analog supply) VNA 21 16 22 I Negative analog voltage (Analog ground) VPD 6, 25, 29 2, 20, 25 2, 12, 27, 33 I Positive digital voltage (Digital supply) VND 5, 22, 26 1, 17, 22 11, 24, 44, 28 I Negative digital voltage (Digital ground) ANALOG INTERFACE PIN DESCRIPTION PIN NAME 32 pin PLCC 32 pin TQFP 44 pin LQFP TYPE RXA 20 15 21 I Receive Analog input TXAN 16 11 17 O Transmit Analog - output TXAP 17 12 18 O Transmit Analog + output VBG 19 14 20 O Analog Band Gap voltage reference (0.1µF to VNA). This pin must not be connected to external circuitry other than the decoupling capacitor. VREF 18 13 19 O Analog reference voltage (0.1µF to VNA) 3 DESCRIPTION 73M2901CL V.22bis Single Chip Modem DIGITAL INTERFACE PIN DESCRIPTION PIN NAME 32 pin PLCC 32 pin TQFP 44 pin LQFP TYPE RESET 13 9 9 I Reset RXCLK 31 27 36 O Receive data synchronous clock TXCLK 28 24 31 O Transmit data synchronous clock TXD 27 23 30 I Serial data input from DTE RXD 30 26 35 O Serial output to DTE USR10 12 8 8 I/O Programmable I/O port. This pin optionally be used to control an external switch for external Line In Use circuitry. USR11 11 7 7 I/O Programmable I/O port. This pin can optionally be used to control an external switch for caller ID operation. 576 10 6 6 I Request to send &76 9 5 5 O Clear to send '65 8 4 4 O Data set ready '&' 7 3 3 O Data carrier detect 5, 4 32 43 O Ring indicator 5(/$< 3 31 40 O Relay driver output USR20 1 29 38 I/O Programmable I/O port DESCRIPTION EXTERNAL INTERRUPTS PIN DESCRIPTION PIN NAME 32 pin PLCC 32 pin TQFP 44 pin LQFP TYPE 5,1* 2 30 39 I External interrupt – Line interface ring detection circuitry input '75 32 28 37 I External interrupt – DTE DTR signal input DESCRIPTION OSCILLATOR PIN DESCRIPTION PIN NAME 32 pin PLCC 32 pin TQFP 44 pin LQFP TYPE OSCIN 24 19 26 I Crystal input for internal oscillator, also input for external source OSCOUT 23 18 25 O Crystal oscillator output 4 DESCRIPTION 73M2901CL V.22bis Single Chip Modem ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER RATING Supply Voltage -0.5V to +4.0V Pin Input Voltage (except OSCIN) -0.5V to + 6.0V Pin Input Voltage (OSCIN) -0.5V to VPD + 0.5V Storage Temperature -55ºC to 150ºC NOTE: This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum conditions for extended periods of time may affect reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER RATING Supply Voltage 2.7V – 3.6V Oscillator Frequency 11.0592MHz +/- 50ppm Operating Temperature -40ºC to 85ºC RECEIVER PARAMETER CONDITIONS MIN Carrier detect On Tip and Ring -43 dBm0 Carrier detect Off Tip and Ring -48 dBm0 Carrier Detect Hysteresis Tip and Ring Receive Level Tip and Ring Idle channel noise 0.2KHz – 4.0KHz Input impedance RXA 150 Receive Gain Boost SFR 96.2h = 1 18.8 19.3 19.8 dB Max Input Level at RxA Vref=1.25V 0.587 0.622 0.658 Vpk Total Harmonic Distortion (THD) 1KHz 450mVpk on RXA -70 -50 dB * THD=2 nd NOM MAX UNIT * * 2 -43 -70 dB * -9 dBm0 -65 dB kΩ rd and 3 harmonic dBm0 refers to the TDK recommended line interface (8dB loss from transmit pins to the line and 5dB loss from the line to the receiver pin). Results may vary depending on the selected DAA components. 0dBm=0.775mVrms; dBm=10log(Vrms2/(1mW)(600Ω)) 5 73M2901CL V.22bis Single Chip Modem TRANSMITTER PARAMETER ITU Guard tone power Calling Tone Answer Tone power DTMF Transmit power Gain adjust tolerance Total Harmonic Distortion (THD) Intermod Distortion Power supply rejection ratio CONDITIONS 550Hz (relative to carrier) 1800Hz (relative to carrier) 1300Hz 2225Hz/2100Hz High band tones Low band tones By step 1KHz sine wave at output (TXAP-TXAN) 1.5Vpk(2.7dBm) for Vref=1.25V nd rd THD=2 and 3 harmonic At output (TXAP-TXAN) 1KHz, 1.2KHz sine waves summed 2Vpk for Vref=1.25V MIN NOM MAX UNIT -5 -3.5 -2 dB -8 -6.5 -5 dB -11 -11 -12 -13.7 -0.3 -10 -10 -11.5 -13.2 0 -9 -9 -11 -12.7 0.3 dBm0 * dBm0 * dBm0 * dBm0 * dBm0 -50 dB -33 dBm -20 dB below low tone 30 dB MAX UNIT -9.6 dBm0 -7.4 dBm0 -5.3 dBm0 -8 -7 dBm0 -9.7 -8.7 dBm0 Each unwanted frequency component Sum of unwanted frequency components in pass band -30dBm signal at VPA 300Hz-30KHz. Measured TXAP to TXAN * MAXIMUM TRANSMIT LEVEL PARAMETER CONDITIONS QAM Vref=1.25V MIN NOM * VPA=3.3V DPSK Vref=1.25V * VPA=3.3V FSK Vref=1.25V * VPA=3.3V DTMF (HIGH TONE) Vref=1.25V S13=$20, VPA=3.3V DTMF (LOW TONE) * S85=80 Vref=1.25V S13=$20, VPA=3.3V * * S85=80 dBm0 refers to the TDK recommended line interface (8.5dB loss from transmit pins to the line and 3.5dB loss from the line to the receiver pin). Results may vary depending on the selected DAA components. 0dBm=0.775mvrms; dBm=20log(Vrms/(0.775mvrms) 6 73M2901CL V.22bis Single Chip Modem DC CHARACTERISTICS VCC=3.3V (Vdd stands for VPD and VPA) PARAMETER SYMBOL Input low voltage (except OSCIN) VIL Input low voltage OSCIN CONDITIONS MIN NOM MAX UNIT -0.5 0.8 V VIL -0.5 0.2Vdd V Input high voltage (except OSCIN) VIH 0.7Vdd +5.5 V Input high voltage OSCIN VIH 0.7Vdd Vdd+0.5 V Output low voltage (except OSCOUT) VOL IOL=4mA 0.45 V Output low voltage OSCOUT VOLOSC IOL=3mA 0.7 V Output high voltage (except OSCOUT) VOH IOH=-4mA Vdd-0.45 V Output high voltage OSCOUT VOHOSC IOH=-3mA Vdd-0.9 V Input leakage current (except OSCIN) IIH Vss<Vin<Vdd Input leakage current OSCIN IIH Vss<Vin<Vdd 1 1 µA 30 µA PARAMETER CONDITIONS MIN NOM MAX UNIT VBG Vdd=3.3V 1.19 1.25 1.31 V VREF Vdd=3.3V 1.19 1.25 1.31 V TXAP to TXAN offset Vdd=3.3V, steady state 50 mV NOM MAX UNIT DC SUPPLY CURRENT VDD = 2.7V (BATTERY EOL) PARAMETER SYMBOL CONDITIONS Maximum Power supply, normal operation IDD1 30pF/pin 9.5 10.5 mA IDD2 30pF/pin 900 1500 µA IDD3 30pF/pin 10 µA PARAMETER SYMBOL CONDITIONS NOM MAX UNIT Maximum Power supply, normal operation IDD1 30pF/pin 10.6 11.9 mA IDD2 30pF/pin 1.1 1.7 mA IDD3 30pF/pin 10 µA Maximum power supply Idle mode Maximum power supply Power down mode MIN DC SUPPLY CURRENT VDD = 3.0V Maximum power supply Idle mode Maximum power supply Power down mode 7 MIN 73M2901CL V.22bis Single Chip Modem DC SUPPLY CURRENT VDD = 3.3V PARAMETER SYMBOL CONDITIONS Maximum Power supply, normal operation IDD1 NOM MAX UNIT 30pF/pin 11.8 13.6 mA IDD2 30pF/pin 1.25 1.85 mA IDD3 30pF/pin 10 µA PARAMETER SYMBOL CONDITIONS NOM MAX UNIT Maximum Power supply, normal operation IDD1 30pF/pin 13.4 15.5 mA IDD2 30pF/pin 1.4 2.0 mA IDD3 30pF/pin 10 µA Maximum power supply Idle mode Maximum power supply Power down mode MIN DC SUPPLY CURRENT VDD = 3.6V Maximum power supply Idle mode Maximum power supply Power down mode 8 MIN 73M2901CL V.22bis Single Chip Modem FIRMWARE DESCRIPTION* FIRMWARE FEATURES An “AT” command interpreter provides command and configuration of the 73M2901CL. This provides the user a uniform interface to control the modem in embedded applications. • “AT” command set • Supports data standards through V.22bis • Provides DAA control firmware (e.g. ring detect, hook control) • Multinational Call progress support (FCC68, CTR21, JATE, etc.) • Caller ID capability The signal processing is performed to provide data to the DAC and process data from the A/D converter. A MAC hardware coprocessor is provided for computation. To provide maximum flexibility, the system host processor can access the internal RAM and Control Register space in the modem. This will allow the OEM user to modify parameters such as filter response, transmit levels through the AT command set using proprietary commands. The host processor can also access the modem I/O port pins, providing extended I/O capability. • FIRMWARE REQUIREMENTS The modem always powers up in the idle (on hook) mode. “AT” commands are issued via the serial interface from the host. All modem configuration commands are received in this manner. The data modem firmware is contained in an internal ROM. The firmware will automatically enter a power saving idle mode if the modem is on hook and there are no incoming host commands. The modem automatically powers up upon receiving the next command. This power up sequence occurs without delay to the host. This function, while saving power, is transparent to the host processor and can be disabled by the host via an “AT” command. The host can also program the modem to power down via external pin (DTR) or via a firmware command. FSK demodulation (V23 or Bell202) o DTMF demodulation o Intra 1st/2nd ring CID data operation o Post Line operation reversal CID data On hook Line-In-Use detection support (No line seizure will occur when a Line-In-Use condition is detected) o Tip/Ring voltage sensing o Quiescent line validation • Off hook Parallel Pick-Up detection support (Line seizure will be aborted as soon as a Parallel Pick-Up condition is detected) • Directly interfaces with standard V.24/EIA-232 bus drivers (3.3V inverted level) serial interface using the built in serial port and firmware control of port pins • Provides tone generation and detection including four imprecise and four precise call progress detect filters with programmable frequency and detection threshold • Blacklisting capability • Long Space disconnect • Inactivity timeout • Host access to program RAM provided • User programmable general purpose I/O * Refer to the TDK 73M2901CL User Guide for a complete description of the software. 9 o 73M2901CL V.22bis Single Chip Modem 73M2901 however special attention should be paid when changing an existing 73M2901 design to use the 73M2901CL. From a hardware standpoint, the key differences involve the User I/O pins USR10, USR11, the $65&+ pin and the HBDEN pin. An additional user I/O pin USR20 replaces the $65&+ pin on the 73M2901CL. This pin may remain safely connected to TXD as long as the host software does not reconfigure USR20 as an output (S104 bit0=0). The 73M2901CL contains a high efficiency low power hybrid driver. Due to this enhancement HBDEN is no longer required. This pin is an internal no-connect and can safely remain connected to its previous VPD or GND. The functions of USR10 and USR11 are related to Caller ID and Line In Use/Parallel Pickup support. TDK Semiconductor’s 73M2901CL single chip modem includes all the basic modem functions. Programmable configuration options make this device highly adaptable to a wide variety of applications. Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify low-level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. The crystal oscillator should be held to a 50ppm tolerance. The following recommendations should be taken into consideration when starting new designs. LAYOUT CONSIDERATIONS Software enhancements to the 73M2901CL are typically achieved by the addition of new AT commands. The device can be considered a superset of the 73M2901. When converting a design to the 73M2901CL it is recommended that the user check the commands and register settings for backward compatibility to the earlier parts*. Good analog/digital design rules must be used to control system noise in order to obtain high performance in modem designs. The more digital circuitry present in the application, the more attention to noise control is needed. High speed, digital devices should be locally bypassed, and the telephone line interface and the modem should be located next to each other near where the telephone line connection is accessed. It is recommended that power supplies and ground traces should be routed separately to the analog and digital portions on the board. Digital signals should not be routed near low-level or high impedance analog traces. TELEPHONE LINE INTERFACE Transmit levels at the line are dependent on the interface used between the pins and the line. The internal hybrid line drivers eliminate the need for additional active circuitry to drive the line-coupling transformer. The analog outputs (TXAP and TXAN) can be connected directly to the transformer (with the required impedance matching series resistor or network) however some low cost transformers may be affected by the limited amount of DC current generated by the analog outputs (DC offset); hence it is recommended to use a coupling capacitor with those transformers to insure maximum performance. The line interface circuit shown on the following page represents the basic components and values for interfacing the TDK 73M2901CL analog pins to the telephone line. The values of these components have been calculated to minimize the transmission and reception path hybrid losses and are linked by the following equation: R15=0.242 x R13. The 73M2901CL should be considered a high performance analog device. A 10µF electrolytic capacitor in parallel with a 0.1µF Ceramic capacitor should be placed between each VPD and VND pin as well as between VPA and VNA. A 0.1µF ceramic capacitor should be placed between VREF and VNA as well as VBG and VNA. Use of ground planes and large traces on power is recommended. 73M2901CL DESIGN COMPATIBILITY The TDK 73M2901CL is an enhanced version of the TDK 73M2901C and has a number of new features. These parts are highly compatible with the earlier * (refer to the TDK 73M2901CL User Guide for complete details) 10 73M2901CL V.22bis Single Chip Modem performance while operating over a range of typical operating conditions. A DPSK modem will exhibit better BER performance test curves receiving in the low band (answer mode) than in the high band (originate mode). MODEM PERFORMANCE CHARACTERISTICS The curves presented in this data sheet define modem IC performance under a variety of line conditions typical of those encountered over Public Switched Telephone Network. BER VS. RECEIVE LEVEL This test measures the dynamic range of the modem. Because signal levels vary widely over dial up lines, the widest possible dynamic range is desirable. The SNR is held constant at the indicated values as the Receive level is lowered from a very high to a very low signal level. The width of the bowl of these curves, taken at the BER break points is the measure of the dynamic range. BER VS. SNR This test represents the ability of the modem to operate over noisy lines with a minimum amount of data transfer errors. Since some noise is generated in the best dial up lines, the modem must operate with the lowest signal to noise ratio (SNR) possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in RECOMMENDED SCHEMATIC ARRANGEMENT VCC3_3D 11.0592 MHz C1 C2 RST 27pF Y1 TXDB OSCIN OSCOUT 25 RXDB 26 27 DTRB 28 29 30 HOOKB 31 RIB 32 10uF 0.1uF VPD RXD RXCLK DTR USR20 RING RELAY RI T1P3 TXAP + R15 5.1K RXA VNA RXA VBG VREF TXAP TXAN VPA RESET 16 15 RXA 14 VBG 13 VREF 12 TXAP 11 10 9 RST 2901CL_TQFP32 R23 C20 0.1uF T1 3 2 4 1 C4 .082UF RXA_TAP 671-8005 NC R13 21K R2 2K TXAN TXAN U2 VCC3_3A C7 C8 0.1uF 0.1uF + C9 22uF R28 C10 0.1uF 120K 6 5 1 4 2 1 2 3 4 5 6 7 8 VCC3_3A R17 475 LDA110* DCDB DSRB CTSB RTSB 4 1 VCC3_3D RINGB/PPUB/LIUB/LREVB DCDB DSRB CTSB RTSB U3 TLP627 VCC3_3 3 + 4 C5 10uF C6 VCC3_3D 0.1uF U4 TLP627 VCC3_3D R16 100 HOOKB U11P2 3 R20 22K U10P2 2 LIUCHECKB 1 R18 100 2 RXDB DTRB TXDB RIB DCDB DSRB CTSB RTSB VCC3_3 C14 TXCLK TXD VND N/C VPD OSCIN OSCOUT VND U1 C13 24 23 22 21 20 19 18 17 + C12 10uF J1 CON10 ISOLATION BARRIER VCC3_3D VCC3_3D C11 0.1uF 10 9 8 7 6 5 4 3 2 1 33pF TXDB VND VPD DCD DSR CTS RTS USR11 USR10 R1 10K C3 C20R29 10uF OSCOUT + [js1] 11 73M2901CL V.22bis Single Chip Modem TYPICAL USA APPLICATION SCHEMATIC PPU Circuit CID_COUPLED R4 13K R5 13K R6 27K 2 R3 33K Q1B 1 Q3 Q2 Q2B 1 CMPT6429 2 CMPT6429 Q3EQ2E 2 Q3B Q1 2N5087 1 R7 1K Q1C 3 3 3 Q2C Q3C R21 100 OHMS T1 R12 20K R10 62K C16 1uF DAA_COM CID_COUPLED C 3 + C15 10uF R14 62K D2CR25 ISOLATION BARRIER 2 CLL5239B 9.1V 0.5W D2 CMR1F-04M DAA_COM 671-8005 R19 20K LIUDET D3 R19Q14CC D7 AD3AD7A A C C 1 A 4 A D1 CMR1F-04M 12V RING/LREVDET U2 6 5 RING/LREV detection D8 R11 9.1K C17 1 C17R11 D5 D6 AD5AD6A A R11D5C C C 1N4001 22V 4 2 DAA_COM 0.47UF 250V 22V DAA_PLUS L1 NLC322522T-4R7M 4 4 E1 P3100EA70 TECCOR SIDACTOR - 2 + 1 3 U11P2 2 U4 TLP627 C18 0.15uF 250V F1 TR250-145 RAYCHEM POLYSWITCH J2 U5 Z602 TIP1 L2 NLC322522T-4R7M 3 CID coupling R23C22 3 LIUDET 4 2 1 U10P2 R8 75K TIPF1 0 OHMS TIPL1 U3 TLP627 R22 1 LDA110* RINGL2 R9 C19 R9C19 9.1K RING/LREV detection 12 0.47uF 250V RING 4 3 2 1 CON4 73M2901CL V.22bis Single Chip Modem BER CURVES BER vs. SNR BER vs. Receive Level 13 73M2901CL V.22bis Single Chip Modem 32 PIN PLCC PIN-OUT PIN NAME PIN NAME PIN NAME PIN NAME 1 USR20 9 &76 17 TXAP 25 VPD 2 5,1* 10 576 18 VREF 26 VND 3 5(/$< 11 USR11 19 VBG 27 TXD 4 5, 12 USR10 20 RXA 28 TXCLK 5 VND 13 RESET 21 VNA 29 VPD 6 VPD 14 NC 22 VND 30 RXD 7 '&' 15 VPA 23 OSCOUT 31 RXCLK 8 '65 16 TXAN 24 OSCIN 32 '75 32 PIN TQFP PIN-OUT PIN NAME PIN NAME PIN NAME PIN NAME 1 VND 9 RESET 17 VND 25 VPD 2 VPD 10 VPA 18 OSCOUT 26 RXD 3 '&' 11 TXAN 19 OSCIN 27 RXCLK 4 '65 12 TXAP 20 VPD 28 '75 5 &76 13 VREF 21 NC 29 USR20 6 576 14 VBG 22 VND 30 5,1* 7 USR11 15 RXA 23 TXD 31 5(/$< 8 USR10 16 VNA 24 TXCLK 32 5, 44 PIN LQFP PIN-OUT PIN NAME PIN NAME PIN NAME PIN NAME 1 N/C 12 VPD 23 N/C 34 N/C 2 VPD 13 N/C 24 VND 35 RXD 3 '&' 14 N/C 25 OSCOUT 36 RXCLK 4 '65 15 NC 26 OSCIN 37 '75 5 &76 16 VPA 27 VPD 38 USR20 6 576 17 TXAN 28 VND 39 5,1* 7 USR11 18 TXAP 29 N/C 40 5(/$< 8 USR10 19 VREF 30 TXD 41 N/C 9 RESET 20 VBG 31 TXCLK 42 N/C 10 N/C 21 RXA 32 N/C 43 5, 11 VND 22 VNA 33 VPD 44 VND 14 73M2901CL V.22bis Single Chip Modem PACKAGE PIN DESIGNATIONS (Top View) N/C RXD RXCLK DTR USR20 RING RELAY N/C N/C RI 32-Pin TQFP 73M2901CLIGV VND 32-Lead PLCC 73M2901CLIH N/C 1 44 43 42 41 40 39 38 37 36 35 34 33 VPD 2 32 N/C DCD 3 31 TXCLK DSR 4 30 TXD CTS 5 29 N/C RTS 6 28 VND USR11 7 27 VPD USR10 8 26 OSCIN RESET 9 25 OSCOUT 10 24 VND 44-Pin LQFP 73M2901CLIGT 15 VNA RXA VBG VREF TXAP TXAN VPA N/C N/C 11 23 12 13 14 15 16 17 18 19 20 21 22 N/C VND VPD N/C VPD N/C 73M2901CL V.22bis Single Chip Modem MECHANICAL DRAWINGS 32 Pin PLCC 73M2901CLIH 16 73M2901CL V.22bis Single Chip Modem 32 Pin TQFP 73M2901CLIGV 17 73M2901CL V.22bis Single Chip Modem 44 Pin LQFP 73M2901CLIGT ORDERING INFORMATION PART DESCRIPTION 73M2901CL 32-Pin Plastic Leaded Chip Carrier 73M2901CL 32-Pin Thin Quad Flat Pack 73M2901CL 44-Pin Quad Flat Pack ORDER NUMBER 73M2901CLIH 73M2901CLIGV 73M2901CLIGT PACKAGING MARK 73M2901CLIH 73M2901CLIGV 73M2901CLIGT No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at http://www.tdksemiconductor.com or contact your local TDK Semiconductor representative. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com 2001 TDK Semiconductor Corporation 05/24/02- V1.2 18