TOSHIBA TB1311AFG

TB1311AFG
Preliminary
Preliminary
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB1311AFG
Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1311AFG includes audio and video SW blocks, prefilters
for A/D converters, sync separators, and an H/V format detector for
TV signals.
The TB1311AFG contributes to a reduction in the proportion of the
PCB occupied by LCR filters and to the simplification of designs on
analog interfaces.
2
The TB1311AFG has an I CBUS interface through which various
functions can be controlled.
P-QFP80-1420-0.80C
Weight: 1.6 g (typ.)
Features
Audio SW block
Audio (L/R) inputs
Audio (L/R) output: 3 channels
࡮
࡮
Audio block
Attenuator
࡮
Video SW block
CVBS inputs
Y/C inputs
Component video inputs (co-use as RGB inputs)
SCART inputs
Output: 2 channels
Monitor output
࡮
࡮
࡮
࡮
࡮
࡮
Video block
Gain switching: -3 dB / 0 dB / +3 dB
Bandwidth filter: prefilter for ADC; 4.5 to 46 MHz variable
࡮
࡮
Sync separation block
Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i,
VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60
HD/VD input: 1 channel; positive and negative input acceptable
HD/VD output: positive and negative output selectable
Masking pseudo-sync for the copyguard signal
࡮
࡮
࡮
࡮
Others
Line detector for Japanese D-pin
S2, S1, insertion detection for S-pin
Horizontal and vertical frequency counter
Format detection circuit to input signal
No-input detection
Automatic sync process switching mode
Programmable number of audio/video inputs
࡮
࡮
࡮
࡮
࡮
࡮
࡮
1
2005-12-20
Preliminary
TB1311AFG
Block Diagram 1 (Simplified Overview)
This IC does not support weak signals, ghost signals or other nonstandard signals.
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory
purposes.
2
2005-12-20
TB1311AFG
Preliminary
Block Diagram 2 (Video Block)
T
U
O
1
B
/1
b
C
T
U
O
1
R
/1
r
C
T
U
O
1
S
B
V
C
T
U
O
2
B
/2
b
C
T
U
O
2
R
/2
r
C
T
U
O
R
O
IT
N
O
M
4
19
21
23
17
2
34
T
U
O
iv
Y
10
T
U
O
2
S
B
V
C
8
T
U
O
2
G
/2
Y
6
T
U
O
1
G
/1
Y
S
B
V
C
/
G
/
Y
C
/
B
/
b
C
R
r/
C
S
B
V
C
S
B
V
C
/
G
/
Y
C
/
B
/
b
C
R
r/
C
S
B
V
C
S
B
V
C
Y
teu
M
teu
M
Bd
+6/
Bd
3+
teu
M
Bd
+6/
Bd
3+
HT
ID
WD
NA
B
Bd
+6/
Bd
3+
HT
ID
W
DN
AB
Bd
-3
Bd
+6/
Bd
3+
"
1
0
0
=
T
U
O
1
S
B
V
C
n
e
h
w
"
HT
ID
W
DN
AB
Bd
-3
teu
M
teu
M
Bd
+6/
Bd
3+
HT
ID
W
DN
AB
Bd
-3
teu
M
Bd
+6/
Bd
3+
HT
ID
W
DN
AB
Bd
-3
teu
M
Bd
+6/
Bd
3+
HT
ID
W
DN
AB
Bd
-3
Bd
+6/
Bd
3+
teu
M
"
1
0
0
=
T
U
O
2
S
B
V
C
n
e
h
w
"
HT
ID
W
DN
AB
Bd
-3
Bd
6+
teu
M
Bd
-3
IX
M
CY
HT
ID
W
DN
AB
Bd
-3
"CbCr PIN3"
"CbCr PIN4"
"Yvi OUT"
"CbCr PIN1"
"CbCr PIN2"
"MON OUT"
"CVBS2 OUT"
"CVBS1 OUT"
"YCbCr2 OUT"
"YCbCr1 OUT"
IN
1Y
S
IN
1
C
S
IN
2
C
S
IN
3
S
B
V
C
IN
4
S
B
V
C
IN
5
S
B
V
C
IN
6
S
B
V
C
IN
1
G
/1
Y
IN
1
B
/1
b
C
IN
1
R
/1
r
C
IN
2
G
/2
Y
IN
2
B
/2
b
C
SA
IB
TE
D
CD
IN
2
R
/2
r
C
IN
3
G
/3
Y
SA
IB
"
7
S
"
SA
IB
TE
D
CD
IN
3
B
/3
b
C
IN
3
R
/3
r
C
IN
4
G
/4
Y
IN
4
B
/4
b
C
71
TE
D
CD
SA
IB
"
3
S
"
"
4
P
M
A
L
C
"
73
TE
D
CD
SA
IB
"
5
S
"
SA
IB
/P
IT
CN
YS
75
TE
D
CD
SA
IB
"
6
S
"
51
SA
IB
"
1
S
"
53
49
61
41
TE
D
CD
38
77
IN
2Y
S
SA
IB
"
2
S
"
SA
IB
/P
IT
CN
YS
55
PI
T
CN
SY
65
PI
T
CN
SY
"
3
P
M
A
L
C
"
67
PI
T
CN
SY
SA
IB
/P
IT
CN
YS
69
"
8
S
"
PI
T
CN
SY
TE
D
CD
59
57
TE
D
CD
SA
IB
36
"
4
S
"
PI
T
CN
SY
"
2
P
M
A
L
C
"
47
SA
IB
79
PI
T
CN
SY
SA
IB
/P
IT
CN
YS
45
"
1
P
M
A
L
C
"
IN
4
R
/4
r
C
as R/G/B
tu
pn as Cb/Cr
i
el
as C
ba
ila
as Y
v
A
as CVBS
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory
purposes.
3
2005-12-20
TB1311AFG
Preliminary
Block Diagram 3 (Audio Block)
AR1 IN
35
ATT
AL1 IN
37
ATT
AR2 IN
42
ATT
AL2 IN
43
ATT
AR3 IN
52
ATT
AL3 IN
54
ATT
AR4 IN
56
ATT
AL4 IN
58
ATT
AR5 IN
62
ATT
AL5 IN
63
ATT
AR6 IN
72
ATT
AL6 IN
74
ATT
AR7 IN
76
ATT
AL7 IN
78
ATT
AR8 IN/DC1(S3)
39
ATT
AL8 IN/DC2(S4)
40
ATT
AR9 IN/DC4(LINE3-1)
46
ATT
AL9 IN/DC5(LINE2-1)
48
ATT
AR10 IN/DC9(LINE3-2)
66
ATT
AL10 IN/DC10(LINE2-2)
68
ATT
“AU1 ATT”
Total 0dB
7
AR1 OUT
5
AL1 OUT
20
AR2 OUT
18
AL2 OUT
3
AR3 OUT
1
AL3 OUT
“AU1 FIX”
Total 0dB
“AU2 ATT”
Total 0dB
“AU2 FIX”
Total 0dB
Other block
Other block
Other block
Other block
Other block
Other block
”
T
U
O
1
U
A
“
”
T
U
O
2
U
A
“
”
T
U
O
3
U
A
“
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory
purposes.
4
2005-12-20
TB1311AFG
Preliminary
Block Diagram 4 (Other Blocks)
S
U
B
C
2
I
C
OF
UR
NE
TQ
E
R
This IC does not support weak signals, ghost signals or other nonstandard signals.
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory
purposes.
5
2005-12-20
Preliminary
TB1311AFG
Pin Assignment
CVBS5 IN
AU Vcc (9V)
AR2 IN
Cr2/R2 OUT
AL2 IN
FB2 OUT
Cb2/B2 OUT
FB1 IN/DC3(SW LINE1)
Cr1/R1 IN
AR2 OUT
AR9 IN/DC4(LINE3-1)
Y2/G2 OUT
Cb1/B1 IN
AL2 OUT
AL9 IN/DC5(LINE2-1)
CVBS2 OUT
Y1/G1 IN
V/S GND
FB3 IN/DC6(LINE1-1)
SYNC2 IN
SYNC FILTER
Cr3/R3 IN
AR3 IN
VD OUT
Cb3/B3 IN
HD OUT
AL3 IN
V/S Vcc (5V)
Y3/G3 IN
Cr1/R1 OUT
AR4 IN
FB1 OUT
SY1 IN
Cb1/B1 OUT
AL4 IN
AR1 OUT
SC1 IN
Y1/G1 OUT
DC7(S1)
AL1 OUT
CVBS1 OUT
CVBS6 IN
AR5 IN
AR3 OUT
AL5 IN
MONITOR OUT
FB2 IN/
DC8(SW LINE2)
AL3 OUT
6
2005-12-20
TB1311AFG
Preliminary
Pin Functions
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
11
3.3V
VCC pin for the logical circuits.
29
Vdd (3.3 V)
500Ω
29
Supply power through a resistor from pin 11
as in the Application Circuit. This pin voltage
is clipped to 3.3 V (typ.) by the internal
regulator.
3.3 V (typ.)
27
27
11
Vss
V/S VCC (5 V)
16
V/S GND
24
AU VCC (9 V)
32
AU GND
36
CVBS3 IN
38
CVBS4 IN
41
CVBS5 IN
61
CVBS6 IN
57
SY1 IN
77
SY2 IN
GND pin for the logical circuits.
VCC pin for the sync and video circuits.
Connect 5.0 V (typ.)
GND pin for the sync and video circuits.
VCC pin for the audio circuits.
Connect 9.0 V (typ.)
GND pin for the audio circuits.



5.0 V (typ.)



9.0 V (typ.)


CVBS or Y input pin.
Sync tip level: 2.3 V (typ.)
Input the CVBS or Y signal in NTSC, PAL or
SECAM via a clamp capacitor.
Y/CVBS signal amplitude:
1.0 Vp-p (with sync)
Chroma signal input pin.
59
79
SC1 IN
SC2 IN
Input C signal via a capacitor.
2.9 V bias (typ.)
Ω
k
2
.0
0
1
The voltage of this pin is detected and the
status is returned to the I2CBUS Read
functions, S4 or S8. It is used for detecting
whether the S-pin is connected or not.
V
1
Burst signal amplitude:
0.3 Vp-p
V
3
11
49
Y1/G1 IN
Y, G or CVBS input pin.
69
Y2/G2 IN
Input the signal via a clamp capacitor.
55
Y3/G3 IN
75
Y4/G4 IN
The clamp system is selectable by
CLAMP1, 2, 3 or 4 registers.
49
55
69
75
Ω
0
0
2
V
.5
1
/
V
3
Sync tip level: 2.3 V (typ.)
200Ω
Bias level: 2.9 V (typ.)
Ω
k
.2
0
0
1
Y/G/CVBS signal amplitude:
1.0 Vp-p (with sync)
V
3
16
2.9 V bias (typ.)
47
Cb1/B1 IN
67
Cb2/B2 IN
Cb, B or C input pin.
53
Cb3/B3 IN
Input the signal via a capacitor.
73
Cb4/B4 IN
Ω
k
2
.0
0
1
V
1
7
V
3
Cb/B signal amplitude:
0.7 Vp-p (without sync)
Burst signal amplitude:
0.3 Vp-p
2005-12-20
TB1311AFG
Preliminary
Pin
No.
Pin Name
Interface Circuit
Function
Input Signal/Output Signal
2.9 V bias (typ.)
45
Cr1/R1 IN
Cr, R or C input pin.
65
Cr2/R2 IN
Input the signal via a capacitor.
Ω
k
2
.0
0
1
V
1
Cr/R signal amplitude:
0.7 Vp-p (without sync)
Burst signal amplitude:
0.3 Vp-p
V
3
11
Sync tip level: 2.3 V (typ.)
Cr, R or CVBS input pin.
51
71
Cr3/R3 IN
Cr4/R4 IN
Ω
0
0
2
51
71
Input the signal via a capacitor.
V
.5
1
/
V
3
The clamp system is changed according to
CbCr PIN3 or 4 registers.
Bias level: 2.9 V (typ.)
200Ω
Cr/R signal amplitude:
0.7 Vp-p (without sync)
Ω
k
2
.0
0
1
CVBS signal amplitude:
1.0 Vp-p (with sync)
V
3
16
35
AR1 IN
37
AL1 IN
42
AR2 IN
43
AL2 IN
52
AR3 IN
54
AL3 IN
56
AR4 IN
58
AL4 IN
62
AR5 IN
63
AL5 IN
72
AR6 IN
74
AL6 IN
76
AR7 IN
78
AL7 IN
35
37
42
43
52
54
56
Audio input pin.
Input the signal via a resistor and a
capacitor. When the resistor value is 5.6 kΩ,
the internal gain becomes 0 dB (typ.).
AR8 IN/DC1
40
AL8 IN/DC2
46
AR9 IN/DC4
48
AL9 IN/DC5
66
AR10 IN/DC9
68
AL10 IN/DC10
The input type is changed by AU8 PIN, AU9
PIN or AU10 PIN.
40.2kΩ
F
p
1
kΩ
7
4
V
5
.4
Bias level: 4.4 V (typ.)
Audio input: 2.8
㨂p-p (100%)
32
24
39
40
46
48
66
68
Audio or DC voltage input pin.
39
24
58
62
63
72
74
76
78
200Ω
40kΩ
76kΩ
32
In the case of use as audio input, input the
signal via a resistor and a capacitor. When
the resistor value is 5.6 kΩ, the internal gain
becomes 0 dB (typ.).
Bias level: 4.4 V (typ.)
11
Audio input: 2.8
In the case of use as DC voltage input, input
the signal via a resistor for protection.
Th1
㨂p-p (100%)
Th2
16
44
FB1 IN/DC3
64
FB2 IN/DC8
50
FB3 IN/DC6
70
FB4 IN/DC11
FB (Fast Blanking) signal or DC voltage
input pin.
Connect a resistor between this pin and
GND.
FB input:
Ω
k
5
2
.3
In the case of use as DC voltage input, input
the signal via a resistor for protection.
V
1
V
3
DC voltage input.
60
DC7
80
DC12
Input the signal via a resistor for protection
purposes.
Ω
k
1
This pin is also used as a test signal output
pin for shipping only.
DC
V
1
8
V
3
2005-12-20
TB1311AFG
Preliminary
Pin
No.
Pin Name
Interface Circuit
Function
Input Signal/Output Signal
Sync tip level: 1.8 V (typ.)
Composite SYNC input pin to separate into
H- and V-SYNC.
33
SYNC1 IN
15
SYNC2 IN
Input the signal via a clamp capacitor.
or
Remark: SYNC1 IN is not available, when
A-SYNC = 1 (ON).
1Vp-p
HD or VD input pin.
31
HD IN
30
VD IN
1.45 V bias (typ.)
Input a separated horizontal or vertical sync
signal (1.0 to 2.0 Vp-p) via a resistor and a
coupling capacitor.
or
The polarity of the input signal is detected
and its leading edge becomes a timing
trigger.
4
CVBS1 OUT
6
Y1/G1 OUT
8
Cb1/B1 OUT
10
Cr1/R1 OUT
17
CVBS2 OUT
19
Y2/G2 OUT
21
Cb2/B2 OUT
23
Cr2/R2 OUT
5
AL1 OUT
7
AR1 OUT
18
AL2 OUT
20
AR2 OUT
1
AL3 OUT
3
AR3 OUT
11
4
6
8
10
17
19
21
23
Video signal output pin.
Refer to Bus Control Functions for details of
the output from each pin.
100Ω
16
24
1
3
5
7
18
20
Audio signal output pin.
Refer to Bus Control Functions for details of
the output from each pin.
32
11
Video signal output pin for a monitor output.
2
MONITOR OUT
AC: -3, 0 or +3 dB (typ.)
AC: +6 dB (typ.)
Refer to Bus Control Functions for details of
the output from the pin.
2
34
Video signal output pin for the sync
separation circuit.
34
Yvi OUT
AC: 0 dB (typ.)
Refer to Bus Control Functions for details of
the output from the pin.
16
HD or VD output pin.
12
HD OUT
13
VD OUT
The polarity of the output is selectable by
HV-POL register.
11
or
The tailing edge of the VD-OUT has a jitter.
Use the leading edge only.
9
12
13
22
FB output pin.
9
FB1 OUT
22
FB2 OUT
14
SYNC FILTER
Note: If necessary, a resistor can be added
between the pin and GND to improve the
transient of the falling edge. The value of
the resistor must be 440 Ω or more.
However, when the resistor is added, the
leak pulse from FB edges to video signals is
also increased.
100Ω
16
A filter pin for sync detection.

Connect a capacitor between this pin and
GND.
9
2005-12-20
TB1311AFG
Preliminary
Pin
No.
Pin Name
Interface Circuit
Function
Input Signal/Output Signal
Crystal connection pin.
28
XTAL

Connect a 3.579545 MHz crystal for NTSC
demodulation to generate internal clocks.
11
25
SDA
SDA pin for I2CBUS.
5kΩ
25
H to L: 1.3 V (typ.)
L to H: 2.1 V (typ.)
50Ω
ACK
27
11
26
SCL
SCL pin for I2CBUS.
26
5kΩ
H to L: 1.3 V (typ.)
L to H: 2.1 V (typ.)
27
10
2005-12-20
TB1311AFG
Preliminary
BUS Control Map
Write Mode
SA
Slave Address: DEH
D7
D6
D5
D4
D3
D2
D1
D0
PRESET
00
CVBS1OUT
fc HALF1
YCbCr1OUT
00000000
01
CVBS2OUT
fc HALF2
YCbCr2OUT
00000000
MON OUT
00000000
02
(0)
03
f0 SW1
BANDWIDTH1
00000000
04
f0 SW2
BANDWIDTH2
00000000
05
FILPASS2
CVBS2 GAIN
YC MIX
YCbCr2 GAIN
06
CbCr PIN4
CbCr PIN3
07
FB2 DL
FB2 MUTE
08
09
FILPASS1
CbCr PIN2
CVBS1 GAIN
CbCr PIN1
FB2 OUT
CLAMP3
FB1 DL
FB1 MUTE
AU2 OUT
00000000
CLAMP1
FB1 OUT
AU2 FIX
AU10 PIN
00010001
00000000
AU2 ATT
AU9 PIN
AU8 PIN
HV-SEP2
0D
A-SYNC
SIG LPF
(0)
(0)
0E
(0)
PS MASK
V-DET
HD WIDTH
0F
H DMY
V DMY
FB2 PIN-M
10
H COUNT MAX
11
SIG DET N
(0)TEST1
FB2 PIN-L
00000000
(0)
AU3 OUT
HV-SEP1
(0)
(0)
HV POL
(0)
00000001
SYNC LPF2 SYNC LPF1
Yvi OUT
HV OUT
00000000
00000000
H COUNT MIN
00000000
SIG RESET N
SIG SW
00000000
00000000
HV DET
HV FREQ2
(0)
SIG RESET
00000000
00000000
AU1 ATT
0B
0C
CLAMP2
AU1 OUT
AU1 FIX
0A
12
YCbCr1 GAIN
CLAMP4
SIG DET IMPE
00000000
SIG DET LVL
00000000
13
(00000000) TEST2
00000000
14
(00000000) TEST3
00000000
Remark: SA = Sub-address.
NOTE: Set 0 (zero) on bits written as (0).
Read Mode
0
Slave Address: DFH
D7
D6
D5
D4
D3
POR
H FM2
V FM2
H IN
V IN
1
2
H FORMAT
FB DET2
FB DET1
D2
D1
D0
V-SYNC-W
HD-POL
VD-POL
∗
V FORMAT
SIG DET
HV-OUT FORMAT
3
DC4
DC3
DC2
DC1
4
DC8
DC7
DC6
DC5
5
DC12
DC11
DC10
DC9
6
S8
S7
S6
S5
S4
7
H FREQ DET
8
V FREQ DET
S3
S2
S1
∗: Undefined
11
2005-12-20
Preliminary
TB1311AFG
Bus Control Functions
Write Mode
Register Name
Function
Preset Value
Selects the output from CVBS1(2) OUT (pin 4 (17)) for SCART connector.
CVBS1(2)OUT
000: Mute
001: Outputs the same Y, selected by YCbCr1(2) OUT
010: CVBS3 (pin 36)
011: CVBS4 (pin 38)
100: CVBS5 (pin 41)
101: CVBS6 (pin 61)
110: Cr3 (as CVBS) (pin 51)
111: Cr4 (as CVBS) (pin 71)
Mute
(000)
Switches the frequency of bandwidth limit filters for Cb/Cr
OFF
fc HALF1(2)
The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y.
(0)
0: OFF (same for 3 outputs)
1: ON (1/2 fc for Cb/Cr)
Selects the output from Y/Cb/Cr OUT1(2) (pins 6, 8, 10 (19, 21, 23)).
YCbCr1(2)OUT
(Y OUT, Cb OUT, Cr OUT) =
0000: Mute (mute, mute, mute)
0001: SY1 (pin 57), SC1 (pin 59), mute
0010: SY2 (pin 77), SC2 (pin 79), mute
0011: CVBS3 (pin 36), mute, mute
0100: CVBS4 (pin 38), mute, mute
0101: CVBS5 (pin 41), mute (Cr1; pin 45, when CbCr PIN1 = 1), mute
0110: CVBS6 (pin 61), mute (Cr2; pin 65, when CbCr PIN2 = 1), mute
0111: Y1 (pin 49), Cb1 (pin 47), Cr1; pin 45 (mute, when CbCr PIN1 = 1)
1000: Y2 (pin 69), Cb2 (pin 67), Cr2; pin 65 (mute, when CbCr PIN2 = 1)
1001: Y3 (pin 55), Cb3 (pin 53), Cr3; pin 51 (mute, when CbCr PIN3 = 1)
1010: Y4 (pin 75), Cb4 (pin 73), Cr4; pin 71 (mute, when CbCr PIN4 = 1)
1011: Cr3 (as CVBS) (pin 51), mute, mute
1100: Cr4 (as CVBS) (pin 71), mute, mute
1101 to 1111: Not available
Mute
(0000)
Refer also to Function Descriptions.
Switches the bandwidth limit filter 1 (2).
OFF
FILPASS1(2)
0: OFF (filters active)
1: ON (bypass)
Mixes Y with C for MONITOR OUT (pin 2).
(0)
OFF
YC MIX
0: OFF (for CVBS)
1: MIX (Y+C)
(0)
Selects the output from MONITOR OUT (pin 2).
When YC MIX = 1, a mixed signal is output.
MON OUT
0000: Mute
0001: SY1 (pin 57) (+SC1 (pin 59))
0010: SY2 (pin 77) (+SC2 (pin 79))
0011: CVBS3 (pin 36)
0100: CVBS4 (pin 38)
0101: CVBS5 (pin 41) (+Cr1 (pin 45), when CbCr PIN1 = 1)
0110: CVBS6 (pin 61) (+Cr2 (pin 65), when CbCr PIN2 = 1)
0111: Y1 (pin 49) (+Cb1 (pin 47))
1000: Y2 (pin 69) (+Cb2 (pin 67))
0001: Y3 (pin 55) (+Cb3 (pin 53))
1010: Y4 (pin 75) (+Cb4 (pin 73))
1011: Cr3 (CVBS) (pin 51))
1100: Cr4 (CVBS) (pin 71))
1101 to 1111: Not available
Mute
(0000)
Refer also to Function Descriptions.
Switches the f0 of the bandwidth limit filter for YCbCr(RGB)
f0 SW1(2)
0: LOW
1: HIGH
Note: This function is not valid for the filter for CVBS. For the CVBS filter, this data is
fixed to 0: LOW.
LOW
(0)
Switches the f0 of the bandwidth limit filter for YCbCr(RGB) and CVBS
BANDWIDTH1(2)
0000000: MIN (low)
1111111: MAX (high)
Note: While HD, VD or FB-out is output, according as the f0 is set to lower, the
crosstalk from HD, VD, FB or SYNC-in to video-outs becomes bigger.
12
MIN
㧔0000000㧕
2005-12-20
TB1311AFG
Preliminary
Register Name
Function
Preset Value
Switches output gain.
0 dB
CVBS1(2) GAIN
Gain of CVBS1(2)-OUT output (pin 4 (17)) is controlled.
00: 0 dB
01: -3 dB
10: +3 dB
(00)
11: Not available
Switches output gain.
Gain of YCbCr1(2)-OUT outputs (pins 6,8,10 (19, 21, 23)) are controlled.
YCbCr1(2) GAIN
00: 0 dB
01: -3 dB
10: +3 dB
11: Not available
0 dB
(00)
Remark: GAIN = 01 (-3 dB) is recommended for the 1125/50p/60p format since this
offers superior frequency characteristics to those of other modes.
Changes CbCr1-IN pins function.
CbCr PIN1
0: Component Cb/Cr input
(pin 49: Y/G, pin 47: Cb/B, pin 45: Cr/R, pin 41: CVBS)
Cb/Cr input
(0)
1: Separated C input
(pin 49: Y, pin 47: C, pin 41: Y, pin 45: C)
Changes CbCr2-IN pins function.
CbCr PIN2
0: Component Cb/Cr input
(pin 69: Y/G, pin 67: Cb/B, pin 65: Cr/R, pin 61: CVBS)
Cb/Cr input
(0)
1: Separated C input
(pin 69: Y, pin 67: C, pin 61: Y, pin 65: C)
Changes CbCr3-IN pins function.
CbCr PIN3
0: Component Cb/Cr input
(pin 55: Y/G, pin 53: Cb/B, pin 51: Cr/R)
Cb/Cr input
(0)
1: Separated C input
(pin 55: Y, pin 53: C, pin 51: CVBS)
Changes CbCr4-IN pins function.
CbCr PIN4
0: Component Cb/Cr input
(pin 75: Y/G, pin 73: Cb/B, pin 71: Cr/R)
Cb/Cr input
(0)
1: Separated C input
(pin 75: Y, pin 73: C, pin 71: CVBS)
Switches Y1 (2, 3, 4) clamping mode.
CLAMP1(2,3,4)
The clamping mode for pin 49 (69, 55, 75) is set.
0: SYNC TIP CLAMP (for Y/G with sync)
1: BIAS (for RGB without sync)
Turns on the delay to FB1 (2)-OUT (pin 9 (22)).
SYNC TIP
(0)
OFF
FB1(2) DL
0: OFF
1: ON (+30 ns)
Mutes FB1 (2)-OUT (pin 9 (22)).
(0)
OFF
FB1(2) MUTE
0: OFF
1: MUTE
Switches the output from FB1(2)-OUT (pin 9 (22)).
FB1(2) OUT
00: FB1 (pin 44)
10: FB3 (pin 50)
01: FB2 (pin 64)
11: FB4 (pin 70)
(0)
FB1
(00)
Switches audio outputs from AL/AR1 (2,3)-OUT (pins 5/7 (18/20, 1/3)).
AU1(2,3) OUT
0000: MUTE
0010: AL/AR2 (pins 43/42)
0100: AL/AR4 (pins 58/56)
0110: AL/AR6 (pins 74/72)
1000: AL/AR8 (pins 40/39)
1010: AL/AR10 (pins 68/66)
0001: AL/AR1 (pins 37/35)
0011: AL/AR3 (pins 54/52)
0101: AL/AR5 (pins 63/62)
0111: AL/AR7 (pins 78/76)
1001: AL/AR9 (pins 48/46)
1011 to 1111: Not available
13
AL/AR1
(0001)
2005-12-20
Preliminary
Register Name
Function
TB1311AFG
Preset Value
Sets audio volume to AL/AR1 (2)-OUT (pin 5/7 (18/20)) fixed.
0: Fixed gain (0 dB)
AU1(2) FIX
1: OFF (Attenuated by AU1(2) ATT)
Note: The DC offset on audio outputs occurs when this function is turned on or off.
While audio outputs are valid, switching of this function is not available.
Fixed
(0)
Remark: The gain is defined where the series-connected resistor is 5.6 kΩ.
Attenuates audio volume to AL/AR1(2)-OUT (pins 5/7 (18/20)).
AU1(2) ATT
0000000: MIN
1111111: MAX
Changes the AL/AR8-IN pin function.
AU8 PIN
DC
0: DC input for S-pin (pin 39: DC1(S3), pin 40: DC2(S4))
1: Audio-IN8 (pin 39: AR8, pin 40: AL8)
Changes the AL/AR9-IN pin function.
AU9 PIN
(0)
DC
0: DC input for D-pin (pin 46: DC4(LINE2), pin 48: DC5(LINE1))
1: Audio-IN9 (pin 46: AR9, pin 48: AL9)
Changes the AL/AR10-IN pin function.
AU10 PIN
MIN
㧔0000000㧕
(0)
DC
0: DC input for D-pin (pin 66: DC9(LINE2), pin 68: DC10(LINE1))
1: Audio-IN10 (pin 66: AR10, pin 68: AL10)
(0)
Switches the separation level.
The H/V sync separation level to SYNC1(2)-IN (pin 33 (15)) is switched.
HV-SEP1(2)
00: LOW
11: HIGH
LOW
(00)
Remark: The separation level is changed according to a ratio of negative sync width
per 1H period.
Turns on the LPF for the sync-tip clamp.
SYNC LPF1(2)
SYNC LPF1(2) for SYNC1(2)-IN pin changes the speed of the sync-tip clamp
response. Turn this function on for no-input detection.
0: OFF
OFF
(0)
1: ON
Automatic sync processing mode.
A-SYNC
Sync processing mode is changed in accordance with the results obtained by the
internal format detection circuits. Format detection is performed for SYNC2-IN or
HD/VD-IN signal selected by HV DET. The result of detection is returned to H
FORMAT, V FORMAT, H FM2 and V FM2.
HV FREQ setting is invalid when this mode is active.
OFF
(0)
0: OFF (Manual switching mode by HV FREQ2 setting)
1: ON
Remark: SYNC1-IN (pin 33) is not available when A-SYNC = 1 (ON). Format
detection and H/V separation are then executed for SYNC2-IN (pin 15).
Turns on the LPF for the sync input pin (pin 33; SYNC1-IN).
SIG LPF
When no-input detection for weak strength signals is required, turn this function on
to reduce noise on the input. Turn this function off for detections such as H
FORMAT, V FORMAT, H FREQ DET and V FREQ DET.
0: OFF
OFF
(0)
1: ON
Switches the output from Yvi-OUT (pin 34).
Yvi OUT
0000: MUTE
0010: SY2 (pin 77)
0100: CVBS4 (pin 38)
0110: CVBS6 (pin 61)
1000: Y2 (pin 69)
1010: Y4 (pin 75)
1100: Cr4 (as CVBS) (pin 71)
1101 to 1111: Not available
0001: SY1 (pin 57)
0011: CVBS3 (pin 36)
0101: CVBS5 (pin 41)
0111: Y1 (pin 49)
1001: Y3 (pin 55)
1011: Cr3 (as CVBS) (pin 51)
MUTE
(0000)
Switches the mask mode for pseudo-sync.
ON
PS MASK
0: ON (Normal)
1: OFF (for “Sync on G”)
(0)
(1) OFF mode is used for “Sync on G” input.
14
2005-12-20
Preliminary
Register Name
Function
TB1311AFG
Preset Value
Switches the V format detection mode.
50/60 only
V-DET
0: 50/60Hz only
1: Full detection
(0)
Switches the width of HD-OUT (pin 12) from SYNC2-IN (pin 15).
0: WIDE
HD WIDTH
1: NARROW
Remark: HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format
owing to crosstalk from HD-OUT to video signals so that spike noises on
video signals will occur.
WIDE
(0)
Switches the polarity of HD/VD output.
Positive
HV-POL
The polarity of HD/VD OUT (pin 12, 13) is set.
(0)
0: Positive
1: Negative
Selects the input for format detection.
HV DET
When A-SYNC = 0 (Manual Mode)
0: SYNC1-IN (pin 33)
1: HD/VD-IN (pins 31/30)
SYNC
(0)
When A-SYNC = 1 (Automatic Mode)
This function is invalid. The input is selected by HV OUT.
Switches the outputs from HD/VD-OUT (pin 12/13).
SYNC2-IN
HV OUT
0: SYNC2-IN (pin 15)
1: HD/VD-IN (pins 31/30)
(0)
Outputs the dummy HD at no input.
H DMY
The frequency of the dummy HD output depends on the HV FREQ2 setting (when
A-SYNC = OFF) or HV-OUT FORMAT (when A-SYNC = ON). No-input detection
is based on H IN result.
0: OFF
1: ON (Dummy HD output at no input)
OFF
(0)
Note: The HD output does not synchronize with input sync, when A-SYNC = OFF
and when a sync is input.
Outputs the dummy VD at no input.
V DMY
The frequency of the dummy VD output depends on HV FREQ2 setting (when
A-SYNC = OFF) or HV-OUT FORMAT (when A-SYNC = ON). No-input detection
is based on the V IN result.
0: OFF
1: ON (Dummy VD output at no input)
OFF
(0)
Note: The VD output does not synchronize with input sync, when A-SYNC = OFF
and when a sync is input.
Changes FB2-OUT pin (pin 22) function.
In FB2 PIN-M/L = ON, the level of pin 22 becomes HIGH when the Read registers
below change. The level of pin 22 becomes LOW after the I2CBUS reading. The
pin voltage is used for a sign to detect input signal changes for a microprocessor.
For FB2 PIN-M/L = ON, set A-SYNC = 1 (ON) and FB2 MUTE = 1 (MUTE).
FB2 PIN-M, L
FB2 PIN-M
FB2 PIN-L
Mode
0
0
OFF (FB2-OUT)
OFF
0
1
Mode 1 for no-input detection
(00)
1
0
Mode 2 for format detection
1
1
Not available
Referential Read registers for FB2 PIN-M/L = Mode 1:
FB-DET1, SIG-DET
Referential Read registers for FB2 PIN-M/L = Mode 2:
H-FM2, V-FM2, H-IN, V-IN, HV-OUT FORMAT
15
2005-12-20
TB1311AFG
Preliminary
Register Name
Function
Preset Value
Input format setting.
Set the horizontal and vertical mode according to the format that is input.
When A-SYNC = ON mode, this setting is invalid.
HV FREQ2
00000: 15.625 kHz, 50 Hz (625i)
00001: 15.75 kHz, 60 Hz (525i)
00010: 31.25 kHz, 50 Hz (625p)
00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz)
00100: 28.125 kHz, 50 Hz (1125/50i)
00101: 33.75 kHz, 60 Hz (1125/60i)
00110: 37.5 kHz, 50 Hz (750/50p)
00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz)
01000: 31.25 kHz, 50 Hz (1250i)
01001: 37.9 kHz, 60 Hz (SVGA @60 Hz)
01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz)
01011: 75 kHz, 60 Hz (UXGA @60 Hz)
01100: 56.25 kHz, 50 Hz (1125/50p)
01101 to 01111: Not available
10000: 15.734 kHz, 30 Hz (525/30p)
10001: 27 kHz, 24 Hz (1125/24p)
10010: 28.125 kHz, 25 Hz (1125/25p)
10011: 33.75 kHz, 30 Hz (1125/30p)
10100: 27 kHz, 48 Hz (1125/24sf)
10101 to 11111: Not available
15.625 kHz, 50 Hz
(00000)
Selects the H-sync count number for the higher threshold for the no-input detection.
32 counts
H COUNT MAX
0000: 32 counts
1111: 62 counts
(2 counts / step)
Selects the H-sync count number for the lower threshold for the no-input detection.
(0000)
16 counts
H COUNT MIN
000: 16 counts
111: 30 counts
(2 counts / step)
Selects the number of signal detections for the input existence threshold of the
no-input detection.
(000)
1 count
SIG DET N
0000: 1 count
0001: 2 counts to 1111: 30 counts
(0000)
(2 counts / step)
Selects the number of signal detection for input non-existence threshold of the
no-input detection.
1 count
SIG RESET N
0000: 1 count
0001: 2 counts to 1111: 30 counts
(0000)
(2 counts / step)
Resets the counter for no-input detection.
Normal
SIG RESET
When 1 is sent, the counter for no-input detection is cleared at that time.
(0)
0: Normal
1: Reset
Selects the input to the counter for no-input detection.
SYNC2-IN
SIG SW
0: SYNC2-IN (pin 15)
1: SYNC1-IN (pin 33)
(0)
Changes the internal impedance for no-input detection.
SIG DET IMPE
The time constant of LPF for no-input detection is changed by this function and the
capacitor value of SYNC FILTER (pin 14).
20 kΩ
(00)
00: 20 kΩ
10: 10 kΩ
01: 15 kΩ
11: 6 kΩ
Changes the threshold for no-input detection.
SIG DET LVL
TEST1,2,3
00: 0.55 V
10: 1.05 V
01: 0.80 V
11: 1.30 V
Test modes for shipping test. Set all zero.
16
0.55 V
(00)
all 0
2005-12-20
TB1311AFG
Preliminary
Read Mode
Register Name
Function
Power On Reset
POR
0: Normal
1: Register preset
After power on, 1 is returned at first read. 0 is returned at second and subsequent reads.
Horizontal format detection 2
H FM2
0: Known
1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on H FORMAT data.
Vertical format detection 2
V FM2
0: Known
1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on V FORMAT data.
Input detection to horizontal syncs
H IN
0: No input
1: Signal detected
Input detection to vertical syncs
V IN
0: No input
1: Signal detected
V-SYNC width detection
0: Wide
V-SYNC-W
1: Narrow
Detects V-SYNC width for detecting 1250i format.
Under A-SYNC = 1 (ON), V-SYNC-W shows 1 when VD width from VD-IN pin is narrower than approx
69 µs, or when V-SYNC width from SYNC-IN pin is narrower than approx 54 µs.
Polarity detection to HD-IN
HD-POL
0: Positive
1: Negative
Detects the width from the HD-IN pin to determine whether it is negative or not.
When the High level of the input is wider than approx 13.5 us, HD-POL shows 1.
Polarity detection to VD-IN
VD-POL
0: Positive
1: Negative
Detects the width from the VD-IN pin to determine whether it is negative or not.
When the High level of the input is wider than approx 4.5 ms, VD-POL shows 1.
Horizontal format detection
H FORMAT
0000: 15.625/15.75 kHz 0001: 28.125 kHz
0010: 31.25/31.5 kHz
0100: 37.5/37.9 kHz
0101: 45/48 kHz
0110: 56.25 kHz
1000: 75 kHz
1001 to 1111: Undefined
0011: 33.75 kHz
0111: 64/67.5 kHz
Detects a horizontal format (horizontal frequency).
Vertical format detection
V FORMAT
000: 50 Hz
100: 25 Hz
001: 60 Hz
101: 24 Hz
010: 48 Hz
110 to 111: Undefined
011: 30 Hz
Detects a vertical format (horizontal frequency) according to V FREQ DET data.
Voltage detection of FB pin for SCART connector
FB DET1(2)
0: Not always high
1: Always high
Detects the voltage of FB-IN pin, selected by FB1(2) OUT (to pin 9 (22)) to determine whether the
voltage is always high or not.
No-input detection.
0: No input
SIG DET
1: A signal detected
The signal to the no-input detection circuit is selected by SIG SW. Refer to the relevant functions for H
COUNT MAX, H COUNT MIN, SIG DET N, SIG RESET N, SIG RESET, SIG DET IMPE and SIG DET
LVL.
17
2005-12-20
TB1311AFG
Preliminary
Register Name
Function
Format detection result. H and V dummy output frequencies depend on this result.
HV-OUT FORMAT
00000: 15.625 kHz, 50 Hz (625i)
00010: 31.25 kHz, 50 Hz (625p)
00100: 28.125 kHz, 50 Hz (1125/50i)
00110: 37.5 kHz, 50 Hz (750/50p)
01000: 31.25 kHz, 50 Hz (1250i)
01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz)
01100: 56.25 kHz, 50 Hz (1125/50p)
01101 to 01111: Not available
10000: 15.734 kHz, 30 Hz (525/30p)
10010: 28.125 kHz, 25 Hz (1125/25p)
10100: 27 kHz, 48 Hz (1125/24sf)
10101 to 11111: Not available
00001: 15.75 kHz, 60 Hz (525i)
00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz)
00101: 33.75 kHz, 60 Hz (1125/60i)
00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz)
01001: 37.9 kHz, 60 Hz (SVGA @60 Hz)
01011: 75 kHz, 60 Hz (UXGA @60 Hz)
10001: 27 kHz, 24 Hz (1125/24p)
10011: 33.75 kHz, 30 Hz (1125/30p)
DC voltage detection for D-pin or S-pin
00: Low (0 V)
01: Mid (2.2 V)
10: Undefined
11: High (5 V)
Remark 1: See below for the relationship between this function number and the pin number.
DC1 - pin 39, DC2 - pin 40, DC3 - pin 44, DC4 - pin 46, DC5 - pin 48, DC6 - pin 50, DC7 - pin 60,
DC8 - pin 64, DC9 - pin 66, DC10 - pin 68, DC11 - pin 70, DC12 - pin 80
DC1 to 12
Remark 2; D-pin
SW LINE:
LINE1:
LINE2:
LINE3:
00: Connected
00: 525 (480)
00: Interlace
00: 4:3
Remark 3; about S-pin
00: 4:3
01: ---01: 750 (720)
01: ---01: 4:3 letter box
10: ---10: ---10: ---10: ----
11: Not connected
11: 1125 (1080)
11: Progressive
11: 16:9
01: 4:3 letter box
10: ----
11: 16:9
Detects whether S-pin is connected or not.
0: Low (not connected)
S1 to 8
1: Open (connected)
Remark 1:
An external circuit is necessary to use this function. Refer to the Function description.
Remark 2: See below for the relationship between this function number and the pin number.
S1 - pin 45, S2 - pin 47, S3 - pin 53, S4 - pin 59, S5 - pin 65, S6 - pin 67, S7 - pin 73, S8 - pin 79
Counts the vertical frequency of an input selected by SYNC SW.
When V-DET = 0:
00000000: over 3.5 kHz
01001111: 44 Hz or less
01010000 to 11111111: No input
V FREQ DET
When V-DET = 1:
00000000: over 3.5 kHz
10011001: 23 Hz or less
10011010 to 11111111: No input
How to calculate a vertical frequency (Y):
Convert data read from V FREQ DET into a decimal value and call it X.
Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4)
[Hz]
The error range of X is −1 to +1.
Counts the horizontal frequency of an input selected by SYNC SW.
H FREQ DET
When for SYNC-IN;
00000001: No input
11111111: over 85 kHz
When for HD/VD-IN;
00000000: No input
11111111: over 85 kHz
How to calculate a horizontal frequency (Y):
Convert data read from H FREQ DET into a decimal value and call it X.
Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X)
[Hz]
The error range of X is −1 to +1.
Note 1: In determining the decision algorithms (detection range, detection times, and so on) for H/V frequency
detection, it is necessary to take into account both previously mentioned cautions and other factors such as
2
signal conditions and I CBUS data transmission in the course of prototype TV set evaluation.
Note 2: The READ BUS flags indicate that a certain signal is detected at a given moment. However, the detection
result will not be very reliable if only one flag is checked. To obtain accuracy, it is recommended that a
judgment should be made on the basis of confirming several times and verifying agreement among the
majority of flags read in a sequence and/or at the same time.
18
2005-12-20
TB1311AFG
Preliminary
Function Descriptions
Output selections
Outputs are switched by I2CBUS registers, as in the following tables.
YCbCr1 OUT
Register Settings
CbCr1 OUT CbCr PIN4CbCr PIN3 bCr PIN2CbCr PIN1
Y1/G1 OUT
(Pin 6)
Outputs
Cb1/B1 OUT
(Pin 8)
Cr1/R1 OUT
(Pin 10)
Available Input
YCbCr
CVBS
YC
RGB
0000
∗
∗
∗
∗
Mute
Mute
Mute
0001
∗
∗
∗
∗
SY1 (pin 57)
SC1 (pin 59)
Mute
y
y
0010
∗
∗
∗
∗
SY2 (pin 77)
SC2 (pin 79)
Mute
y
y
0011
∗
∗
∗
∗
CVBS3 (pin 36)
Mute
Mute
y
y
0100
0101
0110
0111
1000
1001
∗
∗
∗
∗
CVBS4 (pin 38)
Mute
Mute
∗
∗
∗
0
CVBS5 (pin 41)
Mute
Mute
y
∗
∗
∗
1
CVBS5 (pin 41)
Cr1 (pin 45)
Mute
y
∗
∗
0
∗
CVBS6 (pin 61)
Mute
Mute
y
∗
∗
1
∗
CVBS6 (pin 61)
Cr2 (pin 65)
Mute
y
y
∗
∗
∗
0
Y1 (pin 49)
Cb1 (pin 47)
Cr1 (pin 45)
y
y
∗
∗
∗
1
Y1 (pin 49)
Cb1 (pin 47)
Mute
y
y
∗
∗
0
∗
Y2 (pin 69)
Cb2 (pin 67)
Cr2 (pin 65)
y
y
∗
∗
1
∗
Y2 (pin 69)
Cb2 (pin 67)
Mute
y
y
∗
0
∗
∗
Y3 (pin 55)
Cb3 (pin 53)
Cr3 (pin 51)
y
y
∗
1
∗
∗
Y3 (pin 55)
Cb3 (pin 53)
Mute
y
y
y
0
∗
∗
∗
Y4 (pin 75)
Cb4 (pin 73)
Cr4 (pin 71)
y
y
1
∗
∗
∗
Y4 (pin 75)
Cb4 (pin 73)
Mute
y
y
1011
∗
∗
∗
∗
Cr3 (pin 51)
Mute
Mute
y
1100
∗
∗
∗
∗
Cr4 (pin 71)
Mute
Mute
y
1101 to
1111
∗
∗
∗
∗
1010
y
y
y
y
Not available
∗: Don’t care
YCbCr2 OUT
Register Settings
CbCr1 OUT bCr PIN4CbCr PIN3 bCr PIN2CbCr PIN1
Y2/G2 OUT
(Pin 19)
Outputs
Cb2/B2 OUT
(Pin 21)
Cr2/R2 OUT
(Pin 23)
Available Input
YCbCr
CVBS
YC
RGB
0000
∗
∗
∗
∗
Mute
Mute
Mute
0001
∗
∗
∗
∗
SY1 (pin 57)
SC1 (pin 59)
Mute
y
y
0010
∗
∗
∗
∗
SY2 (pin 77)
SC2 (pin 79)
Mute
y
y
0011
∗
∗
∗
∗
CVBS3 (pin 36)
Mute
Mute
y
0100
∗
∗
∗
∗
CVBS4 (pin 38)
Mute
Mute
y
∗
∗
∗
0
CVBS5 (pin 41)
Mute
Mute
y
∗
∗
∗
1
CVBS5 (pin 41)
Cr1 (pin 45)
Mute
y
∗
∗
0
∗
CVBS6 (pin 61)
Mute
Mute
y
0101
0110
0111
1000
y
∗
∗
1
∗
CVBS6 (pin 61)
Cr2 (pin 65)
Mute
y
y
∗
∗
∗
0
Y1 (pin 49)
Cb1 (pin 47)
Cr1 (pin 45)
y
y
∗
∗
∗
1
Y1 (pin 49)
Cb1 (pin 47)
Mute
y
y
∗
∗
0
∗
Y2 (pin 69)
Cb2 (pin 67)
Cr2 (pin 65)
y
y
∗
∗
1
∗
Y2 (pin 69)
Cb2 (pin 67)
Mute
y
y
∗
0
∗
∗
Y3 (pin 55)
Cb3 (pin 53)
Cr3 (pin 51)
y
y
∗
1
∗
∗
Y3 (pin 55)
Cb3 (pin 53)
Mute
y
y
0
∗
∗
∗
Y4 (pin 75)
Cb4 (pin 73)
Cr4 (pin 71)
y
y
1
∗
∗
∗
Y4 (pin 75)
Cb4 (pin 73)
Mute
y
y
1011
∗
∗
∗
∗
Cr3 (pin 51)
Mute
Mute
y
1100
∗
∗
∗
∗
Cr4 (pin 71)
Mute
Mute
y
1101 to
1111
∗
∗
∗
∗
1001
1010
y
y
y
y
Not available
∗: Don’t care
19
2005-12-20
TB1311AFG
Preliminary
MONITOR OUT
Register Settings
MON OUT
0000
0001
0010
YC MIX CbCr PIN4 CbCr PIN3 CbCr PIN2 CbCr PIN1
∗
0
1
0
1
∗
∗
∗
∗
∗
∗
Outputs
MONITOR OUT
(Pin 2)
∗
Mute
∗
SY1 (pin 57)
SY2 (pin 77)
∗
∗
∗
∗
∗
CVBS3 (pin 36)
∗
∗
∗
0100
∗
∗
∗
∗
∗
CVBS4 (pin 38)
∗
∗
∗
∗
0
CVBS5 (pin 41)
0
∗
∗
∗
1
∗
∗
∗
0
∗
0
∗
∗
1
∗
0110
1
0111
1000
1001
1010
0
1
0
1
0
1
0
1
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
CVBS5 (pin 41)
y
y
y
y
y
y
y
y
CVBS5 (pin 41) + Cr1 (pin 45)
CVBS6 (pin 61)
CVBS6 (pin 61)
y
y
y
CVBS6 (pin 61) + Cr2 (pin 65)
Y1 (pin 49)
y
y
Y1 (pin 49) + Cb1 (pin 47)
Y2 (pin 69)
y
y
Y2 (pin 69) + Cb2 (pin 67)
Y3 (pin 55)
y
y
Y3 (pin 55) + Cb3 (pin 53)
Y4 (pin 75)
y
y
Y4 (pin 75) + Cb4 (pin 73)
1011
∗
∗
∗
∗
∗
1100
∗
∗
∗
∗
∗
Cr4 (pin 71)
1101 to 1111
∗
∗
∗
∗
∗
Not available
Cr3 (pin 51)
YC
y
SY2 (pin 77) + SC2 (pin 79)
∗
1
CVBS
SY1 (pin 57) + SC1 (pin 59)
0011
0101
Available Input
y
y
∗: Don’t care
20
2005-12-20
Preliminary
TB1311AFG
Vertical sync separation for 1250i/50
When HV FREQ2 = 01000, the vertical sync separation for the 1250i/50 is accomplished through the use of a special
circuit. The phase of the VD-out (pin 13) depends on the H-SYNC timing shown in the figure below. There is no VD-out
when there is no H-SYNC input.
In the manual sync processing mode (A-SYNC = OFF), use READ BUS functions, V-SYNC-W and H, V FORMAT (or H,
V FREQ DET) to detect the 1250i/50.
Note: The tailing edge of the VD-OUT has a jitter. Use the leading edge only.
HD width
HD-OUT width is selectable by HD WIDTH as below. A setting in which HD WIDTH = 1 (NARROW) is recommended
for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals causing spike noise on video signals.
1125/60p signal
SYNC-IN
(Y-IN)
HD-OUT
(HD WIDTH = 1)
0.7 s (typ.)
HD-OUT
(HD WIDTH =0 )
1.7 s (typ.)
HD/VD input amplitude
When a 5.6 kΩ is added before the input pin like the following figure, 5.0 Vp-p pulse input is allowed. However, the
acceptable minimum amplitude then becomes 2.0 Vp-p.
Normal application
For large-input application
21
2005-12-20
TB1311AFG
Preliminary
Automatic sync processing mode (A-SYNC)
Counted horizontal and vertical frequency data to input signal are returned to READ BUS functions, H, V FREQ DET.
Also, the detected format is returned to H, V FORMAT and H, V FM2 when the H/V frequencies are in internal defined
ranges. Input detection results for H, V-SYNC or HD,VD, which indicate whether or not input exists, are returned to H,V
IN. HV-OUT FORMAT indicates the active mode.
In automatic sync processing mode (when A-SYNC = ON), this device operates as indicated in the following table
according to these READ data. Then, the SYNC1-IN pin is not used for format detection.
Input Condition
Standard format
HV-OUT FORMAT,
H, V FORMAT Status
H, V FM2 Status
H, V IN Status
Known
Signal
The format as input
HD, VD Outputs
The separated sync as
input
The status indicates not
The separated sync as
the current condition
Unknown
Signal
input
but the last detected
format.
Dummy HD and VD, of
Known:
The status indicates not
which the frequency
The status indicates not
the current condition
No input
No input
depends on the HV-OUT
the current condition but
but the last detected
FORMAT status
the last detected format.
format.
Note 3: Dummy HD and VD may become unstable while the mode is changing from one format to another.
Nonstandard
format
Manual sync processing mode (A-SYNC = OFF)
In this mode, the SYNC1-IN pin is used only for detecting the input format and the SYNC2-IN pin is used only for
separating H and V syncs for HD and VD outputs. It is possible to detect some input formats by means of time-sharing
while separating syncs to another input.
The following is an example of how to detect H/V frequency when A-SYNC = OFF.
1. Input the signal from Yvi-OUT pin into the SYNC1-IN pin.
2. Read data such as H, V FREQ DET and H, V FORMAT.
3. Detect the H/V frequency by microprocessor or similar means, depending on the data obtained.
4. Input the detected signal into the SYNC2-IN pin and set HV FREQ2 and so on for the SYNC2-IN pin to the
detected mode.
5. Continue to monitor the obtained data for the SYNC1-IN pin, such as H, V FREQ DET and H, V FORMAT. When
any alterations are recognized, re-set HV FREQ2 and so on for the SYNC2-IN pin.
Decision algorithms (for detection range, detection times and so on) for H/V frequency detection should be determined
taking into account the above-mentioned errors in measuring H/V frequencies and other factors such as signal
2
conditions and I CBUS data transmission in the course of prototype TV set evaluation.
By the way, in A-SYNC = OFF and H, V DMY = ON mode, dummy HD and VD are output according to the HV
FREQ2 setting when there is no input.
S
U
B
C
2
I
S
U
B
C
2
I
Fig. Signal route when A-SYNC = ON
Fig. Signal route when A-SYNC = OFF
22
2005-12-20
Preliminary
TB1311AFG
Sync separation level
The sync separation level is changed according to the ratio of H-sync width to one line. Typical sync separation levels
for each format are as follows.
HV-SEP data
625/50i
525/60i
625/50p
525/60p
1125/50i
1125/60i
750/50p
750/60p
1250/50i
1125/50p
1125/60p
525/30p
1125/24p
1125/25p
1125/30p
1125/24sf
VGA/60
SVGA/60
XGA/60
SXGA/60
00
01
10
11
18
18
19
19
27
25
25
24
22
28
27
18
27
27
26
28
20
20
20
22
26
26
27
27
34
33
32
31
30
36
34
26
34
34
32
34
26
27
27
29
31
31
32
32
40
38
38
36
36
41
39
31
40
40
38
40
32
33
33
34
43
43
44
44
52
50
50
49
48
52
52
43
52
52
50
52
43
44
44
45
Expressed as percentages, where 286 mVp-p sync applies to 525/60i and 300 mVp-p sync applies otherwise
The format detection and sync separation performances are changed due to the separation level set by HV-SEP setting
and the connected coupling capacitor value. The careful evaluations are required to set the separation level under
consideration of expected input conditions such as a suppressed sync input, an input with V-sag, and APL (Average
Picture Level) fluctuations.
For “Sync on G” signal, HD-OUT is not output during the V-sync period because there is no H-sync during the V-sync
period.
23
2005-12-20
TB1311AFG
Preliminary
No-input detection
This function detects whether there is input or not. It is useful for detecting no-input of 525i or 625i even if which is a
weakened signal strength.
(1)0 (no-input) ! 1 (detected)
When Nmin
N1
Nmax, and when N2
Ndet, SIG DET returns 1.
Where, Nmin: the number set by H COUNT MIN
Nmax: the number set by H COUNT MAX
Ndet: the number set by SIG DET N
N1: the number of the H-sync count in the counter during an internal window (approx. 2 ms)
N2: the number of conditions that “Nmin
N1
Nmax” is detected
҇
҇
҈
҇
҇
(2) 1 (detected) ! 0 (no-input)
When N1
Nmin, N1
Nmax, and when N3
Nreset, SIG DET returns 0.
Where, Nreset: the number set by SIG RESET N
N3: the number of conditions that “N1
Nmin and N1
Nmax” is detected
҇
҈
҈
҇
҈
inp
R
E
T
LI
F
C
N
Y
S
.p
a
C
.t
x
E
Fig. Block diagram for no-input detection
Decide how to use no-input detection after making a thorough evaluation using a prototype TV set.
24
2005-12-20
TB1311AFG
Preliminary
S-pin insertion detection
C-IN pins detect the DC level to determine whether the S-pin is inserted or not.
Fig. Application of S-pin insertion detection
Audio gain
Audio gain is controlled by AU1(2) ATT. The following figure shows the typical characteristic, where the
series-connected resistor is 5.6 kΩ.
㪉㪇
㪇
㪴
㪙㪻
㪲㩷
㫅㫆
㫀㫋
㪸㫌
㫅㪼
㫋㫋
㪘
㪄㪉㪇
㪄㪋㪇
㪄㪍㪇
㪄㪏㪇
㪄㪈㪇㪇
㪇
㪉㪇
㪋㪇
㪍㪇
㪏㪇
㪈㪇㪇
㪈㪉㪇 㪈㪉㪎
㪘㪬㪈㩿㪉㪀㩷㪘㪫㪫㩷㪻㪸㫋㪸
25
2005-12-20
TB1311AFG
Preliminary
Typical characteristics
㪈㪇㪇
㪝㫀㫏㪼㪻㩷㫄㫆㪻㪼㩷㩿㪘㪬㩷㪝㪠㪯㩷㪔㩷㪇㪀
㪘㪫㪫㩷㫄㫆㪻㪼㩷㩿㪘㪬㩷㪝㪠㪯㩷㪔㩷㪈㪃㩷㪘㪬㩷㪘㪫㪫㩷㪔㩷㫄㪸㫏㪀
㪴㩼
㪲㩷 㪈㪇
㫅㫆
㫀㫋
㫉㫆
㫋㫊
㫀㪻
㩷㪺 㪈
㫀㫅
㫆
㫄
㫉㪸
㪿㩷
㫃㪸
㫋㫆 㪇㪅㪈
㪇
㪫
㪇㪅㪇㪈
㪇
㪇㪅㪇
㪇㪅㪌
㪈㪅㪇
㪈㪅㪌
㪉㪅㪇
㪉㪅㪌
㪊㪅㪇
㪠㫅㫇㫌㫋㩷㪲㪭㫉㫄㫊㪴
Fig. Audio total harmonic distortion (input resistance: 5.6 kΩ)
㪈㪇
㪇
㪴 㪄㪈㪇
㪙㪻
㪲㩷
㫀㫅㪸 㪄㪉㪇
㪞
㪄㪊㪇
㪽㪇㩷㪪㪮㩷㪔㩷㫃㫆㫎㪃㩷㪙㪘㪥㪛㪮㪠㪛㪫㪟㩷㪔㩷㫄㫀㫅㪃㩷㪽㪺㩷㪟㪘㪣㪝㩷㪔㩷㫆㫅
㪽㪇㩷㪪㪮㩷㪔㩷㫃㫆㫎㪃㩷㪙㪘㪥㪛㪮㪠㪛㪫㪟㩷㪔㩷㫄㫀㫅
㪄㪋㪇
㪽㪇㩷㪪㪮㩷㪔㩷㪿㫀㪾㪿㪃㩷㪙㪘㪥㪛㪮㪠㪛㪫㪟㩷㪔㩷㫄㫀㫅
㪽㪇㩷㪪㪮㩷㪔㩷㪿㫀㪾㪿㪃㩷㪙㪘㪥㪛㪮㪠㪛㪫㪟㩷㪔㩷㫄㪸㫏
㪄㪌㪇
㪇㪅㪈
㪈
㪈㪇
㪈㪇㪇
㪝㫉㪼㫈㫌㪼㫅㪺㫐㩷㪲㪤㪟㫑㪴
Fig. Typical prefilter frequency characteristics
26
2005-12-20
TB1311AFG
Preliminary
㪌㪇
㪽㫆㩷㪪㪮㩷㪔㩷㪿㫀㪾㪿
㪽㫆㩷㪪㪮㩷㪔㩷㫃㫆㫎
㪴㫑
㪟
㪤
㪲㩷 㪋㪇
㪀㫋
㫅㫀
㫆㫇
㩷 㪊㪇
㪙㪻
㩷㪊
㪄㩿
㩷㫐
㪺㫅 㪉㪇
㪼㫌
㫈㪼
㪽㫉㩷
㪽㪽 㪈㪇
㫋㫆㫌
㪚
㪽㫆㩷㪪㪮㩷㪔㩷㪿㫀㪾㪿㪃㩷㪽㪺㩷㪟㪘㪣㪝㩷㪔㩷㫆㫅
㪽㫆㩷㪪㪮㩷㪔㩷㫃㫆㫎㪃㩷㪽㪺㩷㪟㪘㪣㪝㩷㪔㩷㫆㫅
㪇
㪇
㪉㪇
㪋㪇
㪍㪇
㪏㪇
㪈㪇㪇
㪈㪉㪇 㪈㪉㪎
㪙㪘㪥㪛㪮㪠㪛㪫㪟㩷㪻㪸㫋㪸
Fig. Typical cutoff frequency (-3 dB point) characteristics of prefilter
㪉㪌㪇
㪽㫆㩷㪪㪮㩷㪔㩷㪿㫀㪾㪿
㪽㫆㩷㪪㪮㩷㪔㩷㫃㫆㫎
㪉㪇㪇
㪽㫆㩷㪪㪮㩷㪔㩷㪿㫀㪾㪿㪃㩷㪽㪺㩷㪟㪘㪣㪝㩷㪔㩷㫆㫅
㪽㫆㩷㪪㪮㩷㪔㩷㫃㫆㫎㪃㩷㪽㪺㩷㪟㪘㪣㪝㩷㪔㩷㫆㫅
㪴㫊
㫅㪲 㪈㪌㪇
㩷㪼
㫀㫄
㫋㩷
㫐㪸
㫃㪼 㪈㪇㪇
㪛
㪌㪇
㪇
㪇
㪉㪇
㪋㪇
㪍㪇
㪏㪇
㪈㪇㪇
㪈㪉㪇 㪈㪉㪎
㪙㪘㪥㪛㪮㪠㪛㪫㪟㩷㪻㪸㫋㪸
Fig. Typical delay-time (group delay @ 1 MHz) characteristics of prefilter
Recommended crystal oscillator
When a connected crystal oscillator is used for the XO, the following oscillation specifications are required.
Oscillation frequency (fundamental): 3.579545 MHz (for NTSC decoding)
Frequency tolerance: +/- 50 ppm
External CW input into crystal oscillator pin
Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 28 through a
capacitor as below.
The required specs on the CW are as follows.
Input frequency (fundamental): 3.579545 MHz +/- 50 ppm
Input amplitude: 1.0Vp-p +/- 0.5Vp-p
27
2005-12-20
TB1311AFG
Preliminary
How to deal with unused pins
Unused pins should be dealt with as below. Pins not mentioned below should be connected properly.
Pin No.
Pin Name
Procedure
Pin No.
Pin Name
Procedure
1
AL3 OUT
Procedure 3
46
AR9 IN/DC4
Procedure 1
2
MONITOR OUT
Procedure 3
47
Cb1/B1 IN
Procedure 1
3
AR3 OUT
Procedure 3
48
AL9 IN/DC5
Procedure 1
4
CVBS1 OUT
Procedure 3
49
Y1/G1 IN
Procedure 1
5
AL1 OUT
Procedure 3
50
FB3 IN/DC6
Procedure 2
6
Y1/G1 OUT
Procedure 3
51
Cr3/R3 IN
Procedure 1
7
AR1 OUT
Procedure 3
52
AR3 IN
Procedure 1
8
Cb1/B1 OUT
Procedure 3
53
Cb3/B3-IN
Procedure 1
9
FB1 OUT
Procedure 3
54
AL3 IN
Procedure 1
10
Cr1/R1 OUT
Procedure 3
55
Y3/G3 IN
Procedure 1
12
HD OUT
Procedure 3
56
AR4 IN
Procedure 1
13
VD OUT
Procedure 3
57
SY1 IN
Procedure 1
14
SYNC FILTER
Procedure 3
58
AL4 IN
Procedure 1
15
SYNC2 IN
Procedure 1
59
SC1 IN
Procedure 1
17
CVBS2 OUT
Procedure 3
60
DC7
Procedure 2
18
AL2 OUT
Procedure 3
61
CVBS6 IN
Procedure 1
19
Y2/G2 OUT
Procedure 3
62
AR5 IN
Procedure 1
20
AR2 OUT
Procedure 3
63
AL5 IN
Procedure 1
21
Cb2/B2 OUT
Procedure 3
64
FB2 IN/DC8
Procedure 2
22
FB2 OUT
Procedure 3
65
Cr2/R2 IN
Procedure 1
23
Cr2/R2 OUT
Procedure 3
66
AR10 IN/DC9
Procedure 1
30
VD IN
Procedure 4
67
Cb2/B2 IN
Procedure 1
31
HD IN
Procedure 4
68
AL10 IN/DC10
Procedure 1
33
SYNC1 IN
Procedure 1
69
Y2/G2 IN
Procedure 1
34
Yvi OUT
Procedure 3
70
FB4 IN/DC11
Procedure 2
35
AR1 IN
Procedure 1
71
Cr4/R4 IN
Procedure 1
36
CVBS3 IN
Procedure 1
72
AR6 IN
Procedure 1
37
AL1 IN
Procedure 1
73
Cb4/B4-IN
Procedure 1
38
CVBS4 IN
Procedure 1
74
AL6 IN
Procedure 1
39
AR8 IN/DC1
Procedure 1
75
Y4/G4 IN
Procedure 1
40
AL8 IN/DC2
Procedure 1
76
AR7 IN
Procedure 1
41
CVBS5 IN
Procedure 1
77
SY2 IN
Procedure 1
42
AR2 IN
Procedure 1
78
AL7 IN
Procedure 1
43
AL2 IN
Procedure 1
79
SC2 IN
Procedure 1
44
FB1 IN/DC3
Procedure 2
80
DC12
Procedure 2
45
Cr1/R1 IN
Procedure 1



Procedure 1: Connect a 0.01 µF capacitor between this pin and GND.
Procedure 2: Connect to GND.
Procedure 3: Leave open.
Procedure 4: Connect a 10 kΩ resistor between this pin and GND.
28
2005-12-20
TB1311AFG
Preliminary
2
How to start the I CBUS
After power on, send bus data as follows. Use software to handle the procedure.
1. Turn on the power.
2. Transmit all the write data.
2
How to transmit/receive via the I CBUS
Slave Address: DEH / DFH
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
1
1
0/1
Start and Stop Conditions
SDA
SCL
S
P
Start condition
Stop condition
Bit Transmission
SDA
SCL
SDA must not be changed
SDA may be changed
Acknowledgement
SDA from
transmitter
High impedance at bit 9
SDA from receiver
Low impedance at bit
9 only
SCL from master
1
8
9
S
Clock pulse for acknowledgement
29
2005-12-20
TB1311AFG
Preliminary
Data Transmit Format 1
S
Slave address
7-bit
0 A
MSB
S: Start condition
Sub-address
8-bit
A
Transmit data
8-bit
A P
MSB
MSB
A: Acknowledgement
P: End condition
Data Transmit Format 2
S
Slave address
0 A
Sub-address
㨯㨯㨯㨯㨯㨯
A
Transmit data 1
Sub-address
A
A
㨯㨯㨯㨯㨯㨯 Transmit data n
A P
Data Receive Format
S
Slave address
7-bit
1 A
MSB
Receive data 1
8-bit
㨯㨯㨯㨯㨯㨯㨯㨯㨯
Receive data n
A P
MSB
MSB
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement.
The slave receiver changes to a transmitter.
The end condition is always created by the master.
Optional Data Transmit Format (Automatic Increment Mode)
S
Slave address
7-bit
0 A 1
MSB
Sub-address
7-bit
MSB
A
Transmit data 1
8-bit
MSB
㨯㨯㨯㨯
Transmit data n
8-bit
A P
MSB
In this way, sub-addresses are automatically incremented from the specified sub-address and data are set.
I2CBUS Conditions
Parameter
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
−
1.1
V
High level input voltage
VIH
2.4
−
V/S-Vcc
V
Hysteresis of Schmitt trigger inputs
Vhys
−
0.7
−
V
Low level output voltage at 3 mA sink current
VOL1
0
−
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ii
-10
−
10
µA
Capacitance for each I/O pin
Ci
−
−
10
pF
kHz
SCL clock frequency
Hold time START condition
Low period of SCL clock
fSCL
0
−
400
tHD;STA
0.6
−
−
µs
tLOW
1.3
−
−
µs
tHIGH
0.6
−
−
µs
Set-up time for a repeated START condition
tSU;STA
0.6
−
−
µs
Data hold time
tHD;DAT
0
−
−
ns
Data set-up time
tSU;DAT
100
−
−
ns
Set-up time for STOP condition
tSU;STO
0.6
−
−
µs
tBUF
1.3
−
−
µs
High period of SCL clock
Bus free time between a STOP and START condition
Note: This parameter is not tested during production and is provided only as information to assist the design of applications.
30
2005-12-20
TB1311AFG
Preliminary
Maximum Ratings (Ta = 25°C)
Characteristic
Symbol
Rating
9 V Vcc
VCCmax9
12.0
5 V Vcc
VCCmax5
6.0
3.3 V Vcc
VCCmax3
6.0
Input pin voltage
Vin
GND − 0.3 to Vcc + 0.3
V
Y or Sync input amplitude (pin 15, 33, 36, 38, 41, 49, 51,
55, 57, 61, 69, 71, 75, 77)
Yin
2.0
Vp-p
PD(Note 4)
2451
mW
Power dissipation reduction rate
1/θja
19.6
mW/°C
Operating temperature
Topr
−20 to 75
°C
Storage temperature
Tstg
−55 to 150
°C
Supply voltage
Power dissipation
Unit
V
Note 4: Refer to the figure below. Note, however, that the condition applies only where the device is mounted on a
board 114.3 x 76.2 x t:1.6 mm, Cu 20%. Mount the devive on a board which is larger than it.
Power consumption reduction ratio
PD (mW)
2451
1471
0
0
25
75
150
Ambient temperature Ta (°C)
Figure
PD - Ta Curve
Note 5: Install the product correctly. Otherwise, it may result in break down, damage and/or degration to the product
or equipment.
The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be
exceeded during operation, even for an instant.
If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably
altered and the reliability and lifetime of the device can no longer be guaranteed.
Moreover, these operations with exceeded ratings may cause break down, damage and/or degradation to any other
equipment. Applications using the device should be designed such that each maximum rating will never be exceeded in
any operating conditions.
Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in
this documents.
31
2005-12-20
TB1311AFG
Preliminary
Operating conditions
Characteristic
Description
Min
Typ.
Max
Pin 24
8.5
9.0
9.5
Pin 11
4.7
5.0
5.3
Pin 29; Supply power from V/S Vcc (pin 11) via a
resistor.
3.1
3.3
3.5
Y/G signal input amplitude
Pins 49, 55, 69, 75; with sync

1.0

Vp-p
CVBS/SY input amplitude
Pins 36, 38, 41, 49, 55, 57, 61, 69, 75, 77 (51, 71); with
sync

1.0

Vp-p
Y/G signal input frequency
Pins 49, 55, 69, 75
0

60
MHz
CVBS/SY input frequency
Pins 36, 38, 41, 49, 55, 57, 61, 69, 75, 77 (51, 71)
0

8
MHz
SC (Chroma) signal input amplitude
Pin 59, 79 (45, 47, 53, 65, 67, 73)


2
Vp-p
Cb, Cr, Pb, Pr signal input amplitude
Pins 45, 47, 51, 53, 65, 67, 71, 73; 100% color bar
signal

0.7

Vp-p
Cb, Cr, Pb, Pr signal input frequency
Pins 45, 47, 51, 53, 65, 67, 71, 73
0

60
MHz
R, G, B signal input amplitude
Pins 45, 47, 49, 51, 53, 55, 65, 67, 69, 71, 73, 75;
100% white signal without sync

0.7

Vp-p
R, G, B signal input frequency
Pins 45, 47, 49, 51, 53, 55, 65, 67, 69, 71, 73, 75
0

60
MHz
HD, VD signal input amplitude
Pins 30, 31
1.0

2.0
Vp-p
HD input frequency
Pins 31 for freq counter
0

85
kHz
VD input frequency
Pins 30 for freq counter
23

3500
Hz
H
1.0
Pins 44, 50, 64, 70

3.0
FB input level
L
GND

0.4
80


H
3.5

V/S
Vcc
M
1.4
2.2
2.4
L
GND

0.6
L
GND

0.6
V


3
mA
Supply voltage (VCC)
FB input width
DC detection input
voltage
Pins 44, 50, 64, 70
DC1 to 12
S1 to 8
SDA input current
Pins 39, 40, 44, 46, 48, 50, 60, 64, 66,
68, 70, 80
Pins 45, 47, 53, 59, 65, 67, 73, 79
Pins 25
Unit
V
V
ns
V
Remark: Supply power to all Vcc pins (pin 11, 24, 29).
32
2005-12-20
TB1311AFG
Preliminary
Electrical Characteristics
2
(Unless otherwise specified, AU VCC = 9 V, V/S VCC = 5 V, Vdd = 3.3 V, Ta = 25°C, I CBUS data: preset values)
Current Consumption (AU8/9/10 PIN = 1, f0 SW1/2 = 1, BANDWIDTH1/2 = max)
Pin Name
Symbol
Test Conditions
Min
Typ.
Max
AU VCC (pin 24)
ICCAU

7.5
9.5
12.5
V/S VCC (pin 11)
ICCVS

100
125
165
Vdd (pin 29)
ICCD
Resistance to 5 V; R = 180 Ω
6.3
9.4
12.8
Unit
mA
Pin Voltage (test condition: no signal input)
Pin No.
Pin Name
Symbol
Test Conditions
Min
Typ.
Max
1
AL3 OUT
V1
−
3.8
4.1
4.4
2
MONITOR OUT
V2
−
0.9
1.2
1.5
3
AR3 OUT
V3
−
3.8
4.1
4.4
4
CVBS1 OUT
V4
−
1.0
1.3
1.6
5
AL1 OUT
V5
−
3.8
4.1
4.4
6
Y1/G1 OUT
V6
−
1.0
1.3
1.6
7
AR1 OUT
V7
−
3.8
4.1
4.4
8
Cb1/B1 OUT
V8
−
1.0
1.3
1.6
10
Cr1/R1 OUT
V10
−
1.0
1.3
1.6
14
SYNC FILTER
V14
−
3.0
3.3
3.6
15
SYNC2 IN
V15
−
1.5
1.8
2.1
17
CVBS2 OUT
V17
−
1.0
1.3
1.6
18
AL2 OUT
V18
−
3.8
4.1
4.4
19
Y2/G2 OUT
V19
−
1.0
1.3
1.6
20
AR2 OUT
V20
−
3.8
4.1
4.4
21
Cb2/B2 OUT
V21
−
1.0
1.3
1.6
23
Cr2/R2 OUT
V23
−
1.0
1.3
1.6
28
XTAL
V28
−
3.8
4.05
4.3
30
VD IN
V30
−
1.2
1.45
1.7
31
HD IN
V31
−
1.2
1.45
1.7
33
SYNC1 IN
V33
−
1.5
1.8
2.1
34
Yvi OUT
V34
−
1.9
2.2
2.5
35
AR1 IN
V35
−
4.2
4.4
4.6
36
CVBS3 IN
V36
−
2.0
2.3
2.6
37
AL1 IN
V37
−
4.2
4.4
4.6
38
CVBS4 IN
V38
−
2.0
2.3
2.6
39
AR8 IN/DC1
V39
−
4.2
4.4
4.6
40
AL8 IN/DC2
V40
−
4.2
4.4
4.6
33
Unit
V
2005-12-20
TB1311AFG
Preliminary
Pin No.
Pin Name
Symbol
Test Conditions
Min
Typ.
Max
41
CVBS5 IN
V41
−
2.0
2.3
2.6
42
AR2 IN
V42
−
4.2
4.4
4.6
43
AL2 IN
V43
−
4.2
4.4
4.6
45
Cr1/R1 IN
V45
−
2.6
2.9
3.2
46
AR9 IN/DC4
V46
−
4.2
4.4
4.6
47
Cb1/B1 IN
V47
−
2.6
2.9
3.2
48
AL9 IN/DC5
V48
−
4.2
4.4
4.6
49
Y1/G1 IN
V49
−
2.0
2.3
2.6
51
Cr3/R3 IN
V51
−
2.6
2.9
3.2
52
AR3 IN
V52
−
4.2
4.4
4.6
53
Cb3/B3 IN
V53
−
2.6
2.9
3.2
54
AL3 IN
V54
−
4.2
4.4
4.6
55
Y3/G3 IN
V55
−
2.0
2.3
2.6
56
AR4 IN
V56
−
4.2
4.4
4.6
57
SY1 IN
V57
−
2.0
2.3
2.6
58
AL4 IN
V58
−
4.2
4.4
4.6
59
SC1 IN
V59
−
2.6
2.9
3.2
61
CVBS6 IN
V61
−
2.0
2.3
2.6
62
AR5 IN
V62
−
4.2
4.4
4.6
63
AL5 IN
V63
−
4.2
4.4
4.6
65
Cr2/R2 IN
V65
−
2.6
2.9
3.2
66
AR10 IN/DC9
V66
−
4.2
4.4
4.6
67
Cb2/B2 IN
V67
−
2.6
2.9
3.2
68
AL10 IN/DC10
V68
−
4.2
4.4
4.6
69
Y2/G2 IN
V69
−
2.0
2.3
2.6
71
Cr4/R4 IN
V71
−
2.6
2.9
3.2
72
AR6 IN
V72
−
4.2
4.4
4.6
73
Cb4/B4 IN
V73
−
2.6
2.9
3.2
74
AL6 IN
V74
−
4.2
4.4
4.6
75
Y4/G4 IN
V75
−
2.0
2.3
2.6
76
AR7 IN
V76
−
4.2
4.4
4.6
77
SY2 IN
V77
−
2.0
2.3
2.6
78
AL7 IN
V78
−
4.2
4.4
4.6
79
SC2 IN
V79
−
2.6
2.9
3.2
34
Unit
V
2005-12-20
TB1311AFG
Preliminary
Audio Block
Characteristic
Symbol
Min
Typ
Max
-1.0
0
1.0

-90
-80
0
1.0
2.0
100



0.02
0.05

0.1
0.3
Note A, Note B
5.6
6.5

Vp-p
Offset on AU1(2,3) OUT between
AU1(2,3) OUT = 0000 to 1010
-30
0
30
mV
Vattof
Offset on AU1(2) OUT between
AU1(2) ATT = max to min
-100
0
100
mV
Vrrr
100 Hz and 100 mVp-p ripple is
added to AU Vcc, Note A
30
45

dB
Mute mode attenuation
Gaumute
Input = 2.8Vp-p, 1 kHz, Note A
75
85

dB
Crosstalk among inputs
Gaucrs
Input = 2.8Vp-p, 1 kHz, Note A
75
85

dB
S/N ratio
Gausn
Input = 2.8Vp-p, 1 kHz, Note A
80
90

dB
Imau1
Pins 35, 37, 42, 43, 52, 54, 56, 58,
62, 63, 72, 74, 76, 78
65
87
109
Imau2
AU8/9/10 = 1 (Audio input mode),
Pins 39, 40, 46, 48, 66, 68
65
87
109
Imaudc
AU8/9/10 = 0 (DC input mode),
Pins 39, 40, 46, 48, 66, 68
122
163
204
I/O gain for Fixed mode
(AL/AR1, AL/AR2, AL/AR3)
I/O gain for ATT mode
(AL/AR1, AL/AR2)
Gauf
AU ATT = min
Gaumin
AU ATT = max
Gaumax
I/O frequency characteristic
fau
Total harmonic distortion Fixed mode
(AL/AR1, AL/AR2, AL/AR3)
thdf
Total harmonic distortion for
ATT mode
(AL/AR1, AL/AR2)
Test Conditions
Input = 2.8 Vp-p, 1 kHz,
input resistance 5.6 kΩ
-3 dB point, Note A
input = 2.8 Vp-p 1 kHz, Note A
AU ATT
= max
thdmax
Input dynamic range
Vdyau
Output offset voltage
Vauswof
ATT Control offset
Ripple rejection ratio
Input impedance of input pins
Unit
dB
kHz
%
kΩ
Note A: This parameter is not tested during production and is provided only as information to assist the design of applications.
Note B: Input = 1 kHz. The amplitude when the total harmonic distortion becomes 1%.
Video Block
Characteristic
Input dynamic
range
I/O gain
Symbol
Sync-tip clamp mode
Vdsync
Bias mode
Vdbias
Monitor out
Vdmoni
GAIN = -3 dB
G-3
GAIN = 0 dB
G0
GAIN = +3 dB
G+3
GAIN = +6 dB
Yvi-OUT
Test Conditions
FILPASS = 0, BANDWIDTH = max,
Sine wave input for Bias mode, Y
with sync for others.
Min
Typ.
Max
1.5
1.7

1.4
2.1

1.35
1.5

CVBS-OUT, YCbCr-OUT
FILPASS = 0/1, input = 0.2Vp-p 10
kHz, BANDWIDTH = cnt, f0 SW = 1
-3.5
-3.0
-2.5
-0.5
0
0.5
2.5
3.0
3.5
G+6
MONITOR OUT
5.5
6.0
6.5
Gyvi
Yvi-OUT
-0.5
0
0.5
Gycmy
SY-IN to MONITOR-OUT, no input
into SC-IN, YC MIX = 1
5.5
6.0
6.5
Gycmc
SC-IN to MONITOR-OUT, no input
into SY-IN, YC MIX = 1
5.5
6.0
6.5
YC MIX gain
Unit
Vp-p
dB
dB
35
2005-12-20
TB1311AFG
Preliminary
Characteristic
I/O frequency
characteristic 1-1
(YCbCr)
I/O frequency
characteristic 1-2
(YCbCr)
I/O frequency
characteristic 1-3
(YCbCr)
I/O frequency
characteristic 1-4
(CbCr)
I/O frequency
characteristic 1-5
(CbCr)
YCbCr GAIN = -3 dB
YCbCr GAIN = 0 dB
YCbCr GAIN = +3 dB
Symbol
fg-3
fg0
fLmax
BANDWIDTH = cnt
fLcnt
BANDWIDTH = min
fLmin
BANDWIDTH = max
fHmax
BANDWIDTH = cnt
fHcnt
BANDWIDTH = min
fHmin
BANDWIDTH = max
fhfLmax
BANDWIDTH = cnt
fhfLcnt
BANDWIDTH = min
fhfLmin
BANDWIDTH = max
fhfHmax
BANDWIDTH = cnt
fhfHcnt
BANDWIDTH = min
fhfHmin
YCbCr GAIN = -3 dB
Differential 1-2 of
frequency
characteristic
among YCbCr
outputs
BANDWIDTH = max
Differential 1-3 of
frequency
characteristic
among YCbCr
outputs
YCbCr GAIN = 0 dB
YCbCr GAIN = +3 dB
FILPASS = 0, GAIN = 00, f0 SW = 0,
0.2 Vp-p input, -3 dB point, Note A
FILPASS = 0, GAIN = 00, f0 SW = 1,
0.2 Vp-p input, -3 dB point, Note A
FILPASS = 0, GAIN = 00, f0 SW = 0,
fc HALF = 1, -3 dB point, Note A
FILPASS = 0, GAIN = 00, f0 SW = 1,
fc HALF = 1, 0.2 Vp-p input, -3 dB
point, Note A
fdg-3
fdg0
FILPASS = 1, 0.2 Vp-p input, -3 dB
point, Note A
fdg+3
fdHmax
BANDWIDTH = cnt
fdLcnt
BANDWIDTH = min
fdHmin
BANDWIDTH = max
fdHmax
BANDWIDTH = cnt
fdHcnt
BANDWIDTH = min
fdHmin
YCbCr GAIN = -3 dB
FILPASS = 1, 0.2 Vp-p input, -3 dB
point, Note A
fg+3
BANDWIDTH = max
Differential 1-1 of
frequency
characteristic
among YCbCr
outputs
Test Conditions
FILPASS = 0, f0 SW = 0, 0.2 Vp-p
input, -3 dB point, Note A
FILPASS = 0, f0 SW = 1, 0.2 Vp-p
input, -3 dB point, Note A
TdL-3
I/O delay time 1-1
(YCbCr)
YCbCr GAIN = 0 dB
YCbCr GAIN = +3 dB
BANDWIDTH = max
TdL0
TdL+3
TdLmax
I/O delay time 1-2
(YCbCr)
BANDWIDTH = cnt
TdLcnt
BANDWIDTH = min
TdLmin
BANDWIDTH = max
TdHmax
I/O delay time 1-3
(YCbCr)
FILPASS = 1, 1 MHz, Note A
BANDWIDTH = cnt
TdHcnt
BANDWIDTH = min
TdHmin
FILPASS = 0, GAIN = 00, f0 SW = 0,
1 MHz, Note A
FILPASS = 0, GAIN = 00, f0 SW = 1,
1 MHz, Note A
36
Min
Typ.
Max
80
100

80
100

80
100

14.0
16.5
18.0
9.5
10.5
11.5
4.2
4.7
5.2
41
46
51
27
30.3
34
12
13.4
15
7.4
8.3
9.1
4.6
5.2
5.8
2.1
2.4
2.6
21
24.1
27
14
15.7
18
6.0
6.8
8.0

0


0


0

-0.90
0
0.90
-0.5
0
0.5
-0.23
0
0.23
-3.2
0
3.2
-1.05
0
1.05
-0.70
0
0.70

4
10

4
10

4
10
28
33
38
45
48
55
96
107
120
10
16
20
15
20
25
35
39
45
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
2005-12-20
TB1311AFG
Preliminary
Characteristic
Symbol
Test Conditions
Min
55
60
65
FILPASS = 0, GAIN = 00, f0 SW = 0,
fc HALF = 1, 1 MHz, Note A
80
91
100
190
220
260
20
24
30
29
34
39
BANDWIDTH = max TdhfLmax
I/O delay time 1-4
(CbCr)
BANDWIDTH = cnt
TdhfLcnt
BANDWIDTH = min
TdhfLmin
BANDWIDTH = max TdhfHmax
I/O delay time 1-5
(CbCr)
Differential 1-1 of
delay time among
YCbCr outputs
TdhfHcnt
BANDWIDTH = min
TdhfHmin
66
72
80
YCbCr GAIN = -3 dB
Tddg-3
-10
0
10
YCbCr GAIN = 0 dB
Tddg0
-10
0
10
-10
0
10
-10
0
10
-10
0
10
-10
0
10
0
8
20
5
14
20
25
33
45
BANDWIDTH = max
TddHmax
TddHcnt
BANDWIDTH = min
TddHmin
Differential 1-3 of
delay time
between Y and
Cb/Cr outputs
BANDWIDTH = max
TddHmax
BANDWIDTH = cnt
TddHcnt
BANDWIDTH = min
TddHmin
Differential 1-4 of
delay time
between Cb and
Cr outputs
BANDWIDTH = max
TddHmax
BANDWIDTH = cnt
TddHcnt
BANDWIDTH = min
TddHmin
I/O frequency
characteristic 2-1
CVBS GAIN = -3 dB
I/O frequency
characteristic 2-2
(CVBS)
FILPASS = 1, 1 MHz, Note A
Tddg+3
BANDWIDTH = cnt
(CVBS)
FILPASS = 0, f0 SW = 0, 1 MHz,
Note A
FILPASS = 0, f0 SW = 1,
fc HALF = 1, 1 MHz, Note A
FILPASS = 0, f0 SW = 0,
fc HALF = 1, 1 MHz, Note A
fg-3c
CVBS GAIN = 0 dB
fg0c
CVBS GAIN = +3 dB
fg+3c
BANDWIDTH = max
fmaxc
FILPASS = 1, 0.2 Vp-p input, -3 dB
point, Note A
FILPASS = 0, GAIN = 00, 0.2 Vp-p
input, -3 dB point, Note A
0
10
0
10
-20
0
20
60
80

60
80

60
80

14.0
16.4
18.0
9.5
10.6
11.5
fcntc
BANDWIDTH = min
fminc
4.1
4.6
4.9
CVBS GAIN = -3 dB
TdL-3

5
10
CVBS GAIN = 0 dB
TdL0

5
10
CVBS GAIN = +3 dB
TdL+3

5
10
30
34
40
45
49
55
100
108
120
BANDWIDTH = max
FILPASS = 1, 1 MHz, Note A
Tdmaxc
I/O delay time 2-2
(CVBS)
-10
-10
BANDWIDTH = cnt
I/O delay time 2-1
(CVBS)
Max
BANDWIDTH = cnt
YCbCr GAIN = +3 dB
Differential 1-2 of
delay time among
YCbCr outputs
FILPASS = 0, GAIN = 00, f0 SW = 1,
fc HALF = 1, 1 MHz, Note A
Typ.
BANDWIDTH = cnt
Tdcntc
BANDWIDTH = min
Tdminc
FILPASS = 0, GAIN = 00,
1 MHz, Note A
Unit
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
I/O frequency characteristic 3
(MONITOR)
fgm
0.2 Vp-p input, -3 dB point, Note A
60
80

MHz
I/O frequency characteristic 4 (Yvi)
fgm
0.2 Vp-p input, -3 dB point, Note A
80
100

MHz
5 MHz sin wave input, Note A

-70
-60
dB

-70
-60

-60
-55

3

Mute mode attenuation
Among input channels
Gmute
Gcrschs
5 MHz sin wave input, Note A
Crosstalk
Among inputs in a channel
Gcrsins
HD, VD, FB or SYNC-in to
Video-outs
Gcrsync
While HD, VD or FB-out is output.
BANDWIDTH=min, NOTE A
37
dB
mV
2005-12-20
TB1311AFG
Preliminary
Synchronization Block (Test Condition: A-SYNC = 1 (ON))
Characteristic
Symbol
525/60i
H/V-sync separation level
Test Conditions
Min
Typ
Max
Vsep100
HV-SEP = 00, Note A, Note C
12
18
24
Vsep101
HV-SEP = 01, Note A, Note C
20
26
32
Vsep110
HV-SEP = 10, Note A, Note C
26
31
38
Vsep111
HV-SEP = 11, Note A, Note C
38
43
50
Vsep200
HV-SEP = 00, Note A, Note C
20
25
30
Vsep201
HV-SEP = 01, Note A, Note C
28
33
38
Vsep210
HV-SEP = 10, Note A, Note C
33
38
43
Vsep211
HV-SEP = 11, Note A, Note C
45
50
55
Vsep300
HV-SEP = 00, Note A, Note C
14
20
26
Vsep301
HV-SEP = 01, Note A, Note C
21
27
33
Vsep310
HV-SEP = 10, Note A, Note C
27
33
39
Vsep311
HV-SEP = 11, Note A, Note C
38
44
50
1125/60i
Unit
%
%
SVGA/60
%
Threshold amplitude for HD input
VthHD
HV OUT = 1
0.8


Vp-p
Threshold amplitude for VD input
VthVDn
HV OUT = 1
0.9


Vp-p
VhdH
High level
1.0
1.2
1.4
VhdL
Low level

0.1
0.4
Thdw0
HD WIDTH = 0
1.6
1.7
1.8
Thdw1
HD WIDTH = 1
0.6
0.7
0.8
H sync-in to HD-out
Thdp1
HV OUT = 0, 1125/60p input,
Note D
70
90
110
ns
HD-in to HD-out
Thdp2
HV OUT = 1, Note A
25
34
40
ns
VvdH
High level
1.0
1.2
1.4
VvdL
Low level

0.1
0.4
Tvdws
Separated VD-OUT

290

HD-OUT voltage
V
HD-OUT width
µs
HD-OUT phase
VD-OUT voltage
Sync sep
1250i ODD
Tvdwodd
1250i EVEN
Tvdweven
When 1250i input
VD-OUT width

285


270

µs
µs
Free-run 1
Tvdwfi
Free-run VD-OUT in interlace mode

4

Free-run 2
Tvdwfp
Free-run VD-OUT in progressive
mode

8

0.15
0.20
0.25
H
310
320
330
ns
25
34
40
ns
V sync-in to VD-out
VD-OUT phase
V
H sync-in to VD-out
VD-in to VD-out
Tvdp
Except 1250/50i input, Note D
1250/50i input, H sync-in to VD-out,
Tvdp1250
Note D
Tvdphv
HV OUT = 1, Note A
H
Note C: 286 mVp-p sync input for 525/60i, 0.3 Vp-p sync input for 1125/60i and SVGA/60.
Note D: See the figures below.
38
2005-12-20
TB1311AFG
Preliminary
Characteristic
Dummy HD-OUT frequency
Symbol
Test Conditions
Typ.
Max
fh156
HV FREQ2 = 00000, H DMY = 1

15.564

fh157/60i
HV FREQ2 = 00001, H DMY = 1

15.701

fh312
HV FREQ2 = 00010, H DMY = 1

31.401

fh315
HV FREQ2 = 00011, H DMY = 1

31.401

fh281/50i
HV FREQ2 = 00100, H DMY = 1

27.966

fh337/60i
HV FREQ2 = 00101, H DMY = 1

33.771

fh375
HV FREQ2 = 00110, H DMY = 1

37.288

fh450
HV FREQ2 = 00111, H DMY = 1

44.746

fh1250
HV FREQ2 = 01000, H DMY = 1

31.401

fh379
HV FREQ2 = 01001, H DMY = 1

37.288

fh640
HV FREQ2 = 01010, H DMY = 1

66.288

fh750
HV FREQ2 = 01011, H DMY = 1

74.577

fh562
HV FREQ2 = 01100, H DMY = 1

55.932


15.700

HV FREQ2 = 10001, H DMY = 1

27.117

fh281/25p HV FREQ2 = 10010, H DMY = 1

27.965

fh337/30p HV FREQ2 = 10011, H DMY = 1

33.769

fh270/48sf HV FREQ2 = 10100, H DMY = 1

27.965

fh157/30p HV FREQ2 = 10000, H DMY = 1
fh270
Dummy VD-OUT frequency
Min
fv625i
HV FREQ2 = 00000, V DMY = 1

312.5

fv525i
HV FREQ2 = 00001, V DMY = 1

262.5

fv625p
HV FREQ2 = 00010, V DMY = 1

625

fv525p
HV FREQ2 = 00011, V DMY = 1

525

fv1125i50
HV FREQ2 = 00100, V DMY = 1

562.5

fv1125i60
HV FREQ2 = 00101, V DMY = 1

562.5

fv750p50
HV FREQ2 = 00110, V DMY = 1

750

fv750p60
HV FREQ2 = 00111, V DMY = 1

750

fv1250iO
HV FREQ2 = 01000, V DMY = 1,
ODD

624.5

fv1250iE
HV FREQ2 = 01000, V DMY = 1,
EVEN

625.5

fvsvga
HV FREQ2 = 01001, V DMY = 1

628

fvsxga
HV FREQ2 = 01010, V DMY = 1

1066

fvuxga
HV FREQ2 = 01011, V DMY = 1

1250

fv1125p50 HV FREQ2 = 01100, V DMY = 1

1125

fv525p30
HV FREQ2 = 10000, V DMY = 1

525

fv1125p24 HV FREQ2 = 10001, V DMY = 1

1125

fv1125p25 HV FREQ2 = 10010, V DMY = 1

1125

fv1125p30 HV FREQ2 = 10011, V DMY = 1

1125

fv1125s24 HV FREQ2 = 10100, V DMY = 1

562.5

39
Unit
kHz
H
2005-12-20
TB1311AFG
Preliminary
Other Blocks
Characteristic
Symbol
Test Conditions
Min
Typ.
Max
Unit
XTAL oscillation amplitude
Vosc
Note A, Note E

0.4

Vp-p
FB input threshold voltage
VthFB
Pins 44, 50, 64, 70
0.6
0.75
0.9
V
VfbH
High level
1.0
1.2
1.4
VfbL
Low level

0.1
0.4
DL OFF
Tfbdoff
FB DL = 0
20
40
60
DL ON
Tfbdon
FB DL = 1
50
70
90
tnsfil1
SIG LPF = 1, Note F, Note A
0.5
1.3
1.8
Imnsfil200 SIG DET IMPE = 00, Note G
14
20
26
Imnsfil201 SIG DET IMPE = 01, Note G
11
15
19
Imnsfil210 SIG DET IMPE = 10, Note G
7
10
13
Imnsfil211 SIG DET IMPE = 11, Note G
4.2
6.0
7.8
FB-OUT voltage
V
I/O delay time for FB
ns
No signal detection filter
µs
kΩ
Impedance for no-signal detection filter
Vthns00
SIG DET LVL = 00, Note H
0.45
0.55
0.65
Vthns01
SIG DET LVL = 01, Note H
0.70
0.80
0.90
Vthns10
SIG DET LVL = 10, Note H
0.95
1.05
1.15
Vthns11
SIG DET LVL = 11, Note H
1.20
1.30
1.40
VdcthLM
Pins 39, 40, 44, 46, 48, 50, 60, 64,
66, 68, 70, 80
0.8
1.0
1.2
2.8
3.0
3.2
Pins 45, 47, 53, 59, 65, 67, 73, 79
0.8
1.0
1.2
No signal detection threshold voltage
Њ
MЊH
L M
DC detection threshold (DC)
DC detection threshold (S)
V
VdcthMH
VdcthS
V
V
Note E: This is the amplitude of the oscillation wave at the point between the crystal and the series capacitor.
Note F: Remove the external capacitor connected with the SYNC FILTER pin (pin 14), HV SEP1 = 00, SIG DET IMPE = 11. The
delay time from SYNC1-IN input (525/60i) to the SYNC FILTER waveform.
Note G: Remove the external capacitor connected with the SYNC FILTER pin (pin 14). Connect 10 kΩ resistor between the SYNC
FILTER pin and GND. No input into SYNC1-IN. Measure the current (Ir) on the resistor. Imnsfil2xx = 3.3 / Ir – 10 kΩ.
Note H: Remove the external capacitor connected with the SYNC FILTER pin (pin 14). Input a 0 V - Vthnsxx [V] pulse of 15.7 kHz
into the SYNC FILTER pin. The pulse voltage during SIG DET status changes.
40
2005-12-20
TB1311AFG
Preliminary
Test Circuit
+
+
47μF
100μF
0.01μF
0.01μF
75Ω
A
B
A
B
+
47μF
0.01μF
75Ω
1μF
CVBS5 IN
100pF
1μF
AR2 IN
5.6kΩ
100pF
AL2 IN
5.6kΩ
FB1/DC3
Cr1/R1 IN
1μF
DC4
1μF
100pF
100pF
AL9 IN
1μF
75Ω
Cb1/B1 IN
1μF
SW48
AR3 IN
Cb3/B3 IN
AL3 IN
Y3/G3 IN
AR4 IN
SY1 IN
AL4 IN
SC1 IN
DC7
Cr2/R2 OUT
AL2 IN
FB2 OUT
#23
Cr1/R1 IN
AR9 IN/DC4(LINE3-1)
1μF
75Ω
1μF
100pF
5.6kΩ 1μF
75Ω
1μF
100pF
5.6kΩ 1μF
75Ω
1μF
100pF
5.6kΩ 1μF
75Ω
1μF
100pF
5.6kΩ 1μF
100pF
75Ω
75Ω
Y1/G1 IN
V/S GND
FB3 IN/DC6(LINE1-1)
SYNC2 IN
Cr3/R3 IN
AR3 IN
VD OUT
Cb3/B3 IN
HD OUT
AL3 IN
V/S Vcc (5V)
Y3/G3 IN
Cr1/R1 OUT
Y2/G2 OUT
10Ω
AL2 OUT
#17
AR4 IN
FB1 OUT
SY1 IN
Cb1/B1 OUT
AL4 IN
AR1 OUT
#14 0.1μF
180pF
VD OUT
HD OUT
#11
0.01μF
Y1/G1 OUT
AL1 OUT
DC7(S1)
AR5 IN
AR3 OUT
AL5 IN
MONITOR OUT
CVBS1 OUT
FB2 IN/
DC8(SW LINE2)
A
B
AL3 OUT
A
+
47μF
Cr1/R1 OUT
10Ω
510Ω
#8
SC1 IN
CVBS2 OUT
#15
#10
AR5 IN
FB2 /DC8
510Ω
SYNC FILTER
CVBS6 IN
5.6kΩ 1μF
AR2 OUT
#19
CVBS2 OUT
100pF
100pF
Cb2/B2 OUT
10Ω
AL2 OUT
CVBS6 IN
5.6kΩ 1μF
FB2 OUT
510Ω
Y2/G2 OUT
Cb1/B1 IN
Cr2/R2 OUT
#21
AR2 OUT
1μF
AL5 IN
510Ω
10Ω
Cb2/B2 OUT
AL9 IN/DC5(LINE2-1)
75Ω
FB3/DC6
Cr3/R3 IN
AR2 IN
SW46
5.6kΩ
DC5
Y1/G1 IN
AU Vcc (9V)
FB1 IN/DC3(SW LINE1)
5.6kΩ
AR9 IN
CVBS5 IN
FB1 OUT
10Ω
Cb1/B1 OUT
510Ω
AR1 OUT
#6
10Ω
Y1/G1 OUT
510Ω
AL1 OUT
CVBS1 OUT
AR3 OUT
MONITOR OUT
AL3 OUT
B
Components in test circuits are used only to obtain and confirm the device characteristics. These components and
circuits are not guaranteed to prevent malfunction or failure in the application equipment.
41
2005-12-20
TB1311AFG
Preliminary
Application Circuit 1 (Typical Values)
5.6kΩ 1μF
100pF
AL5 IN
5.6kΩ 1μF
0Ω
100kΩ
Cb1 IN
DC5(LINE2-1)
Y1 IN
>
1
inp DC6(LINE1-1)
D
<
0.1μF
1kΩ
1μF
0.1μF
1kΩ
1μF
0.1μF
1kΩ
25
26
24
23
22
21
18
17
12
11
13
14
16
20
27
28
29
30
31
32
33
15
41
42
43
44
45
46
47
48
10
9
8
44
45
46
1kΩ
1μF
/N
I
01
R
A
AL1 OUT
AR3 OUT
MONITOR OUT
AL3 OUT
)2
3-E
N
IL
(9
C
D
N
I
2
B
/2
b
C
/
IN
01
L
A
2)E2N
IL
(0
1
C
D
IN
2
G
/2
Y
/
N
I
4
B
F
F
μ
1
F
F p
0
μ 0
1
1
F
μ
1
F kΩ
Ω
μ 0
0
0
1
1
kΩ
6
.
5
CVBS1 OUT
changed by “CbCr PIN4”
F
F p
0
μ 0
1
1
47
DC4(LINE3-1)
FB2 IN/
DC8(SW LINE2)
IN
2
R
/2
r
C
Y1/G1 OUT
kΩ
6
.
5
2)E1N
IL
(1
1
C
D
IN
4
R
/4
r
C
N
I
4
B
/4
b
C
N
I
6
R
A
IN
4
G
/4
Y
N
I
L6
A
N
I
7
R
A
N
I
Y2S
F
F p
0
μ 0
1
1
F
μ
1
F
F p
0
μ 0
1
1
F
μ
1
F
F p
0
μ 0
1
1
F
μ
1
F
F p
0
μ 0
1
1
F
μ
1
F
p
0
0
1
kΩ
6
.
5
kΩ
6
.
5
kΩ
6
.
5
kΩ
6
.
5
N
I
S6
B
V
C
IN
2B
F
N
I
2R
SCART 2
N
I
2B
N
I
2
G
N
I
10L
A
N
I
10R
A
Audio 10
N
I
4B
F
N
I
r4
C
N
I
b4
C
N
I
Y4
Component
Video 4
N
I
6R
A
N
I
L6
A
Audio 6
N
I
7R
A
N
I
L7
A
Audio 7
The function of pins 66 and 68 are changed by “AU10 PIN”
+
510Ω
FB1 OUT
10Ω
Cr1/R1 OUT
510Ω
Cb1/B1 OUT
tu
o
ni
a
M
Y1/G1 OUT
10Ω
CVBS1 OUT
510Ω
AR1 OUT
AL1 OUT
tu
o
ro
itn
o
M
AR3 OUT
MONITOR OUT
AL3 OUT
2)S
(2
1
C
D
N
I
2
C
S
N
I
L7
A
F
μ
kΩ
0 .1
1
0
0.1μF
48
Cr1 IN
0.1μF
49
DC3(SW LINE1)
AL5 IN
150kΩ
50
V
5
AR5 IN
0.01μF
10Ω 47μF
N
I
Y2S
N
I
2
C
S
S-pin 2
V
5
150kΩ
kΩ
1
>
2
inp
D
<
2)E
IN
L
W
S(
8
C
D
F
μ
1
F
F
μ kΩ μ
1
.
0 1 1
IN
r2
C
2)3E
IN
(L9
C
D
F
F
μ kΩ μ
1
.
0 1 1
IN
2b
C
2)2E
IN
(L0
1
C
D
70
AR5 IN
AR1 OUT
CVBS6 IN
180pF
69
5
oi
du
A
100pF
AL4 IN
DC7(S1)
F
μ
.1
0
68
1μF
Cb1/B1 OUT
2”
IN
P
r
bC
C
“
by
de
gn
ah
c
HD OUT
T
T
A
r
o
P
M
A
67
0.1μF
SY1 IN
SC1 IN
VD OUT
66
10kΩ
SC1 IN
AL2 OUT
64
SY1 IN
tu
o
bu
S
AR2 OUT
510Ω
10Ω
65
1
n
piS
100pF
FB1 OUT
7
5.6kΩ 1μF
Y2/G2 OUT
CVBS2 OUT
6
100pF
510Ω
10Ω
5
AL4 IN
AR4 IN
Cr2/R2 OUT
Cb2/B2 OUT
+
Cr1/R1 OUT
4
1μF
V/S Vcc (5V)
3
5.6kΩ 1μF
AR4 IN
FB2 OUT
510Ω
10Ω
2
100pF
4
o
diu
A
Y3/G3 IN
+
1
Y3 IN
AL3 IN
F F
μ μ
1
0
0
.0 + 1
0
80
1μF
79
5.6kΩ 1μF
HD OUT
78
Cb3 IN
VD OUT
77
100pF
SYNC FILTER
76
Cr3 IN
AR3 IN
Cb3/B3 IN
3”
IN
P
r
bC
C
“
by
de
gn
ah
c
75
3
oe
di
V
Cr3/R3 IN
74
tn
en
op
m
o
C
Y2/G2 OUT
V/S GND
TB1311AFG
1μF
AR2 OUT
SYNC2 IN
73
5.6kΩ 1μF
Cb2/B2 OUT
72
AL3 IN
FB2 OUT
71
100pF
Cr2/R2 OUT
Y1/G1 IN
69
0Ω
1μF
AR3 IN
AU Vcc (9V)
FB3 IN/DC6(LINE1-1)
68
3
iod
u
A
A
D
S
CVBS2 OUT
67
FB3 IN
L
C
S
1”
IN
P
r
bC
C
“
by
de
gn
ah
c
66
”
N
IP
9
U
A
“
by
de
gn
ah
c
rea
48
dn
a
64
sn
ip
fo
onit
ncu
f
eh
T
ss
V
L
A
TX
+
Ω
0
7
4
49
1μF
100kΩ
)
3V
3.(
dd
V
N
I
D
V
N
I
D
H
D
N
G
U
A
Ω
0
7
4
50
5.6kΩ 1μF
AL9 IN/DC5(LINE2-1)
N
I
1
C
N
YS
T
U
O
viY
z
H
M
5
4
5
9
7
5
.3
51
100pF
AL9 IN
IN
1R
A
F
μ
1
Ω
0
F
8
p
1
0
F 1
W
2
/ μ
1 1
.0
0
+
AL2 OUT
52
AR9 IN
Cb1/B1 IN
53
1μF
AR9 IN/DC4(LINE3-1)
54
9
oi
du
A
Cr1/R1 IN
55
100pF
5.6kΩ 1μF
FB1 IN/DC3(SW LINE1)
56
1μF
N
I
S3
B
V
C
IN
1L
A
0.1μF
Ω
0
0 F
1
μ+
7
F 4
μ
.7
4
A
SD
57
100kΩ
F
F p
μ 0
0
1
1
L
SC
IN
D
V
IN
D
H
5V
cc
V
9V
cc
V
58
0Ω
FB1 IN
AL2 IN
59
5.6kΩ 1μF
N
I
S4
B
V
C
AR2 IN
60
G1 IN
F
μ
1
IN
1L
A
Ω
0
0
1
kΩ
.6
5
F
F F p
0
μ 1
μ 0
1
1
CVBS5 IN
61
100pF
)3
(S1
C
D
62
100pF
5.6kΩ 1μF
B1 IN
/
N
I
8R
A
63
R1 IN
1
T
R
A
C
S
F
F p
μ 0
0
1
1
64
1μF
CVBS5 IN
)4
(S2
C
D
kΩ
.6
5
IN
1
R
A
Power Supply
SU
B
C
2I
19
/
N
I
8L
A
AL2 IN
kΩ
.6
5
39
AR2 IN
N
I
S3
B
V
C
65
2
iod
u
A
40
F
F p
μ 0
0
1
1
N
I
S4
B
V
C
34
kΩ
.6
5
39
40
F
F
Ω
μ Ω
μ
k 1
k 1
0
1 .0 0
1 .0
IN
8
R
A
IN
8L
A
)
C
(P
D
V
/
D
H
1
iod
u
A
35
”
N
I
P
8
U
“A
yb
de
gn
ah
c
3
S
B
V
C
70
)3
S(
1
C
D
4
S
B
V
C
36
)4
S(
2
C
D
8
iod
u
A
37
3
ni
pS
ro
f
38
4
ni
pS
ro
f
F
kΩ
1μ
.
0 1
IN
2Y
2)1E
IN
(L1
1
C
D
Input video signals driven with low impedance.
The application circuits shown in this document are examples provided for reference purposes only. Thorough
evaluation is required in the mass production design phase.
By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
42
2005-12-20
TB1311AFG
Preliminary
Application Circuit 2 (Examples of Connectors)
20
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
SCART
AR-out
AL-out
V-out
50
49
48
47
46
45
44
43
42
41
SCART connector
8
9
10
11
12
13
14
1
2
3
4
5
6
7
D
11
6
12
7
1
13
8
2
14
9
3
15
10
4
D-SUB15
5
5V
50
49
48
47
46
45
44
50
D-pin
49
48
47
46
45
44
31
30
D-SUB15
The application circuits shown in this document are examples provided for reference purposes only. Thorough
evaluation is required in the mass production design phase.
By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
43
2005-12-20
TB1311AFG
Preliminary
Application Circuit 3 (System Configuration)
(1) For nonstandard signals such as CVBS, YC (S-video), 525i, 625i or so.
Color decoder / IP converter / ...
TB1311
Video
SW
Sync-in
Video-in
Video block
ADC
PLL
Freq
counting
block
Sync block
I/P converter
Scaler
HD/VD-in
Sync
SW
PAL/NTSC/SECAM
Color decoder
Sync processor
The TB1311AFG does not support weak signals, ghost signals or other nonstandard signals. Therefore, these signals
should be dealt with through the use of another device capable of handling these signals, such as a color-decoder. In
these cases, the signal switcher and the video circuits of the TB1311AFG can be used. In some cases, “no-input
detection” can be also used for these signals.
The TB1311AFG cannot distinguish between component and RGB video. The different kinds of input signal should be
separated through the use of different signal-specific input pins; for example, specific-purpose pins for RGB video input
only or component video input only.
(2) For standard component video (SMPTE STANDARD) and standard RGB video (VESA STANDARD)
Color decoder / IP converter / ...
TB1311
Video
SW
Sync-in
Sync block
Sync
SW
Video-in
Video block
Freq
counting
block
HD/VD-in
ADC
PLL
PAL/NTSC/SECAM
Color decoder
Sync processor
I/P converter
Scaler
The TB1311AFG can detect a format type for standard signal inputs.
The application circuits shown in this document are examples provided for reference purposes only. Thorough
evaluation is required in the mass production design phase.
By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
44
2005-12-20
Preliminary
TB1311AFG
Package Dimensions
P-QFP80-1420-0.80C
Unit: mm
Weight: 1.6 g (typ.)
45
2005-12-20
Preliminary
TB1311AFG
About solderability, following conditions were confirmed
Solderability
(1) Use of Sn-37Pb solder Bath
· solder bath temperature = 230°C
· dipping time = 5 seconds
· the number of times = once
· use of R-type flux
(2) Use of Sn-3.0Ag-0.5Cu solder Bath
· solder bath temperature = 245°C
· dipping time = 5 seconds
· the number of times = once
· use of R-type flux
46
2005-12-20