TB62300FG TOSHIBA BiCD IC Silicon Monolithic TB62300FG Dual Full-Bridge Driver for DC Motor The TB62300FG is a dual brushed DC motors driver IC employing a chopper-based forward/reverse full-bridge mechanism. It controls two brushed DC motors at high precision. The motor supply voltage is up to 40 V and the VDD supply voltage is 5.0 V. Features • A single IC can drive two brushed DC motors. • Monolithic Bi-CMOS IC • Low ON-resistance (Ron) = 0.3 Ω (Tj = 25°C at 2.0 A typ.) • Selectable current control: PWM current control using the PHASE pin or serial control • 5-bit DA converter for specifying current value and 2-bit DA converter for determining torque • MIXED DECAY mode enables specification of current decay rate in four steps. • Self-oscillation chopping frequency with external resistor and capacitor • High-speed chopping at 100 kHz or higher • ISD, TSD, and POR (VDD/VM) protection circuits • Charge pump circuit (two external capacitors) for driving output • 36-pin package: HSOP36 with heat sink • Output voltage: 40 V (max) • Output current: 2.5 A max (in steady-state phase) or 8 A max (pulsed output) Weight: 0.79 g (typ.) Note: The values specified in this document are designed values, which are not guaranteed. 1 2005-04-04 TB62300FG Block Diagram 1. Overview (for single axis) VDD Sleep Circuits used to set current value DATA 16-bit shift register CLK Chopping reference circuit 16-bit latch Chopping waveform generator circuit STROBE Vref Mixed decay timming, table logic circuit Current range controller (2-bit D/A) CR Current control data logic circuit Waveform squaring circuit Current value controller (5-bit D/A) Current feedback circuit MODE RS VRS circuit Output control circuit RS comparator circuit PHASE Mixed decay control Output pre driver VM ENABLE BRAKE ISD circuit Ccp 2 TSD circuit Output circuit (H-bridge) Charge pump circuit VDDR/VMR circuit Ccp 1 Protection circuit Out X Brushed DC Motor High-voltage (VM) Logic data Analog data IC pin 2 2005-04-04 TB62300FG Pin Assignment RS A 1 36 RS B VREF A 2 35 SLEEP VREF B 3 34 ENABLE B CR 4 33 ENABLE A VM 5 32 PHASE B Ccp 1 6 31 PHASE A Ccp 2 7 30 DATA B Ccp 3 8 29 DATA A VDD 9 28 CLK B LGND LGND 27 CLK A NC 10 TSTO 11 26 STROBE B TSTI 12 25 STROBE A BRAKE A 13 24 MODE B BRAKE B 14 23 MODE A 22 NC NC 15 OUT A − 16 21 OUT B − 20 PGND PGND 17 OUT A + 18 19 OUT B + Note: When designing a ground line, make sure that all ground pins are connected to the same ground trail and remember to take heat radiation into account. When pins that are used to toggle between modes are controlled by a switch, pull up or down the pins to avoid high impedance. The IC may be destroyed due to short circuit between outputs, to supply, or to ground. Design output lines, VDD (VM) lines and ground lines with great care. When power supply pins (VM, RS, OUT, P-GND, VSS and CCP) that are exposed to high current, or logic input pins are not connected correctly, excessive current or malfunction may cause the IC to break down. 3 2005-04-04 TB62300FG Pin Description Pin Number Symbol Function Remarks 1 RS A A-ch output power supply pin (current detection pin) Reference pin for A-axis supply voltage 2 VREF A A-ch reference voltage input pin Reference power supply pin for A-axis current 3 VREF B B-ch reference voltage input pin Reference power supply pin for B-axis current 4 CR External chopping reference pin Pin used to set the chopping frequency 5 VM Supply voltage monitor pin Monitor (reference) pin for motor supply voltage 6 Ccp 1 Charge pump capacitor pin Pin for connecting a charge pump capacitor 7 Ccp 2 Charge pump capacitor pin Pin for connecting a charge pump capacitor 8 Ccp 3 Charge pump capacitor pin Pin for connecting a charge pump capacitor 9 VDD Logic power supply Logic supply current input pin 10 NC NC pin Note: Usually, leave this pin open. 11 TSTO Test pin (usually not used) Note: Usually, leave this pin open. 12 TSTI Test pin (usually not used) Note: Usually, connect this pin to LGND. 13 BRAKE A A-ch brake mode pin Forced brake mode 14 BRAKE B B-ch brake mode pin Forced brake mode 15 NC NC pin Note: Usually, leave this pin open. 16 OUT A − A-ch negative output pin A − output pin 17 PGND VM ground Power ground 18 OUT A + A-ch positive output pin A + output pin 19 OUT B + B-ch positive output pin B + output pin 20 PGND VM ground Power ground 21 OUT B − B-ch negative output pin B − output pin 22 NC NC pin Note: Usually, leave this pin open. 23 MODE A A-ch data mode switching pin Pin used to toggle between serial input and PWM control 24 MODE B B-ch data mode switching pin Pin used to toggle between serial input and PWM control 25 STROBE A A-ch latch signal input pin Data input: latched on rising edge 26 STROBE B B-ch latch signal input pin Data input: latched on rising edge 27 CLK A A-ch clock input pin Data input: referred to rising edge 28 CLK B B-ch clock input pin Data input: referred to rising edge 29 DATA A A-ch data input pin Data input: 30 DATA B B-ch data input pin Data input: 31 PHASE A A-ch phase switching pin PWM signal input pin: 32 PHASE B B-ch phase switching pin PWM signal input pin:: 33 ENABLE A A-ch output forced OFF pin L: output stopped 34 ENABLE B B-ch output forced OFF pin L: output stopped 35 SLEEP Operation stopped mode Internal logic cleared and charge pump stopped 36 RS B B-ch output power supply pin (current detection pin) Reference pin for B-axis supply voltage FIN1 LGND Logic ground Logic ground FIN2 LGND Logic ground Logic ground 4 2005-04-04 TB62300FG Pin Description (Supplementary) Pull-up/pull-down status and operation within the IC for input pins Pin Number Symbol Internal Pull-up/down Output Operation at High Output Operation at Low 10 NC Open Does not affect normal operation of the IC. Does not affect normal operation of the IC. 11 TSTO Output pin (usually low) Does not affect normal operation of the IC (with the same withstand voltage as for VDD). Does not affect normal operation of the IC. 12 TSTI Input pin (no pull-up or down) Toshiba test mode Normal operation mode 13 BRAKE A No pull-up or down 14 BRAKE B No pull-up or down 15 NC Open Does not affect normal operation of the IC. Does not affect normal operation of the IC. 22 NC Open Does not affect normal operation of the IC. Does not affect normal operation of the IC. 23 MODE A No pull-up or down 24 MODE B No pull-up or down 25 STROBE A No pull-up or down 26 STROBE B No pull-up or down 27 CLK A No pull-up or down 28 CLK B No pull-up or down 29 DATA A No pull-up or down 30 DATA B No pull-up or down 31 PHASE A No pull-up or down 32 PHASE B No pull-up or down 33 ENABLE A No pull-up or down 34 ENABLE B No pull-up or down 35 SLEEP Pull-down with a 50-kΩ resistor 5 2005-04-04 TB62300FG Truth Table (1) Pin logic overview Pin Number Symbol Function Logic H : Serial signal input control L : PWM control 23 MODE A A-ch data mode switching pin 24 MODE B B-ch data mode switching pin 25 STROBE A A-ch latch signal input pin H : Latched on rising edge 26 STROBE B B-ch latch signal input pin L : Pass-through 31 PHASE A A-ch phase switching pin H : Positive phase 32 PHASE B B-ch phase switching pin L : Negative phase Note: When PWM control is selected, serial data bits D0 to D6 are valid while D7 to D13 are invalid. H : Sleep released 35 SLEEP Operation stopped mode L : Sleep state All internal circuits, including charge pumps, are stopped. 33 ENABLE A A-ch output forced OFF pin H : Output enabled Output transistors turned on 34 ENABLE B B-ch output forced OFF pin 13 BRAKE A A-ch brake mode pin H : Brake applied PHASE and ENABLE pins disabled 14 BRAKE B B-ch brake mode pin L : Brake released L : Output disabled Output transistors turned off Truth Table (2) Overall logic External Pins Serial Status SLEEP ENABLE A/B BRAKE A/B MODE A/B PHASE A/B PHASE 0 X X X X X Sleep mode 1 0 X X X X Disable mode 1 1 X X X Breake ON 0 0 1 X Forward 0 0 X Reverse 1 X 1 Forward 1 X 0 Reverse 6 2005-04-04 TB62300FG IC State for Each Function Function Internal Logic Output Charge Pump OSC Reset OFF OFF OFF Maintained OFF Operating Operating Reset OFF OFF OFF SLEEP ENABLE POR Recovery Time tONG = 2.0 ms (typ.)/4.0 ms (max) N/A tONG = 2.0 ms (typ.)/4.0 ms (max) ISD Reset OFF OFF OFF tONG = 2.0 ms (typ.)/4.0 ms (max) TSD Reset OFF OFF OFF tONG = 2.0 ms (typ.)/4.0 ms (max) Serial Input Signals Order of data input Data Bit 0 Name Initial State When PWM is Operating 1 ÷ fchop ÷ 16 × 7 Enabled 25% Enabled Mixed decay mode (37.5%) Enabled 100% Disabled 0 Negative Disabled Initial Value Function TBlank 0 0 Set blanking time to prevent false detection due to noise 1 TBlank 1 2 TBlank 2 3 Torque 0 4 Torque 1 5 Decay mode 0 6 Decay mode 1 7 Current 0 8 Current 1 1 1 0 Set current range 0 1 Set decay mode 0 1 1 Set current 9 Current 2 1 10 Current 3 1 11 Current 4 1 12 Phase Switch phase 13 ⎯ ⎯ ⎯ ⎯ ⎯ 14 ⎯ ⎯ ⎯ ⎯ ⎯ 15 ⎯ ⎯ ⎯ ⎯ ⎯ Strobe Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clock Register A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Notes on TBlank Setting When using PWM control and serial control simultaneously, constant-current chopping may be disabled depending on the TBlank setting. Using constant-current chopping requires the following phase width in Fast Decay mode: (TBlank setting + 2/fcr) × 2 7 2005-04-04 TB62300FG Setting Table (1): D0, D1, D2 Blanking time settings Data Bit Name 0 TBlank 0 1 TBlank 1 2 TBlank 2 Function Set blanking time to prevent false detection due to noise TBlank 2 TBlank 1 TBlank 0 Setting TBlank (typ.) 0 0 0 1 ÷ fChop ÷ 16 × 1 0 0 1 1 ÷ fChop ÷ 16 × 2 0 1 0 1 ÷ fChop ÷ 16 × 3 0 1 1 1 ÷ fChop ÷ 16 × 4 1 0 0 1 ÷ fChop ÷ 16 × 5 1 0 1 1 ÷ fChop ÷ 16 × 6 1 1 0 1 ÷ fChop ÷ 16 × 7 1 1 1 1 ÷ fChop ÷ 16 × 8 Torque 1 Torque 0 Setting Torque (typ.) 0 0 25% 0 1 50% 1 0 75% 1 1 100% Torque Mode 1 Torque Mode 0 Setting Decay Mode 0 0 Slow decay mode 0 1 Mixed decay mode: 37.5% 1 0 Mixed decay mode: 75.0% 1 1 Fast decay mode Setting Table (2): D3, D4 Torque settings Data Bit Name 3 Torque 0 4 Torque 1 Function Set current range Setting Table (3): D5, D6 Decay mode settings Data Bit Name 5 Decay mode 0 6 Decay mode 1 Function Set decay mode 8 2005-04-04 TB62300FG Setting Table (4): D7, D8, D9, D10, D11 Current settings Data Bit Name 7 Current 0 8 Function Current 4 Current 3 Current 2 Current 1 Current 0 Setting Current 0 0 0 0 0 0% Current 1 0 0 0 0 1 3% Set current 9 Current 2 0 0 0 1 0 6% 10 Current 3 0 0 0 1 1 9% 11 Current 4 0 0 1 0 0 12% 0 0 1 0 1 16% 0 0 1 1 0 19% 0 0 1 1 1 22% 0 1 0 0 0 25% 0 1 0 0 1 29% 0 1 0 1 0 32% 0 1 0 1 1 35% 0 1 1 0 0 38% 0 1 1 0 1 41% 0 1 1 1 0 45% 0 1 1 1 1 48% 1 0 0 0 0 51% 1 0 0 0 1 54% 1 0 0 1 0 58% 1 0 0 1 1 61% 1 0 1 0 0 64% 1 0 1 0 1 67% 1 0 1 1 0 70% 1 0 1 1 1 74% 1 1 0 0 0 77% 1 1 0 0 1 80% 1 1 0 1 0 83% 1 1 0 1 1 87% 1 1 1 0 0 90% 1 1 1 0 1 93% 1 1 1 1 0 96% 1 1 1 1 1 100% Setting Table (5): D12 Phase settings Data Bit Name 12 Phase Function Switch phase Phase Setting Phase 0 Negative 1 Positive 9 2005-04-04 TB62300FG PWM Operation 1 2 3 4 5 6 ･････ fCR (fchop*16) PHASE Internal reset signal Phase Blank Time Serial Blanking Time Input range for fcr clock 1/fcr*2 Example: 1/fcr*2 1/fcr*TBlank Total Blanking Time Example: 1/fcr*2 + 1/fcr*TBlank Output control signal Notes: ･fcr is 16 times the fchop frequency. ･PHASE is an external signal. ･The internal reset signal resets the internal clocks and counters. ･Phase Blank Time is time between either edge of the external PHASE signal and the leading edge of serial blanking time. Description The output H bridge is driven by an external PHASE signal. It, however, also uses the fcr signal, generated with external CR, to generate blanking time and Mixed Decay time. The above logic is configured to handle the two signals, PHASE and fcr, which are asynchronous to each other. The logic generates internal reset signal edges from external PHASE edges, resulting in the width equal to two fcr cycles. The fcr-based counter assumes the first fcr falling edge following the PHASE edge as the first count. The maximum phase difference between the PHASE and fcr signals is, therefore, one fcr cycle. The serial blanking time starts at the second count based on the fcr clock (The first three samples of serial blanking time signal must be 000). The last stage output is switched by the edge of the external PHASE signal. That means there is an interval of two fcr cycles before the set blanking time starts. To cover the interval, the logic generates the time between the PHASE signal edge and blanking time start as phase blank time, during which comparison is masked off in the same way as in blanking time. Consequently, the blanking time as viewed from outside the IC is within the range from one fcr cycle (TBlank (000)) to eight fcr cycles (TBlank (111)) + I phase difference between PHASE and fcr (up to two fcr cycles). 10 2005-04-04 TB62300FG Absolute Maximum Ratings (Topr = 25°C) Characteristics Symbol Test Condition Rating Unit Logic supply voltage VDD ⎯ −0.4 to 7.0 V Maximum output voltage VM ⎯ 40 V 8.0 A Peak output current (Note: preliminary specification) IOUT (Peak) Continuous output current tW ≤ 500 ns IOUT (Cont) ⎯ 2.5 A Logic input voltage VIN ⎯ −0.5 to VDD V Current detection pin voltage VRS ⎯ VM ± 4.5 V V IC alone 1.4 W Power dissipation PD When mounted on a board (Note) 3.2 W Operating temperature Topr ⎯ −40 to 85 °C Storage temperature Tstg ⎯ −55 to 150 °C Junction temperature Tj ⎯ 150 °C Note: When Topr = 45°C, Tj = 150°C and θja = 32°C Recommended Operating Conditions (Topr = 0 to 85°C) Characteristics Symbol Supply voltage (Note 1) VDD Output voltage (Note 1) VM Output current (Note: preliminary specification) Test Condition ⎯ VDD = 5.0 V Min Typ. Max Unit 4.5 5.0 5.5 V 18.0 24.0 33.0 V IOUT (Peak) VM = 33.0 V, tw ≤ 500 ns ⎯ 6.4 7.2 A IOUT (Cont) VM = 33.0 V ⎯ 1.5 1.8 A 0 ⎯ ⎯ Logic input voltage range VIN Clock frequency fCLK Chopping frequency fchop VDD = 5.0 V 20 Vref reference voltage Vref VM = 24.0 V, TORQUE = 100% 2.0 Current detection pin voltage VRS VDD = 5.0 V 0 VDD = 5.0 V VDD V 25.0 MHz 30 150 kHz 3.0 VDD V ±1.0 ±1.5 V 1.0 Tj ⎯ ⎯ ⎯ 120 °C Oscillator capacitor COSC ⎯ ⎯ 270 ⎯ pF Oscillator resistor ROSC ⎯ ⎯ 3.9 ⎯ kΩ Charge pump capacitor A CCPA ⎯ ⎯ 0.22 ⎯ µF CCPB ⎯ ⎯ 0.022 ⎯ µF tri/tfi ⎯ ⎯ 0.1 5.0 µs Junction temperature Charge pump capacitor B Input rise and fall rate (Note 2) Note 1: Do not reduce VDD to 0 V (ground) while VM voltage is applied. Such an attempt may damage the IC because there is a current path from the VM pin to VDD pin and the internal logic is undefined when VDD is not applied. Leaving VDD open (Hi-Z) is less likely to damage the IC, although it is not recommended. Note 2: The circuit configuration of this IC cannot handle extremely slow data input (on pins BREAK A, BREAK B, SLEEP, ENABLE A, ENABLE B, PHASE A, PHASE B, DATA A, DATA B, CLK A, CLK B, STROBE A, STROBE B, MODE A, and MODE B). Applying a slow signal having a period longer than 5 µs may cause the IC to oscillate. (1) (2) Calculating the current IOUT = 1/3 × Vref (V) × (Torque (%) ÷ RRS (Ω) ) × Current (%) where 1/3 is the Vref (GAIN):Vref attenuation ratio. Calculating the oscillation frequency fCR = 1/(KA) × (C × R + KB × C)) × [Hz] KA = 0.523, KB = 600, fchop = fCR/16 [Hz] [Example] When COSC = 270 pF and ROSC = 3.9 kΩ: fCR = 1.57 MHz and fchop = 1.57/16 = 98.4 kHz 11 2005-04-04 TB62300FG Electrical Characteristics 1 DC Characteristics (unless otherwise specified, VM = 24 V, VDD = 5.0 V, Topr = 25℃) Characteristics Symbol High Input voltage Low Input current Test Circuit Test Condition Min Typ. Max CLK, STROBE, DATA, MODE, PHASE, ENABLE and PHASE 2.0 ⎯ ⎯ VIL pins ⎯ ⎯ 0.8 IIH1 CLK, STROBE, DATA, MODE, ⎯ ⎯ 1.0 IIL1 PHASE, ENABLE and PHASE pins ⎯ ⎯ 1.0 ⎯ ⎯ 200.0 ⎯ ⎯ 1.0 ⎯ 3.0 4.5 0.3 1.0 4.3 7.0 VIH DC DC IIH2 SLEEP pin IIL2 Current consumed by logic power IDD1 supply IDD2 DC VDD = 5.0 V, fcr stopped In SLEEP mode Output open, fCLK = 1 kHz, logic operating, VDD = 5 V, IM1 VM = 24 V, all output stages ⎯ Unit V µA µA mA stopped, charge pump charged DC VM current consumption Output standby current Upper Output open, fCLK = 4 kHz, internal logic operating mA IM2 (100-kHz chopping), output stages operating without load, charge pump charged ⎯ 20.0 28.0 IM3 In SLEEP mode ⎯ 0.5 1.0 IOH VRS = VM = 24 V, Vout = 0 V, ENABLE = Low, −400 ⎯ ⎯ −200 ⎯ ⎯ ⎯ ⎯ 1.0 DATA = All low Output bias current Upper IOB DC VRS = VM = 24 V, Vout = 24 V, ENABLE = Low, µA DATA = All low Output leakage current Comparator reference voltage ratio VRS = VM = Ccp A = Vout Lower IOL High VRS (H) Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 11 = 100% set ⎯ 100 ⎯ Mid High VRS (MH) Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 10 = 75% set 73 75 77 48 50 52 23 25 27 = 24 V, SLEEP= Low DC Mid Low VRS (ML) Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 01 = 50% set Low VRS (L) Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 00 = 25% set 12 % 2005-04-04 TB62300FG Electrical Characteristics 2 DC Characteristics (unless otherwise specified, VM = 24 V, VDD = 5.0 V, Topr = 25℃) Symbol Test Circuit Test Condition Min Typ. Max Unit Output current interchannel error ∆IOUT1 DC Error in output current between channels (IOUT = 1.5 A) −5.0 ⎯ 5.0 % Output current setting error ∆IOUT2 DC IOUT = 1.5 A −5.0 ⎯ 5.0 % IRS DC Characteristics RS pin current µA RON1 IOUT = 1.5 A, VDD = 5.0 V, Tj = 25 °C, forward direction ⎯ 0.3 0.4 RON1 IOUT = 1.5 A, VDD = 5.0 V, Tj = 25 °C, reverse direction ⎯ 0.3 0.4 RON2 IOUT = 1.5 A, VDD = 5.0 V, Tj = 105 °C, forward direction ⎯ 0.4 0.55 RON2 IOUT = 1.5 A, VDD = 5.0 V, Tj = 105 °C, reverse direction ⎯ 0.4 0.55 VM = 24 V, VDD = 5.0 V, ENABLE, output operation 2.0 ⎯ VDD V ⎯ ⎯ 100 µA 1/2.82 1/3 1/3.18 ⎯ Output transistor drain-source DC ON-resistance VREF input voltage Vref DC VREF input current Iref DC Vref = 3.0 V, VM = 24 V, VDD = 5.0 V, Ω SLEEP Vref VREF attenuation ratio TSD operating temperature (GAIN) (Note 1) Overcurrent protection circuit operating current Output OFF mode supply voltage DC Vref = 3.0 V, VM = 24 V, VDD = 5.0 V, SLEEP TjTSD DC VDD = 5 V, VM = 24 V 130 ⎯ 170 °C ISD DC VDD = 5 V, VM = 24 V ⎯ 6.0 ⎯ A Vpor (VDD) DC VM = 24 V ⎯ 3.0 ⎯ Vpor (VM) DC V VDD = 5 V ⎯ 15.0 ⎯ Note 1: Thermal shutdown (TSD) circuit When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal reset circuit turns output off. The TSD activation temperature can be set within the range from 130°C (min) to 170°C (max). Once the TSD circuit is activated, output is stopped until a pulse (L to H to L) is subsequently applied to the SLEEP pin. The charge pump is halted while the TSD circuit is active. The TSD circuit does not include hysteresis. Applying a pulse (L to H to L) to the SLEEP pin deactivates the circuit. Note 2: Overcurrent protection circuit (ISD) This circuit is activated when a current pulse exceeding the specified output value is applied for a period of 1/2fCHOP (min) to fCHOP (max). The circuit activates the internal reset circuit to turn output off. Once it is activated, output is stopped until a pulse (L to H to L) is subsequently applied to the SLEEP pin. While the ISD circuit is active, the IC is placed in SLEEP mode with the charge pump halted. 13 2005-04-04 TB62300FG AC Characteristics (Topr = 25°C, VM = 24 V, VDD = 5 V with load of 6.8 mH/5.7 Ω) Characteristics Clock frequency Symbol Test Circuit fCLK ⎯ Test Condition Min Typ. Max Unit 1.0 ⎯ 25.0 MHz 40.0 ⎯ ⎯ 20.0 ⎯ ⎯ twn 20.0 ⎯ ⎯ tWSTROBE 40.0 ⎯ ⎯ 20.0 ⎯ ⎯ 20.0 ⎯ ⎯ tw (tCLK) Minimum clock pulse width Minimum STROBE pulse width twp tSTROBE (H) AC AC tSTROBE (L) Minimum SLEEP pulse width Phase difference between PHASE signal and fcr Blanking time for preventing false detection Data setup time ns tWSTROBE AC tONG ⎯ ⎯ ns tp AC ⎯ ⎯ 1/fCR ns ⎯ 300 ⎯ ns 20.0 ⎯ ⎯ 20.0 ⎯ ⎯ 20.0 ⎯ ⎯ 20.0 ⎯ ⎯ tBLNIK tsSIN-CLK (Note 1) AC tsST-CLK Data hold time ns thSIN-CLK AC thST-CLK ns ns STROBE setup time (relative to CLK) tsSSB-CLK AC 20.0 ⎯ ⎯ STROBE hold time (relative to CLK) thSB-CLK AC 20.0 ⎯ ⎯ tf ⎯ 40.0 100 tf ⎯ 40.0 100 tpLH ⎯ 100 200 ⎯ 580 1000 tpLZ ⎯ 100 200 tpHZ ⎯ 350 700 tpZL ⎯ 1000 2000 tpZH ⎯ 350 700 1.1 1.3 1.5 MHz 20.0 ⎯ 150.0 kHz ⎯ 30.0 ⎯ kHz ⎯ 2.0 4.0 ms Output transistor switching time CR reference signal oscillation frequency tpHL AC Cosc = 270 pF, Rosc = 3.9 kΩ fCR ns ns fchop (min) Chopping frequency fchop (typ.) fchop (max) Oscillation frequency fchop Charge pump rise time tONG When fCR = 480 kHz AC Note 1: The blanking time is internally fixed but it can be elongated by applying a serial blanking time signal. 14 2005-04-04 TB62300FG Test Circuit (DC) IDD1 IDD2 CR Cosc = 560 pF Iref 5V 0V A 5V 0V 5V 0V 5V 0V LGND DATA A A VM STROBE B A 5V 0V CLK A A LGND A CLK B RRS A SLEEP A LGND (FIN) A A PHASE A 5V 0V 5V 0V A PHASE B B A ENABLE A B 5V 0V 5V 0V A ENABLE B A MODE A 5V 0V A MODE B 5V 0V A BRAKE A 5V 0V A BRAKE B Ccp 1 Ccp 2 Ccp 1 0.22 µF IOL IOH IOB RRS A 0.22 Ω A IOUT1, 2 M DC Motor 5V 0V V IM1, IM2, IM3 V VRS DATA B A 1 µF A A RRS B M DC Motor A RRS B 0.22 Ω IRS P-GND PGND Ccp 3 24 V 5V 0V Vref B STROBE A LGND 3V A 5V 0V 1 µF Vref A 3V Vref A Rosc = 3.6 kΩ 100 µF LGND Iref VDD Vref 5V A SGND Ccp 2 0.022 µF LGND 15 2005-04-04 TB62300FG Test Circuit (AC) fCLK, tw (tCLK), twp, twn, twSTROBE, tSTROBE (H), tSTROBE (L), tsSIN-CLK, tsST-CLK, thSIN-CLK, thST-CLK Iref 1 µF CR LGND STROBE A 5V 0V CLK A 5V 0V DATA A 5V 0V STROBE B 5V 0V CLK B 5V 0V DATA B 5V 0V SLEEP Vref B Vref 5V 0V LGND 5V 0V A PHASE A 5V 0V 5V 0V A PHASE B A ENABLE A 5V 0V 5V 0V A ENABLE B A MODE A 5V 0V A MODE B 5V 0V A BRAKE A 5V 0V A BRAKE B tBLNIK VM IOL IOH IOB V VRS RRS A RRS A A VSS (FIN) LGND 1 µF Cosc = 560 pF A 1.0 Ω A IOUT1, 2 A M DC Motor B M DC Motor B RRS B Ccp 1 0.22 µF RRS B IRS 1.0 Ω PGND 100 µF P-GND Ccp 1 Ccp 2 V A Ccp 3 24 V SGND Vref A 3V Rosc = 3.6 kΩ Vref 5V VDD 3V fchop, fosc PGND Ccp 2 0.022 µF tONG 16 2005-04-04 TB62300FG AC Test Waveforms DATA DATA 15 50% DATA 0 tw (tCLK) thDATA CLOCK tsDATA 50% tsSTROBE STROBE DATA 1 tdCLOOK twn twn 50% twSTROBE 50% SLEEP twSLEEP PHASE 50% Out A tpLH tpHL PHASE ENABLE 50% tpZL Out A tpZH tpLZ tpHZ 17 2005-04-04 TB62300FG Waveform in Mixed Decay Mode (Current Waveform) fchop fchop Internal CR CLK signal IOUT NF Set current value Set current value NF 25% Mixed Decay Mode RNF MDT (Mixed Decay Timming) point Output Transistor Operating Mode RRS RRS RS pin RRS RS pin U1 U2 U1 OFF OFF L1 L2 L1 OFF ON ON ON VM VM VM (Note) RS pin (Note) Load U2 U1 OFF OFF L2 ON L1 L2 ON OFF PGND Charge mode ON (Note) Load Load PGND U2 PGND Slow mode Fast mode Output Transistor Operation Functions CLK U1 U2 L1 L2 Charge ON OFF OFF ON Slow OFF OFF ON ON Fast OFF ON ON OFF Note: The above table is an example where current flows in the direction of the arrows in the above figures. When the current flows in the opposite direction of the arrows, see the table below. CLK U1 U2 L1 L2 Charge OFF ON ON OFF Slow OFF OFF ON ON Fast ON OFF OFF ON 18 2005-04-04 TB62300FG Power Supply Sequence (Recommended) VDD (max) VDD (min) VDD VDDR GND VM VM VM (min) VMR GND Non-reset Internal reset Reset SLEEP input (Note1) H L Takes up to tONG until operable Non-operable area Note 1: If VDD drops to the level of the VDDR or below while the specified voltage is applied to the VM pin, the IC is internally reset. This is a protective measure against malfunction. Likewise, if VM drops to the level of VMR or below while regulation voltage is applied to VDD, the IC is internally reset as a protective measure against malfunction. To avoid malfunction, when turning on VM or VDD, applying a signal to the SLEEP pin at the above timing is recommended. It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on before driving a motor. Note 2: When the VM value is between 3.3 to 5.5 V, the internal reset is released, thus output may be active. In such a case, the charge pump circuit cannot operate properly because of insufficient voltage. The IC should be held in SLEEP mode until VM reaches 13 V or more. Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset. At that time, a current of several mA flows due to a current path between VM and VDD. When the output voltage is high, make sure that the specified voltage is applied to VDD. 19 2005-04-04 TB62300FG PD – Ta (Package power dissipation) PD – Ta 3.5 (2) Power dissipation PD (W) 3 2.5 2 1.5 1 (1) 0.5 0 0 25 50 75 Ambient temperature 100 125 150 Ta (°C) Transient thermal resistance (1) HSOP36 Rth (j-a) without a board (96°C/W) (2) When mounted on a board (140 mm × 70 mm × 1.6 mm: 38°C/W: typ.) Note: Rth (j-a): 8.5°C/W 20 2005-04-04 TB62300FG Relationship between VM and VH (charge pump voltage) Note: VDD = 5 V Ccp 1 = 0.22 µF, Ccp 2 = 0.022 µF, fchop = 150 kHz (Care must be taken about the temperature charges of charge pump capacitor.) VM – VH (& Vcharge UP) 50 VH voltage Charge up voltage VM voltage 40 Charge pump output voltage VH voltage, charge up voltage (V) Apply SLEEP signal. 30 VM voltage VMR 20 Maximum rating 10 Recommended operation area Usable area 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Supply voltage VM (V) Charge pump voltage VH = VDD + VM (= Ccp A) (V) (Maximum rating is VDD (7 V) + VM (40 V)) 21 2005-04-04 TB62300FG Operation of Charge Pump Circuit RRS RS VDD = 5 V VM VH Ccp A 7 i2 Output Tr2 Comparator and Controller Output H switch VM = 24 V Vz Di3 Di2 Di1 (1) i1 (2) (2) R1 Ccp B Ccp 2 0.022 µF Ccp 1 0.22 µF Ccp C Tr1 VH = VM + VDD = charge pump voltage i1 = charge pump current i2 = gate block power dissipation • Initial charging (1) (2) (3) When RESET is released, Tr1 is turned on and Tr2 turned off. Ccp 2 is charged from VM via Di1. After Tr1 is turned off and Tr2 is turned on, and Ccp 1 is charged from Ccp 2 via Di2. When the voltage difference between VM and VH (Ccp A pin voltage = charge pump voltage) reaches VDD or higher, operation halts (in the steady-state phase). • Actual operation (4) (5) The charge of Ccp 1 charge is used at fchop switching and the potential of VH drops. The circuit is charged up by the operations of (1) and (2) above. Output switching Initial charging Steady-state phase VH VM (1) (2) (3) (4) (5) (4) (5) t 22 2005-04-04 TB62300FG Charge Pump Rise Time Ccp 1 voltage VDD + VM VM + (VDD × 90%) VM 5V STANDBY 50% 0V tONG tONG: Time taken for capacitor Ccp 2 (charging capacitor) to fill up Ccp 1 (storing capacitor) to VM + VDD after a reset is released. The internal circuits cannot drive the gates correctly until the voltage of Ccp 1 reaches VM + VDD. Be sure to wait for tONG or longer before driving the motors. Basically, the larger the Ccp 1 capacitance is, the smaller the voltage fluctuation is, though the initial charge up time is longer. The smaller the Ccp 1 capacitance is, the shorter the initial charge-up time is, but the voltage fluctuation is larger. Depending on the combination of capacitors (especially with small capacitance), voltage may not be sufficiently boosted. When the voltage does not increase sufficiently, RON of output DMOS becomes lower than the reference value, which raises the temperature. Thus, use the capacitors under the capacitor combination conditions (Ccp 1 = 0.22 µF, Ccp 2 = 0.022 µF) recommended by Toshiba. 23 2005-04-04 TB62300FG External Capacitor for Charge Pump When driving a motor while VDD = 5 V, fchop = 150 kHz, L = 10 mH under the conditions of VM = 27 V and 2.0 A, the logical values for Ccp 1 and Ccp 2 are as shown in the graph below: Ccp 1 – Ccp 2 0.05 Applicable range 0.045 Ccp 2 capacitance (µF) 0.04 0.035 0.03 0.025 0.02 Recommended value 0.015 0.01 0.005 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Ccp 1 capacitance 0.45 0.5 (µF) Choose Ccp 1 and Ccp 2 to be combined from the above applicable range. We recommend Ccp 1:Ccp 2 at 10:1 or more. (If our recommended values (Ccp = 0.22 µF, Ccp 2 = 0.022 µF) are used, the drive conditions in the specification sheet are satisfied. (There is no capacitor temperature characteristic as a condition.) When setting the constants, make sure that the charge pump voltage is not below the specified value and set the constants with a margin (the larger Ccp 1 and Ccp 2, the more the margin). Some capacitors exhibit a large change in capacitance according to the temperature. Make sure the above capacitance is obtained under the IC ambient temperature. 24 2005-04-04 TB62300FG Recommended Application Circuit The values of external constants are example recommended values. For values under different input conditions, see the above-mentioned recommended operating conditions. (The following shows an example when fcho = 501 Hz (CR frequency = 800 kHz and constant-current limiter = 2.27 A) with serial signals placed in initial status.) Cosc = 560 pF CR 1 µF SGND Vref A 3V Rosc = 3.6 kΩ Vref 5V LGND 5V 0V STROBE A 5V 0V CLK A 5V 0V DATA A 5V 0V STROBE B 5V 0V CLK B 5V 0V DATA B 5V 0V SLEEP Vref B VM RRS A A LGND (FIN) LGND RRS A 0.11 Ω A M DC Motor 5V 0V PHASE A 5V 0V 5V 0V PHASE B 5V 0V 5V 0V ENABLE B 5V 0V 5V 0V MODE B 5V 0V BRAKE B B M DC Motor B ENABLE A RRS B RRS B 0.11 Ω MODE A PGND Ccp 1 Ccp 2 Ccp 1 0.22 µF Ccp 3 24 V P-GND BRAKE A 100 µF 10 µF VDD LGND Ccp 2 0.022 µF LGND Note: It is recommended to add bypass capacitors as required. Make sure that all gound pins are connected to the same ground rail. STROBE, CLK, and DATA must be tied to LGND if serial input is not used for settings or motor control. Because there may be short circuits between outputs, to supply, or to ground, be careful when designing output lines, VDD (VM) lines, and ground lines. 25 2005-04-04 TB62300FG Connection Diagram (when external forced PWM mode is used) 10 µF 3 V 3 V 0.5 Ω 10 µF 3.9 kΩ 2 VREF A SLEEP 35 3 VREF B ENABLE B 34 4 CR ENABLE A 33 5 VM PHASE B 32 DATA B 30 DATA A 29 CLK B 28 5V 10 µF 9 VDD LGND LGND NC 10 TEST A CLK A 27 NC 11 TEST B STROBE B 26 12 TEST C STROBE A 25 13 BRAKE A MODE B 24 14 BRAKE B MODE A 23 NC 22 15 NC 16 OUT A − M 0.5 Ω PHASE A 31 6 Ccp 1 0.022 µF 7 Ccp 2 0.22 µF 8 Ccp 3 5V 24 V 100 µF 270 pF RS B 36 1 RS A OUT B − 21 PGND 20 17 PGND 18 OUT A + M OUT B + 19 : Signal from central unit 26 2005-04-04 TB62300FG Package Dimensions HSOP36-P-450-0.65 Unit: mm Weight: 0.79 g (typ.) 27 2005-04-04 TB62300FG RESTRICTIONS ON PRODUCT USE 030619EBA • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 28 2005-04-04