www.fairchildsemi.com Application Note AN-6027 Design of Power Factor Correction Circuit Using FAN7530 1. Introduction The FAN7530 is an active power factor correction (PFC) controller for the boost PFC application that operates in the critical conduction mode (CRM). The critical conduction mode boost power factor converter operates at the boundary of continuous conduction mode and discontinuous conduction mode. The CRM PFC controllers are of two kinds: the current-mode CRM PFC controller and the voltage-mode CRM PFC controller. For the current mode, a boost switch is turned on when the inductor current reaches zero and turned off when the inductor current meets the desired current reference. In this case, the rectified AC line voltage should be sensed to generate the current reference, as in the FAN7527B; however, the sensing network can cause addi- tional power loss. In the voltage mode, the switch turn-on is the same as that of the current mode, but the switch turn-off is determined by an internal ramp signal. The ramp signal is compared with an error amplifier output and the switch turnon time is controlled to be constant, as shown in Figure 1. If the turn-on time is constant, the peak inductor current is proportional to the rectified AC line voltage, as shown in Figure 2. In this way, the input current waveform follows the waveform of the input voltage, thereby obtaining a good power factor. The FAN7530 is a voltage-mode CRM PFC controller. Because the voltage-mode CRM PFC controller does not need the rectified AC line voltage information, it can save the power loss of the sensing network. L D VOUT VOUT AC AC IN Turn-On Turn-On S R Turn-Off Turn-Off Q OCP RSENSE SENSE Feedback Feedback OVP Disable Ramp Error Amp Figure 1. Voltage Mode CRM Boost PFC Circuit Inductor Current MOSFET Conduction Diode Conduction Peak Inductor Current Average Input Current Gating Signal Constant On-time & Variable Off-time Figure 2. CRM Boost PFC Inductor Current Waveform © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com AN6027 APPLICATION NOTE Figure 3 shows the block diagram of the FAN7530. The only difference between the FAN7529 and the FAN7530 is the pin configuration of pin 2 and pin 3. For the FAN7529, the INV pin and the COMP pin are adjacent, but because the voltage of pin 1 is 2.5V and the operating range of pin 2 is from 1V to 5V, the PFC output voltage can increase at light load if pins 1 and 2 are shorted. For the FAN7530, however, the INV pin and the MOT pin are adjacent. Because the voltage of the MOT pin is 2.9V, the over-voltage protection works if pin 1 and pin 2 are shorted. Block Diagram 2.5V Ref VCC 8 UVLO Vref VCC Internal Bias 12V 8.5V Drive Output Disable 150μs Timer ZCD 5 S 6.5V Q 1.4V 1.5V R Zero Current Detector CS OVP 4 Disable 40k 8pF 0.8V Ramp Signal MOT 2 7 OUT 13V 2.675V 2.5V 0.45V 0.35V Current Protection Comparator Vref 1V Offset Error Amplifier Sawtooth Generator Gm 1V~5V Range 6 3 GND COMP 1 INV Figure 3. Block Diagram of the FAN7530 Showing Error Amplifier Block, Zero Current Detector Block, Sawtooth Generator Block, Over-Current Protection Block, and Switch Drive Block © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 2 AN6027 APPLICATION NOTE 2. Device Block Description the junction capacitor of the MOSFET resonates with the boost inductor and the auxiliary winding voltage decreases resonantly. If it reaches 1.4V, the zero current detector turns on the MOSFET. The ZCD pin is protected internally by two clamps: the 6.5V HIGH clamp and the 0.65V LOW clamp, as shown in Figure 5. 2.1 Error Amplifier Block The error amplifier block consists of a transconductance amplifier, output OVP comparator, and disable comparator. For the output voltage control, a transconductance amplifier is used instead of the conventional voltage amplifier. The transconductance amplifier (voltage controlled current source) aids the implementation of OVP and disable function. The output current of the amplifier changes according to the voltage difference of the inverting input and the noninverting input of the amplifier. The output voltage of the amplifier is compared with the internal ramp signal to generate the switch turn-off signal. The OVP comparator shuts down the output drive block when the voltage of the INV pin is higher than 2.675V and there is 0.175V hysteresis. The disable comparator disables the operation of the FAN7530 when the voltage of the inverting input is lower than 0.45V and there is 100mV hysteresis. An external, small-signal MOSFET can be used to disable the IC, as shown in Figure 4. The IC operating current decreases to under 65µA to reduce power consumption if the IC is disabled. Turn-on Signal Timer S Q R VIN ZCD 5 6.5V 1.4V 1.5V Zero Current Detector Figure 5. Zero Current Detector Block 2.675V OVP Disable 0.45V 2.5V Gm 2 IPEAK 0.35V tzero Inductor Current V OUT V ref (2.5V) Error Amp Figure 6 shows typical ZCD-related waveforms. Because the ZCD pin has some capacitance, there can be some delay caused by Rzcd and the turn-on time can be delayed. 0A ton tdis INV toff 1 COMP INEG Disable Signal n·(V OUT-V IN) V AUX 0V -n·V IN Delay Time V clamp Figure 4. Error Amplifier Block ZCD Voltage V th R ZCD Delay 2.2 Zero Current Detection Block OUT The zero current detector (ZCD) generates the turn-on signal of the MOSFET when the boost inductor current reaches zero using an auxiliary winding coupled with the inductor. Because the polarity of the auxiliary winding is opposite the inductor winding, the auxiliary winding voltage is negative and proportional to the rectified AC line voltage when the MOSFET is turned on. If the MOSFET is turned off, the voltage becomes positive and proportional to the difference between VOUT and VIN. If the inductor current reaches zero, © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 0V V OUT V DS Minimum Voltage Turn-on 0V Figure 6. Zero Current Detector Waveform www.fairchildsemi.com 3 AN6027 APPLICATION NOTE Ideally, the switch must be turned on when the inductor current reaches zero; but because of the structure of the ZCD block and Rzcd delay, it is turned on after some delay time. During this delay time, the stored charge of the COSS (MOSFET output capacitor) is discharged through the path indicated in Figure 7. This charge is transferred into a small filter capacitor, Cin1, which is connected to the bridge diode. Therefore, there is no current flow from the input side, meaning the input current Iin is zero during this period. For better total harmonic distortion (THD), it is important to make tzero / TS as small as possible. As shown in Figure 6, tzero is proportional to L ⋅ C oss but ton and tdis are proportional to L. Therefore tzero / TS is approximately inversely proportional to L . Therefore THD increases as the inductance decreases. Reducing the inductance can decrease the inductor size and cost but the switching loss increases because of the increased switching frequency. In real case, boost diode’s junction capacitance and boost inductor’s parasitic capacitance should be added to COSS when calculating tzero. That means it is important to minimize the parasitic capacitance of the boost inductor and diode junction capacitance for better THD. iin L AC IN D Off Signal 1V Offset MOT Sawtooth Generator 3 2.9V Error Amp Output Figure 8. Sawtooth Generator Block 2.4 Over-Current Protection Block The MOSFET current is sensed using an external sense resistor for over-current protection. If the CS pin voltage is higher than 0.8V, the over-current protection comparator generates a protection signal to turn off the MOSFET. An internal R/C filter has been included to filter switching noise. CS 4 OCP S ig n a l 40k 8pF 0 .8 V V OUT O v e r-C u rre n t P ro te c tio n C o m p a ra to r iL C IN1 CO Q Figure 9. Over-Current Protection Block C OSS 2.5 Switch Drive Block The FAN7530 contains a single totem-pole output stage designed specifically for a direct drive of a power MOSFET. The drive output is capable of up to 500mA peak sourcing current and 800mA peak sinking current with a typical rise and fall time of 50ns with a 1.0nF load. Additional circuitry has been added to keep the drive output in a sinking mode whenever the UVLO is active. The output voltage is clamped at 13V to protect the MOSFET gate even when the VCC voltage is higher than 13V. Figure 7. Current Flow During tzero In the ZCD block, there is an internal timer to provide a means to start or restart the switching if the drive output has been low for more than 150µs from the falling edge of the drive output. Without this timer, the PFC converter does not work because the inductor current is always zero when the IC initially starts operation and the ZCD winding voltage does not become positive without any switching. 2.3 Sawtooth Generator Block The output of the error amplifier and the output of the sawtooth generator are compared to determine the MOSFET turn-off instant. The slope of the sawtooth is determined by an external resistor connected at the maximum on time (MOT) pin. The voltage of the MOT pin is 2.9V and the slope is proportional to the current flowing output of the MOT pin. The maximum on time is determined when the output of the error amplifier is 5V. When a 40.5kΩ resistor is connected, the maximum on time is 24µs. As the resistance increases, the maximum on time increases, because the slope decreases. The MOSFET on time is zero when the output of the error amplifier is lower than 1V. © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 4 AN6027 APPLICATION NOTE 3.Circuit Components Design 3.1 Power Stage Design 4 ⋅ fsw (min) 1) Boost Inductor Design The boost inductor value is determined by the output power and the minimum switching frequency. The minimum switching frequency must be above the audio frequency (20kHz) to prevent audible noise. The maximum switching period, TS(max), is a function of Vin(peak) and Vo, the output voltage. It can have a maximum value at the highest input voltage or at the lowest input voltage according to Vo. Compare TS(max) at Vin(peak_min) and Vin(peak_max), then select the higher value for the maximum switching period. The boost inductor value can be obtained by Equation 6. ton = L ⋅ IL( peak ) (t ) Vin( peak ) sin(ωt ) = L⋅ = L⋅ toff = L ⋅ = L⋅ 2 ⋅ Iin( peak ) sin(ωt ) Vin( peak ) sin(ωt ) ⎞ ⎟ ⎟ ⎠ (6) The auxiliary winding voltage is lowest at the highest line. So the turn number of the auxiliary winding can be obtained by Equation 7. The voltage should be higher than the ZCD threshold voltage of 1.5V. 1.5V ⋅ NP Naux > (1) (7) (Vo − 2Vin( peak _ max) ) 3) Input Capacitor Design The voltage ripple of the input capacitor is maximum when the line is lowest and the load is heaviest. If fsw(min) >> fac, the input current can be assumed to be constant during a switching period. Vin( peak ) Inductor Current 2 ⋅ I in (2) Vo − Vin( peak ) sin(ωt ) 2 ⋅ Iin( peak ) sin(ωt ) Input Current Vo − Vin( peak ) sin(ωt ) 2 ⋅ Vo ⋅ Io η ⋅ Vin( peak ) I in t on / 2 (3) t on t off Figure 10. Input Current and Inductor Current Waveform During a Switch Cycle TS = ton + toff ⎛ ⎞ 1 sin(ωt ) = 2 ⋅ L ⋅ Iin( peak ) ⎜ + ⎟ (4) ⎜ Vin( peak ) Vo − Vin( peak ) sin(ωt ) ⎟ ⎝ ⎠ Vin( peak ) ⋅ sin(ωt ) ⎞ 4 ⋅ L ⋅ Vo ⋅ Io ⎛ = ⎜1+ ⎟ 2 ⎜ η ⋅ Vin( peak ) ⎝ Vo − Vin( peak ) sin(ωt ) ⎟⎠ 4 ⋅ L ⋅ Vo ⋅ Io (max) ⎛ Vin ( peak ) = ⎜1 + 2 ⎜ Vo − Vin ( peak ) η ⋅ Vin ( peak ) ⎝ ⎛ Vin ( peak ) ⋅ Vo ⋅ Io (max) ⎜ 1 + ⎜ V o − Vin ( peak ) ⎝ 2) Auxiliary Winding Design 2 ⋅ Iin( peak ) IL( peak ) (t ) Iin( peak ) = TS (max) η ⋅ Vin ( peak )2 L= ⎞ ⎟ ⎟ ⎠ Cin ≥ ≥ ≥ (5) 2 ton 2 0 ΔVin(max) ∫ Iin ( peak _ max) ⎛ ⎜⎜ Iin( peak _ max) − 2 ton ⎝ ton ⋅ Iin( peak _ max) 2 ⋅ ΔVin(max) ⎞ t ⎟⎟ dt ⎠ (8) L ⋅ Io2(max) ⋅ Vo2 ΔVin(max) ⋅ Vin3( peak _ min) The input capacitor must be larger than the value calculated by Equation 8 and the maximum input capacitance is limited by the input displacement factor (IDF), defined as IDF≡cosθ. As shown in Figure 11, the input capacitor generates 90° © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 5 AN6027 APPLICATION NOTE 4) Output Capacitor Design leading current, which causes phase difference between the line current and the line voltage. The phase difference increases as the capacitance of the input capacitor increases. Therefore, the input capacitor must be smaller than Cin(max) calculated by Equation 12. Cin(max) is the sum of all the capacitors connected at the input side. Va = VA = Vin( peak ) cos(ωt ) The output capacitor is selected by the relationship between the input and output power. As shown in Figure 13, the minimum output capacitance is determined by Equation 14. IIN (9) ID + + i A = i a + ic = Ia cos(ωt ) − ω ⋅ Cin ⋅ Vin( peak ) sin(ωt ) LOAD CO VIN i a = Ia cos(ωt ) IO PFC − (10) VO − Figure 12. PFC Configuration ⎛ ω ⋅ Cin ⋅ Vin( peak ) ⎞ ⎟⎟ Ia ⎝ ⎠ Ia = tan cos−1(IDF ) ω ⋅ Vin( peak ) θ = tan−1 ⎜⎜ Cin(max) ( = 2 ⋅ Vo ⋅ Io ω ⋅ Vin2( peak _ max) (11) Pin = Iin( rms ) ⋅ Vin( rms ) ⋅ (1 − cos(2ωt ) ) = IDVo ) ID = ( tan cos−1(IDF ) ) Iin ( rms ) ⋅ Vin( rms ) Vo (1 − cos(2ωt )) = Io ⋅ (1 − cos(2ωt ) ) (12) (13) ID(avg) = IO (1- cos(2ωt)) Lin iA ia iC + Cin VA − IO + PFC Circuit Va ΔVO = − IO ωCO VO Input Filter Figure 13. Diode Current and Output Voltage Waveform Im iA Co(min) ≥ iC θ ia 2π ⋅ fac ⋅ ΔVo(max) (14) 5) MOSFET and Diode Selection Re The maximum MOSFET RMS current is obtained by Equation 15 and the conduction loss of the MOSFET is calculated by Equation 16. When MOSFET turns on, the MOSFET current rises from zero, so the turn-on loss is negligible. The MOSFET turn-off loss and the MOSFET discharge loss are obtained by Equations 17 and 18, respectively. The switching frequency of the critical conduction mode boost PFC converter varies according to the line and load conditions. VA Figure 11. Input Voltage and Current Displacement Due to Input Filter Capacitance © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 Io(max) www.fairchildsemi.com 6 AN6027 APPLICATION NOTE The switching frequency is the average value during a line period. The total MOSFET loss can be calculated by Equation 19 and a MOSFET can be selected considering the MOSFET thermal characteristic. IQrms = IL( peak _ max) = η ⋅ Vin(LL ) 1 4 2 ⋅ Vin( LL ) − 6 9π ⋅ Vo 2 Pon = IQrms ⋅ RDSon = R o1 1 4 2 ⋅ Vin( LL ) − 6 9π ⋅ Vo 2 2 ⋅ Vo ⋅ Io(max) Pturn −off = PFC OUT 1 Cp (15) 4 Coss.Vo ⋅ Vo2 ⋅ fsw 3 + Pturn −off + Pdisch arg e Pdisch arg e = PMOSFET = Pon Figure 14. Output Voltage Sensing Circuit (17) The feedback loop bandwidth must be lower than 20Hz for the PFC application. If the bandwidth is higher than 20Hz, the control loop may try to reduce the 120Hz ripple of the output voltage and the line current may be distorted, decreasing the power factor. A capacitor is connected between COMP and GND to eliminate the 120Hz ripple voltage by 40dB. If a capacitor is connected between the output of the error amplifier and the GND, the error amplifier works as an integrator and the error amplifier compensation capacitor can be calculated by Equation 23. To improve the power factor, Ccomp must be higher than the calculated value. If the value is too high, the output voltage control loop may become slow. (18) (19) The diode average current can be calculated by Equation 20. The total diode loss can be calculated by Equation 21. Select a diode considering diode thermal characteristic. IDavg = Io(max) (20) PDiode = Vf ⋅ IDavg (21) Ccomp = gm ⋅ 3.2 Control Circuit Design 1) Output Voltage Sensing Resistor and Feedback Loop Design © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 Ro 2 0.01⋅ 2π ⋅ 120Hz ⋅ (Ro1 + Ro 2 ) (23) To improve the output voltage regulation, a resistor and a capacitor can be added to a simple integrator, as shown in Figure 15. The resistor, Rcomp, increases mid-band gain and the capacitor, Cfilter, which is 1/10~1/5 of the Ccomp, is used to filter high-frequency noise. The gain of the error amplifier with the circuit in Figure 15 is shown in Figure 16. The output voltage sensing resistors, Ro1 and Ro2, are determined by the output voltage at the high line by Equation 22. The output voltage sensing resistors cause power loss, therefore Ro1 should be higher than 1MΩ. Too high resistance can cause some delay of the OVP circuit due to internal capacitance (Cp), which may slightly increase the OVP level. Ro1 Vo _ high − 2.5 = Ro 2 2.5 R o2 (16) 1 Vo ⋅ IL( peak _ max) ⋅ tf ⋅ fsw 6 2 2 Vo ⋅ Io(max) ⋅ tf ⋅ fsw 3 η ⋅ Vin( LL ) INV (22) www.fairchildsemi.com 7 AN6027 APPLICATION NOTE crossing point of the AC line, as shown in Figure 18. To minimize the zero crossing distortion, COSS must be minimized and a larger inductor should be used. There is a limitation in minimizing COSS and using a large inductor because a small MOSFET increases MOSFET conduction loss and a larger inductor is more expensive. VOUT Error Amp Ro1 INV 1 Gm Ro2 Vref 3 INEG = (25) COMP IPEAK Rcomp tzero Inductor Current Cfilter Ccomp Coss ⋅ (Vo − Vin ) L 0A ton tdis INEG toff Figure 15. Error Amplifier Circuit n·(VOUT-VIN) VAUX Integrator C comp 0V -n·VIN Proportional gain R comp Delay Time Freq Vclamp ZCD Voltage C filter High frequency Noise filter Vth RZCD Delay 0V OUT Figure 16. Gain of the Error Amplifier Figure 17. ZCD Waveforms 2) Zero Current Detection Resistor Design If the RZCD is selected appropriately, the MOSFET can be turned on when the Vds voltage is minimum to reduce switching loss. It is recommended to design the RZCD to turn on the MOSFET when the Vds voltage is minimum. The ZCD current should be less than 10mA; therefore the zero current detection resistor, RZCD is determined by Equation 24. ⎛ N ⋅V ⎞ RZCD = ⎜ aux o − 5.8V ⎟ /10mA ⎜ Np ⎟ ⎝ ⎠ To improve the zero crossing distortion, the MOSFET turnon time should be increased near the AC line zero crossing point. If a resistor is connected between the MOT and the auxiliary winding, as shown in Figure 19, the function can be implemented easily. Because the auxiliary winding voltage is negatively proportional to the input voltage during the MOSFET turn-on time, the current I2 is proportional to the input voltage (as shown in Figure 19). Therefore, the slope of the internal ramp changes according to input voltage as the current flowing out of the MOT pin changes, as shown in Figure 20. I2 current is maximum at the highest line voltage and the zero crossing improvement is best when I2 is 100% ~ 200% of I1. R2 value should be chosen by experiment. (24) Because the ZCD pin has some capacitance, the ZCD resistor and the capacitor cause some delay for ZCD detection, as shown in Figure 17. Because of this delay, the MOSFET is not turned on when the inductor current reaches zero and the MOSFET junction capacitor and the inductor resonate. The inductor current changes its direction and flows negatively. The peak value of this negative current is determined by Equation 25. As shown in Equation 25, the negative current increases as the input voltage is close to zero and COSS increases. This negative current decreases average inductor current and causes zero crossing distortion near the zero © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 8 AN6027 APPLICATION NOTE 3) Start-up Circuit Design To start up the FAN7530, the start-up current must be supplied through a start-up resistor. The resistor value is calculated by Equations 26 and 27. The start-up capacitor must supply IC operating current before the auxiliary winding supplies IC operating current, maintaining VCC voltage higher than the UVLO voltage. The start-up capacitor is determined by Equation 28. Output Voltage 1st Input Current 3rd RST ≤ 5th Vin( peak _ min) − Vth(st )max PRST = CST ≥ Figure 18. Zero Crossing Distortion (26) IST max Vin2( rms _ max) ≤ 1W (27) Idcc 2π ⋅ fac ⋅ HY(ST )min (28) RST 4) Current Sense Resistor Design L AC IN VAUX I2 D The CS pin voltage is highest when the AC line voltage is lowest and the output power is maximum. The current sense resistor is determined by Equations 29 and 31, limiting the power loss of the resistor to under 1W. VO NAUX RZCD R2 ZCD Rsense < CO VCC FAN7529 INV PRsense MOT CS I1 COMP R1 0.8V IL( peak _ max) η ⋅ Vin( peak _ min) ⎛ Vo ⋅ Io(max) = 2⋅⎜ ⎜ ⎝ η ⋅ Vin( peak _ min) Rsense < GND = 0.8V 4 ⋅ Vo ⋅ Io(max) (29) 2 ⎞ ⎟ ⋅ Rsense < 1W ⎟ ⎠ 1 ⎛ η ⋅ Vin ( peak _ min) ⋅⎜ 2 ⎜⎝ Vo ⋅ Io(max) ⎞ ⎟ ⎟ ⎠ (30) 2 (31) Figure 19. Zero Crossing Improvement Circuit Ramp Slope Change Slope Decrease VAC Slope Increase VEAO On-time Increase Ramp Variable On-time On-time Decrease Figure 20. On-Time Variation According to VAC © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 9 AN6027 APPLICATION NOTE 4. Design Example A 100W converter is used here to illustrate the design procedure using a design spreadsheet. Enter the system parameters in the file to get the designed parameters. The system parameters are as follows: • • • • • • • • • Maximum output power Input voltage range Output voltage AC line frequency PFC efficiency Minimum switching frequency Input displacement factor (IDF) Input capacitor ripple voltage Output voltage ripple 100W 90Vrms~264Vrms 392V 60Hz 90% 37kHz 0.98 24V 8V 4.1 Inductor Design The boost inductor is determined by Equation 6. Calculate it at both the lowest voltage and the highest voltage of the AC line and choose the lower value. The calculated value in this example is 403µH. To get the calculated inductor value, EI30 core is used and the primary winding is 44 turns. The air gap is 0.6mm at both legs of the EI core. The auxiliary winding number, determined by Equation 7, is five; but if more windings are used, the number is six. ZCD pin and the ground to increase the delay time for the MOSFET minimum voltage turn-on. 4.7 Start-up Circuit Design The maximum start-up resistor is 1.63MΩ and the minimum is 140kΩ, as determined by Equations 26-27. The selection is 330kΩ. The VCC capacitance must be larger than 7µF, calculated by Equation 28, so the selected value is 47µF. 4.8 Current Sense Resistor Design The maximum current sense resistance is 0.23Ω as a result of Equation 31 and the selected value is 0.2Ω. 4.9 MOT Resistor Design The MOT resistor is determined to get the maximum on-time when the AC line voltage is lowest and the output power is maximum. The calculated value is 20.44kΩ and the maximum on-time is 12.26µs. To improve THD performance, a 33kΩ resistor is used for the MOT resistor and a 370kΩ resistor is connected between the MOT pin and the auxiliary winding. The maximum on-time is determined by Equation 32 and the MOT resistor is determined by Equation 33. MOT = 4.2 Input Capacitor Design The minimum input capacitance is determined by the input voltage ripple specification. The calculated minimum input capacitor value is 0.33µF. The maximum input capacitance is restricted by the IDF. The calculated value is 0.77µF. The selected value is 0.63µF (sum of all the capacitors connected to the input side, C1, C2, C3, C4, and C5). 4.3 Output Capacitor Design The minimum output capacitor is determined by Equation 14 and the calculated value is 85µF. The selected value for the capacitor is 100µF. 4.4 MOSFET and Diode Selection RMOT > (33) Error Amp. Output Switching Nosie The upper output voltage sense resistor is chosen to be 2MΩ and the bottom output voltage sense resistor is 12.6kΩ. The error amplifier compensation capacitance must be larger than 0.1µF, as calculated by Equation 23. Therefore, 0.22µF capacitor is used. © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 MOT × 1012 600 (32) As shown in Figure 21, noise voltage can be added to the internal ramp signal during MOSFET turn-on. Because of this noise, the AC line current waveform can be distorted if the error amplifier output voltage is close to 1V. It is recommended to use higher resistor for MOSFET turn-on if there is waveform distortion and use a turn-off diode to speed up the turn-off process. 4.5 Output Voltage Sense Resistor and Feedback Loop Design The calculated value is 3.1kΩ and the selected value is 20kΩ. A 47pF ceramic capacitor is connected between the ⋅ 10−6 4.10 MOSFET Gate Drive Resistor Design By calculating Equations 15-19, a 500V/13A MOSFET FQPF13N50C is selected, and a 600V/1A diode BYV26C is selected by the result of Equations 20-21. 4.6 Zero Current Detection Resistor Design 2 ⋅ L ⋅ Po η ⋅ Vin2( rms _ min) Internal Ramp Signal IC OUT Signal Figure 21. Turn-on Noise on Internal Ramp Signal Figure 22 shows the designed application circuit diagram and Table 2 shows the 100W demo board components list. www.fairchildsemi.com 10 AN6027 APPLICATION NOTE T1 PFC OUTPUT VAUX D2 C5 R4 R3 R5 V1 5 6 C6 CS COMP R1 R8 F1 ZCD 7 R11 4 2 1 INV C1 C9 FAN7530 R2 3 C2 R6 C11 OUT Vcc 8 D1 GND ZD1 C3 C4 LF1 Q1 MOT NTC R10 D3 C10 R9 BD C7 R7 C8 AC INPUT Figure 22. Application Circuit Schematic © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 11 AN6027 APPLICATION NOTE Table 2. 100W Demo Board Part List PART# VALUE NOTE PART# Fuse F1 V1 RT1 VALUE NOTE Capacitor 250V/3A C1 150nF/275VAC Box Capacitor TNR C2 470nF/275VAC Box Capacitor C3,C4 2.2nF/3kV Ceramic Capacitor NTC C6 22µF/25V Electrolytic Capacitor 10D-9 C7 47nF/50V Ceramic Capacitor Resistor C8 220nF MLCC 471 470V R1 42kΩ 1/4W C9 100µF/450V Electrolytic Capacitor R2 370kΩ 1/4W C10 12nF/100V Film Capacitor R3 330kΩ 1/2W C11 47pF/50V Ceramic Capacitor R4 150Ω 1/2W R5 20kΩ 1/4W BD KBL06 Fairchild R6 100Ω 1/4W D1 1N4148 Fairchild R7 0.2Ω 1/2W D2 BYV26C 600V/1A R8 10kΩ 1/4W D3 SB140 Fairchild R9 10kΩ 1/4W ZD1 1N4746 Fairchild R10 2MΩ 1/4W R11 12.6kΩ 1/4W IC1 LF1 Diode Inductor T1 400µH(44T:6T) EI3026 IC Primary: 0.2φ*10, from Pin 5 to Pin 3 FAN7530 Secondary: 0.2φ, from Pin 2 to Pin 4 Line Filter MOSFET 38mH Wire 0.45mm Q1 FQPF13N50C 500V/13A Table 3. Performance Data 100W 50W 90VAC 110VAC 220VAC 264VAC PF 0.999 0.998 0.991 0.985 THD 3.97% 4.43% 5.25% 5.47% Efficiency 90.3% 92.7% 94.7% 95.2% PF 0.998 0.997 0.974 0.956 THD 4.81% 5.28% 6.74% 7.67% Efficiency 90.1% 90.8% 91.7% 92.5% © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 12 AN6027 APPLICATION NOTE Table 4. 200W Demo Board Part List (600µH, Wide Input Range Application) PART# VALUE NOTE PART# VALUE Fuse F1 V1 RT1 NOTE Capacitor 250V/5A C1 470nF/275VAC Box Capacitor TNR C2 470nF/275VAC Box Capacitor C3,C4 2.2nF/3kV Ceramic Capacitor NTC C6 47µF/25V Electrolytic Capacitor 10D-9 C7 47nF/50V Ceramic Capacitor Resistor C8 220nF MLCC 471 470V R1 37kΩ 1/4W C9 220µF/450V Electrolytic Capacitor R2 250kΩ 1/4W C10 12nF/100V Film Capacitor R3 330kΩ 1/2W C11 47pF/50V Ceramic Capacitor R4 150Ω 1/2W R5 20kΩ 1/4W BD KBU8K Fairchild R6 100Ω 1/4W D1 1N4148 Fairchild R7 0.1Ω 1W D2 SUF30J 600V/3A R8 10kΩ 1/4W D3 SB140 Fairchild R9 10kΩ 1/4W ZD1 1N4746 Fairchild R10 2MΩ 1/4W R11 12.6kΩ 1/4W IC1 LF1 Diode Inductor T1 200µH(30T:3T) PQ3230 IC Primary: 0.1φ*100, from Pin 5 to Pin 3 FAN7530 Secondary: 0.2φ, from Pin 2 to Pin 4 Line Filter MOSFET 22mH Wire 0.7mm Q1 FDPF20N50 Fairchild Table 5. Performance Data 200W 150W 100W 85VAC 115VAC 230VAC 265VAC PF 0.999 0.998 0.993 0.990 THD 3.8% 4.3% 6.5% 6.5% Efficiency 91.8% 94.8% 96.9% 97.3% PF 0.999 0.998 0.990 0.985 THD 4.7% 5.2% 7.0% 6.9% Efficiency 93.3% 95.5% 96.9% 97.0% PF 0.997 0.996 0.981 0.971 THD 6.5% 7.4% 9.0% 8.5% Efficiency 94.3% 95.3% 96.2% 96.0% © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 13 AN6027 APPLICATION NOTE Table 6. 300W Wide Input Range Application Part List PART# VALUE NOTE PART# Fuse F1 V1 RT1 VALUE NOTE Capacitor 250V/5A C1 680nF/275VAC Box Capacitor TNR C2 680nF/275VAC Box Capacitor C3,C4 2.2nF/3kV Ceramic Capacitor NTC C6 47µF/25V Electrolytic Capacitor 6D-22 C7 33nF/50V Ceramic Capacitor Resistor C8 220nF MLCC 471 470V R1 60kΩ 1/4W C9 33µF/450V Electrolytic Capacitor R2 330kΩ 1/4W C10 12nF/100V Film Capacitor R3 330kΩ 1/2W C11 9pF/50V Ceramic Capacitor R4 100Ω 1/2W R5 20kΩ 1/4W BD KBU8J Fairchild R6 100Ω 1/4W D1 1N4148 Fairchild R7 0.06Ω 1W D2 SUF30J 600V/3A R8 10kΩ 1/4W D3 SB140 Fairchild R9 10kΩ 1/4W ZD1 1N4746 Fairchild R10 2MΩ 1/4W R11 12.6kΩ 1/4W IC1 LF1 Diode Inductor T1 200µH(36T:3T) PQ3535 IC Primary: 0.1φ, *100, from Pin 5 to Pin 3 FAN7530 Secondary: 0.2φ, from Pin 2 to Pin 4 Line Filter MOSFET 40mH Wire 1mm Q1 FQA28N50 Fairchild Table 7. Performance Data 300W 225W 150W 75W 85VAC 115VAC 230VAC 265VAC PF 0.999 0.998 0.993 0.988 THD 4.5% 4.7% 6.4% 6.5% Efficiency 91.4% 94.5% 97.4% 97.7% PF 0.999 0.998 0.989 0.982 THD 3.9% 4.7% 6.1% 6.2% Efficiency 92.8% 95.1% 97.4% 97.7% PF 0.998 0.997 0.978 0.963 THD 4.8% 5.8% 7.4% 7.4% Efficiency 94.0% 95.7% 97.0% 97.3% PF 0.994 0.989 0.929 0.885 THD 9.3% 10.8% 11.2% 12.0% Efficiency 94.8% 95.9% 95.3% 95.2% © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 14 AN6027 APPLICATION NOTE Nomenclature RST: start-up resistance Ccomp: compensation capacitance Rzcd: zero current detection resistance CIN: input capacitance tf: MOSFET current falling time COUT: output capacitance toff: switch off time CST: start-up capacitance ton: switch on time fac: AC line frequency TS: switching period fsw(max): maximum switching frequency Vin (peak): input voltage peak value fsw(min): minimum switching frequency Vin (peak_low): input voltage peak value at low line fsw: switching frequency Vin (peak_max): maximum input voltage peak value HY(ST) min: minimum UVLO hysteresis Vin (peak_min): minimum input voltage peak value ID: boost diode current Vin (rms): input voltage RMS value IDavg: diode average current Vin (rms_max): maximum input voltage RMS value IDrms: diode RMS current Vin (rms_min): minimum input voltage RMS value Iin (peak): input current peak value Vin (t): input voltage Iin (peak_max): maximum of the input current peak value VO or VOUT: output voltage Iin (rms): input current RMS value ΔVin (max): maximum input voltage ripple Iin (t): input current ΔVO (max): maximum output voltage ripple IL (t): inductor current η: converter efficiency IL(peak) (t): inductor current peak value during one switching ω: AC line angular frequency cycle IL(peak): inductor current peak value during one AC line cycle IL(peak_max): maximum inductor current peak value IO (max): maximum output current IO: output current IQrms: MOSFET RMS current ISTmax: maximum start-up supply current L: boost inductance Naux: auxiliary winding turn number NP: boost inductor turn number Pin: input power PO(max): maximum output power PO: output power Rsense: current sense resistance © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 www.fairchildsemi.com 15 AN6027 APPLICATION NOTE DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reason ably expected to result in significant injury to the user. © 2006 Fairchild Semiconductor Corporation Rev. 1.0.3 • 1/11/07 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 16

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