UNISONIC TECHNOLOGIES CO., LTD LS3718 CMOS IC 20-BIT SERIAL TO PARALLEL CONVERTER DESCRIPTION The UTC LS3718 is a 20-bit serial to parallel converter utilizing CMOS Technology. It is incorporates control circuit, shift register, latch and driver into a single ship. It is suitable for MCU interface. The effective interface assignment of MPU is available as the connection between UTC LS3718 and MPU is required only 4 lines. The device is designed to operate up to 5MHz. When the serial data input to the DATA terminal and the data is output from parallel output buffer through serial in parallel out shift register and parallel data latches. The data can through the shift register serial output to the SO terminal. Therefore the UTC LS3718 can cascade connection to expand the output data number. The hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25mA) can drive LED directly. *Pb-free plating product number: LS3718L FEATURES * 20-Bit serial in parallel out * Cascade connection * Operating voltage 5V±10% * Hysteresis input 0.5V typ * Output current 25mA * Operating frequency 5MHz or more ORDERING INFORMATION Ordering Number Normal Lead Free Plating LS3718-S28-R LS3718L-S28-R LS3718-S28-T LS3718L-S28-T www.unisonic.com.tw Copyright © 2007 Unisonic Technologies Co., Ltd Package Packing SOP-28 SOP-28 Tape Reel Tube 1 of 8 QW-R121-015.A LS3718 CMOS IC PIN CONFIGURATION P9 P10 P11 P12 P13 P14 VSS P15 P16 P17 P18 P19 P20 SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P8 P7 P6 P5 P4 P3 VSS P2 P1 CLR STB CLK DATA PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME P9 P10 P11 P12 P13 P14 VSS P15 P16 P17 P18 P19 P20 SO DATA CLK STB CLR P1 P2 VSS P3 P4 P5 P6 P7 P8 VDD I/O O O O O O O O O O O O O O I I I I O O O O O O O O DESCRIPTION Parallel Data Output Pin 9 Parallel Data Output Pin 10 Parallel Data Output Pin 11 Parallel Data Output Pin 12 Parallel Data Output Pin 13 Parallel Data Output Pin 14 GND Parallel Data Output Pin 15 Parallel Data Output Pin 16 Parallel Data Output Pin 17 Parallel Data Output Pin 18 Parallel Data Output Pin 19 Parallel Data Output Pin 20 Serial Data Output Pin Serial Data Input Pin Clock Signal Input Pin Data Strobe, Low Actived Data Reset, Low Actived Parallel Data Output Pin 1 Parallel Data Output Pin 2 GND Parallel Data Output Pin 3 Parallel Data Output Pin 4 Parallel Data Output Pin 5 Parallel Data Output Pin 6 Parallel Data Output Pin 7 Parallel Data Output Pin 8 Power Supply UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 8 QW-R121-015.A LS3718 CMOS IC BLOCK DIAGRAM P1~P20 driver STB CLR control CLK latch shift register SO DATA UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 8 QW-R121-015.A LS3718 CMOS IC ABSOLUTE MAXIMUM RATINGS (Ta=25℃) PARAMETER SYMBOL RATINGS UNIT Supply Voltage VDD -0.5~+7.0 V Input Voltage VIN VSS-0.5~VDD+0.5 V Output Voltage VOUT VSS-0.5~VDD+0.5 V Output Current IOUT ±25 mA Power Dissipation PD 500 mW Junction Temperature TJ +125 ℃ Operating Temperature TOPR -25 ~ +85 ℃ Storage Temperature TSTG -40 ~ +150 ℃ Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. ELECTRICAL CHARACTERISTICS (VDD=4.5~5.5V, VSS=0V, Ta=25℃) PARAMETER Operating Voltage Operating Current Input Leakage Current High-Level Input Voltage Low-Level High-Level Output Voltage Low-Level MAX UNIT 5.5 V VIH=VDD, VIL=VSS 0.1 mA VIN=0~VDD -10 10 µA 0.7VDD VDD V VSS 0.3 VDD IOH=-0.4mA 4.0 4.97 VDD SO Terminal V IOL=+3.2mA VSS 0.11 0.4 IOH=-25mA VDD-1.5 VDD-0.5 VDD V High-Level VOHP IOH=-15mA VDD-1.0 VDD-0.3 VDD P1~P20 VDD-0.5 VDD-0.2 VDD IOH=-10mA Output Voltage Terminals (Note) IOL=+25mA VSS 0.5 1.5 Low-Level VOLP V IOL=+15mA VSS 0.3 0.8 VSS 0.2 0.4 IOL=+10mA Note: Specified value represent output current per pin. When use, total current consideration and less than power dissipation rating operation should be required. SYMBOL VDD IS II(LEAK) VIH VIL VOH VOL TEST CONDITIONS MIN 4.5 TYP SWITCHING CHARACTERISTICS (VDD=4.5~5.5V, VSS=0V, Ta=-20~75℃) PARAMETER Data Set-up Time Data Hold Time Set-up Time Hold Time Output Delay Time Max. Operating Frequency Note: COUT=50pF SYMBOL tSD tHD tSSTB tHSTB tPD O tPD PCK tPD PSTB tPD PCLR fMAX TEST CONDITIONS DATA-CLK CLK-DATA STB-CLK CLK-STB CLK-SO CLK-P1~P20 STB-P1~P2 CLR-P1~P20 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN 20 20 30 30 TYP MAX 70 100 80 80 5 UNIT ns ns ns ns ns ns ns ns MHz 4 of 8 QW-R121-015.A LS3718 CMOS IC SWITCHING CHARACTERISTICS TEST WAVEFORM fMAX CLK tSD DATA tHD STB tHSTB tSSTB CLK tPD o SO CLK tPD pck STB P1~P 20 H CLK STB tPD STB P1~P 20 CLR DATA tPD PCLR P1~P 20 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 8 QW-R121-015.A LS3718 CMOS IC FUNCTION DESCRIPTION RESET When the CLR terminal is "L" level, all latches are reset and all of parallel output are "L" level. Normally, the CLR terminal should be "H" level. DATA TRANSMISSION When the STB terminal is "H" level and input the clock signal to the CLK terminal, the serial data input the DATA terminal and shift in the shift register by synchronizing at rising edge of the clock signal. When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latch. Even if the STB terminal is "L" level, the input clock signal shift the data in the shift register, therefore, the clock signal controlled is needed. CASCADE CONNECTION The serial data input from DATA terminal and output from the SO terminal through internal shift register unrelated to the CLR and STB status. Furthermore, the 4 input terminals have a hysteresis characteristic by using the schmitt trigger structure to decrease the noise. CLK STB CLR X X L H H L H L H DESCRIPTION All latch are reset (the data in the shift register is not change). All of parallel outputs are "L". The serial data input from DATA terminal to the shift register (the data in the latch is not change). The data in the shift register transfer to the latch. And the data in the latch output from the parallel output. The CLK input in the STB="L" and CLR="H" state, the data shift in the shift register and latched data also change in accordance with the shift register. Note: X: Don’t care UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 8 QW-R121-015.A LS3718 CMOS IC TIMING CHART UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 8 QW-R121-015.A LS3718 CMOS IC TYPICAL APPLICATION CIRCUIT Cascade Connection ………… ………… P1~P20 P1~P20 SO SO UTC LS3718 DATA CLK STB CLR UTC LS3718 DATA CLK STB CLR MPU UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 8 QW-R121-015.A