UTC-IC UC2843B

UNISONIC TECHNOLOGIES CO., LTD
UC2843B
Preliminary
LINEAR INTEGRATED CIRCUIT
HIGH-PERFORMANCE
CURRENT-MODE PWM
CONTROLLERS
„
DESCRIPTION
The UTC UC2843B provides off-line or DC-DC fixed-frequency
current-mode control design with minimum external components.
Internally-implemented circuits include an under-voltage lockout
(UVLO) and a precision reference with accuracy at the error amplifier
input. The UTC UC2843B also contain internal circuits which include
a pulse width modulation (PWM) comparator providing current-limit
control, logic ensuring latched operation, and a totem-pole output
stage designed to source or sink high-peak current. The output
stage is low when it is in off-state condition and suitable for
N-channel MOSFETs driving.
The UTC UC2843B also has following advantages: the start-up
current lower than 0.5mA while the oscillator discharge current is
specified to 8.3mA (Typ.). In UVLO conditions, the output has a
maximum saturation voltage of 1.2V when sinking 10mA@VCC = 5V.
The typical UVLO threshold of the UTC UC2843B is 8.4V (on)
and 7.6V (off) and can operate to duty cycles approximately 100%.
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FEATURES
Current mode operation:500 kHz
Low start-up current value<0.5mA
Latching PWM for cycle-by-cycle current limiting
Trimmed oscillator discharge current
Automatic feed-forward compensation
Internally trimmed reference with UVLO
High-current totem-pole output UVLO with hysteresis
Double-pulse suppression
Halogen free
ORDERING INFORMATION
Ordering Number
UC2843BG-S08-R
Package
SOP-8
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Copyright © 2009 Unisonic Technologies Co., Ltd
Packing
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UC2843B
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Preliminary
PIN CONFIGURATION
COMP 1
VFB 2
„
LINEAR INTEGRATED CIRCUIT
8 VREF
7 VCC
ISENSE 3
6 OUTPUT
RT/CT 4
5 GND
PIN DESCRIPTION
PIN NO.
1
PIN NAME
COMP
2
VFB
3
ISENSE
4
RT/CT
5
GND
6
OUTPUT
7
VCC
8
VREF
DESCRIPTION
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the
switching power supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses
this information to terminate the output switch conduction.
The Oscillator frequency and maximum Output duty cycle are programmed by
connecting resistor RT to VREF and capacitor CT to ground. Operation to 500 kHz is
possible.
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A
are sourced and sunk by this pin.
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through
resistor RT.
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„
Preliminary
LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
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Preliminary
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING(Ta=25°C, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage (Low impedance source)
VCC
30
V
Analog Input Voltage (VFB and ISENSE)
VIN
-0.3~+6.3
V
Supply Current
ICC
30
mA
Output Current
IOUT
±1
A
Error Amplifier Output Sink Current
IO(SINK)
10
mA
Power Dissipation
PD
702
mW
Output Energy (Capacitive load)
W
5
μJ
Junction Temperature
TJ
150
°C
Operating Temperature
TOPR
-40~+85
°C
Storage Temperature
TSTG
-65~+150
°C
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. All voltages are concerning the device GND terminal.
„
THERMAL DATA
PARAMETER
Junction to Ambient
„
SYMBOL
θJA
MIN
TYP
MAX
178
UNIT
°C/W
MIN
TYP
MAX
30
5.5
5.5
30
25
200
-20
500
+85
UNIT
V
V
V
V
mA
mA
mA
kHz
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
RT/CT
VFB and ISENSE
Output Voltage (OUTPUT)
Supply Current, Externally Limited
Output Current
Reference Output Current
Oscillator Frequency
Operating Temperature
SYMBOL
VCC
VIN
VOUT
ICC
IOUT
IO(REF)
fOSC
Ta
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0
0
0
100
-40
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Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
(VCC = 15 V, RT = 10kΩ, CT = 3.3nF, TJ=25°C, unless otherwise specified)
PARAMETER
REFERENCE SECTION
Reference Output Voltage
Line Regulation
Load Regulation
Average Temperature Coefficient Of
Output Voltage
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit Current
OSCILLATOR SECTION
Frequency
SYMBOL
VREF
ΔVOUT
ΔVOUT
Frequency Change with
Temperature
Oscillator Voltage Swing
Discharge Current
ERROR-AMPLIFIER SECTION
Voltage Feedback Input
Input Bias Current
Open Loop Voltage Gain
Unity Gain Bandwidth
Power Supply Rejection Ratio
Output Sink Current
Output Source Current
Output Voltage Swing High State
CURRENT-SENSE SECTION
Current Sense Input Voltage Gain
Maximum Current Sense Input
Threshold
Power Supply Rejection Ratio
Input Bias Current
Propagation Delay
OUTPUT SECTION
VREF
eN
VCC =12V~25V, IOUT =1mA~20mA
f = 10Hz~10kHz, TJ =25°C
TJ=25°C FOR 1000 hours
ISC
ΔfOSC
ΔV
ΔfOSC
ΔT
VOSC
IDISC
VFB
II(BIAS)
GVO
GBW
PSRR
ISINK
ISOURCE
VOH
VOL
MAX
UNIT
4.95
5
6
6
5.05
20
25
V
mV
mV
0.2
0.4
mV/°C
5.1
TJ =25°C,
RT =62kΩ, CT =1nF,
Min =225 kHz, Max =275 kHz
TJ = Full range
4.9
-30
50
5
-100
25
-180
V
μV
mV
mA
49
52
55
kHz
56
kHz
1
%
48
VCC = 12V ~ 25V
0.2
TJ = Full range
5
Peak to peak
TJ =25°C, RT/CT =2V
RT/CT =2V
7.8
7.5
COMP =2.5V
2.45
VOUT =2V~4V
65
0.7
60
2
-0.5
5
VCC =12V~25V
VFB =2.7V, COMP=1.1V
VFB =2.3V, COMP =5V
VFB =2.3V, RL =15kΩ to GND
VFB =2.7V, RL =15kΩ to GND
1.7
8.3
%
8.8
8.8
V
mA
mA
2.5
-0.3
90
1
70
6
-0.8
6
0.7
2.55
-1
1.1
V
μA
dB
MHz
dB
mA
mA
V
V
(Note 2,3)
2.85
3
3.15
V/V
VTH
COMP =5V (Note 2)
0.9
1
1.1
V
70
-2
150
-10
300
dB
μA
ns
13.5
13.5
0.1
1.5
0.4
2.2
V
V
V
V
PSRR
II(BIAS)
tD
VOH
Low-Level Output Voltage
VOL
VCC =12V~25V (Note 2)
VFB =0V~2V
IOH =-20mA
IOH =-200mA
IOL =20mA
IOL =200mA
13
12
VUVLO
VCC =5V, IOL=1mA
0.7
1.2
V
tR
tF
CL =1nF, TJ = 25°C
CL =1nF, TJ = 25°C
50
50
150
150
ns
ns
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TYP
GV
High-Level Output Voltage
Under-Voltage Lockout
Output Voltage
Output Voltage Rise Time
Output Voltage Fall Time
IOUT =1mA, TJ =25°C
VCC = 12V~25V
IOUT = 1mA~20mA
MIN
TS
fOSC
Frequency Change with Voltage
TEST CONDITIONS
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Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
UNDERVOLTAGE-LOCKOUT SECTION
Startup Threshold
VTH
7.8
Minimum Operating Voltage
VCC(MIN)
7
After Start-Up
PULSE-WIDTH MODULATOR SECTION
Maximum Duty Cycle
DC(MAX)
94
Minimum Duty Cycle
DC(MIN)
SUPPLY VOLTAGE
Power Startup Supply Current
ICC+IC
Power Operating Supply Current
ICC+IC
VFB and ISENSE at 0V
Power Supply Zener Voltage
VZ
ICC =25mA
30
Notes: 1. Adjust VCC above the start threshold before setting it to 15V.
2. Measured at the trip point of the latch, with VFB at 0V.
3. Measured between ISENSE and COMP, with the input changing from 0V ~ 0.8V.
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TYP
MAX
UNIT
8.4
9
V
7.6
8.2
V
96
100
0
%
%
0.3
11
34
0.5
17
mA
mA
V
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Preliminary
LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION
Error amplifier (EA) configuration circuit:
0.5mA
2.5V
EA
VFB
Z1
Z2
Error
Amplifier
COMP
Note: Error amplifier can source or sink up to 0.5mA.
Current-sense circuit:
Notes: 1. Peak current (IS) is determined by the formula: IS(max) = 1 V/RS
2. A small RC filter formed by resistor Rf and capacitor Cf may be required to suppress switch transients.
The oscillator frequency is set using the circuit:
VREF
RT
RT/CT
CT
GND
The frequency is calculated as followed:
f = 1 / RTCT
For RT > 5kΩ:
f = 1.72 / RTCT
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Preliminary
LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION(Cont.)
Open-Loop Laboratory Test Fixture
In the open-loop laboratory test fixture, high peak currents and loads need grounding techniques. The transistor
and 5-kΩ potentiometer sample the oscillator waveform, applying an adjustable ramp to the ISENSE terminal. Timing
and bypass capacitors should be connected closely to the GND terminal in a single-point ground.
Shutdown Technique
The PWM controller can be shut down through two methods: the one is raising voltage (above 1 V) at ISENSE, the
other is pulling the COMP terminal below a voltage two diode drops above ground. Either method can leave the
output of the PWM comparator high (refer to block diagram). To reset the PWM latch is dominant so the output can
stay low in the case of the next clock cycle is coming and the COMP or ISENSE terminal is removed beyond this
shutdown condition. For example, an externally-latched shutdown can be accomplished by adding an SCR reset by
cycling VCC below the lower UVLO threshold. So the reference turns off then allows the SCR to reset at this
condition.
1kΩ
VREF
COMP
Shutdown
330Ω
ISENSE
500Ω
To Current-Sense
Resistor
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Preliminary
LINEAR INTEGRATED CIRCUIT
APPLICATION INFORMATION(Cont.)
Shutdown Technique (cont.)
A fraction of the triangular-wave oscillator can be summed resistively with the current-sense signal providing
slope compensation for converters, which requiring duty cycles over 50%. Please note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
VREF
0.1µF
RT
RT/CT
CT
R1
ISENSE
R2
ISENSE
C
RSENSE
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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