FXLA2203 Dual-Mode, Dual-SIM-Card Level Translator Features Description Easy-to-Use “Single Pin” SIM Card Swap Control The FXLA2203 allows either two hosts to simultaneously communicate with two Subscriber Identity Modules (SIM), or two User Identity Modules (UIM). Dual Mode refers to the mobile phones that are compatible with more than one form of data transmission or network (such as GSM, CDMA, WCDMA, TDSCDMA, or CDMA2000), resulting in a dual-baseband processor configuration. In a dual-mode application, the FXLA2203 host ports interface directly with the baseband processors (see Figure 9). Internal Pull up Resistors for Bi-Directional I/O Pin Channel Swap Time: 130ns (Typical) Simultaneous Dual-Mode, Dual-SIM Communication Host Ports: 1.65V to 3.6V Voltage Translation Card Ports: 1.65V to 3.6V Voltage Translation Leverages the Presence of Existing PMIC LDOs ISO7816 Compliant The bi-directional I/O open-drain channel features autodirection and internal 10KΩ pull-up resistors. RST and CLK provide unidirectional translation from host to card only. Power Switch RON: 0.5Ω (Typical) Supports Class B 3V SIM / UIM Cards Supports Class C: 1.8V SIM / UIM Cards Non-Preferential Host VCC Power-Up Sequencing Activation / Deactivation Timing Compliant per ISO7816-03 Outputs Switch to 3-State if Host VCC at GND Power-Off Protection Packaged in 24-Terminal UMLP (2.5mm x 3.5mm) Direction Control Not Needed Applications Dual-Mode Dual-SIM Applications Mobile TV: OMA BCAST GSM, CDMA, WCDMA, TDSCDMA CDMA2000, 3G Cellular Phones Either host can swap SIM slots with the assertion of a single control pin: CH_Swap. The typical channel swap time is 130ns. The FXLA2203 does not contain internal Low Dropout Regulator (LDOs). Instead, the FXLA2203 architecture incorporates two low-RON internal power switches for routing existing PMIC (Power Management Integrated Circuit) LDOs to individual SIM slots. This reduces overall system power, leverages existing LDO system resources, and aligns with the philosophy that centralizing LDOs in the PMIC facilitates power management. Since the FXLA2203 does not block the LDO function to the SIM card, existing activation / deactivation timing transparency is maintained between Hosts, PMICs, and SIM cards. The device allows voltage translation from as high as 3.6V to as low as 1.65V. Each port tracks its own port power supply. Ordering Information Part Number FXLA2203UMX Operating Temperature Range -40 to 85°C © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 Package 24-Terminal, 2.5mm x 3.4mm Ultrathin Molded Leadless Package (UMLP), 0.4mm Pitch Packing Method Tape and Reel www.fairchildsemi.com FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator August 2012 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Block Diagram Figure 1. Block Diagram Notes: 1. VCC must always be greater than or equal to (≥) VCC1 and VCC2. 2. Hybrid driver explained in detail in Figure 12 - I/O Pin Functional Diagram. 3. See Table 2 for CH_Swap truth table. © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 2 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Pin Configuration Figure 2. Top Through View Figure 3. Bottom View Pin Definitions Pin # Name Signal 1 NC NC 2 VCC1 I 3 VCC_Card1 O 4 GND GND 5 VCC_Card2 O Power Output for Card Slot 2 6 VCC2 I Power Supply 2 Input: Coming from PMIC 2 LDO 7 RST_2 O Reset Output to Card Slot 2 8 I/O_2 I/O Data I/O for Card Slot 2; Open Drain 9 CLK_2 O Clock Output to Card Slot 2 10 CLK_H_2 I Clock Input of Host Interface 2 11 RST_H_2 I Reset Input of Host Interface 2 12 I/O_H_2 I Data I/O of Host Interface 2; Open Drain 13 VCC_H_2 Supply 14 GND GND 15 VCC Supply 16 EN I GPIO Enable. LOW disables both SIM card slots. HIGH enables both SIM card slots. Connect to VCC if not used. Default level after power up is LOW. 17 Ch_Swap I Channel Swap. “1” host 1 to card slot 1, host 2 to card slot 2. “0” host 1 to card slot 2, host 2 to card slot 1. Connected to VCC if not used. Default level after power up is LOW. 18 VCC_H_1 Supply 19 I/O_H_1 I/O 20 RST_H_1 I Reset Input of Host Interface 1 21 CLK_H_1 I Clock Input of Host Interface 1 22 CLK_1 O Clock Output to Card Slot 1 23 I/O_1 I/O Data I/O for Card Slot 1; Open Drain 24 RST_1 O Reset Output to Card Slot 1 © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 Description No Connection Power Supply 1 Input: Coming from PMIC 1 LDO Power Output for Card Slot 1 Ground Power Supply of Host Interface 2 Ground Power Supply of Control Pins: EN and CH_Swap Power Supply of Host Interface 1 Data I/O of Host Interface 1; Open Drain www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Supply Voltage VIN DC Input Voltage VO (4) IIK IOK IOH/IOL ICC Output Voltage DC Input Diode Current DC Output Diode Current Conditions Min. Max. Unit VCC -0.5 5.0 V VCC_H_n, VCCn -0.5 4.6 V Host Ports and Card Ports -0.5 4.6 Control Input (EN and CH_Swap) -0.5 5.0 Output 3-State -0.5 4.6 Output Active (Host Port) -0.5 VCC +0.5 Output Active (Card Port) -0.5 VCC +0.5 VI<0V -50 VO<0V -50 VO>VCC +50 DC Output Source / Sink Current(4) -50 TSTG Storage Temperature Range Power Dissipation at 5MHz ESD Electrostatic Discharge Capability Human Body Model, (5) JESD22-A114 Charged Device Model, JESD22-C101 -65 V mA mA +50 mA ±100 mA +150 °C 0.57 W DC VCC or Ground Current (per Supply Pin) PDISS V Card Side Pins 3-5, 7-9, 14, 22-24 9 All Other Pins 3 Card Side Pins 3-5, 7-9, 14, 22-24 2 All Other Pins 2 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Absolute Maximum Ratings kV Notes: 4. IO absolute maximum ratings must be observed. 5. Human Body Model (HBM): R=1500Ω, C=100pF. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Power Supply(6) VIN Input Voltage(7) VOUT TA dt/dV ΘJA Output Voltage(7) Conditions Max. Unit VCC 1.65 4.35 V VCC_H_n, VCCn 1.65 3.60 V Host Port 0 3.6 V Card Port 0 3.6 V Host Port 0 3.6 V Card Port 0 3.6 V Host Port I/O Pin 0 VCC_H_n +0.3V V Card Port I/O Pin 0 VCCn +0.3V V -40 +85 °C 10 ns/V 52.1 C/W Operating Temperature, Free Air Input Edge Rate Min. RST and CLK Junction-to-Ambient Thermal Resistance Notes: 6. VCC must always be equal to, or greater than, VCC1 and VCC2. 7. All unused inputs and input/outputs must be held at their respective VCC or GND. © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 4 TA=-40°C to +85°C; pins I/O_1, I/O_2, I/O_H_1, I/O_H_2 (open drain). Symbol Parameter VCC_H_n (V) VCCn (V) Min. Data Inputs of Host Interface 1.65 – 3.60 1.65 - 3.60 0.7 x VCC_H_n V VIH_card Data Inputs of Card Interface 1.65 – 3.60 1.65 - 3.60 0.7 x VCCn V VIL_host Data Inputs of Host Interface 1.65 – 3.60 1.65 - 3.60 0.4 V VIL_card Data Input of Card Interface 1.65 – 3.60 1.65 - 3.60 0.15 x VCCn V VOH_host IOH=-20µA 1.65 – 3.60 1.65 - 3.60 0.7 x VCC_H_n V IOH=-20µA 1.65 – 3.60 1.65 - 3.60 0.7 x VCCn V IOL=1mA, VIL=0V 1.65 – 3.60 1.65 - 3.60 0.05 V IOL=1mA, VIL=0V 1.65 – 3.60 1.65 - 3.60 0.05 V IOL=1mA, VIL=0.100V 1.65 – 3.60 1.65 - 3.60 0.15 V IOL=1mA, VIL=0.100V 1.65 – 3.60 1.65 - 3.60 0.15 V IOL=1mA, VIL=0.250V 1.65 – 3.60 1.65 - 3.60 0.3 V IOL=1mA, VIL=0.250V 1.65 – 3.60 1.65 - 3.60 0.3 V 3.60 0 ±1.0 µA VIH_host High-Level Input Voltage Low-Level Input Voltage VOH_card VOL_host VOL_card VOL_host VOL_card VOL_host VOL_card High-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage Conditions Typ. Max. Unit IOFF VO=0V to 3.6V Power-Off Host and Card Leakage Current Sides IOZ 3-State Output Leakage VO=0V or 3.6V, EN=GND, Host and Card Sides 3.60 3.60 ±1.0 µA IOZ 3-State Output Leakage VO=0V or 3.6V, EN=1, Host and Card Sides 0 3.60 ±1.0 µA Rpull_up Internal Pull-Up Resistor 1.65 – 3.60 1.65 - 3.60 11 KΩ © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 9 10 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator DC Electrical Characteristics www.fairchildsemi.com 5 TA=-40°C to +85°C; pins EN, CH_Swap. Symbol Parameter Conditions VIL Low-Level Input Voltage VIH High-Level Input Voltage IL Input Leakage Current ICCT Increase in ICC per Pin VCC (V) VI=VCC or GND, I/O Floating Min. Max. Unit 3.60 0.65 V 1.80 0.45 V 3.60 1.2 V 1.80 0.9 V 1.65 – 3.60 ±1 µA VIN=1.8V 3.60 12 µA VIN=0.9V 1.80 10 µA DC Electrical Characteristics TA=-40°C to +85°C; pins RST_1, RST_2, RST_H_1, RST_H_2, CLK_1, CLK_2, CLK_H_1, CLK_H_2. Symbol Parameter Conditions VCC_H_n (V) VCCn (V) Min. Typ. Max. Unit 0.35 x VCC_H_n V VIL Low-Level Input Voltage 1.65 – 3.60 1.65 – 3.60 VIH High-Level Input Voltage 1.65 – 3.60 1.65 – 3.60 VOL Low-Level Output Voltage IOL=20µA 1.65 – 3.60 1.65 – 3.60 VOH High-Level Output Voltage IOH=-20µA 1.65 – 3.60 1.65 – 3.60 Input Leakage Current VI=VCC or GND 1.65 – 3.60 3.60 ±1 µA Power-Off Leakage Current VO=0V to 3.6V 3.60 0 ±1 µA VO=0V or 3.6V, EN=GND 3.60 3.60 ±1 VO=0V or 3.6V, EN=1 0 3.60 ±1 II IOFF IOZ 3-State Output Leakage 0.65 x VCC_H_n V 0.12 x VCCn 0.80 x VCCn V V µA ICC Quiescent Supply Current VI=VCC or GND; IO=0, EN=VCC, I/O Floating 1.65 – 3.60 1.65 – 3.60 3 µA ICCZ Power-Down Supply VI=VCC or GND; Current IO=0, EN=GND 1.65 – 3.60 1.65 – 3.60 3 µA 0.8 Ω RONPS Power Switch On Resistance, EN=1 ION=50mA, VCCn to VCC_Cardn 1.65 – 3.60 1.65 – 3.60 0.5 ROFPS Power Switch OFF Resistance, EN=0 CH_Swap=0 and 1, VCC1/2=3.3V 1.65 – 3.60 1.80 – 3.60 50 © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator DC Electrical Characteristics MΩ www.fairchildsemi.com 6 Card Port (RST, CLK) Unless otherwise specified, output load: CL=30pF, RL ≥ 1MΩ; TA=-40°C to +85°C; VCCn=1.65V to 3.60V. Symbol Parameter (8,10) tr Output Rise Time Card Port (9,10) tf Output Fall Time Card Port Typ. Max. Unit 1 5 ns 1 5 ns Notes: 8. See Figure 6. 9. See Figure 7. 10. tr, tf guaranteed by characterization; not production tested. Host and Card Port (I/O Only) Unless otherwise specified, output load: CL=30pF, RL≥1MΩ, and open-drain outputs; TA=-40°C to +85°C; VCCn=1.65V to 3.60V; and VCC_H_n=1.65V to 3.60V. Symbol Conditions tr(11,13) tf (12,13) tr(11,13) Open Drain Inputs with 500µA ISINK(13) tf(12,13) Parameter Typ. Max. Unit Output Rise Time Card Port (10% - 90%) 200 500 ns Output Fall Time Card Port (90% - 10%) 2.5 4.0 ns Output Rise Time Host Port (10% - 90%) 200 500 ns Output Fall Time Host Port (90% - 10%) 2 3 ns Notes: 11. See Figure 6. 12. See Figure 7. 13. tr, tf guaranteed by characterization; not production tested. FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator AC Characteristics VCC_H_n=1.65V to 3.60V(16) Unless otherwise specified, TA=-40°C to +85°C and VCCn=1.65V to 3.60V. Symbol CH_Swap Direction Path Typ. Max. Unit tswap HL, LH Host Card RST, CLK, I/O and Power Switches 130 400 ns Notes: 14. 15. 16. The power switch swap time assumes no decoupling capacitors on the VCC_Card pins. 17. tswap is the time required for the CH_Swap pin to swap host to SIM slot connections. 18. The I/O pin swap time assumes a push / pull driver; otherwise, the rise time (RC time constant) of an open-drain driver masks the actual I/O pin switch time. Maximum Frequency(19) Unless otherwise specified, CLK (Host to Card), TA=-40°C to +85°C, and card port VCCn=1.65V to 3.60V. Host Port: VCC_H_n CH_Swap Minimum 1 30 0 30 1.6V to 3.6V Unit MHz Note: 19. Maximum frequency is guaranteed but not tested. Power Dissipation Capacitance TA=+25°C. Symbol Parameter Conditions Typical Unit Cpd Power Dissipation Capacitance VCC_H_n=VCCn=VCC=3.3V, VI=0V or VCC, CH_Swap=1, CLK1 and CLK2 Switching at 5MHz 23 pF © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 7 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Test Diagrams VCC TEST SIGNAL DUT C1 R1 Figure 4. Test Circuit Table 1. AC Test Conditions VCCO C1 R1 1.8V± 0.15V 30pF 1MΩ 2.5V ± 0.2V 30pF 1MΩ 3.3 ± 0.3V 30pF 1MΩ tr DATA IN Vmi VCCI 90% x CC GND VO tpxx tpxx DATA OUT Vmo VO T VCCO 10% x CC VOL Time Figure 5. Input Edge Rates for RST and CLK Figure 6. Active Output Rise Time Notes: 20. Input tR=tF=2.0ns, 10% to 90% at VI=2.5V. 21. Input tR=tF=2.5ns, 10% to 90% at VI=2.5V. V OH 90% x VO tfl tW CC T DATA IN 10% x CC VCCI/2 VCCI/2 VCCI GND Maximum Data Rate, f = 1/tW V OL Time Figure 7. Active Output Fall Time © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 Figure 8. Maximum Data Rate www.fairchildsemi.com 8 Figure 9 illustrates an FXLA2203 used in a dual-mode / dual-SIM application. The FXLA2203 does not contain any internal LDOs. Instead, the FXLA2203 architecture incorporates two low-RON internal power switches for routing existing Power Management Integrated Circuit (PMIC) LDOs to individual SIM slot VCC pins. HOST PORT CARD PORT 1.8V / 3V 0.1µF VCC H_1 HOST 1 PMIC LDO 1 1.8V / 3V WCDMA TDSCDMA VCC1 RST_H_1 RST_1 RST CLK_1 CLK I/O I/O_1 CLK_H_1 VCC_Card1 I/O_H_1 VCC SIM Slot 1 1.8V / 3V GND 0.1µF Control Can Be Either Host CH_Swap GND EN 0.1µF I/O_H_2 HOST 2 GSM VCC_ Card2 CLK_H_2 I/O_2 CLK_2 RST_2 RST_H_2 PMIC LDO 2 1.8V / 3V VCC2 VCC I/O CLK RST SIM Slot 2 1.8V / 3V FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Application Information GND VCC_H_2 1.8V / 3V 1.8V / 3V 0.1µF 0.1µF VCC Figure 9. Typical Dual-Mode Application CH_Swap Truth Table CH_Swap controls simultaneous communication between Host 1 or Host 2, and either SIM Card according to Table 2 — CH_Swap pin. This simple solution is faster and less 2 complicated than SPI or I C communication protocols. Dual-Mode, Dual-SIM Truth Table. Either host can swap SIM slots (130ns typical) with the assertion of the Figure 10. CH_Swap © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 9 Enable CH_SWAP Configuration 1 1 Host 1 SIM Slot 1 1 1 Host 2 SIM Slot 2 1 0 Host 1 SIM Slot 2 1 0 Host 2 SIM Slot 1 Voltage Translation Description architecture offers a flexible solution for problematic VCC domain disagreements. For example, if Host 1 operates at 1.65V and Host 2 operates at 2.5V, while slot 1 is populated with a 3.0V SIM card and slot 2 is populated with a 1.8V SIM card, the FXLA2203 provides seamless voltage translation across all four VCC domains. The FXLA2203 provides full voltage translation, or level shifting, from 1.65V – 3.6V between Host 1 or Host 2 and either SIM card (according to Table 3). The host sides reference VCC_H_1 and VCC_H_2, respectively, while each SIM slot references the external PMIC LDO voltage level determined by the CH_Swap pin. This Figure 11. FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Table 2. Dual-Mode, Dual-SIM Truth Table Voltage Translation Table 3. Translation Truth Table Enable CH_Swap SIM Slot 1 Voltage Levels SIM Slot 2 Voltage Levels 1 1 PMIC LDO1 / VCC1 PMIC LDO2 / VCC2 1 0 PMIC LDO2 / VCC2 PMIC LDO1 / VCC1 Note: 22. VCC must always be greater than or equal to (≥) VCC1 and VCC2. © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 10 The ISO7816-3 specification, which governs the SIM card physical layer requirements, identifies the I/O pin as a bi-directional open-drain pin. To provide autodirection for the I/O pin, the FXLA2203 architecture (Figure 12) implements two series NpassGates and two dynamic drivers. This hybrid architecture is highly beneficial in a SIM card interface. VCC/2 threshold. When either the host or card port threshold is reached, the port’s edge detectors trigger both dynamic drivers to drive their ports in the HIGH-toLOW (HL) direction, accelerating the falling edge. Figure 13. Scope Shot of I/O and Clock Signals CH1: CLK Pin (Yellow), CH2: I/O PIN (Blue) Driven by the FXLA2203 Figure 12. I/O Pin Functional Diagram The hybrid bi-directional I/O channel contains two series NpassGates and two dynamic drivers. This architecture allows auto-direction functionality without the need for a direction pin from either the host or the SIM card and accomplishes an automatic change in direction without the presence of an edge. Activation / Deactivation To ensure the SIM card electrical circuits do not activate before the contacts of the SIM card are mechanically connected, ISO7816-3 2006 mandates the activation sequence of events described in Figure 14. The FXLA2203 provides full transparency to the activation timing between host and SIM card. Due to open-drain technology, hosts and SIM cards do not use push-pull drivers on the I/O pin. Logic LOWs are pulled down (Isink), while logic HIGHs are “let go” (3state). During a logic LOW on the I/O pin, both series NpassGates are turned on and act like a very low resistive short between the host and the SIM card. When the host or card lets go of a previously held LOW on the I/O pin, the rise time is largely determined by the RC time constant, where R is the internal pull-up resistor (10KΩ) and C is the I/O signal trace capacitance. The FXLA2203 acts as a very low resistive short between the host and SIM card (during a LOW) until either of the port’s VCC/2 thresholds are reached. After the RC time constant has reached the VCC/2 threshold of either port, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the LOW-to-HIGH (LH) direction, accelerating the rising edge. The resulting rise time resembles the CH2 waveform (blue) of Figure 13. Effectively, two distinct slew rates appear in the rise time. The first slew rate (slower) is the RC time constant of the I/O signal trace. The second slew rate (faster) is the dynamic driver accelerating edge. Figure 14. Activation Timing (ISO 7816-3 2006) To ensure the SIM card electrical circuits properly deactivate before the contacts of the SIM card are mechanically connected, ISO7816-3 2006 mandates the sequence of events described in Figure 15 The FXLA2203 provides full transparency to the deactivation timing between host and SIM card. If both the host and card ports of the I/O pin are HIGH, a high-impedance path exists between the host and card ports because both of the series NpassGates are turned off. If a host or SIM card pulls the I/O pin LOW, that device’s driver pulls down (Isink) the I/O pin until the HIGH-to-LOW (HL) edge reaches the host or card port’s © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator I/O Pin Function Figure 15. Deactivation (ISO 7816-3 2006) www.fairchildsemi.com 11 Recommended power-up sequence (see Figure 16): Table 4. Power Supply Pins Pin Name Function 1. Apply power to VCC. 1 VCC EN and CH_Swap Supply 2. Assert EN LOW (FXLA2203 disabled). 2 VCC_H_1 Host 1 Supply 3. 3 VCC_H_2 Host 2 Supply Apply power to VCC1, VCC2, VCC_H_1, and VCC_H_2. 4 VCC1 Power Switch 1 Input 4. Assert EN HIGH (FXLA2203 enabled). 5 VCC2 Power Switch 2 Input 5. Begin activation timing (see Figure 14). Recommended power-down sequence (see Figure 17): The VCC host power sequencing is non preferential; however, VCC must be higher or equal to VCC1 and VCC2. The Enable pin must be LOW while VCC1 and VCC2 ramp up to valid supply voltages or ramp down to 0V. 1. Complete deactivation timing (see Figure 15). 2. Assert EN LOW (FXLA2203 disabled). 3. Ramp down power to VCC1, VCC2, VCC_H_1, and VCC_H_2. A pull-up resistor tying enable to ground should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power up or power down. The size of the pull-up resistor is based upon the current sinking capability of the device driving the Enable pin. Begin Activation Timing per ISO7816 3 2006 Power-Up Sequencing B C VCC_Cardn Z Z Z Z RST_n Z Z Z Z CLK_n Z Z Z Z I/O_n Z Z Z Z Card Ports A 4. Once VCC1 and VCC2 are OFF, ramp down VCC. EN CH_Swap VCC1, VCC2 Host Ports VCC_H_n VCC RST_H_n CLK_H_n I/O_H_n Figure 16. Power-Up Sequencing Figure 17. Notes: 23. A=VCC becomes a valid voltage, EN=LOW. 24. B=VCC1, VCC2, and VCC_H_n become valid voltages, EN=LOW. 25. C=FXLA2203 enabled (EN goes HIGH), ready for activation (ISO7816-3). © 2010 Fairchild Semiconductor Corporation FLXA2203 • Rev. 1.0.5 Power-Down Sequencing Notes: 26. A=Disable FXLA2203, bring EN LOW. 27. B=Ramp down VCC1, VCC2, and VCC_H_n. 28. C=Ramp down VCC once VCC1 and VCC2 are off. www.fairchildsemi.com 12 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Power-Up / Power-Down Sequence if VCC2 and VCC_H_2 share the same voltage potential, these two pins can be tied together. Under these conditions, and once CH_Swap has been established, the host can power up or down the SIM card along with the FXLA2203 host side solely by the LDO voltage. This feature is a convenient method for conserving power. Note that VCC must always remain equal to or greater than VCC1 and VCC2. Table 5. Power Supply Pins Pin Name Function 6 VCC EN and CH_Swap Supply 7 VCC_H_1 Host 1 Supply 8 VCC_H_2 Host 2 Supply 9 VCC1 Power Switch 1 Input 10 VCC2 Power Switch 2 Input The FXLA2203 I/O pins must be driven by open-drain drivers on the host sides and the card sides. The control pins EN and CH_Swap reference VCC. VCC can range from 1.65V to 3.6V and is independent from the other four power pins; however, VCC must always be higher or equal to VCC1 and VCC2. SIM Slot Power Switch Truth Table If EN=1 and CH_Swap=1; then the VCC of SIM Slot 1 (VCC_Card_1) tracks the VCC1 voltage (ext. LDO), while the VCC of SIM Slot 2 (VCC_Card_2) tracks the VCC2 voltage (ext. LDO). If EN=1 and CH_Swap=0; then the VCC of SIM Slot 1 (VCC_Card_1) tracks the VCC2 voltage (ext. LDO), while the VCC of SIM Slot 2 (VCC_Card_2) tracks the VCC1 voltage (ext. LDO). See Table 7. Note that VCC must be > VCC1 and VCC2. VCC_Host_1 and VCC_Host_2 can independently range from 1.65V to 3.6V and are the power supply pins for their respective host-side interfaces; including RST, I/O, and CLK. VCC1 and VCC2 can independently range from 1.65V to 3.6V and are the inputs to the internal power switches. VCC1 and VCC2 should be connected to external PMIC LDOs. Depending on the logic state of the CH_Swap and EN control pins, the external LDOs are routed through the two power switches to either VCC_Card1 or VCC_Card2 (see Table 6). Meanwhile, CH_Swap also routes the host (1 or 2) signal pins; RST, I/O, and CLK to the SIM Slot side (1 or 2). See section “SIM Slot Signals: Active vs. 3-State” for details. The voltage reference of each SIM slot is determined by the LDO voltage assigned to that SIM slot. SIM Slot Signal Truth Table If EN=1 and CH_Swap=1, the Host 1 Input signal pins (CLK_H_1, RST_H_1, and I/O_H_1) are translated to the SIM Slot 1 output signal pins (CLK_1, RST_1, and I/O_1). The VCC1 voltage (ext. LDO) sets the voltage levels of CLK_1, RST_1, and I/O_1. Host 2 input signal pins (CLK_H_2, RST_H_2, and I/O_H_2) are translated to the SIM Slot 2 output signal pins (CLK_2, RST_2, and I/O_2). The VCC2 (ext. LDO) voltage sets the voltage levels of CLK_2, RST_2 and I/O_2. If EN=1 and CH_Swap=0, the Host 1 input signal pins (CLK_H_1, RST_H_1 and I/O_H_1) is translated to the SIM Slot 2 output signal pins (CLK_2, RST_2, and I/O_2). The VCC1 voltage (ext. LDO) sets the voltage levels of CLK_2, RST_2, and I/O_2. Host 2 input signal pins (CLK_H_2, RST_H_2, and I/O_H_2) are translated to the SIM Slot 1 output signal pins (CLK_1, RST_1, and I/O_1). The VCC2 (ext. LDO) voltage sets the voltage levels of CLK_1, RST_1, and I/O_1. RST and CLK are unidirectional pins always going in the SIM slot direction. I/O is a bi-directional, open drain pin. Internal 10KΩ pull-up resistors are provided. The ISO7816 standard identifies an algorithm that allows a Host device to auto-detect the operating voltage of a SIM card. The algorithm is called “class selection” and the FXLA2203 is 100% transparent to class selection. If VCC1 and VCC_H_1 share the same voltage potential; these two pins can be tied together. Likewise, Table 6. Power Switch Truth Table VCC1 VCC2 EN CH_Swap VCC_Card 1 VCC_Card 2 0V – 3.6V 0V – 3.6V 1 1 VCC1 VCC2 0V – 3.6V 0V – 3.6V 1 0 VCC2 VCC1 Table 7. Signal Truth Table EN CH_Swap SIM SLOT 1 SIM Slot 2 1 1 CLK_H_1, RST_H_1, and I/O_H_1 CLK_H_2, RST_H_2, and I/O_H_2 1 0 CLK_H_2, RST_H_2, and I/O_H_2 CLK_H_1, RST_H_1, and I/O_H_1 © 2010 Fairchild Semiconductor Corporation FLXA2203 • Rev. 1.0.5 www.fairchildsemi.com 13 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Operation Description The individual SIM slot signals (CLK, RST, and I/O) are active only if the appropriate VCCn and VCC_H_n supplies are active (1.65V – 3.6V). For example, if EN=1 and CH_Swap is 1, SIM Slot 1 signals (CLK_1, RST_1, and I/O_1) are active only if VCC1 and VCC_H_1 are both active (1.65V – 3.6V). VCC1 sets the voltage levels of CLK_1, RST_1, and I/O_1. If either VCC1 or VCC_H_1 is below 1.65V, SIM Slot 1 signals (CLK_1, RST_1, and I/O_1) are high impedance. Likewise, SIM Slot 2 signals (CLK_2, RST_2, and I/O_2) are active only if both VCC2 and VCC_H_2 are active (1.65V – 3.6V). VCC2 sets the voltage levels of CLK_2, RST_2, and I/O_2. For a complete listing of all the possible power switch and signal combinations, see Table 8. Table 8. Complete Power Switch and Signal Truth Table Inputs Condition 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Outputs VCC EN CH_SWAP VCC_H_1 VCC_H_2 VCC1 VCC2 CLK_1, RST_1, I/O_1 OFF ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON X L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON X X OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF X OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF X OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON Z Z Z Z Z Z Z Z Z Z Z A Z A Z A Z A Z Z Z Z Z Z A A Z Z Z Z Z Z A A CLK_2, RST_2, I/O_2 Z Z Z Z Z Z Z Z A A Z Z Z Z Z Z A A Z Z Z Z Z Z Z Z Z A Z A Z A Z A VCC_Card1 VCC_Card2 OFF Z OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF Z OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON Notes: 29. ON=1.65V – 3.6V. 30. OFF=Powered down or 0V. 31. X=Don’t Care. 32. VCC > VCC1 and VCC2. © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 14 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator If EN=1 and CH_Swap is 0, SIM Slot 1 (CLK_1, RST_1, and I/O_1) signals are active only if VCC2 and VCC_H_2 are active (1.65V – 3.6V). VCC2 sets the voltage levels of CLK_1, RST_1, and I/O_1. Likewise, SIM Slot 2 signals (CLK_2, RST_2, and I/O_2) are active only if both VCC1 and VCC_H_1 are active (1.65V – 3.6V). VCC1 sets the voltage levels of CLK_2, RST_2, and I/O_2. SIM Slot Signals: Active vs. 3-State 2.80 2.23 0.66 0.10 C A 2.50 2X 24 B 0.56 19 1 0.40 2.23 PIN #1 IDENT 3.70 3.40 13 7 0.10 C 0.23 2X TOP VIEW RECOMMENDED LAND PATTERN 0.55 MAX. 0.10 C 0.15 SEATING PLANE 0.08 C C 0.05 0.00 SIDE VIEW 7 23X 0.35 0.45 13 0.40 1 0.45 0.55 24 19 BOTTOM VIEW 0.15 24X 0.25 0.10 C A B 0.05 C Figure 18. 24-Terminal 2.5mm x 3.4mm Ultrathin Molded Leadless Package (UMLP) Product-Specific Dimensions Description Nominal Values (mm) Description Nominal Values (mm) Overall Height PKG Standoff Lead Thickness Lead Width 0.50 0.012 0.15 0.20 Lead Length Lead Pitch Body Length (X) Body Width (Y) 0.40 0.40 2.50 3.40 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/MicroMLP24_TNR.pdf. © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 15 FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator Physical Dimensions FLXA2203 — Dual-Mode, Dual-SIM-Card Level Translator © 2010 Fairchild Semiconductor Corporation FXLA2203 • Rev. 1.0.5 www.fairchildsemi.com 16