FDB3672_F085
N-Channel PowerTrench® MOSFET
100V, 44A, 28mΩ
Features
Applications
• rDS(ON) = 24mΩ (Typ.), VGS = 10V, ID = 44A
• DC/DC converters and Off-Line UPS
• Qg(tot) = 24nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low QRR Body Diode
• High Voltage Synchronous Rectifier
• Optimized efficiency at high frequencies
• UIS Capability (Single Pulse and Repetitive Pulse)
• Direct Injection / Diesel Injection Systems
• Qualified to AEC Q101
• 42V Automotive Load Control
• RoHS Compliant
• Electronic Valve Train Systems
Formerly developmental type 82760
DRAIN
(FLANGE)
D
GATE
SOURCE
G
TO-263AB
FDB SERIES
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
44
A
Continuous (TC = 100oC, VGS = 10V)
31
A
7.2
A
Continuous (Tamb = 25oC, VGS = 10V, RθJA = 43oC/W)
Pulsed
EAS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
120
mJ
Power dissipation
120
W
Derate above 25oC
0.8
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-263
1.25
o
C/W
RθJA
Thermal Resistance Junction to Ambient TO-263 (Note 2)
62
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
January 2009
Device Marking
FDB3672
Device
FDB3672_F085
Package
Reel Size
Tape Width
Quantity
TO-263AB
330mm
24mm
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V
VDS = 80V
VGS = 0V
TC= 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
-
4
ID = 44A, VGS = 10V
-
0.024
0.028
ID = 21A, VGS = 6V,
-
0.031
0.047
ID=44A, VGS=10V, TC=175oC
-
0.054
0.068
-
1710
-
pF
-
247
-
pF
-
62
-
pF
-
24
31
nC
-
3.5
4.5
nC
-
11
-
nC
-
7.2
-
nC
-
4.5
-
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
VGS = 0V to 2V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
Resistive Switching Characteristics
VDS = 25V, VGS = 0V,
f = 1MHz
VDD = 50V
ID = 44A
Ig = 1.0mA
(VGS = 10V)
tON
Turn-On Time
-
-
104
ns
td(ON)
Turn-On Delay Time
-
11
-
ns
tr
Rise Time
-
59
-
ns
td(OFF)
Turn-Off Delay Time
-
26
-
ns
tf
Fall Time
-
44
-
ns
tOFF
Turn-Off Time
-
-
104
ns
ISD = 44A
-
-
1.25
V
ISD = 21A
-
-
1.0
V
VDD = 50V, ID = 44A
VGS = 10V, RGS = 11.0Ω
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD = 44A, dISD/dt =100A/µs
-
-
52
ns
QRR
Reverse Recovered Charge
ISD = 44A, dISD/dt =100A/µs
-
-
80
nC
Notes:
1: Starting TJ = 25°C, L = 0.6mH, IAS = 20A.
2: Pulse Width = 100s
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
Package Marking and Ordering Information
50
VGS = 10V
1.0
40
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
30
0.6
20
0.4
10
0.2
0
0
0
25
50
75
100
150
125
175
25
TC , CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
175
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25
VGS = 10V
175 - TC
150
100
30
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
100
101
Figure 4. Peak Current Capability
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
200
300
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
DC
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
0.001
200
Figure 5. Forward Bias Safe Operating Area
80
100
1
0.1
10
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TC = 25oC
60
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10µs
100
TJ = 175oC
40
TJ = 25oC
20
TJ = -55oC
VGS = 10V
VGS = 7V
60
VGS = 6V
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20
VGS = 5V
0
0
3.5
4.0
4.5
5.0
5.5
6.0
VGS , GATE TO SOURCE VOLTAGE (V)
6.5
0
Figure 7. Transfer Characteristics
1.0
1.5
2.0
2.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
3.0
Figure 8. Saturation Characteristics
40
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE (m Ω)
0.5
35
VGS = 6V
30
25
VGS = 10V
20
15
2.0
1.5
1.0
VGS = 10V, ID = 44A
0.5
0
10
20
30
ID, DRAIN CURRENT (A)
40
50
Figure 9. Drain to Source On Resistance vs Drain
Current
©2009 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.0
0.8
0.6
1.0
0.9
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
-80
200
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
3000
VGS , GATE TO SOURCE VOLTAGE (V)
10
CISS = CGS + CGD
1000
C, CAPACITANCE (pF)
1.1
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 44A
ID = 22A
2
0
10
0.1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2009 Fairchild Semiconductor Corporation
100
0
5
10
15
Qg, GATE CHARGE (nC)
20
25
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD
VGS
-
VGS = 2V
DUT
Qgs2
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tf
tr
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2009 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
Test Circuits and Waveforms
(EQ. 1)
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (oC/W)
(T
–T )
JM
A
P DM = ----------------------------RθJA
80
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2)
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
19.84
( 0.262 + Area )
R θ JA = 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
128
( 1.69 + Area )
R θ JA = 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
rev May 2004
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RSLC2
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
ESLC
-
Lgate 1 9 9.56e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 4.45e-9
RLDRAIN
RSLC1
51
Ebreak 11 7 17 18 105
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
+
.SUBCKT FDB3672 2 1 3 ;
CA 12 8 5.8e-10
Cb 15 14 6.8e-10
Cin 6 8 1.6e-9
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 95.6
RLdrain 2 5 10
RLsource 3 7 44.5
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
S1B
CA
17
18
RVTEMP
S2B
13
CB
19
6
8
VBAT
5
8
EDS
-
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 6.0e-3
Rgate 9 20 1.5
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 9.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
15
14
13
13
8
RBREAK
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))}
.MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6
+ CJO=1.2e-9 M=0.58 TT=3.75e-8 XTI=4.0)
.MODEL DbreakMOD D (RS=15 TRS1=4.0e-3 TRS2=-5.0e-6)
.MODEL DplcapMOD D (CJO=3.8e-10 IS=1.0e-30 N=10 M=0.60)
.MODEL MmedMOD NMOS (VTO=3.6 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.5)
.MODEL MstroMOD NMOS (VTO=4.3 KP=59 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.09 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1)
.MODEL RbreakMOD RES (TC1=9.0e-4 TC2=-1.0e-7)
.MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-3.5e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=-4.3e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
PSPICE Electrical Model
REV May 2004
template FDB3672 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0)
dp..model dbreakmod = (rs=15,trs1=4.0e-3,trs2=-5.0e-6)
dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60)
m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1)
LDRAIN
m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1)
DPLCAP 5
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0) 10
RLDRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3)
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5)
51
RSLC2
c.ca n12 n8 = 5.8e-10
ISCL
c.cb n15 n14 = 6.8e-10
c.cin n6 n8 = 1.6e-9
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTHRES
+ 19 8
+
LGATE
spe.ebreak n11 n7 n17 n18 = 105 GATE
1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
DRAIN
2
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 95.6e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.45e-9
S2A
14
13
13
8
S1B
CA
res.rlgate n1 n9 = 9.56
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 44.5
RBREAK
15
17
18
RVTEMP
S2B
13
19
CB
6
8
EGS
-
IT
14
+
+
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e-7
res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5
res.rgate n9 n20 = 1.5
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=1.0e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6
res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3))
}
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
SABER Electrical Model
th
JUNCTION
REV May 2004
FDB3672
CTHERM1 TH 6 3.2e-3
CTHERM2 6 5 3.3e-3
CTHERM3 5 4 3.4e-3
CTHERM4 4 3 3.5e-3
CTHERM5 3 2 6.4e-3
CTHERM6 2 TL 1.9e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.4e-1
RTHERM6 2 TL 3.5e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB3672
template thermal_model th tl
thermal_c th, tl
{
cctherm.ctherm1 th 6 =3.2e-3
ctherm.ctherm2 6 5 =3.3e-3
ctherm.ctherm3 5 4 =3.4e-3
ctherm.ctherm4 4 3 =3.5e-3
ctherm.ctherm5 3 2 =6.4e-3
ctherm.ctherm6 2 tl =1.9e-2
rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =5.0e-3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =10.5e-2
rtherm.rtherm5 3 2 =3.4e-1
rtherm.rtherm6 2 tl =3.5e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2009 Fairchild Semiconductor Corporation
CASE
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
SPICE Thermal Model
FRFET®
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Datasheet contains the design specifications for product development. Specifications
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Rev. I37
©2009 Fairchild Semiconductor Corporation
FDB3672_F085 Rev. A
FDB3672_F085 N-Channel PowerTrench® MOSFET
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