v4.0 PCI Arbiter Core Fe a t ur es In the most common application, customers use an embedded processor as the master with highest priority and a pure-rotation arbitration scheme among other PCI bus masters. The networking and telecom markets are the targets for this macro. • Support for up to Five PCI Bus Masters • Support for Two Arbitration Schemes – Pure Rotation – Fair Rotation I m p l em e n t at i on • Support for Bus Parking At any given time, more than one PCI bus initiator (Master) device may request use of the PCI bus by asserting its specific request signal (REQn). The Arbiter determines which PCI bus initiator controls the PCI bus by asserting that device’s specific grant signal (GNTn). Figure 1 shows the PCI Arbiter Core interface signals and Figure 2 illustrates the relationship of the PCI bus initiator devices with the Arbiter. • Hidden Bus Arbitration • Interface with 33 MHz and 66 MHz PCI Systems • Implementation in Actel’s SX, SX-A, ProASIC and ProASICPLUS Families • Synthesizable VHDL Source Code • Device Utilization – SX/SX-A 100-150 Modules – ProASIC/ProASICPLUS 124-135 Tiles PCI_CLK G en er al D e sc r i p t i on RSTn The Arbiter core is used to efficiently manage access to a PCI bus that is shared by several masters. Access to the PCI bus is automatically determined by the individual priorities of each master. GNTn(4:0) FRAMEn IRDYn REGn(4:0) Figure 1 • PCI Arbiter Core Interface Signals PCI Device 1 PCI Device 3 PCI Device 2 GNTn2 REQn2 REQn1 GNTn3 GNTn1 REQn3 GNTn4 REQn0 PCI Device 0 GNTn0 PCI Arbiter REQn4 RSTn IRDYn CLK FRAMEn PCI Device 4 Figure 2 • Top-Level Interface of the PCI Bus Initiators with the Arbiter J an u a r y 2 0 0 2 © 2002 Actel Corporation 1 Ar bi tr at io n S che m es Pure rotation is a turn-based method that allows each bus master one transaction in turn if multiple masters are requesting the bus simultaneously. If only one master requests the bus, that master will immediately get the grant. Figure 3 illustrates the pure rotation scheme. Fair rotation is employed if an embedded processor is required to initialize the system but will not be used after that point. By giving it highest priority, the fair rotation scheme allows the embedded processor access to the PCI bus on every other transaction when it is requesting the bus continuously. The other masters use a pure rotation scheme. The fair rotation scheme is illustrated in Figure 4. IDLE Device 0 Device 1 Device 4 Device 2 Device 3 Figure 3 • Pure Rotation Arbitration Device 1 Device 4 Device 0 IDLE Device 2 Device 3 Figure 4 • Fair Rotation Arbitration 2 v4.0 PCI Arbiter Core Bus P ar ki ng 5. The arbiter has been designed to implement bus parking; i.e., it asserts the grant to a default device when none of the request lines are active (there are no devices are requesting the bus). This ensures that a requesting device will received an almost immediate grant. The default case allows the bus to be parked on the device that last acquired the bus. However, by utilizing the constants BUS_PARK, BUS_DEVICE, and BUS_GNTN the user can specify the bus is parked on a device other than the default. Hidd en Bus A rb it ra ti on The PCI specification allows bus arbitration to take place while the currently granted device is performing a data transfer. This feature greatly reduces arbitration overhead and improves bus utilization. do compall.do 6. Simulating the Fair Rotation Arbiter Scheme 1. Invoke the V-System simulator. 2. Change to the “/vhdl/tbench/mti_arb” directory. 3. Create a “work” library. Type the following command at the prompt: vlib work The test bench will be compiled into this directory. 4. Open the file “arb_wrp.vhd” in the “/vhdl/src” directory and set the constant ALGORITHM to a zero. 5. Compile the macro and the test bench. Type the following command at the prompt: do compall.do 6. Simulate the test bench. Type the following command at the prompt: do run_pure.do Beh avi or al S im ul at ion The following procedures is used to simulate the VHDL version of the Arbiter Macro: Simulating the Pure Rotation Arbiter Scheme 1. Invoke the V-System simulator. 2. Change to the “/vhdl/tbench/mti_arb” directory. 3. Create a “work” library. Type the following command at the prompt: U se r Cod e C us to mi z at ion The code is currently written to arbit between 5 master devices. The devices are implemented as states in a finite state machine (FSR). The end user can modify the implementation by adding or subtracting states to meet the number of devices required by the particular application. E st im a ted P er f or m ance and D evi ce U t ili z at ion vlib work The test bench will be compiled into this directory. 4. Simulate the test bench. Type the following command at the prompt: do run_fair.do Maxi m um L at ency The device granted the bus must initiate a transaction (drop FRAMEn signal) within 16 PCI clock cycles. If the time expires and the device has not initiated a transaction, the arbiter removes the grant from the device and the bus to the device with the next highest priority. Compile the macro and the test bench. Type the following command at the prompt: Open the file “arb_wrp.vhd” in the “/vhdl/src” directory and set the constant ALGORITHM to a one. The expected performance and utilization statistics for the 66 MHz PCI Arbiter using the 54SX16–2 and APA750 devices are shown in Table 1. These numbers are based on post layout results using automatic place and route. Table 1 • Utilization and Performance Statistics Utilization (Estimated) Performance Combinatorial Modules Sequential Modules Total Resources Utilization Percent Max Frequency (MHz) A54SX16-2 84 32 116 Modules 8% 84 APA750 135 N/A 135 Tiles 0.4% 71 v4.0 3 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. 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