3 – DC and Power Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 3-1 may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on page 3-3. Table 3-1 • Absolute Maximum Ratings Symbol Parameter Commercial Industrial Units VCC DC core supply voltage –0.3 to 1.65 –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 –0.3 to 1.65 V VCCI DC I/O output buffer supply voltage –0.3 to 3.75 –0.3 to 3.75 V VI I/O input voltage1 VCC33A +3.3 V power supply –0.3 to 3.752 –0.3 to 3.752 V VAREF Voltage reference for ADC –0.3 to 3.75 –0.3 to 3.75 V VCC15A Digital power supply for the analog system –0.3 to 1.65 –0.3 to 1.65 V VCCNVM Embedded flash power supply –0.3 to 1.65 –0.3 to 1.65 V VCCOSC Oscillator power supply –0.3 to 3.75 –0.3 to 3.75 V AV, AC Unpowered, unconfigured –11.0 to 12.6 –11.0 to 12.4 V Analog input (+16 V to +2 V prescaler range) –0.4 to 12.6 –0.4 to 12.4 V Analog input (+1 V to +0.125 V prescaler range) –0.4 to 3.75 –0.4 to 3.75 V Analog input (–16 V to –2 V prescaler range) –11.0 to 0.4 –11.0 to 0.4 V Analog input (–1 V to –0.125 V prescaler range) –3.75 to 0.4 –3.75 to 0.4 V ADC –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) reset asserted or V Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4. 2. Analog data not valid beyond 3.65 V. 3. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits refer to Table 3-2 on page 3-3. Pr e li m i n a ry v0 . 4 3-1 DC and Power Characteristics Table 3-1 • Absolute Maximum Ratings (continued) Symbol AG AT Parameter Commercial Industrial Units Analog input (direct input to ADC) –0.4 to 3.75 –0.4 to 3.75 V Digital input –0.4 to 12.6 –0.4 to 12.4 V –11.0 to 12.6 –11.0 to 12.4 V Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA) –0.4 to 12.6 –0.4 to 12.4 V Low Current Mode (–1 µA, –3 µA, –10 µA, –30 µA) –11.0 to 0.4 –11.0 to 0.4 V High Current Mode3 –11.0 to 12.6 –11.0 to 12.4 V –0.4 to 16.5 –0.4 to 16.0 V Analog input (+16 V, 4 V prescaler range) –0.4 to 16.5 –0.4 to 16.0 V Analog input (direct input to ADC) –0.4 to 3.75 –0.4 to 3.75 V Digital input –0.4 to 16.5 –0.4 to 16.0 V Unpowered, unconfigured Unpowered, unconfigured ADC ADC reset reset asserted asserted or or TSTG3 Storage temperature –65 to +150 °C Tj3 Junction temperature +125 °C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4. 2. Analog data not valid beyond 3.65 V. 3. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits refer to Table 3-2 on page 3-3. 3 -2 Pr e li m i n a r y v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Table 3-2 • Recommended Operating Conditions Symbol Parameter Commercial TA,TJ Ambient and junction temperature VCC 1.5 V DC core supply voltage VJTAG JTAG DC voltage VPUMP Programming voltage Programming mode 3 Operation Industrial Units 0 to +70 –40 to +85 °C 1.425 to 1.575 1.425 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V VCCPLL Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V VCCI 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V 2.97 to 3.63 2.97 to 3.63 V VCC33A +3.3 V power supply VAREF Voltage reference for ADC 2.527 to 2.593 2.527 to 2.593 V VCC15A6 Digital power supply for the analog system 1.425 to 1.575 1.425 to 1.575 V VCCNVM Embedded flash power supply 1.425 to 1.575 1.425 to 1.575 V VCCOSC Oscillator power supply 2.97 to 3.63 2.97 to 3.63 V Unpowered, ADC reset asserted or unconfigured –10.5 to 12.0 –10.5 to 12.0 V Analog input (+16 V to +2 V prescaler range) –0.3 to 12.0 –0.3 to 12.0 V Analog input (+1 V to + 0.125 V prescaler range) –0.3 to 3.6 –0.3 to 3.6 V Analog input (–16 V to –2 V prescaler range) –10.5 to 0.3 –10.5 to 0.3 V Analog input (–1 V to –0.125 V prescaler range) –3.6 to 0.3 –3.6 to 0.3 V Analog input (direct input to ADC) –0.3 to 3.6 –0.3 to 3.6 V Digital input –0.3 to 12.0 –0.3 to 12.0 V Unpowered, ADC reset asserted or unconfigured –10.5 to 12.0 –10.5 to 12.0 V Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA) –0.3 to 12.0 –0.3 to 12.0 V Low Current Mode (–1 µA, –3 µA, –10 µA, –30 µA) –10.5 to 0.3 –10.5 to 0.3 V High Current Mode –10.5 to 12.0 –10.5 to 12.0 V Unpowered, ADC reset asserted or unconfigured –0.3 to 16.0 –0.3 to 15.5 V Analog input (+16 V, +4 V prescaler range) AV, AC 4 AG 4 5 4 AT –0.3 to 16.0 –0.3 to 15.5 V Analog input (direct input to ADC) –0.3 to 3.6 –0.3 to 3.6 V Digital input –0.3 to 16.0 –0.3 to 15.5 V Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-82 on page 2-162. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during normal operation (not programming mode). 4. The input voltage may overshoot by up to 500 mV above the Recommended Maximum (150 mV in Direct mode), provided the duration of the overshoot is less than 50% of the operating lifetime of the device. 5. The AG pad should also conform to the limits as specified inTable 2-45 on page 2-115. 6. Violating the VCC15A recommended voltage supply during an embedded flash program cycle can corrupt the page being programmed. Pr e li m i n a ry v0 . 4 3-3 DC and Power Characteristics Table 3-3 • Input Resistance of Analog Pads Pads AV, AC Pad Configuration Prescaler Range Input Resistance to Ground +16 V to +2 V 1 MΩ (typical) +1 V to +0.125 V > 10 MΩ +16 V to +2 V 1 MΩ (typical) +1 V to +0.125 V > 10 MΩ –16 V to –2 V 1 MΩ (typical) –1 V to –0.125 V > 10 MΩ Digital input +16 V to +2 V 1 MΩ (typical) Current monitor +16 V to +2 V 1 MΩ (typical) –16 V to –2 V 1 MΩ (typical) Analog Input (direct input to ADC) +16 V, +4 V 1 MΩ (typical) Analog Input (positive prescaler) +16 V, +4 V 1 MΩ (typical) Digital input +16 V, +4 V 1 MΩ (typical) Temperature monitor +16 V, +4 V > 10 MΩ Analog Input (direct input to ADC) Analog Input (positive prescaler) Analog Input (negative prescaler) AT Table 3-4 • VCCI Overshoot and Undershoot Limits 1 Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V 2.7 V or less 3.0 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one cycle out of six clock cycle. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3 -4 Pr e li m i n a r y v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Table 3-5 • FPGA Programming, Storage, and Operating Limits Product Grade Commercial Element Retention Minimum Maximum FPGA/FlashROM 500 20 years2 0 85 1k years2 0 85 0 85 Embedded Flash Industrial Storage Temperature (°C) Grade Programming Cycles 20 2 15 k 5 years FPGA/FlashROM 500 20 years –40 85 Embedded Flash 1k 20 years –40 85 15 k 5 years –40 85 Notes: 1. This is a stress rating only. Functional operation at any condition other than those indicated is not implied. 2. If the embedded flash has been programmed less than 1 k times, every time it is programmed, the data will hold for 20 years. If the embedded flash has been programmed more than 1 k times but less than 15 k times, every time it is programmed, the data will hold for 5 years. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every Fusion device. These circuits ensure easy transition from the powered off state to the powered up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1 on page 3-6. There are five regions to consider during power-up. Fusion I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 3-1). 2. VCCI > VCC – 0.75 V (typical). 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation Pr e li m i n a ry v0 . 4 3-5 DC and Power Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 3-1 on page 3-6 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the PowerUp/Down of Fusion FPGAs application note for information on clock and lock recovery. VCC = VCCI + VT Where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH /VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ±0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V Figure 3-1 • I/O State as a Function of VCCI and VCC Voltage Levels 3 -6 Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification Pr e li m i n a r y v0 . 4 VCCI Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures. EQ 3-1 through EQ 3-3 give the relationship between thermal resistance, temperature gradient, and power. TJ – θA θ JA = ---------------P EQ 3-1 θ JB TJ – TB = --------------P θ JC TJ – TC = ---------------P EQ 3-2 EQ 3-3 where θJA = Junction-to-air thermal resistance Table 3-6 • θJB = Junction-to-board thermal resistance θJC = Junction-to-case thermal resistance TJ = Junction temperature TA = Ambient temperature TB = Board temperature (measured 1.0 mm away from the package edge) TC = Case temperature P = Total power dissipated by the device Package Thermal Resistance θJA Still Air 1.0 m/s 2.5 m/s θJC θJB Units U1AFS250-FG256 33.7 30.0 28.3 9.3 24.8 °C/W U1AFS600-FG256 28.9 25.2 23.5 6.8 19.9 °C/W U1AFS1500-FG256 23.3 19.6 18.0 4.3 14.2 °C/W Product Pr e li m i n a ry v0 . 4 3-7 DC and Power Characteristics Theta-JA Junction-to-ambient thermal resistance (θJA) is determined under standard conditions specified by JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution but is useful for comparing the thermal performance of one package to another. A sample calculation showing the maximum power dissipation allowed for the U1AFS600-FG256 package under forced convection of 1.0 m/s and 75°C ambient temperature is as follows: T J(MAX) – T A(MAX) Maximum Power Allowed = ----------------------------------------θ JA EQ 3-4 where θJA = 25.20°C/W (taken from Table 3-6 on page 3-7). TA = 75.00°C – 75.00°C- = 1.39 W Maximum Power Allowed = 110.00°C --------------------------------------------------25.2°C/W The power consumption of a device can be calculated using the Actel power calculator. The device's power consumption must be lower than the calculated maximum power dissipation by the package. If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be increased. Theta-JB Junction-to-board thermal resistance (θJB) measures the ability of the package to dissipate heat from the surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge. Theta-JC Junction-to-case thermal resistance (θJC) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant temperature is applied to the surface in consideration and acts as a boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. Calculation for Heat Sink For example, in a design implemented in an U1AFS600-FG256 package with 2.5 m/s airflow, the power consumption value using the power calculator is 3.00 W. The user-dependent Ta and Tj are given as follows: TJ = 110.00°C TA = 70.00°C From the datasheet: θJA = 23.50°C/W θJC = 6.80°C/W TJ – TA – 70°C- = 1.70 W P = ---------------- = 110°C ---------------------------------θ JA 23.50°C/W EQ 3-5 3 -8 Pr e li m i n a r y v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution The 1.70 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the airflow where the device is mounted should be increased. The design's total junction-to-air thermal resistance requirement can be estimated by EQ 3-6: TJ – TA – 70°C- = 13.33°C/W - = 110°C ---------------------------------θ ja(total) = ---------------P 3.00 W EQ 3-6 Determining the heat sink's thermal performance proceeds as follows: θ JA(TOTAL) = θ JC + θ CS + θ SA EQ 3-7 where θJA θSA = 0.37°C/W = Thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer = Thermal resistance of the heat sink in °C/W θ SA = θ JA(TOTAL) – θ JC – θ CS EQ 3-8 θ SA · = 13.33°C/W – 6.80°C/W – 0.37°C/W = 6.16°C/W A heat sink with a thermal resistance of 6.16°C/W or better should be used. Thermal resistance of heat sinks is a function of airflow. The heat sink performance can be significantly improved with increased airflow. Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA. Design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device. Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard (JESD-51) and assumptions made in building the model. It may not be realized in actual application and therefore should be used with a degree of caution. Junction-to-case thermal resistance assumes that all power is dissipated through the case. Temperature and Voltage Derating Factors Table 3-7 • Array Voltage VCC (V) Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 110°C 1.425 0.88 0.93 0.95 1.00 1.02 1.05 1.500 0.83 0.88 0.90 0.95 0.96 0.99 1.575 0.80 0.85 0.87 0.91 0.93 0.96 Pr e li m i n a ry v0 . 4 3-9 DC and Power Characteristics Calculating Power Dissipation Quiescent Supply Current Table 3-8 • Quiescent Supply Current Characteristics (IDDQ)1 Parameter Conditions and Modes IDC1 U1AFS250 U1AFS600 U1AFS1500 Maximum in operating mode (85°C) 1 30 mA 45 mA TBD 1 20 mA 30 mA TBD 3 mA 5 mA TBD 200 µA 200 µA TBD 10 µA 10 µA TBD Maximum in operating mode (70°C) Typical in operating mode (25°C) IDC2 Typical in standby mode (25°C) IDC3 Typical in sleep mode (25°C) 3,4 1 2,4 Notes: 1. IDC1 includes VCC, VPUMP, and VCCI, currents. Values do not include I/O static contribution, which is shown in Table 3-9 on page 3-11 and Table 3-10 on page 3-13. 2. IDC2 represents the current from the VCC33A and VCCI supplies when the RTC (and the 32 kHz crystal oscillator) is ON, the FPGA is OFF, and the voltage regulator is OFF. 3. IDC3 represents the current from the VCC33A and VCCI supplies when the RTC (and the crystal oscillator), the FPGA, and the voltage regulator are OFF. 4. VCCI supply is ON, since the east and west I/O banks are not cold-sparable. Values do not include I/O static contribution, which is shown in Table 3-9 on page 3-11 and Table 3-10 on page 3-13. 3 -1 0 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Power per I/O Pin Table 3-9 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings VCCI (V) Static Power PDC7 (mW)1 Dynamic Power PAC9 (µW/MHz)2 3.3 V LVTTL/LVCMOS 3.3 – 17.39 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 25.51 2.5 V LVCMOS 2.5 – 5.76 2.5 V LVCMOS – Schmitt trigger 2.5 – 7.16 1.8 V LVCMOS 1.8 – 2.72 1.8 V LVCMOS – Schmitt trigger 1.8 – 2.80 1.5 V LVCMOS (JESD8-11) 1.5 – 2.08 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 2.00 3.3 V PCI 3.3 – 18.82 3.3 V PCI – Schmitt trigger 3.3 – 20.12 3.3 V PCI-X 3.3 – 18.82 3.3 V PCI-X – Schmitt trigger 3.3 – 20.12 3.3 V GTL 3.3 2.90 8.23 2.5 V GTL 2.5 2.13 4.78 3.3 V GTL+ 3.3 2.81 4.14 2.5 V GTL+ 2.5 2.57 3.71 HSTL (I) 1.5 0.17 2.03 HSTL (II) 1.5 0.17 2.03 SSTL2 (I) 2.5 1.38 4.48 SSTL2 (II) 2.5 1.38 4.48 SSTL3 (I) 3.3 3.21 9.26 SSTL3 (II) 3.3 3.21 9.26 LVDS 2.5 2.26 1.50 LVPECL 3.3 5.71 2.17 Applicable to Pro I/O Banks Single-Ended Voltage-Referenced Differential Notes: 1. PDC7 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCC and VCCI. Pr e li m i n a ry v0 . 4 3 - 11 DC and Power Characteristics Table 3-9 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued) VCCI (V) Static Power PDC7 (mW)1 Dynamic Power PAC9 (µW/MHz)2 3.3 V LVTTL/LVCMOS 3.3 – 16.69 2.5 V LVCMOS 2.5 – 5.12 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.45 3.3 V PCI 3.3 – 18.11 3.3 V PCI-X 3.3 – 18.11 LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 3.3 V LVTTL/LVCMOS 3.3 – 16.79 2.5 V LVCMOS 2.5 – 5.19 1.8 V LVCMOS 1.8 – 2.18 1.5 V LVCMOS (JESD8-11) 1.5 – 1.52 Applicable to Advanced I/O Banks Single-Ended Differential Applicable to Standard I/O Banks Notes: 1. PDC7 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCC and VCCI. 3 -1 2 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Table 3-10 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings1 CLOAD (pF) VCCI (V) Static Power PDC8 (mW)2 Dynamic Power PAC10 (µW/MHz)3 3.3 V LVTTL/LVCMOS 35 3.3 – 474.70 2.5 V LVCMOS 35 2.5 – 270.73 1.8 V LVCMOS 35 1.8 – 151.78 1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.55 3.3 V PCI 10 3.3 – 204.61 3.3 V PCI-X 10 3.3 – 204.61 3.3 V GTL 10 3.3 – 24.08 2.5 V GTL 10 2.5 – 13.52 3.3 V GTL+ 10 3.3 – 24.10 2.5 V GTL+ 10 2.5 – 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.22 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II) 30 3.3 42.21 131.76 LVDS – 2.5 7.70 89.62 LVPECL – 3.3 19.42 168.02 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 468.67 2.5 V LVCMOS 35 2.5 – 267.48 1.8 V LVCMOS 35 1.8 – 149.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 103.12 3.3 V PCI 10 3.3 – 201.02 3.3 V PCI-X 10 3.3 – 201.02 Applicable to Pro I/O Banks Single-Ended Voltage-Referenced Differential Applicable to Advanced I/O Banks Single-Ended Notes: 1. Dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. PDC8 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. Pr e li m i n a ry v0 . 4 3 - 13 DC and Power Characteristics Table 3-10 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings1 (continued) CLOAD (pF) VCCI (V) Static Power PDC8 (mW)2 Dynamic Power PAC10 (µW/MHz)3 LVDS – 2.5 7.74 88.92 LVPECL – 3.3 19.54 166.52 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08 2.5 V LVCMOS 35 2.5 – 247.36 1.8 V LVCMOS 35 1.8 – 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46 Differential Applicable to Standard I/O Banks Single-Ended Notes: 1. Dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. PDC8 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. 3 -1 4 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Dynamic Power Consumption of Various Internal Resources Table 3-11 • Different Components Contributing to the Dynamic Power Consumption in MicroBlade-Based Fusion Devices Power Supply Parameter Device-Specific Dynamic Contributions Definition Name PAC1 Clock contribution of a Global Rib VCC 1.5 V 14.5 12.8 11 µW/MHz PAC2 Clock contribution of a Global Spine VCC 1.5 V 2.5 1.9 1.6 µW/MHz PAC3 Clock contribution of a VersaTile row VCC 1.5 V 0.81 µW/MHz PAC4 Clock contribution of a VersaTile used as a sequential module VCC 1.5 V 0.11 µW/MHz PAC5 First contribution of a VersaTile used as a sequential module VCC 1.5 V 0.07 µW/MHz PAC6 Second contribution of a VersaTile used as a sequential module VCC 1.5 V 0.29 µW/MHz PAC7 Contribution of a VersaTile used as a combinatorial module VCC 1.5 V 0.29 µW/MHz PAC8 Average contribution routing net VCC 1.5 V 0.70 µW/MHz PAC9 Contribution of an I/O input pin (standard dependent) VMV/ VCC See Table 3-9 on page 3-11 PAC10 Contribution of an I/O output pin (standard dependent) VCCI/ VCC See Table 3-10 on page 3-13 PAC11 Average contribution of a RAM block during a read operation VCC 1.5 V 25 µW/MHz PAC12 Average contribution of a RAM block during a write operation VCC 1.5 V 30 µW/MHz PAC13 Dynamic Contribution for PLL VCC 1.5 V 2.6 µW/MHz PAC15 Contribution of NVM block during a read operation (F < 33MHz) VCC 1.5 V 358 µW/MHz PAC16 1st contribution of NVM block during a read operation (F > 33MHz) VCC 1.5 V 12.88 mW PAC17 2nd contribution of NVM block during a read operation (F > 33MHz) VCC 1.5 V 4.8 µW/MHz PAC18 Crystal Oscillator contribution VCC33A 3.3 V 0.63 mW PAC19 RC Oscillator contribution VCC33A 3.3 V 3.3 mW PAC20 Analog Block dynamic power contribution of ADC VCC 1.5 V 3 mW of a Setting U1AFS1500 U1AFS600 U1AFS250 Pr e li m i n a ry v0 . 4 Units 3 - 15 DC and Power Characteristics Static Power Consumption of Various Internal Resources Table 3-12 • Different Components Contributing to the Static Power Consumption in Fusion Devices Device-Specific Static Contributions Parameter Definition Power Supply U1AFS1500 U1AFS600 U1AFS250 PDC1 Core static power contribution in operating mode VCC 1.5 V PDC2 Device static power contribution in standby mode VCC33A 3.3 V 0.66 mW PDC3 Device static power contribution in sleep mode VCC33A 3.3 V 0.03 mW PDC4 NVM static power contribution VCC 1.5 V 1.19 mW PDC5 Analog Block static power contribution of ADC VCC33A 3.3 V 8.25 mW PDC6 Analog Block static power contribution per Quad VCC33A 3.3 V 3.3 mW PDC7 Static contribution per input pin – standard-dependent contribution VMV/VCC See Table 3-9 on page 3-11 PDC8 Static contribution per input pin – standard-dependent contribution VMV/VCC See Table 3-10 on page 3-13 PDC9 Static contribution for PLL 3 -1 6 VCC 1.5 V Pr e li m i n a ry v0 . 4 TBD 7.5 2.55 4.50 Units mW mW Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • The number of NVM blocks used in the design • The number of Analog Quads used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-13 on page 3-21. • Enable rates of output buffers—guidelines are provided for typical applications in Table 3-14 on page 3-21. • Read rate and write rate to the RAM—guidelines are provided for typical applications in Table 3-14 on page 3-21. • Read rate to the NVM blocks The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL Operating Mode, Standby Mode, and Sleep Mode PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT Operating Mode PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) + (NPLLS * PDC9) NNVM-BLOCKS is the number of NVM blocks available in the device. NQUADS is the number of Analog Quads used in the design. NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NPLLS is the number of PLLs available in the device. Standby Mode PSTAT = PDC2 Sleep Mode PSTAT = PDC3 Total Dynamic Power Consumption—PDYN Operating Mode PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC-OSC + PAB Pr e li m i n a ry v0 . 4 3 - 17 DC and Power Characteristics Standby Mode PDYN = PXTL-OSC Sleep Mode PDYN = 0 W Global Clock Dynamic Contribution—PCLOCK Operating Mode PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in Table 3-13 on page 3-21. NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. Standby Mode and Sleep Mode PCLOCK = 0 W Sequential Cells Dynamic Contribution—PS-CELL Operating Mode PS-CELL = NS-CELL * (PAC5 + (α1 / 2) * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multitile sequential cell is used, it should be accounted for as 1. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode PS-CELL = 0 W Combinatorial Cells Dynamic Contribution—PC-CELL Operating Mode PC-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode PC-CELL = 0 W Routing Net Dynamic Contribution—PNET Operating Mode PNET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK NS-CELL is the number VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. 3 -1 8 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Standby Mode and Sleep Mode PNET = 0 W I/O Input Buffer Dynamic Contribution—PINPUTS Operating Mode PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode PINPUTS = 0 W I/O Output Buffer Dynamic Contribution—POUTPUTS Operating Mode POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21. β1 is the I/O buffer enable rate—guidelines are provided in Table 3-14 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode POUTPUTS = 0 W RAM Dynamic Contribution—PMEMORY Operating Mode PMEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * β3 * FWRITE-CLOCK) NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. β2 is the RAM enable rate for read operations—guidelines are provided in Table 3-14 on page 3-21. β3 the RAM enable rate for write operations—guidelines are provided in Table 3-14 on page 3-21. FWRITE-CLOCK is the memory write clock frequency. Standby Mode and Sleep Mode PMEMORY = 0 W PLL/CCC Dynamic Contribution—PPLL Operating Mode PPLL = PAC13 * FCLKOUT FCLKIN is the input clock frequency. FCLKOUT is the output clock frequency.1 Standby Mode and Sleep Mode PPLL = 0 W 1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. Pr e li m i n a ry v0 . 4 3 - 19 DC and Power Characteristics Nonvolatile Memory Dynamic Contribution—PNVM Operating Mode The NVM dynamic power consumption is a piecewise linear function of frequency. PNVM = NNVM-BLOCKS * β4 * PAC15 * FREAD-NVM when FREAD-NVM ≤ 33 MHz, PNVM = NNVM-BLOCKS * β4 *(PAC16 + PAC17 * FREAD-NVM)when FREAD-NVM > 33 MHz NNVM-BLOCKS is the number of NVM blocks used in the design (2 in U1AFS600). β4 is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state). FREAD-NVM is the NVM read clock frequency. Standby Mode and Sleep Mode PNVM = 0 W Crystal Oscillator Dynamic Contribution—PXTL-OSC Operating Mode PXTL-OSC = PAC18 Standby Mode PXTL-OSC = PAC18 Sleep Mode PXTL-OSC = 0 W RC Oscillator Dynamic Contribution—PRC-OSC Operating Mode PRC-OSC = PAC19 Standby Mode and Sleep Mode PRC-OSC = 0 W Analog System Dynamic Contribution—PAB Operating Mode PAB = PAC20 Standby Mode and Sleep Mode PAB = 0 W 3 -2 0 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some examples: • • The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – … – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8. Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When non-tristate output buffers are used, the enable rate should be 100%. Table 3-13 • Toggle Rate Guidelines Recommended for Power Calculation Component α1 α2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 3-14 • Enable Rate Guidelines Recommended for Power Calculation Component β1 β2 β3 β4 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% NVM enable rate for read operations 0% Pr e li m i n a ry v0 . 4 3 - 21 DC and Power Characteristics Example of Power Calculation This example considers a shift register with 5,000 storage tiles, including a counter and memory that stores analog information. The shift register is clocked at 50 MHz and stores and reads information from a RAM. The device used is a commercial U1AFS600 device operating in typical conditions. The calculation below uses the power calculation methodology previously presented and shows how to determine the dynamic and static power consumption of resources used in the application. Also included in the example is the calculation of power consumption in operating, standby, and sleep modes to illustrate the benefit of power-saving modes. Global Clock Contribution—PCLOCK FCLK = 50 MHz Number of sequential VersaTiles: NS-CELL = 5,000 Estimated number of Spines: NSPINES = 5 Estimated number of Rows: NROW = 313 Operating Mode PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK PCLOCK = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50 PCLOCK = 41.28 mW Standby Mode and Sleep Mode PCLOCK = 0 W Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—PS-CELL, PC-CELL, and PNET FCLK = 50 MHz Number of sequential VersaTiles: NS-CELL = 5,000 Number of combinatorial VersaTiles: NC-CELL = 6,000 Estimated toggle rate of VersaTile outputs: α1 = 0.1 (10%) Operating Mode PS-CELL = NS-CELL * (PAC5+ (α1 / 2) * PAC6) * FCLK PS-CELL = 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50 PS-CELL = 21.13 mW PC-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK PC-CELL = 6,000 * (0.1 / 2) * 0.00029 * 50 PC-CELL = 4.35 mW PNET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK PNET = (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50 PNET = 19.25 mW PLOGIC = PS-CELL + PC-CELL + PNET PLOGIC = 21.13 mW + 4.35 mW + 19.25 mW PLOGIC = 44.73 mW Standby Mode and Sleep Mode 3 -2 2 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution PS-CELL = 0 W PC-CELL = 0 W PNET = 0 W PLOGIC = 0 W I/O Input and Output Buffer Contribution—PI/O This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with high output slew and driving a 35 pF output load. FCLK = 50 MHz Number of input pins used: NINPUTS = 30 Number of output pins used: NOUTPUTS = 40 Estimated I/O buffer toggle rate: α2 = 0.1 (10%) Estimated IO buffer enable rate: β1 = 1 (100%) Operating Mode PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK PINPUTS = 30 * (0.1 / 2) * 0.01739 * 50 PINPUTS = 1.30 mW POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK POUTPUTS = 40 * (0.1 / 2) * 1 * 0.4747 * 50 POUTPUTS = 47.47 mW PI/O = PINPUTS + POUTPUTS PI/O = 1.30 mW + 47.47 mW PI/O = 48.77 mW Standby Mode and Sleep Mode PINPUTS = 0 W POUTPUTS = 0 W PI/O = 0 W RAM Contribution—PMEMORY Frequency of Read Clock: FREAD-CLOCK = 10 MHz Frequency of Write Clock: FWRITE-CLOCK = 10 MHz Number of RAM blocks: NBLOCKS = 20 Estimated RAM Read Enable Rate: β2 = 0.125 (12.5%) Estimated RAM Write Enable Rate: β3 = 0.125 (12.5%) Operating Mode PMEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * β3 * FWRITE-CLOCK) PMEMORY = (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10) PMEMORY = 1.38 mW Standby Mode and Sleep Mode PMEMORY = 0 W PLL/CCC Contribution—PPLL PLL is not used in this application. Pr e li m i n a ry v0 . 4 3 - 23 DC and Power Characteristics PPLL = 0 W Nonvolatile Memory—PNVM Nonvolatile memory is not used in this application. PNVM = 0 W Crystal Oscillator—PXTL-OSC The application utilizes standby mode. The crystal oscillator is assumed to be active. Operating Mode PXTL-OSC = PAC18 PXTL-OSC = 0.63 mW Standby Mode PXTL-OSC = PAC18 PXTL-OSC = 0.63 mW Sleep Mode PXTL-OSC = 0 W RC Oscillator—PRC-OSC Operating Mode PRC-OSC = PAC19 PRC-OSC = 3.30 mW Standby Mode and Sleep Mode PRC-OSC = 0 W Analog System—PAB Number of Quads used: NQUADS = 4 Operating Mode PAB = PAC20 PAB = 3.00 mW Standby Mode and Sleep Mode PAB = 0 W Total Dynamic Power Consumption—PDYN Operating Mode PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC+ PAB OSC PDYN = 41.28 mW + 21.1 mW + 4.35 mW + 19.25 mW + 1.30 mW + 47.47 mW + 1.38 mW + 0 + 0 + 0.63 mW + 3.30 mW + 3.00 mW PDYN = 143.06 mW Standby Mode PDYN = PXTL-OSC PDYN = 0.63 mW Sleep Mode PDYN = 0 W 3 -2 4 Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Total Static Power Consumption—PSTAT Number of Quads used: NQUADS = 4 Number of NVM blocks available (U1AFS600): NNVM-BLOCKS = 2 Number of input pins used: NINPUTS = 30 Number of output pins used: NOUTPUTS = 40 Operating Mode PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5 + (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) PSTAT = 7.50 mW + (2 * 1.19 mW) + 8.25 mW + (4 * 3.30 mW) + (30 * 0.00) + (40 * 0.00) PSTAT = 31.33 mW Standby Mode PSTAT = PDC2 PSTAT = 0.03 mW Sleep Mode PSTAT = PDC3 PSTAT = 0.03 mW Total Power Consumption—PTOTAL In operating mode, the total power consumption of the device is 174.39 mW: PTOTAL = PSTAT + PDYN PTOTAL = 143.06 mW + 31.33 mW PTOTAL = 174.39 mW In standby mode, the total power consumption of the device is limited to 0.66 mW: PTOTAL = PSTAT + PDYN PTOTAL = 0.03 mW + 0.63 mW PTOTAL = 0.66 mW In sleep mode, the total power consumption of the device drops as low as 0.03 mW: PTOTAL = PSTAT + PDYN PTOTAL = 0.03 mW Pr e li m i n a ry v0 . 4 3 - 25 DC and Power Characteristics Power Consumption Table 3-15 • Power Consumption Parameter Description Condition Min. Typical Max. Units Crystal Oscillator ISTBXTAL Standby Current of Crystal Oscillator IDYNXTAL Operating Current 10 µA RC 0.6 mA 0.032–0.2 0.19 mA 0.2–2.0 0.6 mA 2.0–20.0 0.6 mA 1 mA RC Oscillator IDYNRC Operating Current ACM Operating clock) Current (fixed 200 µA/MHz Operating clock) Current (user 30 µA Idle 795 µA Read operation See Table 3-12 on page 3-16. See Table 3-12 on page 3-16. Erase 900 µA Write 900 µA 20 µW/MHz NVM System NVM Power PNVMCTRL 3 -2 6 Array Operating NVM Controller Operating Power Pr e li m i n a ry v0 . 4 Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution Part Number and Revision Date Part Number 51700104-003-0 Revised October 2008 List of Changes The following table lists critical changes that were made in the current version of the document. This datasheet is based on the Actel Fusion Mixed-Signal FPGAs datasheet. For any past Fusion datasheet changes, refer to the Actel Fusion Mixed-Signal FPGAs datasheet change table. Previous Version Changes in Current Version (Preliminary v0.4) Page Advance v0.3 (August 2008) The version number category was changed from Advance to Preliminary, which means the datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. N/A Advance v0.1 (July 2008) The title of the datasheet changed from Actel Programmable System Chips for the MicroBlade Advanced Mezzanine Card Solution to Actel Fusion MixedSignal FPGAs for the MicroBlade Advanced Mezzanine Card Solution. In addition, all instances of programmable system chip were changed to mixedsignal FPGA. N/A Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. Pr e li m i n a ry v0 . 4 3 - 27