ATMEL AT40KAL

Features
• Functionally and Pin Compatible with the Atmel Rad Hard AT40KAL Series
• Ultra High Performance
•
•
•
•
•
•
•
•
•
•
•
– System Speeds to 85 MHz
– Array Multipliers > 45 MHz
– 14 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
FreeRAM™
– Flexible, Single/Dual Port, Sync/Async 14 ns SRAM
– 18432 Bits of Distributed SRAM Independent of Logic Cells for AT40KAL
384 PCI Compliant I/Os
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin Locking
8 Global Clocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
Cache Logic® Dynamic Full/Partial Reconfigurability In-System
– Unlimited Reprogrammability via Serial or Parallel Modes
– Enables Adaptive Designs
– Enables Fast Vector Multiplier Updates
– Quick-Change™ Tools for Fast, Easy Design Changes
Package Options
– MQFPF160
Industry-standard Design Tools
– Seamless Integration (Libraries, Interface, Full Back-annotation) with Exemplar™,
Mentor®, Synplicity®
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s
of Reusable, Fully Deterministic Logic and RAM Functions
Intellectual Property Cores
– Fir Filters, UARTs, PCI, FFT and Other System Level Functions
Easy Migration to Atmel Gate Arrays for High Volume Production
Supply Voltage 3.3V
Design Tools
– ATDH40M: Mother Board
– ATDH40D160M: Daughter Board for MQFPF160
– ATDS2100PC: IDS Software Design Kit
– ATDH 2225: AT17 Series Configuration Memory ISP Downloadable
QML Q Quality Grade
Military
Reprogrammable
FPGAs with
FreeRAM™
AT40KAL
Preliminary
Rev. 4263B–AERO–06/03
1
***
Table 1. AT40KAL
Device
AT40KAL040
Usable Gates
Rows x Columns
Cells
40K - 50K
48 x 48
2,304
Registers
3,048(1)
RAM Bits
18,432
I/O (max)
384
Note:
1. Packages with FCK will have 8 less clocks.
Description
The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed
14 ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global
clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and 50,000 usable gates. I/O counts range from 128 to
384 in Aerospace standard packages and support 3.3V.
The AT40KAL is designed to quickly implement high performance, large gate count
designs through the use of synthesis and schematic-based tools used on a PC and
Sun™ platform. Atmel’s design tools provide seamless integration with industry standard
tools such as Synplicity, Modelsim, Exemplar and Viewlogic. See the IDS datasheet for
other supported tools.
The AT40KAL can be used as a co-processor for high-speed (DSP/processor-based)
designs by implementing a variety of compute-intensive, arithmetic functions. These
include adaptive finite impulse response (FIR) filters, Fast Fourier Transforms (FFT),
convolvers, interpolators and discrete-cosine transforms (DCT) that are required for
video compression and decompression, encryption, convolution and other multimedia
applications.
Fast, Flexible and
Efficient SRAM
The AT40KAL FPGA offers a patented distributed 11 - 13 ns SRAM capability where the
RAM can be used without losing logic resources. Multiple independent, synchronous or
asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be
created using Atmel’s macro generator tool.
Fast, Efficient Array and
Vector Multipliers
The AT40KAL’s patented 8-sided core cell with direct horizontal, vertical and diagonal
cell-to-cell connections implements ultra fast array multipliers without using any busing
resources. The AT40KAL’s Cache Logic capability enables a large number of design
coefficients and variables to be implemented in a very small amount of silicon, enabling
vast improvement in system speed at much lower cost than conventional FPGAs.
Cache Logic Design
The AT40KAL is capable of implementing Cache Logic (Dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As
new logic functions are required, they can be loaded into the logic cache without losing
the data already there or disrupting the operation of the rest of the chip; replacing or
complementing the active logic. The AT40KAL can act as a reconfigurable co-processor.
Automatic Component
Generators
The AT40KAL FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro
orientation or density of the target device. This enables the fastest, most predictable and
efficient FPGA design approach and minimizes design risk by reusing already proven
functions. The Automatic Component Generators work seamlessly with industry-stan-
2
AT40KAL
4263B–AERO–06/03
AT40KAL
dard schematic and synthesis tools to create the fastest, most efficient designs available.
The patented AT40KAL series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable I/O.
Devices offer 50,000 usable gates, and have 3,056 registers. AT40KAL series FPGAs
utilize a reliable 0.35µ single-poly, 4-metal CMOS process and are 100% factory-tested.
Atmel’s PC- and workstation-based integrated development system (IDS) is used to create AT40KAL series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
3
4263B–AERO–06/03
The Symmetrical
Array
At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1).
The array is continuous from one edge to the other, except for bus repeaters spaced
every four cells (Figure 2 on page 5). At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured
as either a single-ported or dual-ported RAM(1), with either synchronous or asynchronous operation.
Note:
1. The right-most column can only be used as single-port RAM.
Figure 1. Symmetrical Array Surrounded by I/O (AT40K20)
Note:
4
= I/O Pad
= Repeater Row
= AT40K Cell
= Repeater Column
= FreeRAM
AT40KAL has registered I/Os. Group enable every sector for tri-states on obuf’s.
AT40KAL
4263B–AERO–06/03
AT40KAL
Figure 2. Floorplan (Representative Portion)(1)
RV
= Vertical Repeater
RH
= Horizontal Repeater
= Core Cell
RAM
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
Note:
RV
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RAM
1. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Each repeater has connections to two adjacent
local-bus segments and two express-bus segments. This is done automatically using
the integrated development system (IDS) tool.
5
4263B–AERO–06/03
The Busing Network
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus (both sides)
resources. Bus resources are connected via repeaters. Each repeater has connections
to two adjacent local-bus segments and two express-bus segments. Each local-bus
segment spans four cells and connects to consecutive repeaters. Each express-bus
segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the
same plane. Although not shown, a local bus can bypass a repeater via a programmable pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are
implemented through pass gates in the cell-bus interface (see following page).
Express/Express turns are implemented through separate pass gates distributed
throughout the array.
Some of the bus resource on the AT40KAL is used as a dual-function resource. Table 2
shows which buses are used in a dual-function mode and which bus plane is used. The
AT40KAL software tools are designed to accommodate dual-function buses in an efficient manner.
Table 2. Dual-function Buses
Function
Type
Plane(s)
Direction
Cell Output Enable
Local
5
Horizontal and
Vertical
RAM Output Enable
Express
2
Vertical
Bus full length at array edge
Bus in first column to left of RAM block
RAM Write Enable
Express
1
Vertical
Bus full length at array edge
Bus in first column to left of RAM block
RAM Address
Express
1-5
Vertical
Buses full length at array edge
Buses in second column to left of RAM block
RAM Data In
Local
1
Horizontal
RAM Data Out
Local
2
Horizontal
Clocking
Express
4
Vertical
Bus half length at array edge
Set/Reset
Express
5
Vertical
Bus half length at array edge
6
Comments
AT40KAL
4263B–AERO–06/03
AT40KAL
Figure 3. Busing Plane (One of Five)
= AT40K/40KAL
AT40KAL
= Local/Local or Express/Express Turn Point
= Row Repeater
= Column
Express
Express
bus
bus
Local
bus
7
4263B–AERO–06/03
Cell Connections
Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.
Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
CEL
CEL
plane 5
plane 4
plane 3
plane 2
plane 1
Figure 4. Cell Connections
CEL















plane 5 
plane 4 
plane 3 
plane 2 
plane 1 

 Horizontal
 busing plane


WXYZL
CEL
CEL
W
X
Y
Z
L
CEL
CEL





Diagonal
direct connect
CEL
CEL
Orthogonal
direct connect
(a) Cell-to-cell Connections
8
Vertical
busing plane
CEL
(b) Cell-to-bus Connections
AT40KAL
4263B–AERO–06/03
AT40KAL
The Cell
Figure 5 depicts the AT40KAL cell. Configuration bits for separate muxes and pass
gates are independent. All permutations of programmable muxes and pass gates are
legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is connected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by
turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let signals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming
into the logic cell on one local bus plane can be switched onto another plane by opening
two of the pass gates. This allows bus signals to switch planes to achieve greater
routability. Up to five simultaneous local/local turns are possible.
The AT40KAL FPGA core cell is a highly configurable logic block based around two 3input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This
means that any core cell can implement two functions of 3 inputs or one function of 4
inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated
and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every
cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an important feature in the implementation of efficient array multipliers.
Figure 5. The Cell
"1" NW NE SE SW
"1"
"1"
X
N
E
S
W
W
Y
Z
X
W
Y
FB
8X1 LUT
8X1 LUT
OUT
OUT
"1"
"0" "1"
V1
V2
V3
V4
V5
H1
H2
H3
H4
H5
Pass gates
1 0
Z
"1" OEH OEV
D
Q
CLOCK
RESET/SET
Y
X
NW NE SE SW
L
N
E
S
W
X = Diagonal Direct connect or Bus
Y = Orthogonal Direct Connector Bus
W = Bus Connection
Z = Bus Connection
FB = Internal Feed back
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40KAL architecture well suited to most
digital design application areas (see Figure 6).
9
4263B–AERO–06/03
A
B
C
D
LUT
Figure 6. Some Single Cell Modes
Q (Registered)
DQ
and/or
Q
LUT
SUM
or
A
B
C
DQ
SUM (Registered)
LUT
A
B
C
D
CARRY
PRODUCT (Registered) implement array multipliers. An array multiplier is an array
or
of bitwise multipliers, each implemented as a full adder
DSP/Multiplier Mode. This mode is used to efficiently
DQ
PRODUCT
LUT
LUT
and/or
CARRY IN
LUT
2:1 MUX
with an upstream AND gate. Using this AND gate and the
diagonal interconnects between cells, the array multiplier
structure fits very well into the AT40K architecture.
CARRY
DQ
Q
and/or
A
B
C
Arithmetic Mode is frequently used in many designs.
As can be seen in the figure, the AT40K core cell can
implement a 1-bit full adder (2-input adder with both Carry
In and Carry Out) in one core cell. Note that the sum
output in this diagram is registered. This output could then
be tri-stated and/or fed back into the cell.
LUT
and/or
Synthesis Mode. This mode is particularly important for
the use of VHDL design. VHDL Synthesis tools generally
will produce as their output large amounts of random logic
functions. Having a 4-input LUT structure gives efficient
random logic optimization without the delays associated
with larger LUT structures. The output of any cell may be
registered, tri-stated and/or fed back into a core cell.
Counter Mode. Counters are fundamental to almost all
digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially
an increment by one function (i.e., an adder), with the
input being an output (or a decode of an output) from the
previous stage. A 1-bit counter can be implemented in one
core cell. Again, the output can be registered, tri-stated
and/or fed back.
CARRY
Q
Tri-state/Mux Mode. This mode is used in many
telecommunications applications, where data needs to be
routed through more than one possible path. The output of
the core cell is very often tri-statable for many inputs to
many outputs data switching.
EN
10
AT40KAL
4263B–AERO–06/03
AT40KAL
RAM
32 x 4 dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7.
A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sector rows (plane 2). A 5-bit Input Address Bus connects to five
vertical express buses in same column. A 5-bit Output Address Bus connects to five vertical express buses in same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
CLK
CLK
CLK
CLK
Din
Ain
Dout
Aout
32 x 4 RAM
WEN
OEN
CLK
Reading and writing of the 11 - 13 ns 32 x 4 dual-port FreeRAM are independent of
each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are
transparent; when Load is logic 1, data flows through; when Load is logic 0, data is
latched. These latches are used to synchronize Write Adress, Write Enable Not, and Din
signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the memory latch together form an edge-triggered flip
flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0,
11
4263B–AERO–06/03
data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or
WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled
together; they both select CLOCK (for a synchronous RAM) or they both select “1” (for
an asynchronous RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM
clear byte during configuration clears the RAM (see the “AT40KAL/KEL Configuration
Series” application note at www.atmel.com).
Figure 8. RAM Logic
CLOCK
“1”
0
Ain
Aout
1
1
5
Read Address
Load
Latch
Write Address
32 x 4
Dual-port
RAM
Load
Latch
4
0
Load
5
WEN
Din
“1”
“1” OE
Write Enable NOT
4
Load
Latch
Din
Dout
Dout
Clear
RAM-Clear Byte
Figure 9 on page 13 shows an example of a RAM macro constructed using AT40KAL’s
FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note
the very small amount of external logic required to complete the address decoding for
the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will
be unused: they can be used for other logic in the design. This logic can be automatically generated using the macro generators.
12
AT40KAL
4263B–AERO–06/03
Write
Address
2-to-4
Decoder
2-to-4
Decoder
Read
Address
Din(0)
Dout(0)
Din(1)
Dout(1)
Din(2)
Dout(2)
Din(3)
Dout(3)
Din
Ain
Dout
Aout
WEN
OEN
Din
Aout
Dout
Ain
WEN
OEN
Din
Ain
Dout
Aout
WEN
OEN
Din
Aout
Dout
Ain
WEN
OEN
Din(4)
Dout(4)
Din(5)
Dout(5)
Din(6)
Dout(6)
Din(7)
Dout(7)
Din
Ain
WEN
OEN
Dout
Aout
Din
Aout
WEN
OEN
Dout
Ain
Din
Ain
WEN
OEN
Dout
Aout
Din
Aout
WEN
OEN
Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous)
4263B–AERO–06/03
WE
Dout
Ain
Local Buses
Express Buses
Dedicated Connections
AT40KAL
13
Clocking Scheme
14
There are eight Global Clock buses (GCK1 - GCK8) on the AT40KAL FPGA. Each of
the eight dedicated Global Clock buses is connected to one of the dual-use Global
Clock pins. Any clocks used in the design should use global clocks where possible: this
can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations.
In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per
edge column of the array for PCI specification. Even the derived clocks can be routed
through the Global network. Access points are provided in the corners of the array to
route the derived clocks into the global clock network. The IDS software tools handle
derived clocks to global clock connections automatically if used.
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Column Clock mux is at the top of every column of an array and the Sector Clock mux is at
every four cells. The Column Clock mux is selected from one of the eight Global Clock
buses. The clock provided to each sector column of four cells is inverted, non-inverted
or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a
sector that has no clocks. The clock can either come from the Column Clock or from the
Plane 4 express bus (see Figure 10 on page 15). The extreme-left Column Clock mux
has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The
extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to
provide fast clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configuration on power-up, constant “0” is provided to each register’s clock pins. After configuration on power-up, the registers either set or reset, depending on the user’s choice.
The clocking scheme is designed to allow efficient use of multiple clocks with low clock
skew, both within a column and across the core cell array.
AT40KAL
4263B–AERO–06/03
AT40KAL
Figure 10. Clocking (for One Column of Cells)
}



“1”
FCK (2 per Edge Column of the Array)
GCK1 - GCK8
Column Clock Mux
Sector Clock Mux
Global Clock Line
(Buried)
Express Bus
(Plane 4; Half length at edge)
“1”
Repeater
Sector Clock Mux
“1”
“1”
15
4263B–AERO–06/03
Set/Reset Scheme
16
The AT40KAL family reset scheme is essentially the same as the clock scheme except
that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by
any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to
indicate the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux,
there is Sector Set/Reset mux at every four cells. Each sector column of four cells is
set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux
(Figure 11 on page 17). The set/reset provided to each sector column of four cells is
either inverted or non-inverted using the Sector Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in
each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or
Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a
high) is provided by each register (i.e., all registers are set at power-up).
AT40KAL
4263B–AERO–06/03
AT40KAL
Figure 11. Set/Reset (for One Column of Cells)
Each Cell has a programmable Set or Reset
Sector Set/Reset Mux
Repeater
“1”
Global Set/Reset Line (Buried)
“1”
Express Bus
(Plane 5; Half length at edge)
“1”
“1”
Any User I/O can drive Global Set/Reset line
17
4263B–AERO–06/03
I/O Structure
AT40KAL has registered I/Os and group enable every sector for tri-states on obuf’s.
Pad
The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os
have pads: the ones without pads are called Unbonded I/Os. The number of unbonded
I/Os varies with the device size and package. These unbonded I/Os are used to perform
a variety of bus turns at the edge of the array.
Pull-up/Pull-down
Each pad has a programmable pull-up and pull-down attached to it. This supplies a
weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate
the signal level of the pad pin.
The input stage of each I/O cell has a number of parameters that can be programmed
either as properties in schematic entry or in the I/O Pad Attributes editor in IDS.
CMOS
The threshold level is a CMOS-compatible level.
Schmitt
A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenerative comparator circuit that adds 1V hysteresis to the input. This effectively improves the
rise and fall times (leading and trailing edges) of the incoming signal and can be useful
for filtering out noise.
Delays
The input buffer can be programmed to include four different intrinsic delays as specified
in the AC timing characteristics. This feature is useful for meeting data hold requirements for the input signal.
Drive
The output drive capabilities of each I/O are programmable. They can be set to FAST,
MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability
(16 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive
(12 mA at 5V) buffer, while SLOW yields a standard (4 mA at 5V) buffer.
Tri-State
The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open
drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can
be normal (0 or 1), as well.
Source Selection Mux
The Source Selection mux selects the source for the output signal of an I/O. See
Figure 12 on page 21.
Primary, Secondary and
Corner I/Os
The AT40KAL has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O.
Every edge cell except corner cells on the AT40KAL has access to one Primary I/O and
two Secondary I/Os.
Primary I/O
Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and
from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It
also connects into the repeaters on the row immediately above and below the adjacent
core cell. In addition, each Primary I/O also connects into the busing network of the
three nearest edge cells. This is an extremely powerful feature, as it provides logic cells
toward the center of the array with fast access to I/Os via local and express buses. It can
be seen from the diagram that a given Primary I/O can be accessed from any logic cell
on three separate rows or columns of the FPGA. See Figures 12a and 13a.
Secondary I/O
Every logic cell at the edge of the FPGA array has two direct diagonal connections to a
Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O
18
AT40KAL
4263B–AERO–06/03
AT40KAL
connects on the diagonal inputs to the cell above and the cell below. It also connects to
the repeater of the cell above and below. In addition, each Secondary I/O also connects
into the busing network of the two nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via
local and express buses. It can be seen from the diagram that a given Secondary I/O
can be accessed from any logic cell on two rows or columns of the FPGA. See Figure
12a and Figure 13b.
Corner I/O
Logic cells at the corner of the FPGA array have direct-connect access to five separate
I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary
I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KAL FPGA
with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be
accessed both from the corner logic cell and the horizontal and vertical busing networks
running along the edges of the array. This means that many different edge logic cells
can access the Corner I/Os. See Figure 14.
19
4263B–AERO–06/03
Figure 12. South I/O (Mirrored for North I/O)
“0”
“1”
DRIVE
VCC
TRI-STATE
CELL
“0”
PULL-UP
“1”
PAD
CELL
SOURCE SELECT MUX
DELAY
SCHMITT
TTL/CMOS
GND
PULL-DOWN
CELL
“0”
“1”
CELL
DRIVE
VCC
TRI-STATE
Primary I/OI/O
(a)(a)
Primary
“0”
PULL-UP
“1”
PAD
SOURCE SELECT MUX
DELAY
SCHMITT
TTL/CMOS
GND
PULL-DOWN
CELL
(b) Secondary I/O
20
AT40KAL
4263B–AERO–06/03
AT40KAL
Figure 13. West I/O (Mirrored for East I/O)
TRI-STATE
a. Primary I/0
VCC
"0"
"1"
DRIVE
CELL
PULL-UP
"0"
"1"
RST
ICLK
RST
SCHMITT
DELAY
TTL/CMOS
GND
PULL-DOWN
OCLK
PAD
CELL
b. Secondary I/O
21
4263B–AERO–06/03
PAD
VCC
VCC
PULL-DOWN
PAD
PULL-UP
PULL-DOWN
PULL-UP
Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners)
GND
GND
SCHMITT
DELAY
TRI-ST ATE
TTL/CMOS
DRIVE
TTL/CMOS
DRIVE
SCHMITT
DELAY
TRI-ST ATE
ICLK
ICLK
OCLK
RST
OCLK
RST
RST
RST
TRI-STATE
"1"
"0"
"0"
"1"
"0"
"1"
"0"
"1"
RST
DRIVE
VCC
"0"
"1"
PULL-UP
"0"
"1"
RST
OCLK
PAD
CELL
CELL
RST
ICLK
SCHMITT
DELAY
TTL/CMOS
GND
PULL-DOWN
CELL
22
AT40KAL
4263B–AERO–06/03
AT40KAL
Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*Note:
Storage Temperature ..................................... -65 °C to +150°C
Junction Temperature .................................................. +150°C
Voltage on Any Pin
with Respect to Ground (1) ..........................-0.5V to VCC +0.5V
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Supply Voltage (VCC) ................................................ 5V ± 10%
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 4000V
1.
For DC Input Voltage (VI) Minimum voltage of -0.5V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
DC and AC Operating Range
Operating Temperature
-55°C to +125°C
3.3V ± 0.3V
VCC Power Supply
Input Voltage Level (CMOS)
High (VIHC)
70% - 100% VCC
Low (VILC)
0 - 30% VCC
23
4263B–AERO–06/03
DC Characteristics
Symbol
Parameter
VIH
High-level Input Voltage
VIL
VOH
VOL
IIH
Conditions
CMOS
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
High-level Input Current
IIL
Low-level Input Current
IOZH
High-level Tri-state Output
Leakage Current
IOZL
Low-level Tri-state Output
Leakage Current
Min
Max
Units
70% VCC
V
TTL
2.0
CMOS
-0.3
30% VCC
V
TTL
-0.3
0.8
V
IOH = 4 mA
VCC = VCC min
2.4
V
IOH = 12 mA
VCC = 3.0V
2.4
V
IOH = 16 mA
VCC = 3.0V
2.4
V
V
IOL = -4 mA
VCC = 3.0V
0.4
V
IOL = -12 mA
VCC = 3.0V
0.4
V
IOL = -16 mA
VCC = 3.0V
0.4
V
5
µA
300.0
µA
5
µA
-20
µA
VIN = VCC max
-5
With pull-down, VIN = VCC
20
VIN = VSS
-5
With pull-up, VIN = VSS
-300.0
75
-50
Without pull-down, VIN = VCC
max
-5
5
µA
With pull-down, VIN = VCC max
20
300.0
µA
Without pull-up, VIN = VSS
-5
5
mA
-150.0
-110
µA
1
5
mA
10.0
pF
With pull-up, VIN = VSS
for CON
ICC
Standby Current
Consumption
Standby, unprogrammed
CIN
Input Capacitance
All pins
Note:
Typ
-500
1. Parameter based on characterization and simulation; it is not tested in production.
Power-On Power Supply
Requirements
Atmel FPGAs require a minimum rated power supply current capacity to ensure proper
initialization, and the power supply ramp-up time does not affect the current required. A
fast ramp-up time requires more current than a slow ramp-up time.
Table 3. Power-on Supply Requirements
Note:
Description
Maximum Current(1)(2)
Maximum Current Supply
100 mA
1. Devices are guaranteed to initialize properly at 50% of the minimum current listed
above. A larger capacity power supply may result in a larger initiallization current.
2. Ramp-up time is measured from 0V DC to 3.6V DC. Peak current required lasts less
than 2 ms, and occurs near the internal power on reset threshold voltage.
24
AT40KAL
4263B–AERO–06/03
AT40KAL
AC Timing
Characteristics
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: Vcc = 3.0V, temperature = 125°C.
Minimum times based on best case: Vcc = 3.60V, temperature = -55°C.
Maximum delays are the average of tPDLH and tPDHL.
Cell Function
Parameter
Path
AT40KAL
Units
Notes
2-input gate
tPD (max)
x/y -> x/y
1.9
ns
1 unit load
3-input gate
tPD (max)
x/y/z -> x/y
2.3
ns
1 unit load
3-input gate
tPD (max)
x/y/w -> x/y
2.5
ns
1 unit load
4-input gate
tPD (max)
x/y/w/z -> x/y
2.5
ns
1 unit load
Fast carry
tPD (max)
y -> y
1.8
ns
1 unit load
Fast carry
tPD (max)
x -> y
1.7
ns
1 unit load
Fast crry
tPD (max)
y -> x
1.8
ns
1 unit load
Fast carry
tPD (max)
x -> x
1.9
ns
1 unit load
Fast carry
tPD (max)
w -> y
2.4
ns
1 unit load
Fast carry
tPD (max)
w -> x
2.5
ns
1 unit load
Fast carry
tPD (max)
z -> y
2.3
ns
1 unit load
Fast carry
tPD (max)
z -> x
2.3
ns
1 unit load
DFF
tPD (max)
clk -> x/y
2.1
ns
1 unit load
DFF
tPD (max)
R -> x/y
2.8
ns
1 unit load
DFF
tPD (max)
S -> x/y
2.9
ns
1 unit load
DFF
tPD (max)
q -> w
2.2
ns
Incremental -> L
tPD (max)
x/y -> L
1.7
ns
1 unit load
Local output enable
tPZX (max)
oe -> L
1.5
ns
1 unit load
Local output enable
tPXZ (max)
oe -> L
0.8
ns
Core
AC Timing
Characteristics
All input I/O characteristics measured from VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VDD.
All output I/O characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD.
Cell Function
Parameter
Path
AT40KAL
Units
Notes
Repeaters
Repeater
tPD (max)
L -> E
1.2
ns
1 unit load
Repeater
tPD (max)
E -> E
1.2
ns
1 unit load
Repeater
tPD (max)
L -> L
1.2
ns
1 unit load
Repeater
tPD (max)
E -> L
1.2
ns
1 unit load
Repeater
tPD (max)
E -> IO
0.5
ns
1 unit load
Repeater
tPD (max)
L -> IO
0.5
ns
1 unit load
25
4263B–AERO–06/03
Cell Function
Parameter
Path
AT40KAL
Units
Notes
Input
tPD (max)
pad -> x/y
2.7
ns
no extra delay
Input
tPD (max)
pad -> x/y
4.9
ns
1 extra delay
Input
tPD (max)
pad -> x/y
8.1
ns
2 extra delays
Input
tPD (max)
pad -> x/y
11.3
ns
3 extra delays
Output, slow
tPD (max)
x/y/E/L -> pad
11.2
ns
50 pf load
Output, medium
tPD (max)
x/y/E/L -> pad
8.4
ns
50 pf load
Output, fast
tPD (max)
x/y/E/L -> pad
6.9
ns
50 pf load
Output, slow
tPZX (max)
oe -> pad
12.2
ns
50 pf load
Output, slow
tPXZ (max)
oe -> pad
1.9
ns
50 pf load
Output, medium
tPZX (max)
oe -> pad
7.8
ns
50 pf load
Output, medium
tPXZ (max)
oe -> pad
3.3
ns
50 pf load
Output, fast
tPZX (max)
oe -> pad
6.1
ns
50 pf load
Output, fast
tPXZ (max)
oe -> pad
3.3
ns
50 pf load
I/O
26
AT40KAL
4263B–AERO–06/03
AT40KAL
AC Timing
Characteristics
Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC.
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
Cell Function
Parameter
Path
Device
pad -> clock
AT40KAL
Units
Notes
Global Clocks and Set/Reset
GCK Input buffer
tPD (max)
2.5
ns
rising edge clock
FCK Input buffer
tPD (max)
pad -> clock
AT40KAL
1.9
ns
rising edge clock
Clock column driver
tPD (max)
clock -> colclk
AT40KALAT
40KAL
1.1
ns
rising edge clock
Clock sector driver
tPD (max)
colclk -> secclk
AT40KAL
0.7
ns
rising edge clock
GSRN Input buffer
tPD (max)
colclk -> secclk
AT40KAL
7.2
ns
Global clock to output
tPD (max)
clock pad -> out
AT40KAL
13.4
ns
rising edge clock
fully loaded clock tree
rising edge DFF
20 mA output buffer
50 pf pin load
Fast clock to output
tPD (max)
clock pad -> out
AT40KAL
12.4
ns
rising edge clock
fully loaded clock tree
rising edge DFF
20 mA output buffer
50 pf pin load
Notes:
1.
2.
3.
4.
CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant.
Buffer delay is to a pad voltage of 1.5V with one output switching.
Parameter based on characterization and simulation; not tested in production.
Exact power calculation is available in Atmel FPGA Designer software.
27
4263B–AERO–06/03
AC Timing
Characteristics
Cell Function
Parameter
Path
AT40KAL
Units
Notes
Write
tWECYC (min)
cycle time
14
Write
tWEL (min)
we
5.5
ns
pulse width low
Write
tWEH (min)
we
5.5
ns
pulse width high
Write
tsetup (min)
wr addr setup -> we
5.8
ns
Write
thold (min)
wr addr hold -> we
0.0
ns
Write
tsetup (min)
din setup -> we
5.0
ns
Write
thold (min)
din hold -> we
0.0
ns
Write
thold (min)
oe hold -> we
0.0
ns
Write/Read
tPD (max)
din -> dout
7.0
ns
Read
tPD (max)
rd addr -> dout
4.8
ns
Read
tPZX (max)
oe -> dout
3.3
ns
Read
tPXZ (max)
oe -> dout
3.3
ns
Async RAM
ns
rd addr = wr addr
Sync RAM
Write
tCYC (min)
cycle time
14
ns
Write
tCLKL (min)
clk
5.5
ns
pulse width low
Write
tCLKH (min)
clk
5.5
ns
pulse width high
Write
tsetup (min)
we setup -> clk
3.5
ns
Write
thold (min)
we hold -> clk
0.0
ns
Write
tsetup (min)
wr addr setup -> clk
5.5
ns
Write
thold (min)
wr addr hold -> clk
0.0
ns
Write
tsetup (min)
wr data setup -> clk
4.3
ns
Write
thold (min)
wr data hold -> clk
0.0
ns
Write/Read
tPD (max)
din -> dout
7.0
ns
rd addr = wr addr
Write/Read
tPD (max)
clk -> dout
4.9
ns
rd addr = wr addr
Read
tPD (max)
rd addr -> dout
4.8
ns
Read
tPZX (max)
oe -> dout
3.3
ns
Read
tPXZ (max)
oe -> dout
3.3
ns
28
AT40KAL
4263B–AERO–06/03
AT40KAL
FreeRAM Asynchronous
Timing Characteristics
Single Port Write/Read
tCLKH
CLK
tWCS
tWCH
tACS
tACH
WE
ADDR
0
1
3
2
OE
tOXZ
tDCS
tDCH
tOZX
tAD
DATA
Dual Port Write with Read
tCYC
tCLKH
tCLKL
CLK
tWCS
tWCH
tACS
tACH
WE
WR ADDR
0
1
2
tDCS
tDCH
WR DATA
RD ADDR
= WR ADDR 1
tCD
RD DATA
Dual Port Read
0
RD ADDR
1
OE
tOZX
tAD
tOXZ
DATA
29
4263B–AERO–06/03
FreeRAM Synchronous
Timing Characteristics
Single Port Write/Read
tCLKH
CLK
tWCS
tWCH
tACS
tACH
WE
ADDR
0
1
3
2
OE
tOXZ
tDCS
tDCH
tOZX
tAD
DATA
Dual Port Write with Read
tCYC
tCLKH
tCLKL
CLK
tWCS
tWCH
tACS
tACH
WE
WR ADDR
0
1
tDCS
2
tDCH
WR DATA
RD ADDR
= WR ADDR 1
tCD
RD DATA
30
AT40KAL
4263B–AERO–06/03
AT40KAL/EL
Dual Port Read
0
RD ADDR
1
OE
tOZX
tAD
tOXZ
DATA
31
4155A–AERO–06/02
AT40KAL/EL
Table 4. Pad/Pin Assignment
384 I/O
MQFPF160
GND
1
I/O1,
GCK1
(A16)
2
I/O2
(A17)
3
I/O3
384 I/O
MQFPF160
384 I/O
I/O31
I/O66
I/O32
GND
I/O33
I/O67
I/O34
I/O68
MQFPF160
I/O35
VCC
I/O36
I/O69
25
4
GND
I/O70
26
I/O4
5
VCC
I/O71
27
I/O5
(A18)
6
I/O37
I/O72,
FCK2
28
I/O6
(A19)
7
GND
29
I/O38
I/O39
I/O73
I/O40
GND
I/O74
I/O41
I/O7
I/O75
I/O42
I/O8
I/O76
GND
I/O9
I/O10
I/O11
I/O43
15
I/O44
16
I/O79
I/O46
VCC
GND
I/O13
I/O14
I/O78
GND
I/O45
I/O12
I/O77
I/O80
I/O47
(A22)
17
I/O48
(A23)
18
I/O81
I/O82
I/O83
30
I/O84
31
I/O15
8
GND
19
I/O16
9
VCC
20
I/O17
I/O49
21
VCC
I/O18
I/O50
22
I/O85
GND
I/O51
I/O19
I/O52
I/O20
I/O53
23
I/O21
I/O54
24
I/O22
GND
I/O23
I/O55
I/O24
I/O56
GND
I/O86
I/O87
I/O88
I/O89
32
I/O90
33
GND
I/O91
GND
10
I/O57
I/O92
I/O25,
FCK1
11
I/O58
I/O93
34
I/O26
12
I/O94
35
I/O95
(OTS)(1)
36
I/O96,
GCK2
37
M1
38
I/O59
I/O27
(A20)
13
I/O28
(A21)
14
I/O60
VCC
GND
I/O61
VCC
I/O62
I/O29
I/O63
GND
39
I/O30
I/O64
M0
40
GND
I/O65
VCC
41
M2
42
32
4155A–AERO–06/02
384 I/O
MQFPF160
I/O97,
GCK3
43
I/O98
(HDC)
44
I/O99
45
46
I/O102
(LDC)
47
48
GND
I/O133
I/O134
I/O135
I/O136
I/O137
56
I/O138
57
384 I/O
MQFPF160
I/O165
(D12)
66
I/O166
(D11)
67
I/O167
68
I/O168
69
GND
70
I/O169
I/O170
GND
GND
I/O103
I/O139
I/O104
I/O140
I/O105
I/O141
I/O106
I/O142
I/O107
I/O143
(D15)
58
I/O144
(INIT)
59
VCC
60
I/O178
GND
61
I/O179
71
I/O180
72
I/O108
VCC
GND
I/O109
49
I/O110
50
I/O111
I/O112
I/O113
I/O171
I/O172
I/O173
I/O174
GND
I/O145
(D14)
62
I/O146
(D13)
63
I/O116
I/O150
I/O117
GND
VCC
I/O181
I/O182
I/O149
I/O115
I/O177
GND
I/O148
GND
I/O175
I/O176
I/O147
I/O114
I/O183
(D10)
73
I/O184
(D9)
74
I/O151
64
I/O185
I/O119
I/O152
65
I/O186
I/O120
I/O153
GND
I/O154
I/O187
I/O155
I/O188
I/O156
I/O189
75
VCC
I/O190
76
GND
I/O191
(D8)
77
I/O192, GCK4
78
I/O118
GND
51
I/O121
52
I/O122
53
I/O123
54
I/O124
VCC
I/O125
I/O126
GND
I/O127
I/O128
I/O129
I/O130
I/O131
I/O132
33
MQFPF160
VCC
I/O100
I/O101
384 I/O
55
I/O157
I/O158
GND
79
CON
80
I/O161
VCC
81
I/O162
RESET
82
GND
I/O193
(D7)
83
I/O164
I/O194,
GCK5
84
VCC
I/O195
85
I/O159
I/O160
I/O163
AT40KAL/EL
4155A–AERO–06/02
AT40KAL/EL
384 I/O
MQFPF160
384 I/O
I/O196
86
MQFPF160
384 I/O
I/O229
I/O264
I/O197
I/O230
GND
I/O198
I/O231
I/O265
GND
I/O232
I/O266
I/O199
I/O233
I/O267
I/O200
I/O234
I/O268
I/O201
GND
I/O202
I/O235
96
I/O203
I/O236
97
I/O204
I/O237
VCC
I/O238
GND
I/O239(D4)
I/O205
(D6)
87
I/O206
88
I/O207
89
I/O208
90
I/O209
I/O210
I/O269
I/O272
I/O240
99
I/O274
112
VCC
100
I/O275
I/O276
GND
101
I/O241
(D3)
102
I/O242
(CHECK)
103
I/O244
I/O213
I/O246
105
I/O214
GND
93
I/O281
I/O285
115
I/O286
116
I/O287 (D0)
117
118
GND
I/O288,
GCK6
(CSOUT)
I/O252
I/O220
I/O280
I/O284
I/O249
I/O251
92
114
I/O283
I/O250
I/O219,
FCK3
I/O278
GND
I/O248
I/O218
113
I/O282
I/O247
I/O217
I/O277 (D1)
I/O279
104
91
GND
VCC
I/O245
GND
GND
I/O271
111
I/O211
I/O216
I/O270
I/O273
I/O243
I/O215
110
98
GND
I/O212
MQFPF160
VCC
VCC
I/O253
CCLK
119
I/O221
(D5)
94
I/O254
VCC
120
I/O255
TSTCLK
121
I/O222
(CS0)
95
I/O256
GND
122
I/O257
I/O289
(A0)
123
I/O290,
GCK7
(A1)
124
I/O291
125
I/O292
126
GND
I/O223
I/O224
I/O225
I/O226
I/O227
I/O228
GND
VCC
I/O258
GND
I/O259
(D2)
106
I/O260
107
VCC
I/O293
I/O261
108
I/O262,FCK4
109
I/O294
GND
I/O263
34
4155A–AERO–06/02
384 I/O
MQFPF160
384 I/O
I/O295
I/O329
137
I/O361
I/O296
I/O330
138
I/O362
384 I/O
MQFPF160
I/O297
(CS1,A2)
127
I/O298
(A3)
128
I/O299
I/O300
VCC
GND
I/O301(1)
121(1) NC
I/O302
I/O363
I/O364
I/O332
I/O365
I/O333
I/O366
I/O334
GND
I/O335
(A6)
139
I/O367
I/O336
(A7)
140
GND
141
I/O368
I/O369
152
I/O370
153
154
155
I/O303
129
VCC
142
I/O371
(A12)
I/O304
130
I/O337
(A8)
143
I/O372
(A13)
I/O338
(A9)
144
GND
I/O305
I/O306
GND
I/O373
I/O340
I/O308
I/O374
I/O341
I/O309
I/O375
I/O342
I/O310
I/O376
GND
I/O311
I/O312
GND
131
I/O313
132
I/O314
133
I/O315
I/O316
I/O343
145
I/O344
146
VCC
I/O317
VCC
I/O318
GND
GND
I/O349
I/O319
I/O350
I/O320
I/O351
I/O321
I/O352
I/O322
I/O353
I/O323
I/O354
I/O324
GND
GND
I/O355
VCC
I/O356
I/O325
(A4)
134
I/O326
(A5)
135
I/O327
136
I/O378
I/O379
I/O346
I/O347
(A10)
I/O377
GND
I/O345
I/O348
(A11)
I/O328
VCC
I/O339
I/O307
35
GND
I/O331
MQFPF160
I/O380
147
148
I/O381
156
I/O382
157
I/O383
(A14)
158
I/O384,
GCK8
(A15)
159
VCC
160
Note: 1. Shared with TSTCLK
VCC
I/O357
I/O358
I/O359
149
I/O360
150
GND
151
AT40KAL/EL
4155A–AERO–06/02
Part/Package
Availability and User
I/O Counts (Including
Dual-function Pins)
Package
AT40KAL
MQFPF 160
130
MQFPF 256(1)
193
MQFPF 352(1)
289
Note:
1. Contact Atmel for availabilty.
Ordering Information
Part Number
Temperature Range
Quality Flow
25°C
Engineering Samples
AT40KAL040KW1M
-55° to +125°C
Standard Mil
AT40KAL040KW1MMQ
-55° to +125°C
Mil Std 883 Level B
AT40KAL040KW1M-E
36
AT40KAL
4263B–AERO–06/03
AT40KAL
Package Drawing
Multilayer Quad Flat Pack (MQFP) 160-pin
37
4263B–AERO–06/03
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2003. All rights reserved. ATMEL ®, and Cache Logic® are registered trademarks of
Atmel. FreeRAM ™ and QuickChange ™ are trademarks of Atmel.
Concept ®, Verilog ®, and OrCAD ®, are registered trademarks of Cadence Design Systems Inc.; Mentor®, and
Veribest ®, are registered trademarks of Mentor Graphics; Exemplar ™, is a trademark of Mentor Graphics.
Synario ™, is a trademark of Data I/O Corporation; Synopsis ®, is a registered trademark of Synopsis Inc.; Viewlogic ™, is a trademark of Viewlogic Systems, Inc.; Synplicity®, is a registered trademark of Synplify, Inc.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
4263B–AERO–06/03
/xM