Revised September 2001 MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output General Description Features The MM74HC589 high speed shift register utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. ■ 8-bit parallel storage register inputs The MM74HC589 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8bit shift register. Data can also be entered serially the shift register through the SER pin. Both the storage register and shift register have positive-edge triggered clocks, RCK and SCK, respectively. SLOAD pin controls parallel LOAD or serial shift operations for the shift register. The shift register has a 3-STATE output to enable the wire-ORing of multiple devices on a serial bus. ■ Wide operating voltage range: 2V–6V ■ Shift register has direct overriding load ■ Guaranteed shift frequency. . . DC to 30 MHz ■ Low quiescent current: 80 µA maximum (74HC Series) ■ 3-STATE output for ‘Wire-OR' The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Ordering Code: Order Number Package Number Package Description MM74HC589M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC589SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC589N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD OE X X X H Function QH in Hi-Z State X X X L QH is enabled ↑ X X X Data loaded into input latches ↑ X L X Data loaded into shift register H or L X L X from pins Data loaded from latches to shift register Top View X ↑ H X ↑ ↑ H X Shift register is shifted. Data on SER pin is shifted in. Data is shifted in shift register, and data is loaded into latches © 2001 Fairchild Semiconductor Corporation DS005368 www.fairchildsemi.com MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output September 1983 MM74HC589 Block Diagram www.fairchildsemi.com (positive logic) 2 Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC ) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA Supply Voltage (VCC) (VIN, VOUT ) Operating Temperature Range (TA) 600 mW S.O. Package only 500 mW Symbol VIH VIL VOH Parameter VCC V +85 °C 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 2: Unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics 0 −40 Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) V (tr, tf) VCC = 2.0V Power Dissipation (PD) (Note 3) Units 6 Input Rise or Fall Times −65°C to +150°C Storage Temperature Range (TSTG) Max 2 DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Min Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 4) Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 V V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VIN = VIH or VIL VOL |IOUT| ≤ 6.0 mA 4.5V 3.98 3.84 3.7 V |IOUT| ≤ 7.8 mA 6.0V 5.48 5.34 5.2 V Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V VIN = VIH or VIL |IOUT| ≤ 6.0 mA 4.5V 0.26 0.33 0.4 |IOUT| ≤ 7.8 mA 6.0V 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8.0 80 160 µA 6.0V ±0.5 ±5.0 ±10.0 µA IIN Maximum Input ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA Maximum 3-STATE Output in High Leakage Current Impedance State Current IOZ VIN = VIL or VIH VOUT = VCC or GND OE = VIH Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC589 Absolute Maximum Ratings(Note 1) MM74HC589 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter Typ Guaranteed Limit Units 50 30 MHz Maximum Propagation Delay from SCK to QH’ 30 ns tPHL, tPLH Maximum Propagation Delay from SLOAD to QH’ 30 ns tPHL, tPLH Maximum Propagation Delay from LCK to QH’ SLOAD = logic “0” 25 45 ns tPZH, tPZL Output Enable Time RL = 1 kΩ 18 28 ns tPHZ, tPLZ Output Disable Time RL = 1 kΩ, CL = 5 pF 19 25 ns tS Minimum Setup Time from RCK to SCK 10 20 ns tS Minimum Setup Time from SER to SCK 10 20 ns tS Minimum Setup Time from Inputs A thru H to RCK 10 20 ns tH Minimum Hold Time 0 5 ns tW Minimum Pulse Width SCK, RCK, SLOAD 8 16 ns fMAX Maximum Operating Frequency for SCK tPHL, tPLH Conditions AC Electrical Characteristics VCC = 2.0−6V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Maximum Operating 2.0V 6 4.8 4 MHz Frequency for SCK 4.5V 30 24 20 MHz MHz 6.0V tPHL, tPLH Maximum Propagation Delay from SCK or SLOAD to QH 35 28 24 2.0V 62 175 220 265 ns 4.5V 20 35 44 53 ns 6.0V 18 30 37 45 ns 2.0V 120 225 280 340 ns 4.5V 31 45 56 68 ns 6.0V 28 38 48 58 ns tPHL, tPLH Maximum Propagation 2.0V 80 210 265 315 ns Delay from RCK to QH 4.5V 25 42 53 63 ns 6.0V 21 36 45 54 ns 2.0V 80 210 265 313 ns 4.5V 25 52 66 77 ns 6.0V 21 44 56 66 ns 2.0V 70 150 189 224 ns 4.5V 22 30 38 45 ns 6.0V 20 26 32 38 ns 2.0V 70 150 189 224 ns 4.5V 22 30 38 45 ns 6.0V 20 ns tPHL, tPLH Maximum Propagation Delay from SCK or CL = 150 pF SLOAD to QH tPHL, tPLH Maximum Propagation Delay RCK to QH tPZH, tPZL Output Enable Time tPHZ, tPLZ Output Disable Time tS tS tS tH tW CL = 150 pF RL = 1 kΩ RL = 1 kΩ 26 32 38 Minimum Setup Time 2.0V 100 125 150 ns from RCK to SCK 4.5V 20 25 30 ns 6.0V 17 22 25 ns Minimum Setup Time 2.0V 100 125 150 ns from SER to SCK 4.5V 20 25 30 ns 6.0V 17 22 25 ns Minimum Setup Time 2.0V 100 125 150 ns from Inputs A thru H 4.5V 20 25 30 ns to RCK 6.0V 17 22 25 ns Minimum Hold Time 2.0V −5 5 5 5 ns 4.5V 0 5 5 5 ns 6.0V 1 5 5 5 ns Minimum Pulse Width 2.0V 30 80 100 120 ns SCK, RCK, SLOAD, 4.5V 9 16 20 24 ns SLOAD 6.0V 8 14 17 20 ns www.fairchildsemi.com 4 Symbol tr, tf Parameter Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Units Guaranteed Limits Maximum Input Rise and 2.0V 1500 1500 1500 ns Fall Time, Clock 4.5V 500 500 500 ns 6.0V 400 400 400 ns 60 75 90 ns tTHL, tTLH Maximum Output Rise and Fall Time CPD (Continued) 2.0V 25 4.5V 6 12 15 18 ns 6.0V 5 10 12 15 ns Power Dissipation 87 pF Capacitance (Note 5) CIN Maximum Input Capacitance 5 10 10 10 pF COUT Maximum Output Capacitance 15 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC sf + ICC. 5 www.fairchildsemi.com MM74HC589 AC Electrical Characteristics MM74HC589 Timing Diagram www.fairchildsemi.com 6 MM74HC589 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com MM74HC589 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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