93LCS56/66 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect FEATURES BLOCK DIAGRAM VCC • Single supply with programming operation down to 2.5V • Low power CMOS technology - 1 mA active current typical - 5 µA standby current (typical) at 3.0V • x16 memory organization - 128x16 (93LCS56) - 256x16 (93LCS66) • Software write protection of user defined memory space • Self timed erase and write cycles • Automatic ERAL before WRAL • Power on/off data protection • Industry standard 3-wire serial I/O • Device status signal during E/W • Sequential READ function • 1,000,000 E/W cycles guaranteed • Data retention > 200 years • 8-pin PDIP/SOIC and 14-pin SOIC packages • Temperature ranges supported - Commercial (C): 0˚C to +70˚C - Industrial (I): -40˚C to +85˚C V SS ADDRESS DECODER MEMORY ARRAY ADDRESS COUNTER OUTPUT BUFFER DATA REGISTER DO DI MODE DECODE LOGIC PRE PE CS CLOCK GENERATOR CLK DESCRIPTION The Microchip Technology Inc. 93LCS56/66 are low voltage Serial Electrically Erasable PROMs with memory capacities of 2K bits/4K bits respectively. A write protect register is included in order to provide a user defined region of write protected memory. All memory locations greater than or equal to the address placed in the write protect register will be protected from any attempted write or erase operation. It is also possible to protect the address in the write protect register permanently by using a one time only instruction (PRDS). Any attempt to alter data in a register whose address is equal to or greater than the address stored in the protect register will be aborted. Advanced CMOS technology makes this device ideal for low power non-volatile memory applications. PACKAGE TYPES SOIC DIP SOIC CS 1 8 VCC CLK 2 7 PRE PE DI 3 6 PE VSS DO 4 5 VSS CS 1 8 CLK 2 7 PRE DI 3 6 DO 4 5 93LCS56 93LCS66 VCC 93LCS56 93LCS66 NC 1 14 NC CS 2 13 VCC CLK 3 12 PRE NC 4 11 NC DI 5 10 PE DO 6 9 VSS NC 7 8 NC 93LCS56 93LCS66 Microwire is a registered trademark of National Semiconductor Incorporated. 1996 Microchip Technology Inc. Preliminary This document was created with FrameMaker 4 0 4 DS11181D-page 1 93LCS56/66 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name CS CLK DI DO VSS PE PRE VCC VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Protect Register Enable Power Supply DC AND AC ELECTRICAL CHARACTERISTICS VCC = +2.5V to +6.0V Commercial(C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Symbol High level input voltage Low level input voltage Low level output voltage VIH VIL VOL1 VOL2 High level output voltage VOH1 VOH2 Input leakage current ILI Output leakage current ILO Pin capacitance CIN, COUT (all inputs/outputs) Operating current ICC Write ICC Read Min Max Units 2.0 -0.3 — — 2.4 VCC-0.2 -10 -10 — VCC +1 0.8 0.4 0.2 — — 10 10 7 V V V V V V µA µA pF — — 3 1 500 100 30 2 1 — — — — — — — — — — — 400 100 mA mA µA µA µA MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Standby current ICCS — Clock frequency FCLK — Clock high time TCKH 250 Clock low time TCKL 250 Chip select setup time TCSS 50 Chip select hold time TCSH 0 Chip select low time TCSL 250 PRE setup time TPRES 100 PE setup time TPES 100 PRE hold time TPREH 0 PE hold time TPEH 500 Data input setup time TDIS 100 Data input hold time TDIH 100 Data output delay time TPD — Data output disable time TCZ — Note 1: This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. DS11181D-page 2 Conditions VCC ≥ 2.5V VCC ≥ 2.5V IOL = 2.1 mA; VCC = 4.5V IOL = 100 µA; VCC = 2.5V IOH = -400µA; VCC = 4.5V IOH = -100µA; VCC = 2.5V VIN = 0.1V to VCC VOUT = 0.1V to Vcc VIN/VOUT = 0V (Note 1 & 2) Tamb = +25˚C; FCLK = 1 MHz FCLK = 2 MHz; VCC = 3.0V (Note 2) FCLK = 2 MHz; VCC = 6.0V FCLK = 1 MHz; VCC = 3.0V CLK = CS = 0V; VCC = 6.0V CLK = CS = 0V; VCC = 3.0V VCC ≥ 4.5V VCC < 4.5V Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL=100 pF CL=100 pF (Note 2) Preliminary This document was created with FrameMaker 4 0 4 1996 Microchip Technology Inc. 93LCS56/66 DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TABLE 1-2: VCC = +2.5V to +6.0V Commercial(C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Symbol Status valid time Program cycle time TSV TWC TEC TWL — Endurance Min Max Units 1M 500 10 15 30 — ns ms ms ms cycles Conditions CL=100 pF ERASE/WRITE mode (Note 3) ERAL mode WRAL mode 25°C, Vcc = 5.0V, Block Mode (Note 4) 3: Typical program cycle time is 4 ms per word. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. TABLE 1-3: INSTRUCTION SET FOR 93LCS56*/66 93LCS56/66 (x 16 organization) Instruction SB Opcode Address Data In Data Out PRE PE Comments READ 1 10 A7 - A0 — D15-D0 0 X Reads data stored in memory, starting at specified address (.Note). EWEN 1 00 11XXXXXX — High-Z 0 1 Erase/Write Enable must precede all programming modes. ERASE 1 11 A7 - A0 — (RDY/ BSY) 1 Erase data at specified address location if address is unprotected (Note). ERAL 1 00 10XXXXXX — (RDY/ BSY) 0 1 Erase all registers to “FF”. Valid only when Protect Register is cleared. WRITE 1 01 A7 - A0* D15 - D0 (RDY/ BSY) 0 1 Writes register if address is unprotected. WRAL 1 00 01XXXXXX D15 - D0 (RDY/ BSY) 0 1 Writes all registers. Valid only when Protect Register is cleared. EWDS 1 00 00XXXXXX — High-Z 0 X Erase/Write Disable deactivates all programming instructions. PRREAD 1 10 XXXXXXXX — A7-A0 1 X Reads address stored in Protect Register. PREN 1 00 11XXXXXX — High-Z 1 1 Must immediately precede PRCLEAR, PRWRITE and PRDS instructions. PRCLEAR 1 11 11111111 — (RDY/ BSY) 1 1 Clears the Protect Register such that all data are NOT write-protected. PRWRITE 1 01 A7 - A0* — (RDY/ BSY) 1 1 Programs address into Protect Register. Thereafter, memory addresses greater than or equal to the address in Protect Register are write-protected. PRDS 1 00 00000000 — (RDY/ BSY) 1 1 ONE TIME ONLY instruction after which the address in the Protect Register cannot be altered. Note: Address A7 bit is a “don’t care” on 93LCS56. 1996 Microchip Technology Inc. Preliminary DS11181D-page 3 93LCS56/66 2.0 FUNCTIONAL DESCRIPTION 2.4 The 93LCS56/66 is organized as 128/256 registers by 16 bits. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the ready/busy status during a programming operation. The ready/busy status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS. 2.1 START Condition The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and PRDS). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected. 2.2 DI/DO It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation, if A0 is a logic HIGH level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. 2.3 Data Protection During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16 bit output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. 2.5 Erase/Write Enable and Disable (EWEN, EWDS) The 93LCS56/66 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. The PE pin MUST be held “high” while loading the EWEN instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/ Write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. 2.6 ERASE The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The PE pin MUST be latched “high” during loading the ERASE instruction but becomes a “don't care” after loading the instruction. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCLS). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. ERASE instruction is valid if specified address is unprotected. The ERASE cycle takes 4 ms per word typical. 2.7 WRITE The WRITE instruction is followed by 16 bits of data which are written into the specified address. After the last data bit is put on the DI pin, CS must be brought low before the next rising edge of the CLK clock. Both CS and CLK must be low to initiate the self-timed autoerase and programming cycle. The PE pin MUST be latched “high” while loading the WRITE instruction but becomes a “don't care” thereafter. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. DS11181D-page 4 Preliminary 1996 Microchip Technology Inc. 93LCS56/66 The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. WRITE instruction is valid only if specified address is unprotected. The WRITE cycle takes 4 ms per word typical. 2.8 The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. The ERAL cycle takes 15 ms maximum (8 ms typical). Write All (WRAL) The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. PE pin MUST be held “high” while loading the instruction but becomes “don't care” thereafter. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is guaranteed at VCC = 4.5 to 6V and valid only when Protect Register is cleared. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). The WRAL cycle takes 30 ms maximum (16 ms typical). Note: In order to execute either READ, EWEN, ERAL, WRITE, WRAL, or EWDS instructions, the Protect Register Enable (PRE) pin must be held LOW. 1996 Microchip Technology Inc. Protect Register Read (PRREAD) The Protect Register Read (PRREAD) instruction outputs the address stored in the Protect Register on the DO pin. The PRE pin MUST be held HIGH when loading the instruction and remains HIGH until CS goes LOW. A dummy zero bit precedes the 8-bit output string. The output data bits in the memory Protect Register will toggle on the rising edge of the CLK as in the READ mode. 2.11 Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1”. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. PE pin MUST be held “high” while loading the instruction but becomes “don't care” thereafter. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is guaranteed at VCC = 4.5 to 6V and valid only when Protect Register is cleared. 2.9 2.10 Protect Register Enable (PREN) The Protect Register Enable (PREN) instruction is used to enable the PRCLEAR, PRWRITE, and PRDS modes. Before the PREN mode can be entered, the device must be in the EWEN mode. Both PRE and PE pins MUST be held “high” while loading the instruction. The PREN instruction MUST immediately precede a PRCLEAR, PRWRITE, or PRDS instruction. 2.12 Protect Register Clear (PRCLEAR) The Protect Register Clear (PRCLEAR) instruction clears the address stored in the Protect Register and, therefore, enables all registers for programming instructions such as ERASE, ERAL, WRITE, and WRAL. The PRE and PE pin MUST be held HIGH when loading the instruction. Thereafter, PRE and PE pins become “don't care”. A PREN instruction must immediately precede a PRCLEAR instruction. 2.13 Protect Register Write (PRWRITE) The Protect Register Write (PRWRITE) instruction writes into the Protect Register the address of the first register to be protected. After this instruction is executed, all registers whose memory addresses are greater than or equal to the address pointer specified in the Protect register are protected from any programming instructions. Note that a PREN instruction must be executed before a PRWRITE instruction and, the Protect Register must be cleared (by a PRCLEAR instruction) before executing the PRWRITE instruction. The PRE and PE pins MUST be held HIGH while loading PRWRITE instruction. After the instruction is loaded, they become “don't care”. 2.14 Protect Register Disable (PRDS) The Protect Register Disable (PRDS) instruction is a ONE TIME ONLY instruction to permanently set the address specified in the Protect Register. Any attempts to change the address pointer will be aborted. The PRE and PE pins MUST be held HIGH while loading PRDS instruction. After the instruction is loaded, they become “don't care”. Note that a PREN instruction must be executed before a PRDS instruction. Preliminary DS11181D-page 5 93LCS56/66 FIGURE 2-1: SYNCHRONOUS DATA TIMING VIH PRE VIL TPRES PE TPREH VIH VIL TPEH TPES VIH CS TCSS VIL TCKH TCKL TCSH VIH CLK VIL TDIH TDIS VIH DI VIL TPD DO (READ) TCZ TPD VOH TCZ VOL DO VOH (PROGRAM) VOL FIGURE 2-2: TSV STATUS VALID READ TIMING TCSL CS CLK DI 1 1 0 A2 ••• A0 TRI-STATE DO 0 D15 ••• D0 D15* ••• D0 D15* ••• PRE = 0 PE = X * The memory automatically cycles to the next register. Tri-State is a registered trademark of National Semiconductor. FIGURE 2-3: EWEN TIMING PE TCSL CS CLK DI 1 0 0 1 1 X ••• X 6 DON'T CARE BITS DS11181D-page 6 Preliminary PRE = 0 DO = TRI-STATE 1996 Microchip Technology Inc. 93LCS56/66 FIGURE 2-4: EWDS TIMING TCSL CS CLK DI 1 0 0 0 0 ••• X X PRE = 0 PE = X DO = TRI-STATE 6 DON'T CARE BITS FIGURE 2-5: WRITE TIMING PE TCSL CS CLK 1 DI 0 1 A7 ••• A0 D15 ••• D0 BUSY TRI-STATE DO • Address bit A7 becomes a "don't care" for 93LCS56. FIGURE 2-6: PRE = 0 READY TWC WRAL TIMING PE T CSL CS CLK DI 1 0 0 0 1 X ••• X D15 ••• D0 6 DON'T CARE BITS DO TRI-STATE Guaranteed at VCC = 4.5V to 6.0V Protect Register must be cleared 1996 Microchip Technology Inc. BUSY PRE = 0 READY TRISTATE TWL Preliminary DS11181D-page 7 93LCS56/66 FIGURE 2-7: ERASE TIMING PE T CSL CS STANDBY CHECK STATUS CLK 1 DI 1 A7 1 A0 ••• TCZ T SV TRI-STATE • Address bit A7 is a "don't care" for 93LCS56. FIGURE 2-8: READY BUSY DO PRE = 0 TRI-STATE T WC ERAL TIMING PE TCSL CS CHECK STATUS STANDBY CLK 1 DI 0 0 1 0 ••• X X TCZ TSV 6 DON'T CARE BITS DO TRI-STATE TRI-STATE BUSY READY TEC PRE = 0 FIGURE 2-9: Guarantee at VCC = 4.5V to 6.0V Protect Register must be cleared PRREAD TIMING PRE T CSL CS CLK DI 1 1 0 X ••• X 8 DON'T CARE BITS 0 DO • Address bit A7 is a "don't care" for 93LCS56. DS11181D-page 8 A7 A6 ••• A0 •X• PE = X Preliminary 1996 Microchip Technology Inc. 93LCS56/66 FIGURE 2-10: PREN TIMING PRE PE CS TCSL CLK 1 DI 0 0 1 1 X DO = TRI-STATE A EWEN cycle must precede a PREN cycle. ••• X 6 DON'T CARE BITS FIGURE 2-11: PRCLEAR TIMING PRE PE TCSL CS CLK 1 DI 1 1 1 ••• 1 1 1 1 8 BITS OF "1" DO TRI-STATE BUSY READY A PREN cycle must immediately precede a PRCLEAR cycle. TWC FIGURE 2-12: PRWRITE TIMING PRE PE TCSL CS CLK 1 DI 0 1 A7 ••• A0 BUSY DO READY TWC Protect Register MUST be cleared before a PRWRITE cycle. A PREN cycle must immediately precede a PRWRITE cycle. Address bit A7 is a "don't care" for 93LCS56. 1996 Microchip Technology Inc. Preliminary DS11181D-page 9 93LCS56/66 FIGURE 2-13: PRDS TIMING PRE PE TCSL CS CLK DI 1 0 0 0 ••• 0 0 0 0 8 BITS OF "0" READY BUSY DO TWC ONE TIME ONLY instruction. A PREN cycle must immediately precede a PRDS cycle. 3.0 PIN DESCRIPTION 3.1 Chip Select (CS) A HIGH level selects the device. A LOW level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought LOW during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be LOW for 250 ns minimum (TCSL) between consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93LCS56/66. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level) and can be continued anytime with respect to clock HIGH time (TCDD) and clock LOW time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a “Don't Care” if CS is LOW (device deselected). If CS is HIGH, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a start condition the specified number of clock cycles (respectively LOW to HIGH transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and DS11181D-page 10 data bits before an instruction is executed (see instruction set truth table). CLK and DI then become don't care inputs waiting for a new start condition to be detected. Note: 3.3 CS must go LOW between consecutive instructions. Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out is used in the READ and PRREAD mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought HIGH after held LOW for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held LOW or HIGH during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal. 3.5 Program Enable (PE) This pin should be held HIGH in the programming mode or when executing the Protect Register programming instructions. 3.6 Protect Register Enable (PRE) This pin should be held HIGH when executing all Protect Register instructions. Otherwise, it must be held LOW for normal operations. Preliminary 1996 Microchip Technology Inc. 93LCS56/66 93LCS56/66 Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 93LCS56/66 – /P Package: Temperature Range: Device: 1996 Microchip Technology Inc. P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead SM = Plastic SOIC (207 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead Blank = 0°C to +70°C I = -40°C to +85°C 93LCS56/66 93LCS56T/66T Preliminary Microwire Serial EEPROM Microwire Serial EEPROM (Tape and Reel) DS11181D-page 11 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972 991-7177 Fax: 972 991-8588 Dayton Microchip Technology Inc. Suite 150 Two Prestige Place Miamisburg, OH 45342 Tel: 513 291-1654 Fax: 513 291-9175 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714 263-1888 Fax: 714 263-1338 New York Microchip Technmgy Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279 Fax: 905 405-6253 China Microchip Technology Unit 406 of Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700 Fax: 011 86 21 6275 5060 Hong Kong Microchip Technology RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 India Microchip Technology No. 6, Legacy, Convent Road Bangalore 560 025 India Tel: 91 80 526 3148 Fax: 91 80 559 9840 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan, R.O.C Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139 United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 9/3/96 All rights reserved. 1996, Microchip Technology Incorporated, USA. 4/96 Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use, or otherwise. Use of Microchip’s products as critical components in medical devices is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the USA and other countries. All rights reserved. All other trademarks mentioned herein are the property of their DS11181D-page 12 Preliminary 1996 Microchip Technology Inc.