FREESCALE 68HC05SB7

HC05SB7GRS/H
REV 2.1
68HC05SB7
68HC705SB7
SPECIFICATION
(General Release)
August 27, 1998
Consumer Systems Group
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
 Motorola, Inc., 1998
August 27, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 1
GENERAL DESCRIPTION
1.1
FEATURES ...................................................................................................... 1-1
1.2
MASK OPTION ................................................................................................ 1-2
1.3
PEPROM FACTORY PREPROGRAMMED OPTIONS ................................... 1-2
1.4
MCU STRUCTURE.......................................................................................... 1-2
1.5
PIN ASSIGNMENTS ........................................................................................ 1-4
1.6
FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4
1.6.1
VDD, VSS .................................................................................................... 1-4
1.6.2
OSC1, OSC2 ............................................................................................... 1-4
1.6.3
IRQ/VPP ...................................................................................................... 1-5
1.6.4
RESET......................................................................................................... 1-6
1.6.5
CSA ............................................................................................................. 1-6
1.6.6
TM................................................................................................................ 1-6
1.6.7
VM ............................................................................................................... 1-6
1.6.8
CAP (ADC) .................................................................................................. 1-6
1.6.9
ESV.............................................................................................................. 1-7
1.6.10 PA0-PA7 / PWM0-PWM3, SCL0-SCL1, SDA0-SDA1 ................................. 1-7
1.6.11 PB1-PB7 / TCAP, CS0-CS1, AN0-AN3 ....................................................... 1-7
1.6.12 PC4-PC7...................................................................................................... 1-7
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
2.5
MEMORY MAP ................................................................................................ 2-1
INPUT/OUTPUT SECTION.............................................................................. 2-2
INTERRUPT VECTOR MAPPING ................................................................... 2-6
ROM................................................................................................................. 2-6
RAM ................................................................................................................. 2-6
SECTION 3
CENTRAL PROCESSING UNIT
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
REGISTERS .................................................................................................... 3-1
ACCUMULATOR (A)........................................................................................ 3-2
INDEX REGISTER (X) ..................................................................................... 3-2
STACK POINTER (SP) .................................................................................... 3-2
PROGRAM COUNTER (PC) ........................................................................... 3-2
CONDITION CODE REGISTER (CCR) ........................................................... 3-3
Half Carry Bit (H-Bit) .................................................................................... 3-3
Interrupt Mask (I-Bit) .................................................................................... 3-3
Negative Bit (N-Bit) ...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-3
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
MC68HC05SB7
REV 2.1
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
TABLE OF CONTENTS
Section
Page
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.6.3
4.7
4.8
4.8.1
4.8.2
4.9
INTERRUPT VECTORS .................................................................................. 4-1
INTERRUPT PROCESSING............................................................................ 4-2
SOFTWARE INTERRUPT ............................................................................... 4-4
EXTERNAL INTERRUPT................................................................................. 4-4
IRQ/VPP Pin ................................................................................................ 4-4
IRQ Status and Control Register (ISCR) ..................................................... 4-5
CORE TIMER INTERRUPTS........................................................................... 4-6
Core Timer Overflow Interrupt ..................................................................... 4-7
Real-Time Interrupt...................................................................................... 4-7
PROGRAMMABLE TIMER INTERRUPTS ...................................................... 4-7
Input Capture Interrupt................................................................................. 4-7
Output Compare Interrupt............................................................................ 4-7
Timer Overflow Interrupt .............................................................................. 4-7
SM-BUS INTERRUPT...................................................................................... 4-8
ANALOG INTERRUPTS .................................................................................. 4-8
Comparator Input Match Interrupt................................................................ 4-8
Input Capture Interrupt................................................................................. 4-8
CURRENT DETECT INTERRUPT................................................................... 4-8
SECTION 5
RESETS
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
POWER-ON RESET ........................................................................................ 5-2
EXTERNAL RESET ......................................................................................... 5-2
INTERNAL RESETS ........................................................................................ 5-2
Power-On Reset (POR) ............................................................................... 5-2
Computer Operating Properly (COP) Reset ................................................ 5-3
Low Voltage Reset (LVR) ............................................................................ 5-4
Illegal Address Reset................................................................................... 5-4
RESET STATES .............................................................................................. 5-4
CPU ............................................................................................................. 5-4
I/O Registers................................................................................................ 5-4
Core Timer................................................................................................... 5-5
COP Watchdog............................................................................................ 5-5
16-Bit Programmable Timer......................................................................... 5-5
SM-Bus Serial Interface............................................................................... 5-5
Analog Subsystem....................................................................................... 5-6
SECTION 6
LOW POWER MODES
6.1
6.2
STOP MODE.................................................................................................... 6-3
WAIT MODE .................................................................................................... 6-4
MOTOROLA
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MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
6.3
6.4
Page
DATA-RETENTION MODE.............................................................................. 6-4
SLOW MODE................................................................................................... 6-5
SECTION 7
INPUT/OUTPUT PORTS
7.1
7.1.1
7.1.2
7.2
7.3
7.4
PARALLEL PORTS.......................................................................................... 7-1
Port Data Registers ..................................................................................... 7-2
Port Data Direction Registers ...................................................................... 7-2
PORT A............................................................................................................ 7-2
PORT B............................................................................................................ 7-2
PORT C............................................................................................................ 7-2
SECTION 8
SYSTEM CLOCK
8.1
CLOCK SOURCES .......................................................................................... 8-1
8.2
VCO CLOCK SPEED....................................................................................... 8-2
8.2.1
VCO Slow Mode .......................................................................................... 8-2
8.2.2
Setting the VCO Speed ............................................................................... 8-3
SECTION 9
CORE TIMER
9.1
9.2
9.3
9.4
9.5
CORE TIMER STATUS AND CONTROL REGISTER..................................... 9-2
CORE TIMER COUNTER REGISTER (CTCR) ............................................... 9-3
COP WATCHDOG ........................................................................................... 9-4
CORE TIMER DURING WAIT MODE.............................................................. 9-5
CORE TIMER DURING STOP MODE............................................................. 9-5
SECTION 10
16-BIT TIMER
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
TIMER REGISTERS (TMRH, TMRL)............................................................. 10-2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) ................................ 10-4
INPUT CAPTURE REGISTERS .................................................................... 10-5
OUTPUT COMPARE REGISTERS ............................................................... 10-7
TIMER CONTROL REGISTER (TCR) ........................................................... 10-9
TIMER STATUS REGISTER (TSR)............................................................. 10-10
TIMER OPERATION DURING WAIT MODE............................................... 10-11
TIMER OPERATION DURING STOP MODE .............................................. 10-11
SECTION 11
PULSE WIDTH MODULATOR
11.1
11.2
11.3
11.4
D/A DATA REGISTERS (DAC0-DAC3) ......................................................... 11-2
MUX CHANNEL ENABLE REGISTER (MCER) ............................................ 11-3
PWM DURING WAIT MODE ......................................................................... 11-4
PWM DURING STOP MODE......................................................................... 11-4
MC68HC05SB7
REV 2.1
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GENERAL RELEASE SPECIFICATION
August 27, 1998
TABLE OF CONTENTS
Section
Page
SECTION 12
SM-BUS
12.1 SM-BUS INTRODUCTION............................................................................. 12-1
12.2 SM-BUS INTERFACE FEATURES................................................................ 12-1
12.3 SM-BUS SYSTEM CONFIGURATION .......................................................... 12-2
12.4 SM-BUS PROTOCOL .................................................................................... 12-2
12.4.1 START Signal ............................................................................................ 12-3
12.4.2 Slave Address Transmission ..................................................................... 12-3
12.4.3 Data Transfer............................................................................................. 12-3
12.4.4 Repeated START Signal ........................................................................... 12-4
12.4.5 STOP Signal .............................................................................................. 12-4
12.4.6 Arbitration Procedure................................................................................. 12-4
12.4.7 Clock Synchronization ............................................................................... 12-5
12.4.8 Handshaking.............................................................................................. 12-5
12.5 SM-BUS REGISTERS ................................................................................... 12-5
12.5.1 SM-Bus Address Register (SMADR) ......................................................... 12-6
12.5.2 SM-Bus Frequency Divider Register (SMFDR) ......................................... 12-6
12.5.3 SM-Bus Control Register (SMCR) ............................................................. 12-7
12.5.4 SM-Bus Status Register (SMSR)............................................................... 12-8
12.5.5 SM-Bus Data I/O Register (SMDR) ......................................................... 12-10
12.5.6 SM-Bus logic Level .................................................................................. 12-10
12.5.7 SCL as16-bit Timer Input Capture ........................................................... 12-10
12.6 PROGRAMMING CONSIDERATIONS........................................................ 12-11
12.6.1 Initialization .............................................................................................. 12-11
12.6.2 Generation of a START Signal and the First Byte of Data Transfer ........ 12-11
12.6.3 Software Responses after Transmission or Reception of a Byte ............ 12-11
12.6.4 Generation of the STOP Signal ............................................................... 12-13
12.6.5 Generation of a Repeated START Signal................................................ 12-14
12.6.6 Slave Mode.............................................................................................. 12-14
12.6.7 Arbitration Lost......................................................................................... 12-14
12.7 OPERATION DURING WAIT MODE ........................................................... 12-14
12.8 OPERATION DURING STOP MODE .......................................................... 12-14
SECTION 13
CURRENT SENSE AMPLIFIER
13.1
13.2
13.3
13.4
13.5
CURRENT SENSE AMPLIFIER APPLICATION............................................ 13-1
CURRENT SENSE INTERRUPT................................................................... 13-2
CSA STATUS AND CONTROL REGISTER (CSSCR) .................................. 13-2
CSA OPERATION DURING WAIT MODE..................................................... 13-4
CSA OPERATION DURING STOP MODE.................................................... 13-4
MOTOROLA
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MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 14
TEMPERATURE SENSOR
14.1
14.2
14.3
14.4
INTERNAL TEMPERATURE SENSOR ......................................................... 14-1
EXTERNAL TEMPERATURE SENSOR........................................................ 14-2
TEMPERATURE SENSOR OPERATION DURING WAIT MODE................. 14-2
TEMPERATURE SENSOR OPERATION DURING STOP MODE................ 14-2
SECTION 15
ANALOG SUBSYSTEM
15.1 ANALOG MULTIPLEX REGISTERS ............................................................. 15-3
15.2 ANALOG CONTROL REGISTER ................................................................ 15-14
15.3 ANALOG STATUS REGISTER.................................................................... 15-17
15.4 A/D CONVERSION METHODS ................................................................... 15-19
15.5 VOLTAGE MEASUREMENT METHODS .................................................... 15-27
15.5.1 Absolute Voltage Readings ..................................................................... 15-27
15.5.2 Ratiometric Voltage Readings ................................................................. 15-28
15.6 VOLTAGE COMPARATOR FEATURES ..................................................... 15-29
15.7 CURRENT SOURCE FEATURES ............................................................... 15-30
15.8 SAMPLE AND HOLD ................................................................................... 15-30
15.9 PORT B INTERACTION WITH ANALOG INPUTS ...................................... 15-30
15.9.1 Port B Pins As Inputs............................................................................... 15-31
15.10 NOISE SENSITIVITY ............................................................................................................ 15-31
SECTION 16
PERSONALITY EPROM
16.1 PEPROM REGISTERS.................................................................................. 16-2
16.1.1 PEPROM Bit Select Register (PEBSR) ..................................................... 16-2
16.1.2 PEPROM Status and Control Register (PESCR) ...................................... 16-2
16.2 PEPROM PROGRAMMING........................................................................... 16-3
16.3 PEPROM READING ...................................................................................... 16-4
16.4 PEPROM ERASING ...................................................................................... 16-4
16.5 PEPROM PREPROGRAMMED OPTIONS ................................................... 16-5
16.5.1 Data Format in Preprogrammed PEPROM ............................................... 16-5
SECTION 17
INSTRUCTION SET
17.1 ADDRESSING MODES ................................................................................. 17-1
17.1.1 Inherent...................................................................................................... 17-1
17.1.2 Immediate .................................................................................................. 17-1
17.1.3 Direct ......................................................................................................... 17-2
17.1.4 Extended.................................................................................................... 17-2
17.1.5 Indexed, No Offset..................................................................................... 17-2
17.1.6 Indexed, 8-Bit Offset .................................................................................. 17-2
MC68HC05SB7
REV 2.1
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
TABLE OF CONTENTS
Section
17.1.7
17.1.8
17.1.9
17.1.10
17.1.11
17.1.12
17.1.13
17.1.14
17.1.15
Page
Indexed, 16-Bit Offset ................................................................................ 17-3
Relative...................................................................................................... 17-3
Instruction Types ....................................................................................... 17-3
Register/Memory Instructions .................................................................... 17-4
Read-Modify-Write Instructions ................................................................. 17-5
Jump/Branch Instructions .......................................................................... 17-5
Bit Manipulation Instructions...................................................................... 17-7
Control Instructions.................................................................................... 17-7
Instruction Set Summary ........................................................................... 17-8
SECTION 18
ELECTRICAL SPECIFICATIONS
18.1 MAXIMUM RATINGS..................................................................................... 18-1
18.2 OPERATING TEMPERATURE RANGE ........................................................ 18-1
18.3 THERMAL CHARACTERISTICS ................................................................... 18-1
18.4 SUPPLY CURRENT CHARACTERISTICS ................................................... 18-2
18.5 PEPROM PROGRAMMING CHARACTERISTICS........................................ 18-2
18.6 DC ELECTRICAL CHARACTERISTICS........................................................ 18-3
18.7 ANALOG SUBSYSTEM CHARACTERISTICS .............................................. 18-4
18.8 CONTROL TIMING ........................................................................................ 18-5
18.9 RESET CHARACTERISTICS ........................................................................ 18-6
18.10 SM-BUS DC ELECTRICAL CHARACTERISTICS......................................... 18-8
18.11 SM-BUS CONTROL TIMING ......................................................................... 18-8
18.11.1 SM-Bus Interface Input Signal Timing ....................................................... 18-8
18.11.2 SM-Bus Interface Output Signal Timing .................................................... 18-8
SECTION 19
MECHANICAL SPECIFICATIONS
19.1
19.2
28-PIN SOIC (CASE 751F)............................................................................ 19-1
28-PIN SSOP ................................................................................................. 19-2
APPENDIX A
MC68HC705SB7
A.1
A.2
A.3
A.4
A.5
A.6
A.6.1
A.6.2
A.7
A.8
INTRODUCTION..............................................................................................A-1
MEMORY .........................................................................................................A-1
PERSONALITY EPROM (PEPROM)...............................................................A-2
MASK OPTION REGISTER.............................................................................A-2
BOOTLOADER MODE ....................................................................................A-3
EPROM PROGRAMMING ...............................................................................A-3
EPROM Programming Register (EPROG) ..................................................A-3
Programming Sequence ..............................................................................A-4
EPROM ERASING...........................................................................................A-5
EPROM PROGRAMMING SPECIFICATIONS ................................................A-6
MOTOROLA
vi
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
LIST OF FIGURES
Figure
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
4-1
4-2
4-3
4-4
5-1
5-2
5-3
6-1
6-2
7-1
8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
9-5
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
Title
Page
MC68HC05SB7 Block Diagram ....................................................................... 1-3
MC68HC05SB7 Pin Assignments.................................................................... 1-4
EPO Oscillator Connections............................................................................. 1-5
MC68HC05SB7 Memory Map.......................................................................... 2-1
MC68HC05SB7 I/O Registers.......................................................................... 2-2
MC68HC05SB7 I/O Registers $0000-$000F ................................................... 2-3
MC68HC05SB7 I/O Registers $0010-$001F ................................................... 2-4
MC68HC05SB7 I/O Registers $0020-$002F ................................................... 2-5
COP Register (COPR) ..................................................................................... 2-5
MC68HC05SB7 Interrupt Vector Mapping ....................................................... 2-6
MC68HC05 Programming Model ..................................................................... 3-1
Interrupt Stacking Order................................................................................... 4-2
Interrupt Flow Chart ......................................................................................... 4-3
External Interrupt Logic .................................................................................... 4-5
IRQ Status and Control Register (ISCR).......................................................... 4-5
Reset Sources.................................................................................................. 5-1
COP Watchdog Register (COPR) .................................................................... 5-3
Miscellaneous Control Register (MCR)............................................................ 5-3
STOP and WAIT Flowchart.............................................................................. 6-2
Miscellaneous Control Register (MCR)............................................................ 6-5
Port I/O Circuitry............................................................................................... 7-1
MC68HC05SB7 Input Clock Source ................................................................ 8-1
IRQ Status and Control Register (ISCR).......................................................... 8-2
Miscellaneous Control Register (MCR)............................................................ 8-3
VCO Adjust Register (VAR) ............................................................................. 8-3
Core Timer Block Diagram............................................................................... 9-1
Core Timer Status and Control Register (CTSCR) .......................................... 9-2
Core Timer Counter Register (CTCR).............................................................. 9-3
COP Watchdog Register (COPR) .................................................................... 9-4
Miscellaneous Control Register (MCR)............................................................ 9-4
Programmable Timer Block Diagram ............................................................. 10-1
Programmable Timer Block Diagram ............................................................. 10-2
Programmable Timer Registers (TMRH, TMRL)............................................ 10-3
Alternate Counter Block Diagram................................................................... 10-4
Alternate Counter Registers (ACRH, ACRL).................................................. 10-4
Timer Input Capture Block Diagram............................................................... 10-5
Miscellaneous Control Register (MCR).......................................................... 10-5
Analog Control Register (ACR) ...................................................................... 10-6
Input Capture Registers (ICRH, ICRL)........................................................... 10-6
Timer Output Compare Block Diagram .......................................................... 10-7
Output Compare Registers (OCRH, OCRL) .................................................. 10-8
Timer Control Register (TCR) ........................................................................ 10-9
Timer Status Registers (TSR) ...................................................................... 10-10
MC68HC05SB7
REV 2.1
MOTOROLA
vii
GENERAL RELEASE SPECIFICATION
August 27, 1998
LIST OF FIGURES
Figure
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-10
11-8
11-9
11-11
12-1
12-2
12-3
12-4
12-5
13-1
13-2
13-3
14-1
14-2
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
16-1
16-2
16-3
18-1
18-2
18-3
18-4
A-1
A-2
A-3
A-4
Title
Page
PWM Block Diagram ...................................................................................... 11-1
D/A Data Register 0 (DAC0) (MSB) ............................................................... 11-2
D/A Data Register 0 (DAC0) (LSB) ................................................................ 11-2
D/A Data Register 1 (DAC1) (MSB) ............................................................... 11-2
D/A Data Register 1 (DAC1) (LSB) ................................................................ 11-2
D/A Data Register 2 (DAC2) (MSB) ............................................................... 11-2
D/A Data Register 2 (DAC2) (LSB) ................................................................ 11-2
PWM Output Waveform Examples ................................................................ 11-3
D/A Data Register 3 (DAC3) (MSB) ............................................................... 11-3
D/A Data Register 3 (DAC3) (LSB) ................................................................ 11-3
MUX Channel Enable Register (MCER) ........................................................ 11-4
SM-Bus Interface Block Diagram ................................................................... 12-2
SM-Bus Transmission Signal Diagram .......................................................... 12-3
Clock Synchronization.................................................................................... 12-5
Miscellaneous Control Register (MCR)........................................................ 12-10
Flow-chart of SM-Bus Interrupt Routine....................................................... 12-12
Current Sense Amplifier Block ....................................................................... 13-2
CSA Status and Control Register (CSSCR)................................................... 13-3
Miscellaneous Control Register (MCR).......................................................... 13-4
Miscellaneous Control Register (MCR).......................................................... 14-1
External Temperature Sensor Connection..................................................... 14-2
Analog Subsystem Block Diagram................................................................. 15-2
Analog Multiplex Register 1 (AMUX1)............................................................ 15-3
Analog Multiplex Register 2 (AMUX2)............................................................ 15-3
INV Bit Action ................................................................................................. 15-4
Analog Control Register (ACR) .................................................................... 15-14
Analog Status Register ................................................................................ 15-17
Single-Slope A/D Conversion Method.......................................................... 15-19
A/D Conversion - Full Manual Control (Mode 0) .......................................... 15-23
A/D Conversion - Manual/Auto Discharge Control (Mode 1) ....................... 15-24
A/D Conversion - TOF/ICF Control (Mode 2)............................................... 15-25
A/D Conversion - OCF/ICF Control (Mode 3) .............................................. 15-26
Personality EPROM ....................................................................................... 16-1
PEPROM Bit Select Register (PEBSR) ......................................................... 16-2
PEPROM Status and Control Register (PESCR)........................................... 16-2
Stop Recovery Timing Diagram ..................................................................... 18-6
Internal Reset Timing Diagram ...................................................................... 18-7
Low Voltage Reset Timing Diagram............................................................... 18-7
SM-Bus Timing Diagram ................................................................................ 18-9
MC68HC705SB7 Memory Map........................................................................A-1
MC68HC705SB7 Mask Option Register (MOR ...............................................A-2
EPROM Programming Register (EPROG).......................................................A-3
EPROM Programming Sequence ....................................................................A-5
MOTOROLA
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MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
LIST OF TABLES
Table
4-1
7-1
8-1
9-1
10-1
12-1
13-1
13-2
13-3
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
16-1
16-2
17-1
17-2
17-3
17-4
17-5
17-6
17-7
Title
Page
Reset/Interrupt Vector Addresses .................................................................... 4-1
I/O Pin Functions.............................................................................................. 7-1
Clock Source Selection .................................................................................... 8-2
Core Timer Interrupt Rates and COP Timeout Selection................................. 9-3
16-bit Timer Input Capture Source................................................................. 10-6
SM-Bus Clock Prescaler ................................................................................ 12-6
Voltage Across the Sense Resistor against Current ...................................... 13-1
Current Sense Amplifier Gain Select ............................................................. 13-3
Current Detect Output Select ......................................................................... 13-4
Comparator Input Sources ............................................................................. 15-3
Channel Select Bus Combinations................................................................. 15-6
A/D Conversion Options............................................................................... 15-15
A/D Conversion Signals and Definitions ...................................................... 15-21
Sample Conversion Timing .......................................................................... 15-22
Absolute Voltage Reading Errors................................................................. 15-27
Ratiometric Voltage Reading Errors............................................................. 15-29
Voltage Comparator Setup Conditions......................................................... 15-30
PEPROM Bit Selection................................................................................... 16-3
PEPROM Preprogrammed Option ................................................................. 16-5
Register/Memory Instructions ........................................................................ 17-4
Read-Modify-Write Instructions ..................................................................... 17-5
Jump and Branch Instructions........................................................................ 17-6
Bit Manipulation Instructions .......................................................................... 17-7
Control Instructions ........................................................................................ 17-7
Instruction Set Summary .............................................................................. 17-8
Opcode Map................................................................................................. 17-14
MC68HC05SB7
REV 2.1
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
LIST OF TABLES
Table
MOTOROLA
x
Title
Page
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 1
GENERAL DESCRIPTION
The MC68HC05SB7 HCMOS microcontroller is a member of the M68HC05 family
of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU),
which contains an internal oscillator, CPU, RAM, ROM, personality EPROM, I/O,
16-bit timer, core timer, watchdog system, LVR, SM-Bus, PWM, current sense
amplifier, internal temperature sensor and A/D, is designed specifically for smart
battery applications.
1.1
FEATURES
•
Industry standard 8-bit M68HC05 CPU core
•
Power saving STOP, WAIT, DATA-RETENTION and SLOW modes
•
2.1MHz maximum bus frequency from internal VCO or external pin
oscillator
•
6144 bytes of user ROM with the security feature
•
224 bytes of user RAM (64 bytes for stack)
•
System calibration characteristics by 64-bit Personality EPROM
•
19 bidirectional I/O lines
– 4 shared with SM-Bus
– 4 shared with PWM
– 4 shared with A/D analog channels input
– 2 shared with current detect output
– 1 shared with Timer Input Capture (TCAP)
•
16-bit Programmable Timer with Input Capture/Output Compare (driven
by interrupt)
•
15-stage multi-function Core Timer including 8-bit free-running counter
and 4-stage selectable real-time interrupt generator
•
Built-in current sensing amplifiers with selectable gain of 10 and 30
•
Two voltage comparators which can be combined with the 16-bit Timer
to create an 8-channel, single-slope Analog to Digital Converter
•
Built-in internal temperature sensor from 0°C to 70°C
MC68HC05SB7
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
•
4 channels 10-bit PWM running at a fixed clock rate
•
SM-Bus† serial interface compatible with I2C†† Bus
•
Slow ramp up power supply reset capability via LVR
•
Selectable sensitivity on IRQ interrupt (Edge- and Level-Sensitive or
Edge-Only)
•
SM-Bus, current detect, 16-bit timer, analog subsystem and core timer
interrupts
•
Internal 100kΩ pull-up resistor on RESET
•
Low Voltage Reset (LVR)
•
Illegal Address Reset
•
Computer Operating Properly (COP) Watchdog system
•
Available in 28-pin SSOP
NOTE
A bar over a signal name indicates an active low signal. For example, RESET is
active high and RESET is active low. Any reference to voltage, current, or
frequency specified in the following sections will refer to the nominal values. The
exact values and their tolerance or limits are specified in the Electrical
Specifications section.
1.2
MASK OPTION
A single mask option is available on the MC68HC05SB7.
•
1.3
External oscillator on pins OSC1 and OSC2 (EPO):
[enabled or disabled]
PEPROM FACTORY PREPROGRAMMED OPTIONS
The MC68HC05SB7 is available with a factory preprogrammed PEPROM containing any of the following measured parameters:
1.4
•
The internal VCO minimum frequency: programmed or left blank
•
The internal VCO maximum frequency: programmed or left blank
•
The internal bandgap reference voltage: programmed or left blank
•
The internal temperature sensor voltage at 80°C: programmed or left
blank
MCU STRUCTURE
The block diagram of the MC68HC05SB7 is shown in Figure 1-1.
†SM-Bus
is an Intel bus standard.
††I2C Bus is a Philips bus standard.
MOTOROLA
1-2
GENERAL DESCRIPTION
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
RESET
ILLEGAL ADDR
RESET
WATCHDOG
SYSTEM
CORE TIMER
VDD
LOW VOLTAGE
RESET
OSCILLATOR AND
DIVIDE BY 2
CPU CONTROL
OSC1*
(PB2/CS0)
VDD
ALU
68HC05 CPU
VSS
ESVEN
ACCUM
ESV
CPU REGISOSC2*
(PB3/CS1)
INDEX REG
PROGRAM COUNTER
PA7/SDA1
COND CODE REG 1 1 1 H I N Z C
PA4/SCL0
PA3/PWM3
PA2/PWM2
DATA DIR REG
PA5/SDA0
PORT A REG
PA6/SCL1
PA1/PWM1
PC7
PORT C REG
DATA DIR REG
0 0 0 0 0 0 0 0 1 1 STK PTR
IRQ/VPP
PC6
PC5
PC4
4
SM-BUS SERIAL INTERFACE
16-BIT TIMER
4
10-BIT PWM
PA0/PWM0
SCL
TCAP
PB7/AN0
TCSEL
PB4/AN3
PB3/CS1*
PB2/CS0*
STATIC RAM - 224 BYTES
DATA DIR REG
PB5/AN2
PORT B REG
PB6/AN1
MUX
USER ROM - 6656 BYTES
TCAP
PERSONALITY EPROM - 64 BITS
PB1/TCAP
* Selected by Mask Option
TCMP
AN3:0
CS1:0
4
ICF
TCAP
OCF
CSA
2
CURRENT SENSE
AMPLIFIER
COMPARATOR CONTROL
AND
MULTIPLEXER
+
–
COMP
INTERNAL TEMPERATURE
SENSOR AND BANDGAP REFERENCE
TOF
TM
VM
VDD
CAP
Figure 1-1. MC68HC05SB7 Block Diagram
MC68HC05SB7
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-3
GENERAL RELEASE SPECIFICATION
1.5
August 27, 1998
PIN ASSIGNMENTS
The MC68HC05SB7 is available in 28-pin SSOP package. The pin assignments
are shown in Figure 1-2.
PA7/SDA1
1
28
RESET
PA6/SCL1
2
27
PA5/SDA0
PC7
3
26
PA4/SCL0
PC6
4
25
PA3/PWM3
PC5
5
24
PA2/PWM2
PC4
6
23
PA1/PWM1
IRQ/VPP
7
22
PA0/PWM0
PB1/TCAP
8
21
ESV
PB2/CS0 (OSC1)
9
20
VM
PB3/CS1 (OSC2)
10
19
CSA
PB4/AN3
11
18
TM
PB5/AN2
12
17
CAP(ADC)
PB6/AN1
13
16
VSS
PB7/AN0
14
15
VDD
Figure 1-2. MC68HC05SB7 Pin Assignments
1.6
FUNCTIONAL PIN DESCRIPTION
The following paragraphs give a description of the general function of each pin.
1.6.1 VDD, VSS
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply,
and VSS is ground. The MCU operates from a single power supply.
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, special care should be taken to provide good power supply
bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing
requirements vary, depending on how heavily the MCU pins are loaded.
1.6.2 OSC1, OSC2
When selected by a mask option, the OSC1 and OSC2 pins are the connections
for the external pin oscillator (EPO). The OSC1 and OSC2 pins can accept the following sets of components:
1. A crystal as shown in Figure 1-3(a).
2. A ceramic resonator as shown in Figure 1-3(a).
3. An external clock signal as shown in Figure 1-3(b).
MOTOROLA
1-4
GENERAL DESCRIPTION
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
The frequency, fOSC of the EPO or external clock source is divided by two to produce the internal operating frequency, fOP. or fBUS.
Crystal Oscillator
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values
required to provide maximum stability and reliable start-up. The load capacitance
values used in the oscillator circuit design should include all stray capacitances.
The crystal and components should be mounted as close as possible to the pins
for start-up stabilization and to minimize output distortion.
MCU
OSC1
MCU
OSC2
OSC1
OSC2
2MΩ
Unconnected
External Clock
(a) Crystal or Ceramic Resonator Connections
(b) External Clock Source Connection
Figure 1-3. EPO Oscillator Connections
Ceramic Resonator Oscillator
In cost-sensitive applications, a ceramic resonator can be used in place of the
crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The resonator manufacturer’s recommendations should be followed, as the resonator
parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and
components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion.
External Clock
An external clock from another CMOS-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b). This
configuration is possible regardless of whether the crystal/ceramic resonator or
internal VCO is enabled.
1.6.3 IRQ/VPP
The IRQ/VPP input pin drives the asynchronous IRQ interrupt function of the CPU.
The IRQ interrupt function has a bit to provide either only negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering. If the
MC68HC05SB7
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-5
GENERAL RELEASE SPECIFICATION
August 27, 1998
option is selected to include level-sensitive triggering, the IRQ/VPP input requires
an external resistor to VDD for “wired-OR” operation, if desired. If the IRQ/VPP pin
is not used, it must be tied to the VDD supply. The IRQ/VPP pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. The voltage on this
pin may affect the mode of operation and should not exceed VDD.
The IRQ/VPP pin is also used for programming voltage when programming the
Personality EPROM.
See section on Interrupts for more details.
1.6.4 RESET
The RESET pin can be used as an input to reset the MCU to a known start-up
state by pulling it to the low state. It also functions as an output to indicate that an
internal COP watchdog, illegal address, or low voltage reset has occurred. The
RESET pin contains a pullup device to allow the pin to be left disconnected without an external pullup resistor. The RESET pin also contains a steering diode that,
when the power is removed, will discharge to VDD any charge left on an external
capacitor connected between the RESET pin and VSS. The RESET pin also contains an internal Schmitt trigger to improve its noise immunity as an input.
See section on Resets for more details.
1.6.5 CSA
This pin is the input to the current sense amplifier. Usually one terminal of the current path shunt sensing resistor of 0.01Ω is connected to this input pin. The other
terminal is connected to VSS.
See section on Current Sense Amplifier for more details.
1.6.6 TM
This pin is fed from the output of an external temperature sensor. Usually a thermistor with a resistor forms a voltage divider with the voltage value applied to this
input.
See section on Temperature Sensor for more details.
1.6.7 VM
This pin is the battery voltage input of the voltage measurement circuit.
See section on Temperature Sensor for more details.
1.6.8 CAP (ADC)
This pin is connected to an external ramp capacitor to form the slope voltage converter.
See section on Analog Subsystem for more details.
MOTOROLA
1-6
GENERAL DESCRIPTION
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
1.6.9 ESV
This pin provides a switchable 5mA at VOH (at worst case) to an external
EEPROM. The ESVEN bit in the Miscellaneous Control Register enables/disables
the ESV pin.
BIT 7
MCR
R
$000B
W
reset:
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
U = UNAFFECTED BY RESET
ESVEN — ESV Enable
This read/write bit selects whether ESV is enable or not. Reset clears the
ESVEN bit.
1 = ESV enabled.
0 = ESV disabled.
1.6.10 PA0-PA7 / PWM0-PWM3, SCL0-SCL1, SDA0-SDA1
These eight I/O lines comprise the Port A. The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset.
PA0-PA3 are multiplexed with PWM outputs PWM0-PWM3. PA4-PA7 are multiplexed with the two SM-Bus channels - SCL0, SDA0 and SCL1, SDA1.
1.6.11 PB1-PB7 / TCAP, CS0-CS1, AN0-AN3
Pins PB2/CS0 and PB3/CS1 are only available when selected by a mask option.
These seven I/O lines comprise the Port B. The state of any pin is software programmable and all Port B lines are configured as input during power-on or at
reset.
PB1 is configured as the TCAP input pin for the 16-bit timer after a reset, and is
disabled by setting the ICEN bit in the Analog Control Register ($1D).
PB2 and PB3 (when selected) are multiplexed with CS0 and CS1 respectively,
from the current sense interrupt circuit. See section on Current Sense Amplifier for
more details.
PB4-PB7 are multiplexed with the analog input pins of the A/D converter. See section on Analog Subsystem for more details.
1.6.12 PC4-PC7
These four I/O lines comprise the port C. The state of any pin is software programmable and all port C lines are configured as input during power-on or at reset.
MC68HC05SB7
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-7
GENERAL RELEASE SPECIFICATION
MOTOROLA
1-8
August 27, 1998
GENERAL DESCRIPTION
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 2
MEMORY
This section describes the organization of the MC68HC05SB7 on-chip memory.
2.1
MEMORY MAP
In Normal operating mode, the 48 bytes of I/O, 224 bytes of user RAM and 6144
bytes of user ROM are all active as shown in Figure 2-1. The ROM portion of
memory holds the program instructions, fixed data, user defined vectors, and
interrupt service routines. The RAM portion of memory holds variable data. I/O
registers are memory mapped so that the CPU can access their locations in the
same way that it accesses all other memory locations.
$0000
$002F
$0030
$003F
I/O REGISTERS
48 BYTES
UNIMPLEMENTED
16 BYTES
$0040
USER RAM
224 BYTES
$011F
$0120
$05FF
STACK RAM
64 BYTES
$00C0
$00FF
UNIMPLEMENTED
1248 BYTES
$0600
USER ROM
6144 BYTES
$1DFF
$1E00
$1FEF
$1FF0
$1FFF
INTERNAL TEST ROM
496 BYTES
USER VECTORS
16 BYTES
Figure 2-1. MC68HC05SB7 Memory Map
MC68HC05SB7
REV 2.1
MEMORY
MOTOROLA
2-1
GENERAL RELEASE SPECIFICATION
2.2
August 27, 1998
INPUT/OUTPUT SECTION
The first 48 addresses of the memory space, $0000 – $002F, are the I/O section
as summarized in Figure 2-2. These are the addresses of the I/O control registers, status registers, and data registers. Reading from unimplemented locations
will return unknown states, and writing to unimplemented locations will be ignored.
One I/O register is located outside the 48-byte I/O section which is the computer
operating properly (COP) register, mapped at $1FF0.
The assignment of each control, status, and data bit in the I/O register space from
$0000 through $002F are given in Figure 2-3, Figure 2-4, and Figure 2-5.
Addr.
Register Name
Addr.
Register Name
$0000
Port A Data Register
$0018
Timer Counter Register MSB
$0001
Port B Data Register
$0019
Timer Counter Register LSB
$0002
Port C Data Register
$001A
Alternate Counter Register MSB
$0003
Analog MUX Register 1
$001B
Alternate Counter Register LSB
$0004
Port A Data Direction Register
$001C
Reserved
$0005
Port B Data Direction Register
$001D
Analog Control Register
$0006
Port C Data Direction Register
$001E
Analog Status Register
$0007
Analog MUX Register 2
$001F
Reserved
$0008
Core Timer Status & Control Register
$0020
SM-Bus Address Register
$0009
Core Timer Counter
$0021
SM-Bus Frequency Select Register
$000A
CSA Status/Control Register
$0022
SM-Bus Control Register
$000B
Miscellaneous Control Register
$0023
SM-Bus Status Register
$000C
VCO Adjust Register
$0024
SM-Bus Data Register
$000D
IRQ Status & Control Register
$0025
D/A Register 0 H
$000E
Personality EPROM Bit Select Register
$0026
D/A Register 0 L
$000F
Personality EPROM Status & Control Reg.
$0027
D/A Register 1 H
$0010
Reserved
$0028
D/A Register 1 L
$0011
Reserved
$0029
D/A Register 2 H
$0012
Timer Control Register
$002A
D/A Register 2 L
$0013
Timer Status Register
$002B
D/A Register 3 H
$0014
Input Capture Register MSB
$002C
D/A Register 3 L
$0015
Input Capture Register LSB
$002D
MUX Channel Enable Register
$0016
Output Compare Register MSB
$002E
Reserved
$0017
Output Compare Register LSB
$002F
Reserved
Figure 2-2. MC68HC05SB7 I/O Registers
MOTOROLA
2-2
MEMORY
MC68HC05SB7
REV 2.1
August 27, 1998
ADDR
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
REGISTER
R/W
Port A Data
R
PORTA
W
Port B Data
R
PORTB
W
Port C Data
R
PORTC
W
Analog MUX 1
R
AMUX1
W
Port A Data Direction
R
DDRA
W
Port B Data Direction
R
DDRB
W
Port C Data Direction
R
DDRC
W
Analog MUX 2
R
AMUX2
W
CTimer Status/Ctrl
R
CTSCR
W
CTimer Counter
R
CTCR
W
CSA Status/Control
R
CSASCR
W
Misc Control
R
MCR
W
VCO Adjust
R
VAR
W
IRQ Status/Ctrl
R
ISCR
W
PEPROM Bit Select
R
PEBSR
W
PEPROM Status/Ctrl
R
PESCR
W
GENERAL RELEASE SPECIFICATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PC7
PC6
PC5
PC4
HOLD
DHOLD
INV
VREF
MUX3
MUX2
MUX1
MUX0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3
DDRA2
DDRA1
DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3
DDRB2
DDRB1
0
0
0
0
MUX7
MUX6
MUX5
MUX4
RT1
RT0
TMR1
TMR0
0
CSIF
DDRC7 DDRC6 DDRC5 DDRC4
0
0
IREF
0
0
CTOFR
RTIFR
TMR4
TMR3
TMR2
CSCAL
CDEN
CDIE
SCLK
CSSEL
TCSEL
VA4
VA3
VA2
0
IRQF
0
CTOF
RTIF
CTOFE
RTIE
TMR7
TMR6
TMR5
CSEN
X30
X10
TSEN
LVRON
0
COPON
IRQE
VCOEN
LEVEL
PEB7
PEB7
PEB7
PEDATA
0
PEPGM
unimplemented bits
0
CSIFR
ESVEN SMINLEV
VA1
VA0
0
0
IRQR
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
PEPZRF
reserved bits
Figure 2-3. MC68HC05SB7 I/O Registers $0000-$000F
MC68HC05SB7
REV 2.1
MEMORY
MOTOROLA
2-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
$0010
Reserved
$0011
Reserved
ICIE
OCIE
TOIE
ICF
OCF
TOF
ICRH7
ICRH6
ICRL7
ICRL6
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
R/W
BIT 2
BIT 1
BIT 0
0
0
0
IEDG
OLVL
0
0
0
0
0
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
R
R
W
R
TCR
W
Timer Status
R
TSR
W
Input Capture MSB
R
ICRH
W
Input Capture LSB
R
ICRL
W
Output Compare MSB
R
OCRH
W
Output Compare LSB
R
OCRL
W
Timer Counter MSB
R
TMRH
W
Timer Counter LSB
R
TMRL
W
Alter. Counter MSB
R
ACRH
W
Alter. Counter LSB
R
ACRL
W
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
CHG
ATD2
ATD1
ICEN
CPIE
CPEN
0
0
0
0
R
W
Analog Control
R
ACR
W
Analog Status
R
ASR
W
Reserved
BIT 3
W
Timer Control
Reserved
BIT 4
CPF
ISEN
0
0
CPFR
R
W
unimplemented bits
reserved bits
Figure 2-4. MC68HC05SB7 I/O Registers $0010-$001F
MOTOROLA
2-4
MEMORY
MC68HC05SB7
REV 2.1
August 27, 1998
ADDR
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
REGISTER
R/W
SM-Bus Address
R
SMADR
W
SM-Bus Freq. Sel.
R
SMFDR
W
SM-Bus Control
R
SMCR
W
SM-Bus Status
R
SMSR
W
SM-Bus Data
R
SMDR
W
D/A Register 0
R
DAC0
W
D/A Register 0
R
DAC0
W
D/A Register 1
R
DAC1
W
D/A Register 1
R
DAC1
W
D/A Register 2
R
DAC2
W
D/A Register 2
R
DAC2
W
D/A Register 3
R
DAC3
W
D/A Register 3
R
DAC3
W
MUX Channel Enable
R
MCER
W
$002E
Reserved
$002F
Reserved
BIT 7
BIT 6
BIT 5
GENERAL RELEASE SPECIFICATION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SMAD7 SMAD6 SMAD5 SMAD4 SMAD3 SMAD2 SMAD1
SMEN
SMIEN
SMSTA
SMCF
SMAAS
SMBB
FD4
FD3
FD2
SMTX
TXAK
SMUX
SMAL
SRW
SMAL clr
FD1
FD0
SMIF
RXAK
SMIF clr
SMD7
SMD6
SMD5
SMD4
SMD3
SMD2
SMD1
SMD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
DA1-E
DA0-E
D9
D9
D9
D8
D8
D8
D7
D7
D7
D6
D6
D6
PWM_I
D5
D5
D5
DA3-E
D4
D4
D4
DA2-E
R
W
R
W
unimplemented bits
reserved bits
Figure 2-5. MC68HC05SB7 I/O Registers $0020-$002F
ADDR
$1FF0
REGISTER
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COP Register
R
0
0
0
0
0
0
0
0
COPR
W
COPC
Figure 2-6. COP Register (COPR)
MC68HC05SB7
REV 2.1
MEMORY
MOTOROLA
2-5
GENERAL RELEASE SPECIFICATION
2.3
August 27, 1998
INTERRUPT VECTOR MAPPING
The interrupt vectors are contained in the upper memory addresses above $1FF0
as shown in Figure 2-2.
Addr.
Register Name
$1FF0
CDET INTERRUPT VECTOR (MSB)
$1FF1
CDET INTERRUPT VECTOR (LSB)
$1FF2
ANALOG INTERRUPT VECTOR (MSB)
$1FF3
ANALOG INTERRUPT VECTOR (LSB)
$1FF4
SM-BUS INTERRUPT VECTOR (MSB)
$1FF5
SM-BUS INTERRUPT VECTOR (LSB)
$1FF6
TIMER INTERRUPT VECTOR (MSB)
$1FF7
TIMER INTERRUPT VECTOR (LSB)
$1FF8
CTIMER INTERRUPT VECTOR (MSB)
$1FF9
CTIMER INTERRUPT VECTOR (LSB)
$1FFA
EXTERNAL IRQ VECTOR (MSB)
$1FFB
EXTERNAL IRQ VECTOR (LSB)
$1FFC
SWI VECTOR (MSB)
$1FFD
SWI VECTOR (LSB)
$1FFE
RESET VECTOR (MSB)
$1FFF
RESET VECTOR(LSB)
Figure 2-7. MC68HC05SB7 Interrupt Vector Mapping
2.4
ROM
There are a total of 6160 bytes of ROM on chip. This includes 6144 bytes of user
ROM with locations $0600 through $1DFF for the user program storage and
another 16 bytes for user vectors at locations $1FF0 through $1FFF.
2.5
RAM
The 224 addresses from $0040 to $011F serve as both the user RAM and the
stack RAM. The stack begins at address $00C0 and proceeds down to $00FF.
The stack pointer can access 64 locations from $00C0 to $00FF. Using the stack
area for data storage or temporary work locations requires care to prevent it from
being over written due to stacking from an interrupt or subroutine call. The CPU
uses five RAM bytes to save all CPU register contents before processing an interrupt. During a subroutine call, the CPU uses two bytes to store the return address.
The stack pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines or multiple interrupt levels. The CPU
may overwrite data in the RAM during a subroutine or during the interrupt stacking
operation.
MOTOROLA
2-6
MEMORY
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 3
CENTRAL PROCESSING UNIT
The MC68HC05SB7 has an 8k-bytes memory map. The stack has only 64 bytes.
Therefore, the stack pointer has been reduced to only 6 bits and will only
decrement down to $00C0 and then wrap-around to $00FF. All other instructions
and registers behave as described in this chapter.
3.1
REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are not
part of the memory map. These five registers are shown in Figure 3-1 and are
described in the following paragraphs.
7
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
1
6
5
4
3
2
1
0
ACCUMULATOR
A
INDEX REGISTER
X
1
STACK POINTER
SP
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
PC
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 3-1. MC68HC05 Programming Model
MC68HC05SB7
REV 2.1
CENTRAL PROCESSING UNIT
MOTOROLA
3-1
GENERAL RELEASE SPECIFICATION
3.2
August 27, 1998
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The
CPU uses the accumulator to hold operands and results of arithmetic calculations
or non-arithmetic operations. The accumulator is not affected by a reset of the
device.
3.3
INDEX REGISTER (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
•
Indexed addressing
•
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU finds the operand address by adding the
index register content to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register
content to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporary
storage. The index register is not affected by a reset of the device.
3.4
STACK POINTER (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with
memory space less than 64k-bytes the unimplemented upper address lines are
ignored. The stack pointer contains the address of the next free location on the
stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to $00FF. The stack pointer is then decremented as data is pushed onto the
stack and incremented as data is pulled off the stack.
When accessing memory, the ten most significant bits are permanently set to
0000000011. The six least significant register bits are appended to these ten fixed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the
stack pointer wraps around and overwrites the previously stored information. A
subroutine call occupies two locations on the stack and an interrupt uses five
locations.
3.5
PROGRAM COUNTER (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices
with memory space less than 64k-bytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
MOTOROLA
3-2
CENTRAL PROCESSING UNIT
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REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Normally, the address in the program counter increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
3.6
CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to
indicate the results of the instruction just executed. The fifth bit is the interrupt
mask. These bits can be individually tested by a program, and specific actions can
be taken as a result of their states. The condition code register should be thought
of as having three additional upper bits that are always ones. Only the interrupt
mask is affected by a reset of the device. The following paragraphs explain the
functions of the lower five bits of the condition code register.
3.6.1 Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4
of the accumulator during the last ADD or ADC (add with carry) operation. The
half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.6.2 Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.
Interrupts are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interrupt mask is automatically set after the CPU registers are saved
on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally,
the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its state before the interrupt was encountered. After
any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit
(CLI), or WAIT instructions.
3.6.3 Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often tested flag by assigning the
flag to bit 7 of a register or memory location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
to the state of the flag.
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
MC68HC05SB7
REV 2.1
CENTRAL PROCESSING UNIT
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
3.6.5 Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
MOTOROLA
3-4
CENTRAL PROCESSING UNIT
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
An interrupt temporarily stops normal program execution to process a particular
event. An interrupt does not stop the execution of the instruction in progress, but
takes effect when the current instruction completes its execution. Interrupt processing automatically saves the CPU registers on the stack and loads the program counter with a user-defined vector address.
4.1
INTERRUPT VECTORS
Table 4-1. Reset/Interrupt Vector Addresses
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
—
—
1
$1FFE–$1FFF
—
—
—
Same Priority
As Instruction
$1FFC–$1FFD
IRQ/VPP Pin
—
I Bit
IRQE Bit
2
$1FFA–$1FFB
Core Timer
Interrupts
TOF Bit
RTIF Bit
—
I Bit
TOFE Bit
RTIE Bit
3
$1FF8–$1FF9
Programmable
Timer
Interrupts
ICF Bit
OCF Bit
TOF Bit
—
I Bit
ICIE Bit
OCIE Bit
TOIE Bit
4
$1FF6–$1FF7
SM-Bus
Interrupt
SMIF Bit
—
I Bit
SMIE Bit
5
$1FF4–$1FF5
Analog
Interrupt
CPF1 Bit
CPF2 Bit
—
I Bit
CPIE Bit
6
$1FF2–$1FF3
Current Detect
Interrupt
CIF Bit
—
I Bit
CIE Bit
7
$1FF0–$1FF1
Source
Control
Bit
Power-On Logic
RESET Pin
Low Voltage Reset
Illegal Address Reset
—
COP Watchdog
COPON1
Software
Interrupt (SWI)
User Code
External
Interrupt (IRQ)
Function
Reset
1.
COPON enables the COP watchdog timer
Table 4-1 summarizes the reset and interrupt sources and vector assignments.
MC68HC05SB7
REV 2.1
INTERRUPTS
MOTOROLA
4-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of the
higher priority interrupt first. A higher priority interrupt does not actually interrupt a
lower priority interrupt service routine unless the lower priority interrupt service
routine clears the I bit.
4.2
INTERRUPT PROCESSING
The CPU does the following actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in Figure 4-1.
•
Sets the I bit in the condition code register to prevent further interrupts.
•
Loads the program counter with the contents of the appropriate interrupt
vector locations as shown in Table 4-1.
The return from interrupt (RTI) instruction causes the CPU to recover its register
contents from the stack as shown in Figure 4-1. The sequence of events caused
by an interrupt are shown in the flow chart in Figure 4-2.
$0020
(BOTTOM OF RAM)
$0021
$00BE
$00BF
$00C0
(BOTTOM OF STACK)
$00C1
$00C2
UNSTACKING
ORDER
⇓
CONDITION CODE REGISTER
5
1
n+1
n
ACCUMULATOR
4
2
n+2
INDEX REGISTER
3
3
n+3
PROGRAM COUNTER (HIGH BYTE)
2
4
n+4
PROGRAM COUNTER (LOW BYTE)
1
5
⇑
STACKING
$00FD
ORDER
$00FE
$00FF
TOP OF STACK (RAM)
Figure 4-1. Interrupt Stacking Order
MOTOROLA
4-2
INTERRUPTS
MC68HC05SB7
REV 2.1
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GENERAL RELEASE SPECIFICATION
FROM
RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
NO
CORE TIMER
INTERRUPT?
YES
NO
TIMER
INTERRUPT?
YES
NO
SM-BUS
INTERRUPT?
YES
NO
ANALOG
INTERRUPT?
YES
NO
CDET
INTERRUPT?
YES
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL.
NO
EXECUTE INSTRUCTION.
Figure 4-2. Interrupt Flow Chart
MC68HC05SB7
REV 2.1
INTERRUPTS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
4.3
August 27, 1998
SOFTWARE INTERRUPT
The software interrupt (SWI) instruction causes a nonmaskable interrupt.
4.4
EXTERNAL INTERRUPT
The IRQ/VPP pin is the source that generates external interrupt. Setting the I bit in
the condition code register or clearing the IRQE bit in the interrupt status and control register disables this external interrupt.
4.4.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt request. To
help clean up slow edges, the input from the IRQ/VPP pin is processed by a
Schmitt trigger gate. When the CPU completes its current instruction, it tests the
IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit
is clear and the IRQE bit is set, then the CPU begins the interrupt sequence. The
CPU clears the IRQ latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can recognize
the new interrupt request. Figure 4-3 shows the logic for external interrupts.
NOTE
If the IRQ/VPP pin is not in use, it should be connected to the VDD pin.
The IRQ/VPP pin can be negative edge-triggered only or negative edge- and lowlevel-triggered. External interrupt sensitivity is programmed with the LEVEL bit.
With the edge- and level-sensitive trigger option, a falling edge or a low level on
the IRQ/VPP pin latches an external interrupt request. The edge- and level-sensitive trigger option allows connection to the IRQ/VPP pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ/VPP low, an external
interrupt request is present, and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the IRQ/VPP pin
latches an external interrupt request. A subsequent interrupt request can be
latched only after the voltage level on the IRQ/VPP pin returns to a logic one and
then falls again to logic zero.
MOTOROLA
4-4
INTERRUPTS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
VPP TO
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/VPP
VDD
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
IRQR
IRQF
IRQE
RST
IRQ VECTOR FETCH
LEVEL
R
IRQ STATUS/CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-3. External Interrupt Logic
4.4.2 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4, contains an
external interrupt mask (IRQE), an external interrupt flag (IRQF), and a flag reset
bit (IRQR). Unused bits will read as logic zeros. Reset sets the IRQE bit and
clears all the other bits.
BIT 7
ISCR
R
$000D
reset:
W
BIT 6
BIT 5
IRQE
VCOEN
LEVEL
1
1
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
IRQF
0
0
0
0
0
0
IRQR
0
0
Figure 4-4. IRQ Status and Control Register (ISCR)
MC68HC05SB7
REV 2.1
INTERRUPTS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
IRQE — External Interrupt Request Enable
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt processing enabled.
0 = External interrupt processing disabled.
VCOEN — VCO Enable
Please refer to section on System Clock.
LEVEL — External Interrupt Sensitivity
This bit makes the external interrupt inputs level-triggered as well as edge-triggered.
1 = IRQ/VPP pin negative edge-triggered and low level-triggered.
0 = IRQ/VPP pin negative edge-triggered only.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external interrupt
request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending.
0 = No interrupt request pending.
The following condition set the IRQ flag:
•
An external interrupt signal on the IRQ/VPP pin.
The following conditions clear the IRQ flag:
•
When the CPU fetches the interrupt vector.
•
When a logic “1” is written to the IRQR bit.
IRQR — Interrupt Request Reset
This write-only bit clears the IRQF flag bit and prevents redundant execution of
interrupt routines. Writing a logic one to IRQR clears the IRQF. Writing a logic
zero to IRQR has no effect. IRQR always reads as a logic zero. Reset has no
affect on IRQR.
1 = Clear IRQF flag bit.
0 = No effect.
4.5
CORE TIMER INTERRUPTS
The Core Timer can generate the following interrupts:
•
Timer overflow interrupt.
•
Real-time interrupt.
Setting the I bit in the condition code register disables Core Timer interrupts. The
controls and flags for these interrupts are in the Core Timer status and control register (CTSCR) located at $0008.
MOTOROLA
4-6
INTERRUPTS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
4.5.1 Core Timer Overflow Interrupt
An overflow interrupt request occurs if the Core Timer overflow flag (TOF)
becomes set while the Core Timer overflow interrupt enable bit (TOFE) is also set.
The TOF flag bit can be reset by writing a logical one to the CTOFR bit in the
CTSCR or by a reset of the device.
4.5.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag (RTIF) becomes
set while the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can
be reset by writing a logical one to the RTIFR bit in the CTSCR or by a reset of the
device.
4.6
PROGRAMMABLE TIMER INTERRUPTS
The 16-bit programmable Timer can generate an interrupt whenever the following
events occur:
•
Input capture.
•
Output compare.
•
Timer counter overflow.
Setting the I bit in the condition code register disables Timer interrupts. The controls for these interrupts are in the Timer control register (TCR) located at $0012
and in the status bits are in the Timer status register (TSR) located at $0013.
4.6.1 Input Capture Interrupt
An input capture interrupt occurs if the input capture flag (ICF) becomes set while
the input capture interrupt enable bit (ICIE) is also set. The ICF flag bit is in the
TSR; and the ICIE enable bit is located in the TCR. The ICF flag bit is cleared by a
read of the TSR with the ICF flag bit is set; and then followed by a read of the LSB
of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected
by reset.
4.6.2 Output Compare Interrupt
An output compare interrupt occurs if the output compare flag (OCF) becomes set
while the output compare interrupt enable bit (OCIE) is also set. The OCF flag bit
is in the TSR and the OCIE enable bit is in the TCR. The OCF flag bit is cleared by
a read of the TSR with the OCF flag bit set; and then followed by an access to the
LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is
unaffected by reset.
4.6.3 Timer Overflow Interrupt
A Timer overflow interrupt occurs if the Timer overflow flag (TOF) becomes set
while the Timer overflow interrupt enable bit (TOIE) is also set. The TOF flag bit is
in the TSR and the TOIE enable bit is in the TCR. The TOF flag bit is cleared by a
MC68HC05SB7
REV 2.1
INTERRUPTS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
read of the TSR with the TOF flag bit set; and then followed by an access to the
LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected
by reset.
4.7
SM-BUS INTERRUPT
There is one SM-Bus interrupt flag that causes SM-Bus interrupt whenever it is
set and enabled. The interrupt flags is in the SM-Bus Status Register (SMSR) and
the enable bit is in SM-Bus Control Register (SMCR). SM-Bus interrupt can wake
up MCU from WAIT mode.
4.8
ANALOG INTERRUPTS
The analog subsystem can generate the following interrupts:
•
Voltage on positive input of comparator is greater than the voltage on the
negative input of comparator.
•
Trigger of the input capture interrupt from the programmable Timer as
described in Section 4.6 above.
Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these interrupts are in the analog subsystem control register (ACR) located at $001D and the status bits are in the analog subsystem status
register (ASR) located at $001E.
4.8.1 Comparator Input Match Interrupt
A comparator input match interrupt occurs if the compare flag bit (CPF) in the
ASR becomes set while the comparator interrupt enable bit (CPIE) in the ACR is
also set. Reset clears these bits.
4.8.2 Input Capture Interrupt
The analog subsystem can also generate an input capture interrupt through the
programmable Timer. The input capture can be triggered when there is a match in
the input conditions for the voltage comparator. If comparator sets the CPF flag bit
in the ASR and the input capture enable (ICEN) in the ACR is set then an input
capture will be performed by the programmable Timer. If the ICIE enable bit in the
TCR is also set then an input compare interrupt will occur. Reset clears these bits.
NOTE
In order for the analog subsystem to generate an interrupt using the input capture
function of the programmable Timer the ICEN enable bit in the ACR and the ICIE
enable bit in the TCR must both be set.
4.9
CURRENT DETECT INTERRUPT
The Current Sense Amplifier circuit can be configured to generate an interrupt
once it detects a current passing through the current sensing resistor.
MOTOROLA
4-8
INTERRUPTS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 5
RESETS
This section describes the five reset sources and how they initialize the MCU. A
reset immediately stops the operation of the instruction being executed, initializes
certain control bits, and loads the program counter with a user defined reset vector address. The following conditions produce a reset:
•
Initial power up of device (power on reset).
•
A logic zero applied to the RESET pin (external reset).
•
Timeout of the COP watchdog (COP reset).
•
Low voltage applied to the device (LVR reset).
•
Fetch of an opcode from an address not in the memory map (illegal
address reset).
Figure 5-1 shows a block diagram of the reset sources and their interaction.
COPON
LVREN
MCU INTERNAL REGISTER
COP WATCHDOG
LOW VOLTAGE RESET
VDD
POWER-ON RESET
ILLEGAL ADDRESS RESET
VDD
INTERNAL
ADDRESS BUS
100KΩ
S
RST
D
RESET
LATCH
RESET
TO CPU
AND
SUBSYSTEMS
R
3-CYCLE
CLOCKED
ONE-SHOT
INTERNAL
CLOCK
Figure 5-1. Reset Sources
MC68HC05SB7
REV 2.1
RESETS
MOTOROLA
5-1
GENERAL RELEASE SPECIFICATION
5.1
August 27, 1998
POWER-ON RESET
A positive transition on the VDD pin generates a power-on reset. The power-on
reset is strictly for conditions during powering up and cannot be used to detect
drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows
the clock generator to stabilize. If the RESET pin is at logic zero at the end of the
multiple tCYC time, the MCU remains in the reset condition until the signal on the
RESET pin goes to a logic one.
5.2
EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5tCYC generates an external reset.
This pin is connected to a Schmitt trigger input gate to provide and upper and
lower threshold voltage separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the internal RST signal that resets the CPU and peripherals.
The RESET pin can also act as an open drain output. It will be pulled to a low
state by an internal pulldown device that is activated by three internal reset
sources. This RESET pulldown device will only be asserted for 3 - 4 cycles of the
internal clock, fOP, or as long as the internal reset source is asserted. When the
external RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to VDD, as this may overload some power
supply designs when the internal pulldown on the RESET pin activates.
5.3
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
COP Watchdog timer reset, the low voltage reset, and the illegal address detector.
Only the COP Watchdog timer reset, low voltage reset and illegal address detector will also assert the pulldown device on the RESET pin for the duration of the
reset function or 3 - 4 internal clock cycles, whichever is longer.
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 4064 internal processor bus clock cycles after the oscillator becomes
active.
MOTOROLA
5-2
RESETS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 4064 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must drop
below VPOR in order for the internal POR circuit to detect the next rise of VDD.
5.3.2 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic zero to the COPC bit of the COP register at location $1FF0.
COPR
R
$1FF0
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
0
0
0
0
0
0
0
BIT 0
0
COPC
U
U
U
U
U
U
U
0
U = UNAFFECTED BY RESET
Figure 5-2. COP Watchdog Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = No effect on system.
0 = Reset COP watchdog timer.
The COP Watchdog reset will assert the pulldown device to pull the RESET pin
low for three to four clock cycles of the internal bus clock.
After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic
“1” to the COPON bit in the Miscellaneous Control Register (see Figure 5-2).
Once enabled, the COP watchdog can only be disabled by a POR or reset.
MCR
R
$000B
W
reset:
BIT 7
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 5-3. Miscellaneous Control Register (MCR)
COPON — COP ON
COPON is a write-once bit.
1 = Enables COP watchdog system.
0 = No effect on system.
See section on Core Timer for detail on COP watchdog timeout periods.
MC68HC05SB7
REV 2.1
RESETS
MOTOROLA
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GENERAL RELEASE SPECIFICATION
August 27, 1998
5.3.3 Low Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on
the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown
device to pull the RESET pin low for three to four clock cycles of the internal bus
clock. The Low Voltage Reset circuit is enabled/disabled by the LVRON bit in the
Miscellaneous Control Register (see Figure 5-2).
LVRON — LVR ON
This is a read/write bit to disable/enable the LVR circuit.
0 = Low Voltage Reset circuit disabled.
1 = Low Voltage Reset circuit enabled. This is the default setting at POR
or reset.
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the EPROM (locations $0600 –
$1DFF and $1FF0 - $1FFF) or the RAM (locations $0030 – $010F) generates an
illegal address reset. The illegal address reset will assert the pulldown device to
pull the RESET pin low for 3 - 4 cycles of the internal bus clock.
5.4
RESET STATES
The following paragraphs describe how the various resets initialize the MCU.
5.4.1 CPU
A reset has the following effects on the CPU:
•
Loads the stack pointer with $FF.
•
Sets the I bit in the condition code register, inhibiting interrupts.
•
Loads the program counter with the user defined reset vector from
locations $1FFE and $1FFF.
•
Clears the stop latch, enabling the CPU clock.
•
Clears the wait latch, bringing the CPU out of the wait mode.
5.4.2 I/O Registers
A reset has the following effects on I/O registers:
•
Clears bits in data direction registers configuring pins as inputs:
– DDRA7 – DDRA0 in DDRA for port A.
– DDRB7 – DDRB1 in DDRA for port B.
– DDRC3–DDRC0 in DDRA for port C.
•
Has no effect on port A, B or C data registers.
•
Sets the IRQE bit in the interrupt status and control register.
MOTOROLA
5-4
RESETS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
5.4.3 Core Timer
A reset has the following effects on the Core Timer:
•
Clears the Core Timer counter register (CTCR).
•
Clears the Core Timer interrupt flag and enable bits in the Core Timer
status and control register (CTSCR).
•
Sets the real-time interrupt rate selection bits (RT0, RT1) such that the
device will start with the longest real-time interrupt and COP timeout
delays.
5.4.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
5.4.5 16-Bit Programmable Timer
A reset has the following effects on the 16-bit programmable Timer:
•
Initializes the timer counter registers (TMRH, TMRL) to a value of
$FFFC.
•
Initializes the alternate timer counter registers (ACRH, ACRL) to a value
of $FFFC.
•
Clears all the interrupt enables and the output level bit (OLVL) in the
timer control register (TCR).
•
Does not affect the input capture edge bit (IEDG) in the TCR.
•
Does not affect the interrupt flags in the timer status register (TSR).
•
Does not affect the input capture registers (ICRH, ICRL).
•
Does not affect the output compare registers (OCRH, OCRL).
5.4.6 SM-Bus Serial Interface
A reset has the following effects on the SM-Bus serial interface:
•
Clears all bits in the address register (SMADR) and those
unimplemented bit locations are not affected.
•
Clears all bits in the frequency divider register (SMFDR) and those
unimplemented bit locations are not affected.
•
Clears all bits in control register (SMCR) and those unimplemented bit
locations are not affected.
•
Sets SMCF & RXAK bits and clears other bits and those unimplemented
bit locations are not affected.
•
Does not affect the contents of the data I/O register (SMDR).
MC68HC05SB7
REV 2.1
RESETS
MOTOROLA
5-5
GENERAL RELEASE SPECIFICATION
August 27, 1998
A reset therefore disables the SM-Bus and leaves the shared port A pins as general I/O. Any pending interrupt flag is cleared and the SM-Bus interrupt is disabled. Also the clock rate defaults to the fastest rate.
5.4.7 Analog Subsystem
A reset has the following effects on the analog subsystem:
•
Clears all the bits in the multiplex registers (AMUX1, AMUX2) bits except
the hold switch bit (HOLD) which is set.
•
Clears all the bits in the analog control register (ACR).
•
Clears all the bits in the analog status register (ASR).
A reset therefore connects the negative input of comparator to the channel selection bus, which is switched to VSS. The comparator is set up as non-inverting (a
higher positive voltage on the positive input results in a positive output) and both
are powered down. The current source and discharge device on the CAP pin is
also disabled and powered down. Any analog subsystem interrupt flags are
cleared and the interrupts are disabled.
MOTOROLA
5-6
RESETS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 6
LOW POWER MODES
There are four modes of operation that reduce power consumption:
•
Stop mode
•
Wait mode
•
Data retention mode
•
Slow mode
Figure 6-1 shows the sequence of events in stop and wait modes.
MC68HC05SB7
REV 2.1
LOW POWER MODES
MOTOROLA
6-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
STOP
WAIT
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
KEEP OTHER MODULE
CLOCKS ACTIVE.
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
CLEAR CTOF, RTIF, CTOFE, AND RTIE BITS IN TSCR.
CLEAR ICF, OCF AND TOF BITS IN TSR.
CLEAR ICIE, OCIE and TOIE BITS IN TCR.
DISABLE OSCILLATOR
YES
EXTERNAL
RESET?
NO
EXTERNAL
RESET?
YES
YES
EXTERNAL
INTERRUPT?
NO
NO
EXTERNAL
INTERRUPT?
YES
YES
CORE
TIMER
INTERRUPT?
NO
NO
YES
TURN ON OSCILLATOR.
RESET STABILIZATION DELAY TIMER.
NO
YES
YES
PROG.
TIMER
INTERRUPT?
SM-BUS
INTERRUPT?
NO
END OF
STABILIZATION
DELAY?
YES
NO
ANALOG
INTERRUPT?
NO
YES
TURN ON CPU CLOCK.
CDET
INTERRUPT?
NO
YES
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
COP
RESET?
NO
Figure 6-1. STOP and WAIT Flowchart
MOTOROLA
6-2
LOW POWER MODES
MC68HC05SB7
REV 2.1
August 27, 1998
6.1
GENERAL RELEASE SPECIFICATION
STOP MODE
The STOP instruction puts the MCU in a mode with the lowest power consumption
and has the following affect on the MCU:
•
Turns off the CPU clock and all internal clocks by stopping the internal
oscillator. The stopped clocks turn off the COP watchdog, the Core
Timer, the programmable Timer, the analog subsystem and the SM-Bus
Interface.
•
Removes any pending Core Timer interrupts by clearing the Core Timer
interrupt flags (CTOF, RTIF) in the Core Timer status and control register
(CTSCR).
•
Disables any further Core Timer interrupts by clearing the Core Timer
interrupt enable bits (CTOFE, RTIE) in the CTSCR.
•
Removes any pending programmable Timer interrupts by clearing the
timer interrupt flags (ICF, OCF and TOF) in the timer status register
(TSR).
•
Disables any further programmable Timer interrupts by clearing the
timer interrupt enable bits (ICIE, OCIE and TOIE) in the timer control
register (TCR).
•
Enables external interrupts via the IRQ/VPP pin by setting the IRQE bit in
the IRQ status and control register (ISCR). Enables interrupts in general
by clearing the I bit in the condition code register.
The STOP instruction does not affect any other bits, registers or I/O lines.
The following conditions bring the MCU out of stop mode:
•
An external interrupt signal on the IRQ/VPP pin — A high to low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $1FFA and $1FFB.
•
External reset — A logic zero on the RESET pin resets the MCU and
loads the program counter with the contents of locations $1FFE and
$1FFF.
When the MCU exits stop mode, processing resumes after a stabilization delay of
4064 oscillator cycles.
If an external interrupt brings the MCU out of stop mode after an active edge
occurred on the PC3/TCAP during the stop mode, the ICF flag becomes set. An
external interrupt also latches the value of the timer registers into the input capture registers.
If an external reset brings the MCU out of the stop mode after an active edge
occurred on the PC3/TCAP pin during the stop mode, the ICF flag does not
become set. An external reset has no effect on the input capture registers.
MC68HC05SB7
REV 2.1
LOW POWER MODES
MOTOROLA
6-3
GENERAL RELEASE SPECIFICATION
6.2
August 27, 1998
WAIT MODE
The WAIT instruction puts the MCU in a low power wait mode which consumes
more power than the stop mode. The wait mode and has the following affects on
the MCU:
•
Enables interrupts by clearing the I bit in the condition code register.
•
Enables external interrupts by setting the IRQE bit in the IRQ status and
control register.
•
Stops the CPU clock which drives the address and data buses, but
allows the internal oscillator and its clock to continue to run and drive the
Core Timer, programmable Timer, analog subsystem and SM-Bus.
The WAIT instruction does not affect any other bits, registers or I/O lines.
The following conditions restart the CPU clock and bring the MCU out of the wait
mode:
6.3
•
An external interrupt signal on the IRQ/VPP pin — A high to low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $1FFA and $1FFB.
•
A programmable Timer interrupt — A programmable Timer interrupt
driven by an input capture, output compare or timer overflow loads the
program counter with the contents of locations $1FF6 and $1FF7.
•
An SM-Bus interrupt — An SM-Bus interrupt driven by the completion of
transmitted or received 8-bit data loads the program counter with the
contents of locations $1FF4 and $1FF5.
•
An analog subsystem interrupt — An analog subsystem interrupt driven
by a voltage comparison loads the program counter with the contents of
locations $1FF2 and $1FF3.
•
A Core Timer interrupt — A Core Timer overflow or a real time interrupt
loads the program counter with the contents of locations $1FF0 and
$1FF1.
•
A COP watchdog reset — A timeout of the COP watchdog resets the
MCU and loads the program counter with the contents of locations
$1FFE and $1FFF. Software can enable real time interrupts so that the
MCU can periodically exit the wait mode to reset the COP watchdog.
•
External reset — A logic zero on the RESET pin resets the MCU and
loads the program counter with the contents of locations $1FFE and
$1FFF.
DATA-RETENTION MODE
In the data retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 VDC. The data retention feature allows the
MCU to remain in a low power consumption state during which it retains data, but
the CPU cannot execute instructions.
MOTOROLA
6-4
LOW POWER MODES
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
To put the MCU in the data retention mode:
1. Drive the RESET pin to a logic zero.
2. Lower the VDD voltage. The RESET pin must remain low continuously
during data retention mode.
To take the MCU out of the data retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to a logic one.
6.4
SLOW MODE
The Slow Mode feature permits a slow down of all the internal operations and thus
reduces power consumption. It is particularly useful while going to the WAIT
mode. Slow mode is enabled by setting the SCLK bit in the Miscellaneous Control
Register ($0B).
MCR
R
$000B
W
reset:
BIT 7
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 6-2. Miscellaneous Control Register (MCR)
SCLK — Slow Clock
Setting this bit to one will slow down the internal oscillator. Setting this bit to
zero the system will run at the nominal bus speed (fosc/2). This bit is cleared
during power-on or external reset.
1 = Slow clock selected:
Internal operating frequency, fOP =fBUS =fOSC/1600.
0 = Normal clock selected:
Internal operating frequency, fOP =fBUS =fOSC/2.
MC68HC05SB7
REV 2.1
LOW POWER MODES
MOTOROLA
6-5
GENERAL RELEASE SPECIFICATION
MOTOROLA
6-6
August 27, 1998
LOW POWER MODES
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 7
INPUT/OUTPUT PORTS
In normal operating mode there are 19 bidirectional I/O lines arranged as three I/
O ports (Port A, B and C). The individual bits in these ports are programmable as
either inputs or outputs under software control by the data direction registers
(DDRs). All port I/O pins can sink a current of 5mA when programmed as outputs.
7.1
PARALLEL PORTS
Port A, B and C are bidirectional ports. Each port pin is controlled by the corresponding bits in a data direction register and a data register as shown in Figure 71.
Read/Write DDR
Data Direction
Register Bit
Write Data
Data
Register Bit
I/O
PIN
OUTPUT
Read Data
Reset
(RST)
Internal HC05
Data Bus
Figure 7-1. Port I/O Circuitry
Table 7-1. I/O Pin Functions
R/W
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is read.
MC68HC05SB7
REV 2.1
INPUT/OUTPUT PORTS
MOTOROLA
7-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
7.1.1 Port Data Registers
Each port I/O pin has a corresponding bit in the Port Data Register. When a port I/
O pin is programmed as an output the state of the corresponding data register bit
determines the state of the output pin. All port I/O pins can sink a current of 5mA
when programmed as outputs. When a port pin is programmed as an input, any
read of the Port Data Register will return the logic state of the corresponding I/O
pin.
7.1.2 Port Data Direction Registers
Each port I/O pin may be programmed as an input by clearing the corresponding
bit in the DDR, or programmed as an output by setting the corresponding bit in the
DDR.
NOTE
A “glitch” can be generated on an I/O pin when changing it from an input to an
output unless the data register is first preconditioned to the desired state before
changing the corresponding DDR bit from a “0” to a “1”. Therefore, write data to
the I/O Port Data Register before writing a “1” to the corresponding Data Direction
Register.
7.2
PORT A
Port A is an 8-bit bidirectional port with pins shared with the PWM outputs and
SM-Bus serial I/Os. The Port A Data Register is at address $0000 and the Data
Direction Register is at address $0004.
7.3
PORT B
Port B is a 7-bit birdirectional port with pins shared with A/D converter inputs, current detect outputs, and the 16-bit timer TCAP input. The Port B Data Register is
at address $0001 and the Data Direction Register is at address $0005.
When selected by mask option, port pins PB2 and PB3 becomes OSC1 and
OSC2 respectively.
7.4
PORT C
Port C is a 4-bit bidirectional port. The Port C Data Register is at address $0002
and the Data Direction Register is at address $0006.
MOTOROLA
7-2
INPUT/OUTPUT PORTS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 8
SYSTEM CLOCK
This section describes the system clock options for the MC68HC05SB7.
8.1
CLOCK SOURCES
The internal operating clock of the MC68HC05SB7 is derived from two possible
clock sources:
•
External oscillator input via the OSC1 and OSC2 pins - this is enabled
by a mask option on the MC68HC05SB7.
(On the MC68HC705SB7, the OSCS bit in the Mask Option Register
enables/disables external osc input option.)
•
Internal VCO generated.
VCOEN
SCLK
VA0
VA1
VA2
VA3
VA4
VCO
MUX
÷2
fOP
I/O PORT
OSC1
OSC
OSC2
OSCS
Figure 8-1. MC68HC05SB7 Input Clock Source
MC68HC05SB7
REV 2.1
SYSTEM CLOCK
MOTOROLA
8-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
The clock source is selected by the VCOEN bit in the IRQ Status and Control Register at $0D. Table 8-1 shows a summary of the clock source selection.
ISCR
R
$000D
W
reset:
BIT 7
BIT 6
BIT 5
IRQE
VCOEN
LEVEL
1
1
0
BIT 4
BIT 3
BIT 2
0
IRQF
0
BIT 1
BIT 0
0
0
IRQR
0
0
0
0
0
Figure 8-2. IRQ Status and Control Register (ISCR)
VCOEN — VCO ENable
1 = Internal VCO is used as clock source for the MCU.
This is the default setting after a reset.
0 = External OSC is used as clock source for the MCU. If external OSC
is disabled (mask option or MOR in MC68HC705SB7), the internal
VCO is used as clock source.
After a POR or reset, the internal VCO is selected as the default clock source.
.
Table 8-1. Clock Source Selection
External OSC Enabled
(Mask Option)
Disabled
(OSCS=0 in MC68HC705SB7)
Enabled
(OSCS=1 in MC68HC705SB7)
Enabled
(OSCS=1 in MC68HC705SB7)
Internal VCO Enabled
Clock Source Selected
Don’t care
(VCOEN=X)
Internal
Disabled
(VCOEN=0)
External
Enabled
(VCOEN=1)
Internal
NOTE
The user must ensure that the oscillators are stable (4096 clock cycles minimum)
if switching between internal and external oscillators.
8.2
VCO CLOCK SPEED
8.2.1 VCO Slow Mode
The internal VCO has two operating modes: Normal mode and Slow mode.
In Normal mode, the VCO frequency ranges from 1.5MHz to 5.8MHz.
In Slow mode, the VCO frequency ranges from 500Hz to 4kHz.
This clock speed option is selected by setting the SCLK bit in the Miscellaneous
Register at $0B. The default setting at reset is Normal mode.
MOTOROLA
8-2
SYSTEM CLOCK
MC68HC05SB7
REV 2.1
MCR
R
$000B
W
reset:
BIT 7
BIT 6
TSEN
LVRON
0
1
August 27, 1998
GENERAL RELEASE SPECIFICATION
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
0
COPON
0
U = UNAFFECTED BY RESET
Figure 8-3. Miscellaneous Control Register (MCR)
SCLK — Slow CLocK
1 = Slow clock selected – VCO frequency: 500Hz to 4kHz.
0 = Normal clock selected – VCO frequency: 1.5MHz to 5.8MHz.
NOTE
Due to process variations, operating voltages, and temperature requirements, the
quoted VCO frequencies are typical limits, and should be treated as references
only. It is the user’s responsibility to ensure that the resulting internal operating
frequency meets user’s requirement by setting the appropriate value in the VCO
Adjust Register. See below.
8.2.2 Setting the VCO Speed
The speed of the internal VCO can be adjusted by configuring five bits in the VCO
Adjust Register (VAR) as shown in Figure 8-4. Setting VAR=11111 will select the
VCO minimum frequency, and VAR=00000 will select the maximum frequency.
On reset, VAR=10000, which selects the mid-frequency.
For Normal mode, when VAR=10000, VCO frequency is typically 2kHz.
For Slow mode, when VAR=10000, VCO frequency is typically 3.4MHz.
VAR
R
$000C
W
reset:
BIT 7
BIT 6
BIT 5
0
0
0
0
0
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VA4
VA3
VA2
VA1
VA0
1
0
0
0
0
U = UNAFFECTED BY RESET
Figure 8-4. VCO Adjust Register (VAR)
The VCO minimum and maximum frequencies are available preprogrammed as
two 16-bit values in the Personality EPROM (PEPROM). Bit locations $00 to $0F
holds the minimum value, and $10 to $1F holds the maximum value.
See section on Personality EPROM for further details.
MC68HC05SB7
REV 2.1
SYSTEM CLOCK
MOTOROLA
8-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
8-4
SYSTEM CLOCK
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 9
CORE TIMER
This section describes the operation of the Core Timer and the Computer
Operating Properly (COP) watchdog timer. Figure 9-1 shows a block diagram of
the Core Timer.
RESET
INTERNAL
CLOCK (fOP)
OVERFLOW
$0009
÷2
÷4
CORE TIMER COUNTER REGISTER
BITS 0–7 OF 15-STAGE
RIPPLE (COUNT-UP) COUNTER
OSC1 (fOSC)
fOP ÷1024
RTIFR
RTIE
CTOFR
RTIF
CTOFE
CTOF
INTERNAL DATA BUS
CORE TIMER
INTERRUPT
REQUEST
RESET
RT0
RT1
$0008
CORE TIMER STATUS/CONTROL REGISTER
RTI RATE SELECT
$1FF0
fOP ÷216
fOP ÷215
fOP ÷214
÷2
÷2
÷2
÷2
÷2
÷2
COPC
COP REGISTER
fOP ÷217
÷2
POWER-ON
RESET
÷2
÷2
÷2
÷2
S
Q
COP
WATCHDOG
RESET
R
RESET
Figure 9-1. Core Timer Block Diagram
MC68HC05SB7
REV 2.1
CORE TIMER
MOTOROLA
9-1
GENERAL RELEASE SPECIFICATION
9.1
August 27, 1998
CORE TIMER STATUS AND CONTROL REGISTER
The read/write Core Timer status and control register contains the interrupt flag
bits, interrupt enable bits, interrupt flag bit resets, and the rate selects for the real
time interrupt as shown in Figure 9-2.
CTSCR
R
$0008
W
reset:
BIT 7
BIT 6
CTOF
RTIF
0
0
BIT 5
BIT 4
CTOFE
RTIE
0
0
BIT 3
BIT 2
0
0
CTOFR
RTIFR
0
0
BIT 1
BIT 0
RT1
RT0
1
1
Figure 9-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read only flag becomes set when the first eight stages of the Core Timer
counter roll over from $FF to $00. The CTOF flag bit generates a timer overflow
interrupt request if CTOFE is also set. The CTOF flag bit is cleared by writing a
logic one to the CTOFR bit. Writing to CTOF has no effect. Reset clears CTOF.
1 = Overflow in Core Timer has occurred.
0 = No overflow of Core Timer since CTOF last cleared.
RTIF — Real Time Interrupt Flag
This read only flag becomes set when the selected RTI output becomes active.
RTIF generates a real time interrupt request if RTIE is also set. The RTIF
enable bit is cleared by writing a logic one to the RTIFR bit. Writing to RTIF has
no effect. Reset clears RTIF.
1 = Overflow in real time counter has occurred.
0 = No overflow of real time counter since RTIF last cleared.
CTOFE — Core Timer Overflow Interrupt Enable
This read/write bit enables Core Timer overflow interrupts. Reset clears
CTOFE.
1 = Core Timer overflow interrupts enabled.
0 = Core Timer overflow interrupts disabled.
RTIE — Real-Time Interrupt Enable
This read/write bit enables real time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled.
0 = Real-time interrupts disabled.
CTOFR — Core Timer Overflow Flag Reset
Writing a logic one to this write only bit clears the CTOF bit. CTOFR always
reads as a logic zero. Reset does not affect CTOFR.
1 = Clear CTOF flag bit.
0 = No effect on CTOF flag bit.
MOTOROLA
9-2
CORE TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic one to this write only bit clears the RTIF bit. RTIFR always reads
as a logic zero. Reset does not affect RTIFR.
1 = Clear RTIF flag bit.
0 = No effect on RTIF flag bit.
RT1, RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real time interrupt rates, as shown in
Table 9-1. Because the selected RTI output drives the COP watchdog, changing the real time interrupt rate also changes the counting rate of the COP
watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout period
and real-time interrupt period.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may cause
a real time interrupt request to be missed or an additional real time interrupt
request to be generated. Therefore, the COP timer should be cleared (by writing a
just before changing RT1 and RT0.
Table 9-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow Interrupt
(TOF) Period (fOP ÷ 210)
fOP =
2.1 MHz
RT1
RT0
fOP =
1.0 MHz
488 µs
fOP =
2.1 MHz
fOP =
1.0 MHz
fOP =
2.1 MHz
fOP =
1.0 MHz
fOP ÷ 214
7.81 ms
16.4 ms
54.7 ms
114 ms
1
fOP ÷
215
15.6 ms
32.8 ms
109 ms
229 ms
1
0
fOP ÷
216
31.3 ms
65.5 ms
219 ms
458 ms
1
1
fOP ÷ 217
62.5 ms
131 ms
438 ms
916 ms
0
1024 µs
Minimum COP
Timeout Period
(7 or 8 RTI Periods)
0
0
9.2
RTI Rate
Real-Time Interrupt
(RTI) Period
CORE TIMER COUNTER REGISTER (CTCR)
A 15-stage ripple counter is the basis of the Core Timer. The value of the first eight
stages is readable at any time from the read only timer counter register as shown
in Figure 9-2.
CTCR
R
$0009
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
0
0
0
0
0
0
0
0
Figure 9-3. Core Timer Counter Register (CTCR)
MC68HC05SB7
REV 2.1
CORE TIMER
MOTOROLA
9-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
Power on clears the entire counter chain and begins clocking the counter. After
the startup delay (16 or 4064 internal clock cycles) the power on reset circuit is
released, clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or four cycles
of the internal clock. A timer overflow function at the eighth counter stage allows a
timer interrupt every 1024 internal clock cycles.
9.3
COP WATCHDOG
Four counter stages at the end of the Core Timer make up the computer operating
properly (COP) watchdog. The COP watchdog timeout period is shown in Table 91.
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic “0” to the COPC bit of the COP register at location $1FF0.
COPR
R
$1FF0
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
COPC
0
U = UNAFFECTED BY RESET
Figure 9-4. COP Watchdog Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = No effect on system.
0 = Reset COP watchdog timer.
The COP Watchdog reset will assert the pulldown device to pull the RESET pin
low for three to four clock cycles of the internal bus clock.
After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic
“1” to the COPON bit in the Miscellaneous Control Register (see Figure 9-5).
Once enabled, the COP watchdog can only be disabled by a POR or reset.
BIT 7
MCR
R
$000B
W
reset:
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 9-5. Miscellaneous Control Register (MCR)
MOTOROLA
9-4
CORE TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
COPON — COP ON
COPON is a write-once bit.
1 = Enables COP watchdog system.
0 = No effect on system.
NOTE
If the voltage on the IRQ/VPP pin exceeds 2 × VDD, the COP watchdog is disabled,
and remains disabled until the IRQ/VPP voltage falls below 2 × VDD.
9.4
CORE TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
9.5
CORE TIMER DURING STOP MODE
The Core Timer is cleared when going into STOP mode. When STOP is exited by
an external interrupt or an external RESET, the internal oscillator will resume, followed by 4064 cycles internal processor stabilization delay. The timer is then
cleared and operation resumes.
MC68HC05SB7
REV 2.1
CORE TIMER
MOTOROLA
9-5
GENERAL RELEASE SPECIFICATION
MOTOROLA
9-6
August 27, 1998
CORE TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 10
16-BIT TIMER
The MC68HC05SB7 MCU contains a 16-bit programmable Timer with an Input
Capture function and an Output Compare function. Figure 10-1 shows a block
diagram of the 16-bit programmable timer.
PB1
TCAP
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
ICF
INPUT
SELECT
MUX
TMRH ($0018) TMRL ($0019)
IEDG
SCL
OF
SMBUS
CPF
FLAG
BIT
(from
analog
subsystem)
ACRH ($001A) ACRL ($001B)
÷4
16-BIT COUNTER
OVERFLOW (TOF)
16-BIT COMPARATOR
D Q
OCRH ($0016) OCRL ($0017)
TCMP
C
OCF
TCSEL
(bit 2 of $0B)
INTERNAL
CLOCK
(fOSC ÷ 2)
OLVL
ICEN
(bit 4 of $1D)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
TOF
OCF
ICF
OLVL
IEDG
TOIE
OCIE
ICIE
RESET
TIMER STATUS REGISTER
$0012
$0013
INTERNAL DATA BUS
Figure 10-1. Programmable Timer Block Diagram
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
The basis of the capture/compare Timer is a 16-bit free-running counter which
increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and
output compare functions provide a means to latch the times at which external
events occur, to measure input waveforms, and to generate output waveforms and
timing delays. Software can read the value in the 16-bit free-running counter at
any time without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the
high byte inhibits that specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4 MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt flags can be read from the timer status register (TSR) located at
$0013.
10.1
TIMER REGISTERS (TMRH, TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 10-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
LATCH
READ
TMRH
READ
RESET
($FFFC)
TMRH ($0018)
READ
TMRL
TMRL ($0019)
TMR LSB
÷4
16-BIT COUNTER
TIMER
INTERRUPT
REQUEST
TOF
TOIE
OVERFLOW (TOF)
INTERNAL
CLOCK
(fOSC ÷ 2)
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 10-2. Programmable Timer Block Diagram
MOTOROLA
10-2
16-BIT TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
The timer registers (TMRH, TMRL) shown in Figure 10-3 are read-only locations
which contain the current high and low bytes of the 16-bit free-running counter.
Writing to the timer registers has no effect. Reset of the device presets the timer
counter to $FFFC.
TMRH
R
$0018
W
reset:
TMRL
R
$0019
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
1
1
1
1
1
1
1
1
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
1
0
0
Figure 10-3. Programmable Timer Registers (TMRH, TMRL)
The TMRL latch is a transparent read of the LSB until the a read of the TMRH
takes place. A read of the TMRH latches the LSB into the TMRL location until the
TMRL is again read. The latched value remains fixed even if multiple reads of the
TMRH take place before the next read of the TMRL. Therefore, when reading the
MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflow
flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if
the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag
bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any
order or any number of times does not have any effect on the 16-bit free-running
counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and TMRL,
set the I bit in the condition code register (CCR) before reading TMRH and clear
the I bit after reading TMRL.
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-3
GENERAL RELEASE SPECIFICATION
10.2
August 27, 1998
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 10-4. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF flag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL
DATA
BUS
LATCH
READ
ACRH
READ
RESET
($FFFC)
READ
ACRL
ACRL ($001B)
TMR LSB
ACRH ($001A)
INTERNAL
CLOCK
(fOSC ÷ 2)
÷4
16-BIT COUNTER
Figure 10-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in Figure 10-5 are readonly locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
ACRH
R
$001A
W
reset:
ACRL
R
$001B
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
1
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
1
0
0
Figure 10-5. Alternate Counter Registers (ACRH, ACRL)
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains fixed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF flag bit.
MOTOROLA
10-4
16-BIT TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
10.3
INPUT CAPTURE REGISTERS
INTERNAL
DATA
BUS
READ
ICRH
INPUT
SELECT
MUX
IEDG
SCL
CPF
OF
FLAG
SMBUS BIT
EDGE
SELECT
& DETECT
LOGIC
LATCH
ICRH ($0014)
ICRL ($0015)
READ
ICRL
INTERNAL
CLOCK
(fOSC ÷ 2)
÷4
16-BIT COUNTER
($FFFC)
PB1
TCAP
INPUT CAPTURE (ICF)
TIMER
INTERRUPT
REQUEST
RESET
ICF
ICIE
ICEN
(bit 4 of $1D)
IEDG
TCSEL
(bit 2 of $0B)
TIMER STATUS REG.
TIMER CONTROL REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 10-6. Timer Input Capture Block Diagram
The input capture function is a means to record the time at which an event occurs.
The source of the event can be selected from the following:
•
External input via the PB1 pin
•
CPF flag from the voltage comparator in the analog subsystem
•
SCL signal from the SMBUS
The input capture source is selected by the TCSEL and ICEN bits.
MCR
R
$000B
W
reset:
BIT 7
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
Figure 10-7. Miscellaneous Control Register (MCR)
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-5
GENERAL RELEASE SPECIFICATION
ACR
R
$001D
W
reset:
August 27, 1998
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
CHG
ATD2
ATD1
ICEN
CPIE
CPEN
0
0
0
0
0
0
BIT 1
BIT 0
ISEN
0
0
Figure 10-8. Analog Control Register (ACR)
Table 10-1. 16-bit Timer Input Capture Source
TCSEL
ICEN
Selected TCAP Source
0
0
External TCAP via PB1
0
1
CPF from Analog Subsystem
1
0
SCL from SMBus
1
1
SCL from SMBus
When the input capture circuitry detects an active edge on the selected source, it
latches the contents of the free-running timer counter registers into the input capture registers as shown in Figure 10-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal.
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 10-9. The input capture edge detector contains a
Schmitt trigger to improve noise immunity. The edge that triggers the counter
transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not affect
the contents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
ICRH
R
$0014
R
$0015
reset:
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
U
U
U
U
U
U
U
U
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
U
U
U
U
U
U
U
U
W
reset:
ICRL
BIT 7
ICRH7
W
U = UNAFFECTED BY RESET
Figure 10-9. Input Capture Registers (ICRH, ICRL)
MOTOROLA
10-6
16-BIT TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does
not inhibit transfer of the free-running counter. There is no conflict between reading the ICRL and transfers from the free-running timer counters. The input capture
registers always contain the free-running timer counter value which corresponds
to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and ICRL, set
the I bit in the condition code register (CCR) before reading ICRH and clear the I
bit after reading ICRL.
10.4
OUTPUT COMPARE REGISTERS
R/W
OCRH
OCRH ($0016)
R/W
OCRL
OCRL ($0017)
EDGE
SELECT
DETECT
LOGIC
OLVL
16-BIT COMPARATOR
($FFFC)
÷4
16-BIT COUNTER
RESET
TIMER CONTROL REG.
INTERNAL
CLOCK
(fOSC ÷ 2)
TIMER
INTERRUPT
REQUEST
OCF
OLVL
OCIE
OUTPUT COMPARE
(OCF)
TCMP
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 10-10. Timer Output Compare Block Diagram
The Output Compare function is a means of generating an output signal when the
16-bit timer counter reaches a selected value as shown in Figure 10-10. Software
writes the selected value into the output compare registers. On every fourth internal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the timer transfers the output
level (OLVL) from the timer control register (TCR) to the TCMP.
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-7
GENERAL RELEASE SPECIFICATION
August 27, 1998
Software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of
specific frequency and duty cycle on the TCMP.
The planned action on the TCMP depends on the value stored in the OLVL bit in
the TCR, and it occurs when the value of the 16-bit free-running timer counter
matches the value in the output compare registers shown in Figure 10-3. These
registers are read/write bits and are unaffected by reset.
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare flag bit (OCF). The output compare OLVL state will be clocked
to its output latch regardless of the state of the OCF.
OCRH
R
$0016
W
reset:
OCRL
R
$0017
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
U
U
U
U
U
U
U
U
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
U
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 10-11. Output Compare Registers (OCRH, OCRL)
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
clears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown below.
9B
...
...
B7
B6
BF
...
...
9A
MOTOROLA
10-8
16
13
17
SEI
...
...
STA
LDA
STX
...
...
CLI
OCRH
TSR
OCRL
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
16-BIT TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
10.5
GENERAL RELEASE SPECIFICATION
TIMER CONTROL REGISTER (TCR)
The timer control register is shown in Figure 10-12 performs the following functions:
•
Enables input capture interrupts.
•
Enables output compare interrupts.
•
Enables timer overflow interrupts.
•
Control the active edge polarity of the TCAP signal.
•
Controls the active level of the TCMP output.
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
BIT 7
TCR
R
$0012
W
reset:
BIT 6
BIT 5
ICIE
OCIE
TOIE
0
0
0
BIT 4
BIT 3
BIT 2
0
0
0
0
0
0
BIT 1
BIT 0
IEDG
OLVL
Unaffected
0
Figure 10-12. Timer Control Register (TCR)
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB1/
TCAP pin or from CPF flag bit of the analog subsystem voltage comparator.
Reset clears the ICIE bit.
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the TCMP
pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled.
0 = Output compare interrupts disabled.
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer overflow. Reset clears
the TOIE bit.
1 = Timer overflow interrupts enabled.
0 = Timer overflow interrupts disabled.
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin or the CPF flag bit of voltage comparator in the analog
subsystem triggers a transfer of the contents of the timer register to the input
capture register. Reset has no effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-9
GENERAL RELEASE SPECIFICATION
August 27, 1998
OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT
The state of this read/write bit determines whether a logic one or a logic zero
appears on the TCMP when a successful output compare occurs. Reset clears
the OLVL bit.
1 = TCMP goes high on output compare.
0 = TCMP goes low on output compare.
10.6
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 10-13 contains flags for the following events:
•
An active signal on the PB1/TCAP pin or the CPF flag bit of voltage
comparator in the analog subsystem, transferring the contents of the
timer registers to the input capture registers.
•
A match between the 16-bit counter and the output compare registers,
transferring the OLVL bit to the TCMP.
•
An overflow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the flag bits in the TSR.
TSR
R
$0013
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 10-13. Timer Status Registers (TSR)
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB1/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Reset has no effect on ICF.
OCF - OUTPUT COMPARE FLAG
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Reset has no effect on OCF.
TOF - TIMER OVERFLOW FLAG
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Reset has no effect on TOF.
MOTOROLA
10-10
16-BIT TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
10.7
GENERAL RELEASE SPECIFICATION
TIMER OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the WAIT mode.
10.8
TIMER OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
time the counter resumes from its stopped value as if nothing had happened. If
STOP mode is exited via an external reset (logic low applied to the RESET pin)
the counter is forced to $FFFC.
If a valid input capture edge occurs at the PB1/TCAP pin during the STOP mode
the input capture detect circuitry will be armed. This action does not set any flags
or “wake up” the MCU, but when the MCU does “wake up” there will be an active
input capture flag (and data) from the first valid edge. If the STOP mode is exited
by an external reset, no input capture flag or data will be present even if a valid
input capture edge was detected during the STOP mode.
MC68HC05SB7
REV 2.1
16-BIT TIMER
MOTOROLA
10-11
GENERAL RELEASE SPECIFICATION
MOTOROLA
10-12
August 27, 1998
16-BIT TIMER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 11
PULSE WIDTH MODULATOR
The PWM subsystem contains four 10-bit PWM channels, which can be used as
independent D/A converters. Figure 11-1 shows the block diagram for the Pulse
Width Modulator, with channel 0 in details.
Internal Bus
Channel 0
10-bit Counter
fOP ÷ 2
10-bit D/A 0
Data Register
10-bit D/A 0
Data Register
Buffer
Comparator
D/A 0 Multiplexer
To
Channel 1
To
Channel 2
To
Channel 3
Zero
Detector
S
Latch
PWM0
pin
R
Figure 11-1. PWM Block Diagram
The PWM cycle time is 2048 times the MCU internal processor clock (fOP or fBUS).
Duty cycle of the PWM outputs can be programmed by the corresponding D/A
Data Registers (DAC0-DAC3).
MC68HC05SB7
REV 2.1
PULSE WIDTH MODULATOR
MOTOROLA
11-1
GENERAL RELEASE SPECIFICATION
11.1
August 27, 1998
D/A DATA REGISTERS (DAC0-DAC3)
Each PWM channel is programmed with a 10-bit data, in two 8-bit registers.
DAC0
R
$0025
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
BIT 1
BIT 0
D1
D0
0
0
Figure 11-2. D/A Data Register 0 (DAC0) (MSB)
BIT 7
DAC0
R
$0026
W
reset:
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
Figure 11-3. D/A Data Register 0 (DAC0) (LSB)
DAC1
R
$0027
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
BIT 1
BIT 0
D1
D0
0
0
Figure 11-4. D/A Data Register 1 (DAC1) (MSB)
BIT 7
DAC1
R
$0028
W
reset:
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
Figure 11-5. D/A Data Register 1 (DAC1) (LSB)
DAC2
R
$0029
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
BIT 1
BIT 0
D1
D0
0
0
Figure 11-6. D/A Data Register 2 (DAC2) (MSB)
DAC2
R
$002A
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
0
0
0
0
0
0
Figure 11-7. D/A Data Register 2 (DAC2) (LSB)
MOTOROLA
11-2
PULSE WIDTH MODULATOR
MC68HC05SB7
REV 2.1
DAC3
R
$002B
W
reset:
August 27, 1998
GENERAL RELEASE SPECIFICATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
BIT 1
BIT 0
D1
D0
0
0
Figure 11-8. D/A Data Register 3 (DAC3) (MSB)
DAC3
R
$002C
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
0
0
0
0
0
0
Figure 11-9. D/A Data Register 3 (DAC3) (LSB)
A value of $0000 loaded into these registers results in a continuously low output
on the corresponding PWM output pin. A value of $0200 results in a 50% duty
cycle output, and so on. The maximum value, $03FF corresponds to an output
which is at “1” for 1023/1024 of the cycle.
1024T
$000
1023T
$001
512T
512T
$200
1023T
$3FF
T = 2 x tCYC
Figure 11-10. PWM Output Waveform Examples
A new value written to the a D/A register pair will not be effective until the end of
the current PWM period. This provides a monotonic change of the DC component
of the output without overshoots or vicious starts (a vicious start is an output
which gives totally erroneous PWM during the initial period following an update of
the PWM registers). This feature is achieved by double buffering of the PWM D/A
registers.
11.2
MUX CHANNEL ENABLE REGISTER (MCER)
Since the PWM output pins PWM0-PWM3 are multiplexed with the standard I/O
port pins PA0-PA3 respectively, the MCER is provided to switch between the PWM
and standard I/O function for each pin.
MC68HC05SB7
REV 2.1
PULSE WIDTH MODULATOR
MOTOROLA
11-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
Each PWM channel is enabled by setting the corresponding DAn-E bit in the
MCER, shown in Figure 11-11. With a PWM output enabled, the corresponding
port I/O is tri-stated automatically. Reset clears the four DAn-E bits.
The outputs from four channels PWM system can be inhibited by setting the
PWM_I bit in MCER. This bit can be used as a global pull logic “0” for all the
enabled DA’s line before enter STOP mode. The PWM_I bit is also used to disable
the counter while the PWM is not in use for power saving. Reset clears this bit.
BIT 7
MCER
R
$002D
W
reset:
PWM_I
0
BIT 6
BIT 5
BIT 4
0
0
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
DA3-E
DA2-E
DA1-E
DA0-E
0
0
0
0
Figure 11-11. MUX Channel Enable Register (MCER)
DAn-E — D/A Channel n Enable
1 = PWM output selected for PWMn/PAn pin.
0 = Standard I/O selected for PWMn/PAn pin.
PWM_I — PWM Inhibit
1 = Inhibit all four PWM channels; PWM 10-bit counter also stopped.
0 = PWM channels not inhibited.
11.3
PWM DURING WAIT MODE
In WAIT mode, the oscillator is running even though the MCU clock is not present,
the PWM outputs are not affected. To reduce power consumption in WAIT mode, it
is recommended to disable the PWM.
11.4
PWM DURING STOP MODE
In STOP mode, the oscillator is stopped asynchronously with PWM operation. As
a consequence, the PWM output will remain at the state at the moment when the
oscillator is stopped. The PWM pin’s output depended on the state of PWM_I bit.
If this bit is clear, it might be at its high or low state at that moment, and it remains
at that state until STOP mode is exited. If the PWM_I bit is set, it will be inhibited
the state of PWM output in the process and pin output will be in logic low state.
After STOP mode is exited, the PWM output resumes its unfinished portion of the
stopped cycle if PWM_I bit is clear by software.
MOTOROLA
11-4
PULSE WIDTH MODULATOR
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 12
SM-BUS
12.1
SM-BUS INTRODUCTION
The System Management Bus (SM-Bus) is a two wire, bidirectional serial bus
which provides a simple, efficient way for data exchange between devices.
This bus is suitable for applications which need frequent communications over a
short distance between a number of devices. It also provides a flexibility that
allows additional devices to be connected to the bus. The maximum data rate is
100kbit/s, and the maximum communication distance and number of devices that
can be connected is limited by a maximum bus capacitance of 400pF.
The SM-Bus is a true multi-master bus, including collision detection and arbitration to prevent data corruption if two or more masters intend to control the bus
simultaneously. This feature provides the capability for complex applications with
multi-processor control. It may also be used for rapid testing and alignment of end
products via external connections to an assembly-line computer.
Figure 12-1 shows a block diagram of the SM-Bus interface.
12.2
SM-BUS INTERFACE FEATURES
•
Fully compatible to SM-Bus standard
•
Multi-master operation
•
Software programmable for one of 32 different serial clock frequencies
•
Software selectable acknowledge bit
•
Interrupt driven byte by byte data transfer
•
Arbitration lost driven interrupt with automatic mode switching from
master to slave
•
Calling address identification interrupt
•
Generate/detect the START or STOP signal
•
Repeated START signal generation
•
Generate/recognize the acknowledge bit
•
Bus busy detection
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
Internal bus
8
Control register
Status register
SMEN SMIEN SMSTA SMTX TXAK
SMCF SMAAS SMBB SMAL
SRW SMIF SRXAK
Frequency
divider
register
Address
register
M-Bus
interrupt
Interrupt
Address
comparator
SCL
control
SCL
M-Bus clock
generator
sync logic
START, STOP
detector and
arbitration
START, STOP
generator and
timing sync
TX shift
register
RX shift
register
TX
control
RX
control
SDA
control
SDA
Figure 12-1. SM-Bus Interface Block Diagram
12.3
SM-BUS SYSTEM CONFIGURATION
The SM-Bus system uses a serial data line (SDA) and a serial clock line (SCL) for
data transfer. All devices connected to it must have open drain or open collector
outputs and the logical “AND” function is performed on both lines by two pull up
resistors.
12.4
SM-BUS PROTOCOL
Normally a standard communication is composed of four parts, START signal,
Slave Address transmission, Data transfer, and STOP signal. These are described
briefly in the following sections and illustrated in Figure 12-2.
MOTOROLA
12-2
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
MSB
SCL
1
1
0
0
0
0
1
GENERAL RELEASE SPECIFICATION
LSB
MSB
1
1
LSB
1
0
0
0
0
1
Acknowledge bit
1
No acknowledge
SDA
START signal
STOP signal
MSB
SCL
1
1
0
0
0
0
1
LSB
MSB
1
1
LSB
1
0
0
0
0
Acknowledge bit
1
1
No acknowledge
SDA
START signal
repeated START signal
STOP signal
Figure 12-2. SM-Bus Transmission Signal Diagram
12.4.1 START Signal
When the bus is free, (i.e. no master device is engaging the bus and both SCL
and SDA lines are at logical high) a master may initiate communication by sending
a START signal. As shown in Figure 12-2, a START signal is defined as a high to
low transition of SDA while SCL is high. This signal denotes the beginning of new
data transfer (each data transfer may contain several bytes of data) and wakes up
all slaves.
12.4.2 Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave
address transmitted by the Master. This is a seven bit long calling address followed by a R/W-bit. The R/W-bit tells the slave the desired direction of data transfer.
Only the slave with a matched address will respond by sending back an acknowledge bit by pulling SDA low on the 9th clock cycle. (See Figure 12-2)
12.4.3 Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed
byte by byte in the direction specified by the R/W- bit sent by the calling master.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
Each data byte is 8 bits long. Data can be changed only when SCL is low and
must be held stable when SCL high as shown in Figure 12-2. The MSB is transmitted first and each byte has to be followed by an acknowledge bit. This is signalled by the receiving device by pulling the SDA low on the 9th clock cycle.
Therefore one complete data byte transfer needs 9 clock cycles.
If the slave receiver does not acknowledge the master, the SDA line should be left
high by the slave. The master can then generate a STOP signal to abort the data
transfer or a START signal (repeated start) to commence a new transfer.
If the master receiver does not acknowledge the slave transmitter after a byte has
been transmitted, it means an “end of data” to the slave. The slave should now
release the SDA line for the master to generate a “STOP” or “START” signal.
12.4.4 Repeated START Signal
As shown in Figure 12-2, a repeated START signal is used to generate a START
signal without first generating a STOP signal to terminate the communication. This
is used by the master to communicate with another slave or with the same slave in
a different mode (transmit/receive mode) without releasing the bus.
12.4.5 STOP Signal
With reference to Figure 12-2, the master can terminate the communication by
generating a STOP signal to free the bus. However, the master may generate a
START signal followed by a calling command without first generating a STOP signal. This is called repeat start. A STOP signal is defined as a low to high transition
of SDA while SCL is at logical high.
12.4.6 Arbitration Procedure
This interface circuit is a true multi-master system which allows more than one
master to be connected to it. If two or more masters try to control the bus at the
same time, a clock synchronization procedure determines the bus clock, for which
the low period is equal to the longest clock low period and the high is equal to the
shortest one among the masters. A data arbitration procedure determines the priority. The masters will lose arbitration if they transmit logic “1” while another transmits logic “0”. The losing masters will immediately switch over to slave receive
mode and stop its data and clock outputs. The transition from master to slave
mode will not generate a STOP condition in this case. Meanwhile a software bit
will be set by hardware to indicate loss of arbitration.
MOTOROLA
12-4
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
12.4.7 Clock Synchronization
WAIT
Start counting high period
SCL1
SCL2
SCL
Internal counter reset
Figure 12-3. Clock Synchronization
Since wired-AND logic is performed on SCL line, a high to low transition on the
SCL line will affect the devices connected to the bus. The devices start counting
their low period and once a device's clock has gone low, it will hold the SCL line
low until the clock high state is reached. However, the change of low to high in this
device clock may not change the state of the SCL line if another device clock is
still within its low period. Therefore the synchronized clock SCL will be held low by
the device with the longest low period. Devices with shorter low periods enter a
high wait state during this time (See Figure 12-2). When all devices concerned
have counted off their low period, the synchronized SCL line will be released and
go high. There will then be no difference between the device clocks and the state
of the SCL line and all devices will start counting their high periods. The first
device to complete its high period will again pull the SCL line low.
12.4.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte. In such
cases the device will halt the bus clock and force the master clock into a wait state
until the slave releases the SCL line.
12.5
SM-BUS REGISTERS
There are five registers used in the SM-Bus interface. They are described in the
following paragraphs.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-5
GENERAL RELEASE SPECIFICATION
August 27, 1998
12.5.1 SM-Bus Address Register (SMADR)
SMADR
R
$0020
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SMAD7
SMAD6
SMAD5
SMAD4
SMAD3
SMAD2
SMAD1
0
0
0
0
0
0
0
U
SMAD1-SMAD7 are the slave address bits of the SM-Bus module.
12.5.2 SM-Bus Frequency Divider Register (SMFDR)
BIT 7
SMFDR
R
$0021
W
reset:
BIT 6
U
BIT 5
U
U
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FD4
FD3
FD2
FD1
FD0
0
0
0
0
0
FD0-FD4 are used for clock rate selection. The serial bit clock frequency is equal
to the CPU clock divided by the divider shown in Table 12-1.
For a 4MHz external crystal operation (2MHz internal operating frequency), the
serial bit clock frequency of the SM-Bus ranges from 460Hz to 90909Hz. After
POR the clock rate is set to 90909Hz.
Table 12-1. SM-Bus Clock Prescaler
FD4, FD3, FD2, FD1, FD0
DIVIDER
FD4,FD3, FD2, FD1, FD0
DIVIDER
00000
22
10000
352
00001
24
10001
384
00010
28
10010
448
00011
34
10011
544
00100
44
10100
704
00101
48
10101
768
00110
56
10110
896
00111
68
10111
1088
01000
88
11000
1408
01001
96
11001
1536
01010
112
11010
1792
01011
136
11011
2176
01100
176
11100
2816
01101
192
11101
3072
01110
224
11110
3584
01111
272
11111
4352
MOTOROLA
12-6
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
12.5.3 SM-Bus Control Register (SMCR)
SMCR
R
$0022
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
SMEN
SMIEN
SMSTA
SMTX
TXAK
SMUX
0
0
0
0
0
0
BIT 1
BIT 0
U
U
SMEN — SM-Bus Enable
If the SM-Bus enable bit (SMEN) is set, the SM-Bus interface system is
enabled. If SMEN is cleared, the interface is reset and disabled.
The SMEN bit must be set first before any bits of SMCR are set.
1 = SM-Bus enabled.
0 = SM-Bus disabled.
SMIEN — SM-Bus Interrupt Enable
If the SM-Bus interrupt enable bit (SMIEN) is set, the interrupt occurs provided
the SMIF flag in the status register is set and the I-bit in the Condition Code
Register is cleared. If SMIEN is cleared, the SM-Bus interrupt is disabled.
1 = SM-Bus interrupt enabled.
0 = SM-Bus interrupt disabled.
SMSTA — Master/Slave Select
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START
signal is generated on the bus, and master mode is selected. When this bit is
changed from 1 to 0, a STOP signal is generated and the operating mode
changes from master to slave.
In master mode, a bit clear immediately followed by a bit set of this bit generates a repeated START signal (see Figure 12-2) without generating a STOP
signal.
1 = SM-Bus is set for master mode operation.
0 = SM-Bus is set for slave mode operation.
SMTX — Transmit/Receive Mode Select
This bit selects the SM-Bus to transmit or receive.
1 = SM-Bus is set for transmit mode.
0 = SM-Bus is set for receive mode.
TXAK — Acknowledge Enable
If the transmit acknowledge enable bit (TXAK) is cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data.
When TXAK is set, no acknowledge signal response (i.e., acknowledge bit = 1).
1 = Do not send acknowledge signal.
0 = Send acknowledge signal at 9th clock bit.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-7
GENERAL RELEASE SPECIFICATION
August 27, 1998
SMUX — SM-Bus Channel Select
The SMUX bit selects the channel for SM-Bus communications.
1 = Channel 1 (SDA1 and SCL1 pins) selected for SM-Bus.
0 = Channel 0 (SDA0 and SCL0 pins) selected for SM-Bus.
12.5.4 SM-Bus Status Register (SMSR)
SMSR
R
$0023
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
SMCF
SMAAS
SMBB
SMAL
1
0
0
BIT 3
BIT 2
BIT 1
BIT 0
SRW
SMIF
RXAK
SMAL clr
0
SMIF clr
0
0
0
1
SMCF — SM-Bus Data Transfer Complete
This bit indicates when a byte of data is being transmitted. When this bit is set,
the SMIF is also set. An interrupt request to the CPU is generated if the SMIEN
bit is also set.
1 = A byte transfer has been completed.
0 = A byte is being transferred.
SMAAS — SM-Bus Addressed as Slave
This bit is set when its own specific address (SMADR) matches the calling
address. When this bit is set, the SMIF is also set. An interrupt request to the
CPU is generated if the SMIEN bit is also set. Then CPU needs to check the
SRW bit and set its SMTX bit accordingly. Writing to the SM-Bus Control Register clears this bit.
1 = Currently addressed as a slave.
0 = Not addressed.
SMBB — SM-Bus Busy
This bit indicates the status of the bus. When a START signal is detected, the
SMBB is set. If a STOP signal is detected, it is cleared.
1 = SM-Bus busy.
0 = SM-Bus idle.
SMAL — SM-Bus Arbitration Lost
This bit is set by hardware when the arbitration procedure is lost during a master transmission. When this bit is set, the SMIF is also set. An interrupt request
to the CPU is generated if the SMIEN bit is also set. This bit must be cleared by
software.
1 = Lost arbitration in master mode.
0 = No arbitration lost.
MOTOROLA
12-8
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SRW — Slave Read/Write Select
When SMAAS is set, the R/W command bit of the calling address sent from
master is latched into the R/W command bit (SRW). By checking this bit, the
CPU can select slave transmit/receive mode according to the command of
master.
1 = Read from slave, from calling master.
0 = Write to slave from calling master.
SMIF — SM-Bus Interrupt Flag
1 = An SM-Bus interrupt has occurred.
0 = An SM-Bus interrupt has not occurred.
This bit is set when one of the following events occur:
– Transmission (either transmit or receive mode) of one byte
completed. The bit is set at the falling edge of the 9th clock.
– Receive a calling address which matches its own specific address in
slave receive mode.
– Arbitration lost.
RXAK — Receive Acknowledge
When this bit is “0”, it indicates an acknowledge signal has been received after
the completion of 8 bits data transmission on the bus. If RXAK is “1”, it means
no acknowledge signal is detected at the 9th clock. This bit is set upon reset.
1 = No acknowledgment signal detected.
0 = Acknowledgment signal detected after 8 bits data transmitted.
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-9
GENERAL RELEASE SPECIFICATION
August 27, 1998
12.5.5 SM-Bus Data I/O Register (SMDR)
SMDR
R
$0024
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SMD7
SMD6
SMD5
SMD4
SMD3
SMD2
SMD1
SMD0
0
0
0
0
0
0
0
0
In master transmit mode, data written to this register is sent (MSB first) to the bus
automatically. In master receive mode, reading from this register initiates receiving
of the next byte of data. In slave mode, the same function is available after it is
addressed.
12.5.6 SM-Bus logic Level
Two choices of logic level is available for the SM-Bus: TTL or CMOS.
MCR
R
$000B
W
reset:
BIT 7
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
Figure 12-4. Miscellaneous Control Register (MCR)
SMINLEV — SM-Bus Input Level Select
This read/write bit selects whether SM-Bus input level is TTL or CMOS. Reset
clears the SMINLEV bit.
1 = TTL input level is selected.
0 = CMOS input level is selected.
12.5.7 SCL as16-bit Timer Input Capture
The SCL signal can be routed to the 16-bit Timer Input Capture by setting the
TCSEL bit in the Miscellaneous Control Register.
TCSEL — 16-bit Timer Input Capture Source Select
This read/write bit selects the input capture source to the 16-bit Timer. Reset
clears TCSEL.
1 = SM-Bus SCL is routed to input capture of 16-bit Timer.
0 = CPF or external TCAP pin (depends on the state of ICEN bit in ACR,
$1D) is routed to 16-bit Timer.
See section Input Capture of 16-bit Timer for more details.
MOTOROLA
12-10
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
12.6
GENERAL RELEASE SPECIFICATION
PROGRAMMING CONSIDERATIONS
12.6.1 Initialization
1. Update Frequency Divider Register (FDR) to select a SCL frequency.
2. Update SM-Bus Address Register (SMADR) to define its own slave
address.
3. Set SMEN bit of SM-Bus Control Register (SMCR) to enable the SMBus interface system.
4. Modify the bits of SM-Bus Control Register (SMCR) to select Master/
Slave mode, Transmit/Receive mode, interrupt enable or not.
12.6.2 Generation of a START Signal and the First Byte of Data Transfer
After completion of the initialization procedure, serial data can be transmitted by
selecting the “master transmitter” mode. If the device is connected to a multi-master bus system, the state of the SM-Bus busy bit (SMBB) must be tested to check
whether the serial bus is free. If the bus is free (SMBB = 0), the start condition and
the first byte (the slave address) can be sent. An example of a program which
generates the START signal and transmits the first byte of data (slave address) is
shown below:
CHFALG
TXSTART
SEI
BRSET
5,SMSR,CHFLAG
BSET
BSET
4,SMCR
5,SMCR
LDA
STA
#CALLING
SMDR
CLI
;
;
;
;
;
;
;
;
;
;
;
DISABLE INTERRUPT
CHECK THE SMBB BIT OF THE
STATUS REGISTER. IF IT IS
SET, WAIT UNTIL IT IS CLEAR
SET TRANSMIT MODE
SET MASTER MODE
i.e. GENERATE START CONDITION
GET THE CALLING ADDRESS
TRANSMIT THE CALLING
ADDRESS
ENABLE INTERRUPT
12.6.3 Software Responses after Transmission or Reception of a Byte
Transmission or reception of a byte will set the data transferring bit (SMCF) to 1,
which indicates one byte communication is finished. Also, the SM-Bus interrupt bit
(SMIF) is set to generate an SM-Bus interrupt if the interrupt function is enable
during initialization. Software must clear the SMIF bit in the interrupt routine first.
The SMCF bit will be cleared by reading from the SM-Bus DATA I/O Register
(SMDR) in receive mode or writing to SMDR in transmit mode. Software may
serve the SM-Bus I/O in the main program by monitoring the SMIF bit if the interrupt function is disabled. The following is an example of a software response by a
“master transmitter” in the interrupt routine (see Figure 12-5).
MC68HC05SB7
REV 2.1
SM-BUS
MOTOROLA
12-11
GENERAL RELEASE SPECIFICATION
August 27, 1998
CLEAR SMIF
Y
N
MASTER MODE
TX
TX/RX
Y
LAST BYTE
TRANSMITTED
RX
Y
LAST BYTE
TO BE READ
N
CLEAR SMAL
Y
Y
N
N
ARBITRATION
LOST
SMAAS = 1
N
SMAAS = 1
N
Y
RXAK=0
RX
LAST 2nd BYTE
TO BE READ
N
Y
TX/RX
Y (READ)
TX
N
WRITE NEXT
BYTE TO SMDR
SET TXAK = 1
SRW= 1
GENERATE
STOP SIGNAL
READ SMDR
AND STORE
N (WRITE)
SET
TX MODE
GENERATE
STOP SIGNAL
Y
WRITE
TO SMDR
TX NEXT
BYTE
SET
RX MODE
READ DATA FROM
SMDR AND STORE
DUMMY READ
FROM SMDR
ACK FROM
RECEIVER
N
SWITCH TO
RX MODE
DUMMY READ
FROM SMDR
RTI
Figure 12-5. Flow-chart of SM-Bus Interrupt Routine
MOTOROLA
12-12
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
ISR
TRANSMIT
BCLR
BRCLR
1,SMSR
5,SMCR,SLAVE
BRCLR
4,SMCR,RECEIVE
BRSET
0,SMSR,END
LDA
STA
DATABUF
SMDR
GENERAL RELEASE SPECIFICATION
;
;
;
;
;
;
;
;
;
;
CLEAR THE SMIF FLAG
CHECK THE SMSTA FLAG,
BRANCH IF SLAVE MODE
CHECK THE MODE FLAG,
BRANCH IF IN RECEIVE MODE
CHECK ACK FROM RECEIVER
IF NO ACK, END OF
TRANSMISSION
GET THE NEXT BYTE OF DATA
TRANSMIT THE DATA
12.6.4 Generation of the STOP Signal
A data transfer ends with a STOP signal generated by the “master” device. A master transmitter can simply generate a STOP signal after all the data has been
transmitted. The following is an example showing how a stop condition is generated by a master transmitter:
MASTX
END
EMASTX
BRSET
LDA
0,SMSR,END
TXCNT
BEQ
END
LDA
STA
DEC
BRA
BCLR
RTI
DATABUF
SMDR
TXCNT
EMASTX
5,SMCR
;
;
;
;
;
;
;
;
;
;
;
IF NO ACK, BRANCH TO END
GET VALUE FROM THE
TRANSMITTING COUNTER
IF NO MORE DATA, BRANCH TO
END
GET NEXT BYTE OF DATA
TRANSMIT THE DATA
DECREASE THE TXCNT
EXIT
GENERATE A STOP CONDITION
RETURN FROM INTERRUPT
If a master receiver wants to terminate a data transfer, it must inform the slave
transmitter by not acknowledging the last byte of data. This can be done by setting
the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data.
Before reading the last byte of data, a STOP signal must be generated first. The
following is an example showing how a STOP signal is generated by a master
receiver.
MASR
DEC
BEQ
LDA
DECA
RXCNT
ENMASR
RXCNT
LAMAR
BNE
BSET
NXMAR
3,SMCR
ENMASR
BRA
BCLR
NXMAR
5,SMCR
LDA
STA
RTI
SMDR
RXBUF
NXMAR
MC68HC05SB7
REV 2.1
; LAST BYTE TO BE READ
;
;
;
;
;
CHECK LAST 2ND BYTE TO
BE READ
NOT LAST ONE OR LAST SECOND
LAST SECOND, DISABLE ACK
TRANSMITTING
; LAST ONE, GENERATE “STOP”
; SIGNAL
; READ DATA AND STORE
SM-BUS
MOTOROLA
12-13
GENERAL RELEASE SPECIFICATION
August 27, 1998
12.6.5 Generation of a Repeated START Signal
If at the end of data transfer the master still wants to communicate on the bus, it
can generate another START signal followed by another slave address without
first generating a STOP signal. A program example is shown below.
RESTART
BCLR
BSET
5,SMCR
5,SMCR
LDA
STA
#CALLING
SMDR
;
;
;
;
;
ANOTHER START (RESTART) IS
GENERATED BY THESE TWO
CONSEQUENCE INSTRUCTION
GET THE CALLING ADDRESS
TRANSMIT THE CALLING ADDRESS
12.6.6 Slave Mode
In the slave service routine, the master addressed as slave bit (SMAAS) should
be tested to see if a calling of its own address has just been received. If SMAAS is
set, software should set the transmit/receive mode select bit (SMTX bit of SMCR)
according to the R/W-command bit (SRW). Writing to the SMCR clears the
SMAAS automatically. A data transfer may then be initiated by writing information
to SMDR or dummy reading from SMDR.
In the slave transmitter routine, the received acknowledge bit (RXAK) must be
tested before transmitting the next byte of data. If RXAK is set, indicating an “end
of data” signal from the master receiver, then it must switch from transmitter mode
to receiver mode by software and a dummy read must follow to release the SCL
line so that the master can generate a stop signal.
12.6.7 Arbitration Lost
If more than one master want to acquire the bus simultaneously, only one master
wins and the others lost arbitration. The arbitration lost devices immediately switch
to slave receive mode by hardware. Their data output to the SDA line is stopped,
but internal transmitting clock still run until the end of the byte transmitting. An
interrupt occurs when this dummy “byte” transmitting is accomplished with
SMAL=1 and SMSTA = 0. If one master attempt to start transmission while the
bus is being engaged by another master, the hardware will inhibit the transmission; switch the SMSTA bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the SMAL to indicate that the attempt to engage
the bus is failed. Consideration of these cases, the slave service routine should
test the SMAL first, software should clear the SMAL bit if it is set.
12.7
OPERATION DURING WAIT MODE
During WAIT mode the SM-Bus block is idle. If in slave mode it will wake up on
receiving a valid start condition. If the interrupt is enabled the CPU will come out
of WAIT mode after the end of a byte transmission.
12.8
OPERATION DURING STOP MODE
In Stop Mode the SM-Bus is disabled.
MOTOROLA
12-14
SM-BUS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 13
CURRENT SENSE AMPLIFIER
The Current Sense Amplifier module, used in conjunction with the Analog Subsystem, is designed to monitor charge and discharge currents in smart battery
applications.
13.1
CURRENT SENSE AMPLIFIER APPLICATION
A typical connection for the Current Sense Amplifier (CSA) block is illustrated in
Figure 13-1. With a sense resistor, RSENSE of 0.01Ω, the voltage setup across the
node CSA and VSS (ground) will vary to the current (in either charging or discharging mode) as shown in Table 13-1.
Table 13-1. Voltage Across the Sense Resistor against Current
Current flowing
Voltage across the Sense Resistor, RSENSE
10mA
0.1mV
1A
10mV
5A
50mV
RSENSE =0.01Ω
In this case, the CSA is required to measure a current from 10mA to 5A over the
operating temperature from 0°C to 70°C.
With the A/D in the Analog Subsystem set up for 12-bit resolution, the step size is
approximately 1.22mV (VDD =5V). To measure the 0.1mV for the 10mA current
flow, a gain of greater than 10 is required.
The CSA module is designed with two gain settings, 10 and 30. With a 10-bit A/D,
and a gain of 30, the CSA can measure current with a typical resolution of 17mA
steps.
After amplification, the resultant signal is fed to channel 6 (MUX6) of the analog
subsystem for A/D conversion.
MC68HC05SB7
REV 2.1
CURRENT SENSE AMPLIFIER
MOTOROLA
13-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
Batt+
CSCAL
(bit 4 of $0A)
CSEN
(bit 7 of $0A)
CSA
0.01Ω
+
x30 (bit 6 of $0A)
RSENSE
x10 (bit 5 of $0A)
Batt–
To analog
MUX 6 input
VMID
(For internal test)
Gain Adjustment
VSS
CDEN
(bit 3 of $0A)
VDD
VDET
Typically –15mV
+
–
D
Q
CDET
Interrupt
R
CDIFR
(bit 1 of $0A)
Port B
I/O
Logic
CDIE
(bit 2 of $0A)
PB2/
CS0
PB3/
CS1
CS0 and CS1 pins are not
available for CSA functions
when OSC1 and OSC2 are
used; i.e. external crystal osc.
option is used.
Logic
CDEN
(bit 3 of $0A)
CSSEL
(bit 3 of $0B)
Figure 13-1. Current Sense Amplifier Block
13.2
CURRENT SENSE INTERRUPT
The CSA can generate an interrupt once it detects a (discharge) current passes
through the current sensing resistor, RSENSE. The trip current depends on the
value of the sense resistor; it is voltage developed across RSENSE, VDET that trips
the interrupt. VDET is set typically at –15mV, with –10mV being the minimum.
13.3
CSA STATUS AND CONTROL REGISTER (CSSCR)
The CSA status and control register is shown in Figure 13-2.
MOTOROLA
13-2
CURRENT SENSE AMPLIFIER
MC68HC05SB7
REV 2.1
CSSCR
R
$000A
W
reset:
August 27, 1998
GENERAL RELEASE SPECIFICATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
CSEN
X30
X10
CSCAL
CDEN
CDIE
0
0
0
0
0
0
BIT 1
BIT 0
0
CDIF
CDIFR
0
0
Figure 13-2. CSA Status and Control Register (CSSCR)
CSEN — Current Sense Amplifier Enable
This read/write bit enables the CSA module. Reset clears the CSEN bit.
1 = CSA block enabled.
0 = CSA block disabled.
X30, X10 — Current Sense Amplifier Gain Select
These read/write bits enable the respective gain to be selected. See
Table 13-2. Reset clears the X30 and X10 bits.
Table 13-2. Current Sense Amplifier Gain Select
X30
X10
GAIN SELECTED
0
Don’t care
X10
1
0
X30
1
1
Undetermined
CSCAL — Current Sense Amplifier Calibration Enable
This read/write bit enables the CSA calibration. Reset clears the CSCAL bit.
1 = CSA calibration enabled; current amplifier input connected to
ground (VSS).
0 = CSA calibration disabled; current amplifier input from CSA pin.
CDEN — Current Detect Enable
This read/write bit enables the current detect comparator and current detect
output pin (CS0 or CS1) logic. Reset clears the CDEN bit.
1 = Current detect comparator enabled.
0 = Current detect comparator disabled.
CDIE — Current Detect Interrupt Enable
This read/write bit enables interrupts caused by detecting the current passing
through the sensing resistor, RSENSE. Reset clears the CDIE bit.
1 = Current detect interrupt enabled.
0 = Current detect interrupt disabled.
CDIFR — Current Detect Interrupt Flag Reset
Writing a logic “1” to this write-only bit clears the CDIF bit. CDIFR always reads
as a logic zero. Reset does not affect CDIFR.
1 = Clear CDIF bit.
0 = No affect on CDIF bit.
MC68HC05SB7
REV 2.1
CURRENT SENSE AMPLIFIER
MOTOROLA
13-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
CDIF — Current Detect Interrupt Flag
This read-only bit is set when the voltage developed across the sense resistor,
RSENSE is equal to or greater than VDET (the CSA comparator trip voltage,
typically –15mV) CDIF generates an interrupt request to the CPU if CDIE is
also set. The CDIF bit is cleared by writing a logic “1” to the CDIFR bit. Writing
to CDIF has no effect. Reset clears CDIF.
1 = Current detect interrupt has occurred.
0 = No current detect interrupt since CDIF last cleared.
If the OSC1 and OSC2 pins are not enabled (by mask option). The current detect
interrupt from CDIF bit can be reflected to one of two output port pins, PB2/CS0
and PB3/CS1.
MCR
R
$000B
W
BIT 7
BIT 6
TSEN
LVRON
0
1
reset:
BIT 5
0
COPON
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 13-3. Miscellaneous Control Register (MCR)
CSSEL — Current Sense detect output Select
This read/write bit selects either CS0 pin or CS1 pin is used to reflect the current detect interrupt. Reset clears the CSSEL bit.
1 = CS1 enabled, CS0 disabled.
0 = CS0 enabled, CS1 disabled.
Table 13-3. Current Detect Output Select
CDEN
CSSEL
PB2/CS0
PB3/CS1
0
0
PB2
PB3
0
1
PB2
PB3
1
0
CS0
PB3
1
1
PB2
CS1
CS0 and CS1 are not available when OSC1 and OSC2 are used for external oscillator option.
13.4
CSA OPERATION DURING WAIT MODE
In WAIT mode the CSA module continues to operate and may generate an interrupt to trigger the MCU out of WAIT mode.
13.5
CSA OPERATION DURING STOP MODE
In STOP mode the CSA module is disabled; but a CSA interrupt (by CDIF) can
wake-up the MCU from the STOP mode.
MOTOROLA
13-4
CURRENT SENSE AMPLIFIER
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 14
TEMPERATURE SENSOR
The MC68HC05SB7 MCU can measure temperature in two ways: by using the
internal temperature sensor, or by using an external thermistor.
14.1
INTERNAL TEMPERATURE SENSOR
The internal temperature sensor is designed to measure temperature over the
0°C to 70 °C range; with its voltage output connected to channel 5 of the Analog
Subsystem (AN5, see Analog Subsystem section).
The temperature sensor is disabled/enabled by the TSEN bit in the Miscellaneous
Control Register at $0B. The TSEN bit also disables/enables the BandGap
reference voltage.
MCR
R
$000B
W
reset:
BIT 7
BIT 6
TSEN
LVRON
0
1
BIT 5
0
COPON
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
0
0
0
0
0
Figure 14-1. Miscellaneous Control Register (MCR)
TSEN — Internal Temperature Sensor and BandGap Reference Enable
This read/write bit enables the internal temperature sensor and BandGap reference. Reset clears TSEN.
1 = Temperature sensor and bandgap reference enabled.
0 = Temperature sensor and bandgap reference disabled.
NOTE
The temperature gradient is typically 2.2mV/°C ±10%.
The internal temperature sensor is a semiconductor type sensor. Due to process
variations, the absolute output voltage at a given temperature will vary from one
device to another. It is the user’s responsibility to measure and calibrate the
temperature sensor output voltage when the MCU is in the target system.
As an option, the temperature sensor voltage at 80°C is available preprogrammed
into the PEPROM. See PEPROM section.
MC68HC05SB7
REV 2.1
TEMPERATURE SENSOR
MOTOROLA
14-1
GENERAL RELEASE SPECIFICATION
14.2
August 27, 1998
EXTERNAL TEMPERATURE SENSOR
In fast charge control applications, where close monitoring of the charging process is required (especially temperature), an external temperature sensor (thermistor) is recommended. This external thermistor connects to the TM pin (see
Figure 14-2), and its voltage measured via channel 4 (AN4, see Analog Subsystem section) of the Analog Subsystem. For faster temperature response time
and more accurate measurement (required for fast charge control), the thermistor
should be mounted directly to the battery pack.
Batt+
MC68HC05SB7
VM
VDD
TM
Batt–
Thermistor
Figure 14-2. External Temperature Sensor Connection
14.3
TEMPERATURE SENSOR OPERATION DURING WAIT MODE
During WAIT mode the temperature sensor continues to operate normally.
14.4
TEMPERATURE SENSOR OPERATION DURING STOP MODE
In STOP mode the temperature sensor is disabled.
MOTOROLA
14-2
TEMPERATURE SENSOR
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 15
ANALOG SUBSYSTEM
The analog subsystem of the MC68HC05SB7 is based on an on-chip voltage
comparator as shown in Figure 15-1.
This configuration provides following features:
•
The voltage comparator with external access to both inverting and noninverting inputs
•
The voltage comparator can be connected as a single-slope A/D. The
possible single-slope A/D connection provides the following features:
– A/D conversions can use VDD or an external voltage as a reference
with software used to calculate ratiometric or absolute results
– Channel access to up to eight inputs via multiplexer control with
independent multiplexer control allowing multiple input connections
– Access to VDD and VSS for calibration
– Divide by 2 to extend input voltage range
– The comparator can be inverted to calculate input offsets
– Internal sample and hold capacitor
Voltages are resolved by measuring the time it takes an external capacitor to
charge up to the level of the unknown input voltage that is being measured. The
beginning of the A/D conversion time can be started by several means:
•
Output compare from the 16-bit programmable Timer
•
Timer overflow from the 16-bit programmable Timer
•
Direct software control via a register bit
The end of the A/D conversion time can be captured by several means:
•
Input capture in the 16-bit programmable Timer
•
Interrupt generated by the comparator output
•
Software polling of the comparator output using software loop time
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-1
SCL
ICHG
2 TO 1
MUX
TCAP
IDISCHG
CPIE
ANALOG
CONTROL REGISTER
(ACR)
TCSEL
BIT 2 OF MCR ($0B)
CHG
ATD1
ATD2
ISEN
CPEN
ICEN
CHARGE
CURRENT
CONTROL
LOGIC
CAP
100K
CPF
MUX0
CMP
PORTB
LOGIC
MUX1
PORTB
LOGIC
MUX2
PORTB
LOGIC
MUX3
100K
PB7
AN0
SAMPLE
CAP
PB6
AN1
MUX4
AN4
TM
(see Figure 13-1)
INV
VREF
VREF
MUX7
MUX6
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
IBREF
MUX6
CURRENT
SENSE AN6
AMPLIFIER
CIRCUIT
MUX7
MUX3
MUX2
MUX1
MUX0
AN7
VM
VAOFF
VSS
DHOLD
–+
IBREF
MUX5
AN5
INTERNAL
TEMPERATURE
SENSOR
MUX7
TSEN
BIT 7 OF MCR ($0B)
IBREF
DENOTES
INTERNAL
CHIP AVSS
VIB
MUX6
MUX5
INTERNAL
BANDGAP
REFERENCE
ANALOG
MUX REGISTER 2
(AMUX2)
CSA
HOLD
ANALOG
MUX REGISTER 1
(AMUX1)
PB4
AN3
CHANNEL SELECT BUS
PB5
AN2
ANALOG
INTERRUPT
INTERNAL HC05 BUS
INV
ANALOG
STATUS REGISTER
(ASR)
+
COMP
–
VDD
PORTB
LOGIC
16-BIT PROG.
TIMER
ICF
2 TO 1
MUX
VDD
OCF
PB1
TCAP
August 27, 1998
TOF
GENERAL RELEASE SPECIFICATION
MUX4
Figure 15-1. Analog Subsystem Block Diagram
MOTOROLA
15-2
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
15.1
GENERAL RELEASE SPECIFICATION
ANALOG MULTIPLEX REGISTERS
The Analog Multiplex Registers (AMUX1 and AMUX2) control the general interconnection and operation. The control bits in AMUX1 and AMUX2 are shown in
Figure 15-2 and Figure 15-2 respectively.
AMUX1
R
$0003
W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HOLD
DHOLD
INV
VREF
MUX3
MUX2
MUX1
MUX0
1
0
0
0
0
0
0
0
reset:
Figure 15-2. Analog Multiplex Register 1 (AMUX1)
BIT 7
AMUX2
R
$0007
W
BIT 6
BIT 5
0
0
reset:
0
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IBREF
MUX7
MUX6
MUX5
MUX4
0
0
0
0
0
0
Figure 15-3. Analog Multiplex Register 2 (AMUX2)
HOLD, DHOLD
These read/write bits control the source connection to the input to the negative
input of voltage comparator shown in Figure 15-1. This allows the channel
selection bus or the 1:2 divided channel selection bus to charge the internal
sample capacitor and to also be presented to comparator. The decoding of
these sources is given in Table 15-1. During a reset the HOLD bit is set and the
DHOLD bit is cleared, which connects the internal sample capacitor to the
channel selection bus. And since a reset also clears the MUX0:7 bits then the
channel selection bus will be connected to VSS and the internal sample capacitor will be discharged to VSS following the reset.
Table 15-1. Comparator Input Sources
HOLD
DHOLD
Case
Source To Negative Input of Comparator
0
0
Sample Hold
Internal sample capacitor connected to only the negative input of comparator; and subjected to a very
low leakage current.
0
1
Divided Input
Signal to channel selection bus is divided by 2 and
connected to both the internal sample capacitor and
negative input of comparator.
1
0
Direct
Input
Signal to channel selection bus is connected directly
to both the internal sample capacitor and negative
input of comparator.
1
1
Not allowed
MC68HC05SB7
REV 2.1
—
ANALOG SUBSYSTEM
MOTOROLA
15-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
NOTE
When sampling a voltage for later conversion the HOLD and DHOLD bit should be
cleared before making any changes in the MUX channel selection. If the MUX
channel and the HOLD/DHOLD are changed on the same write cycle to the
AMUX1 register, the sampled voltage may be altered during the channel
switching.
INV
This is a read/write bit that controls the phase of the voltage comparator. This
bit allows voltage comparisons with either input node of the voltage comparator
to be presented to the rest of the circuit as the “positive” or “negative” input.
The voltage comparator is defined as non-inverted when the internal positive
node is connected to the external positive input and the output is not inverted.
In this case the output will go to a logical one when the voltage on the positive
input is higher than the voltage on the negative input. Any input offset voltage in
the voltage comparator will be with respect to the negative input.
The voltage comparator is defined as inverted when the internal negative node
is connected to the external positive input and the output is inverted. In this
case the output will still go to a logical one when the voltage on the positive
input is higher than the voltage on the negative input. In the inverted case any
input offset voltage in the voltage comparator will be with respect to the positive
input. This bit is cleared by a reset of the device.
1 = The voltage comparator is internally inverted.
0 = The voltage comparator is not internally inverted.
RISE
WHEN
V+ > V–
V+
VIO
V–
+
COMP
–
RISE
WHEN
V+ > V–
V+
VIO
V–
INV=0
+
COMP
–
INV=1
Figure 15-4. INV Bit Action
NOTE
The effect of changing the state of the INV bit is to only change the polarity of the
input offset voltage. It does not change the output phase of the CPF flag with
respect to the external port pins.
The comparator may generate an output flag when the inputs are exchanged due
to a change in the state of the INV bit. It is therefore recommended that the INV bit
MOTOROLA
15-4
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
not be changed while waiting for a comparator flag. Further, any changes to the
state of the INV bit should be followed by writing a logical one to CPFR bit to clear
an extraneous CPF flag that may have occurred.
VREF
This is a read/write bit that connects the channel select bus to VDD for purposes
of making a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown in
Table 15-2. This bit is cleared by a reset of the device.
1 = Channel select bus connected to VDD if MUX7:0 and IBREF are
cleared.
0 = Channel select bus cannot be connected to VDD.
IBREF
This is a read/write bit that connects the channel select bus to VIB for purposes
of making a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown in
Table 15-2. This bit is cleared by a reset of the device.
1 = Channel select bus connected to VIB if MUX7:0 and VREF are
cleared.
0 = Channel select bus cannot be connected to VIB.
MUX7:0
These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage comparator for purposes of making a voltage measurement. They can be selected individually or combined with any of the other
input sources to the channel select bus as shown in Table 15-2.
NOTE
The VAOFF voltage source shown in Figure 15-1 depicts a small offset voltage
generated by the total chip current passing through the package bond wires and
lead frame that are attached to the single VSS pin. The offset raises the internal
VSS reference (AVSS) in the analog subsystem with respect to the external VSS
pin. Turning on the VSS MUX to the channel select bus connects it to this internal
AVSS reference line.
When making A/D conversions this AVSS offset gets placed on the external
ramping capacitor since the discharge device on the CAP pin discharges the
external capacitor to the internal AVSS line. Under these circumstances the
positive input (+) to the comparator will always be higher than the negative input (–
) until the negative input reaches the AVSS offset voltage plus any offset in the
comparator.
Therefore, input voltages cannot be resolved if they are less than the sum of the
AVSS offset and the comparator offset, because they will always yield a low output
from the comparator
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-5
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
0
0
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
VSS
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
ON
X X 0
0
0
0
0
0
0
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
ON
Z
X X 0
0
0
0
0
0
1
0
Z
Z
Z
Z
Z
Z
Z
Z
ON
Z
Z
X X 0
0
0
0
0
0
1
1
Z
Z
Z
Z
Z
Z
Z
Z
ON
ON
Z
X X 0
0
0
0
0
1
0
0
Z
Z
Z
Z
Z
Z
Z
ON
Z
Z
Z
X X 0
0
0
0
0
1
0
1
Z
Z
Z
Z
Z
Z
Z
ON
Z
ON
Z
X X 0
0
0
0
0
1
1
0
Z
Z
Z
Z
Z
Z
Z
ON
ON
Z
Z
X X 0
0
0
0
0
1
1
1
Z
Z
Z
Z
Z
Z
Z
ON
ON
ON
Z
X X 0
0
0
0
1
0
0
0
Z
Z
Z
Z
Z
Z
ON
Z
Z
Z
Z
X X 0
0
0
0
1
0
0
1
Z
Z
Z
Z
Z
Z
ON
Z
Z
ON
Z
X X 0
0
0
0
1
0
1
0
Z
Z
Z
Z
Z
Z
ON
Z
ON
Z
Z
X X 0
0
0
0
1
0
1
1
Z
Z
Z
Z
Z
Z
ON
Z
ON
ON
Z
X X 0
0
0
0
1
1
0
0
Z
Z
Z
Z
Z
Z
ON
ON
Z
Z
Z
X X 0
0
0
0
1
1
0
1
Z
Z
Z
Z
Z
Z
ON
ON
Z
ON
Z
X X 0
0
0
0
1
1
1
0
Z
Z
Z
Z
Z
Z
ON
ON
ON
Z
Z
X X 0
0
0
0
1
1
1
1
Z
Z
Z
Z
Z
Z
ON
ON
ON
ON
Z
X X 0
0
0
1
0
0
0
0
Z
Z
Z
Z
Z
ON
Z
Z
Z
Z
Z
X X 0
0
0
1
0
0
0
1
Z
Z
Z
Z
Z
ON
Z
Z
Z
ON
Z
X X 0
0
0
1
0
0
1
0
Z
Z
Z
Z
Z
ON
Z
Z
ON
Z
Z
X X 0
0
0
1
0
0
1
1
Z
Z
Z
Z
Z
ON
Z
Z
ON
ON
Z
X X 0
0
0
1
0
1
0
0
Z
Z
Z
Z
Z
ON
Z
ON
Z
Z
Z
X X 0
0
0
1
0
1
0
1
Z
Z
Z
Z
Z
ON
Z
ON
Z
ON
Z
X X 0
0
0
1
0
1
1
0
Z
Z
Z
Z
Z
ON
Z
ON
ON
Z
Z
X X 0
0
0
1
0
1
1
1
Z
Z
Z
Z
Z
ON
Z
ON
ON
ON
Z
X X 0
0
0
1
1
0
0
0
Z
Z
Z
Z
Z
ON
ON
Z
Z
Z
Z
X X 0
0
0
1
1
0
0
1
Z
Z
Z
Z
Z
ON
ON
Z
Z
ON
Z
X X 0
0
0
1
1
0
1
0
Z
Z
Z
Z
Z
ON
ON
Z
ON
Z
Z
X X 0
0
0
1
1
0
1
1
Z
Z
Z
Z
Z
ON
ON
Z
ON
ON
Z
X X 0
0
0
1
1
1
0
0
Z
Z
Z
Z
Z
ON
ON
ON
Z
Z
Z
X X 0
0
0
1
1
1
0
1
Z
Z
Z
Z
Z
ON
ON
ON
Z
ON
Z
MOTOROLA
15-6
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 0
0
0
1
1
1
1
0
Z
Z
Z
Z
Z
ON
ON
ON
ON
Z
Z
X X 0
0
0
1
1
1
1
1
Z
Z
Z
Z
Z
ON
ON
ON
ON
ON
Z
X X 0
0
1
0
0
0
0
0
Z
Z
Z
Z
ON
Z
Z
Z
Z
Z
Z
X X 0
0
1
0
0
0
0
1
Z
Z
Z
Z
ON
Z
Z
Z
Z
ON
Z
X X 0
0
1
0
0
0
1
0
Z
Z
Z
Z
ON
Z
Z
Z
ON
Z
Z
X X 0
0
1
0
0
0
1
1
Z
Z
Z
Z
ON
Z
Z
Z
ON
ON
Z
X X 0
0
1
0
0
1
0
0
Z
Z
Z
Z
ON
Z
Z
ON
Z
Z
Z
X X 0
0
1
0
0
1
0
1
Z
Z
Z
Z
ON
Z
Z
ON
Z
ON
Z
X X 0
0
1
0
0
1
1
0
Z
Z
Z
Z
ON
Z
Z
ON
ON
Z
Z
X X 0
0
1
0
0
1
1
1
Z
Z
Z
Z
ON
Z
Z
ON
ON
ON
Z
X X 0
0
1
0
1
0
0
0
Z
Z
Z
Z
ON
Z
ON
Z
Z
Z
Z
X X 0
0
1
0
1
0
0
1
Z
Z
Z
Z
ON
Z
ON
Z
Z
ON
Z
X X 0
0
1
0
1
0
1
0
Z
Z
Z
Z
ON
Z
ON
Z
ON
Z
Z
X X 0
0
1
0
1
0
1
1
Z
Z
Z
Z
ON
Z
ON
Z
ON
ON
Z
X X 0
0
1
0
1
1
0
0
Z
Z
Z
Z
ON
Z
ON
ON
Z
Z
Z
X X 0
0
1
0
1
1
0
1
Z
Z
Z
Z
ON
Z
ON
ON
Z
ON
Z
X X 0
0
1
0
1
1
1
0
Z
Z
Z
Z
ON
Z
ON
ON
ON
Z
Z
X X 0
0
1
0
1
1
1
1
Z
Z
Z
Z
ON
Z
ON
ON
ON
ON
Z
X X 0
0
1
1
0
0
0
0
Z
Z
Z
Z
ON
ON
Z
Z
Z
Z
Z
X X 0
0
1
1
0
0
0
1
Z
Z
Z
Z
ON
ON
Z
Z
Z
ON
Z
X X 0
0
1
1
0
0
1
0
Z
Z
Z
Z
ON
ON
Z
Z
ON
Z
Z
X X 0
0
1
1
0
0
1
1
Z
Z
Z
Z
ON
ON
Z
Z
ON
ON
Z
X X 0
0
1
1
0
1
0
0
Z
Z
Z
Z
ON
ON
Z
ON
Z
Z
Z
X X 0
0
1
1
0
1
0
1
Z
Z
Z
Z
ON
ON
Z
ON
Z
ON
Z
X X 0
0
1
1
0
1
1
0
Z
Z
Z
Z
ON
ON
Z
ON
ON
Z
Z
X X 0
0
1
1
0
1
1
1
Z
Z
Z
Z
ON
ON
Z
ON
ON
ON
Z
X X 0
0
1
1
1
0
0
0
Z
Z
Z
Z
ON
ON
ON
Z
Z
Z
Z
X X 0
0
1
1
1
0
0
1
Z
Z
Z
Z
ON
ON
ON
Z
Z
ON
Z
X X 0
0
1
1
1
0
1
0
Z
Z
Z
Z
ON
ON
ON
Z
ON
Z
Z
X X 0
0
1
1
1
0
1
1
Z
Z
Z
Z
ON
ON
ON
Z
ON
ON
Z
X X 0
0
1
1
1
1
0
0
Z
Z
Z
Z
ON
ON
ON
ON
Z
Z
Z
MC68HC05SB7
REV 2.1
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MOTOROLA
15-7
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 0
0
1
1
1
1
0
1
Z
Z
Z
Z
ON
ON
ON
ON
Z
ON
Z
X X 0
0
1
1
1
1
1
0
Z
Z
Z
Z
ON
ON
ON
ON
ON
Z
Z
X X 0
0
1
1
1
1
1
1
Z
Z
Z
Z
ON
ON
ON
ON
ON
ON
Z
X X 0
!
0
0
0
0
0
0
Z
Z
Z
ON
Z
Z
Z
Z
Z
Z
Z
X X 0
1
0
0
0
0
0
1
Z
Z
Z
ON
Z
Z
Z
Z
Z
ON
Z
X X 0
1
0
0
0
0
1
0
Z
Z
Z
ON
Z
Z
Z
Z
ON
Z
Z
X X 0
1
0
0
0
0
1
1
Z
Z
Z
ON
Z
Z
Z
Z
ON
ON
Z
X X 0
1
0
0
0
1
0
0
Z
Z
Z
ON
Z
Z
Z
ON
Z
Z
Z
X X 0
1
0
0
0
1
0
1
Z
Z
Z
ON
Z
Z
Z
ON
Z
ON
Z
X X 0
1
0
0
0
1
1
0
Z
Z
Z
ON
Z
Z
Z
ON
ON
Z
Z
X X 0
1
0
0
0
1
1
1
Z
Z
Z
ON
Z
Z
Z
ON
ON
ON
Z
X X 0
1
0
0
1
0
0
0
Z
Z
Z
ON
Z
Z
ON
Z
Z
Z
Z
X X 0
1
0
0
1
0
0
1
Z
Z
Z
ON
Z
Z
ON
Z
Z
ON
Z
X X 0
1
0
0
1
0
1
0
Z
Z
Z
ON
Z
Z
ON
Z
ON
Z
Z
X X 0
1
0
0
1
0
1
1
Z
Z
Z
ON
Z
Z
ON
Z
ON
ON
Z
X X 0
1
0
0
1
1
0
0
Z
Z
Z
ON
Z
Z
ON
ON
Z
Z
Z
X X 0
1
0
0
1
1
0
1
Z
Z
Z
ON
Z
Z
ON
ON
Z
ON
Z
X X 0
1
0
0
1
1
1
0
Z
Z
Z
ON
Z
Z
ON
ON
ON
Z
Z
X X 0
1
0
0
1
1
1
1
Z
Z
Z
ON
Z
Z
ON
ON
ON
ON
Z
X X 0
1
0
1
0
0
0
0
Z
Z
Z
ON
Z
ON
Z
Z
Z
Z
Z
X X 0
1
0
1
0
0
0
1
Z
Z
Z
ON
Z
ON
Z
Z
Z
ON
Z
X X 0
1
0
1
0
0
1
0
Z
Z
Z
ON
Z
ON
Z
Z
ON
Z
Z
X X 0
1
0
1
0
0
1
1
Z
Z
Z
ON
Z
ON
Z
Z
ON
ON
Z
X X 0
1
0
1
0
1
0
0
Z
Z
Z
ON
Z
ON
Z
ON
Z
Z
Z
X X 0
1
0
1
0
1
0
1
Z
Z
Z
ON
Z
ON
Z
ON
Z
ON
Z
X X 0
1
0
1
0
1
1
0
Z
Z
Z
ON
Z
ON
Z
ON
ON
Z
Z
X X 0
1
0
1
0
1
1
1
Z
Z
Z
ON
Z
ON
Z
ON
ON
ON
Z
X X 0
1
0
1
1
0
0
0
Z
Z
Z
ON
Z
ON
ON
Z
Z
Z
Z
X X 0
1
0
1
1
0
0
1
Z
Z
Z
ON
Z
ON
ON
Z
Z
ON
Z
X X 0
1
0
1
1
0
1
0
Z
Z
Z
ON
Z
ON
ON
Z
ON
Z
Z
X X 0
1
0
1
1
0
1
1
Z
Z
Z
ON
Z
ON
ON
Z
ON
ON
Z
MOTOROLA
15-8
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 0
1
0
1
1
1
0
0
Z
Z
Z
ON
Z
ON
ON
ON
Z
Z
Z
X X 0
1
0
1
1
1
0
1
Z
Z
Z
ON
Z
ON
ON
ON
Z
ON
Z
X X 0
1
0
1
1
1
1
0
Z
Z
Z
ON
Z
ON
ON
ON
ON
Z
Z
X X 0
1
0
1
1
1
1
1
Z
Z
Z
ON
Z
ON
ON
ON
ON
ON
Z
X X 0
1
1
0
0
0
0
0
Z
Z
Z
ON
ON
Z
Z
Z
Z
Z
Z
X X 0
1
1
0
0
0
0
1
Z
Z
Z
ON
ON
Z
Z
Z
Z
ON
Z
X X 0
1
1
0
0
0
1
0
Z
Z
Z
ON
ON
Z
Z
Z
ON
Z
Z
X X 0
1
1
0
0
0
1
1
Z
Z
Z
ON
ON
Z
Z
Z
ON
ON
Z
X X 0
1
1
0
0
1
0
0
Z
Z
Z
ON
ON
Z
Z
ON
Z
Z
Z
X X 0
1
1
0
0
1
0
1
Z
Z
Z
ON
ON
Z
Z
ON
Z
ON
Z
X X 0
1
1
0
0
1
1
0
Z
Z
Z
ON
ON
Z
Z
ON
ON
Z
Z
X X 0
1
1
0
0
1
1
1
Z
Z
Z
ON
ON
Z
Z
ON
ON
ON
Z
X X 0
1
1
0
1
0
0
0
Z
Z
Z
ON
ON
Z
ON
Z
Z
Z
Z
X X 0
1
1
0
1
0
0
1
Z
Z
Z
ON
ON
Z
ON
Z
Z
ON
Z
X X 0
1
1
0
1
0
1
0
Z
Z
Z
ON
ON
Z
ON
Z
ON
Z
Z
X X 0
1
1
0
1
0
1
1
Z
Z
Z
ON
ON
Z
ON
Z
ON
ON
Z
X X 0
1
1
0
1
1
0
0
Z
Z
Z
ON
ON
Z
ON
ON
Z
Z
Z
X X 0
1
1
0
1
1
0
1
Z
Z
Z
ON
ON
Z
ON
ON
Z
ON
Z
X X 0
1
1
0
1
1
1
0
Z
Z
Z
ON
ON
Z
ON
ON
ON
Z
Z
X X 0
1
1
0
1
1
1
1
Z
Z
Z
ON
ON
Z
ON
ON
ON
ON
Z
X X 0
1
1
1
0
0
0
0
Z
Z
Z
ON
ON
ON
Z
Z
Z
Z
Z
X X 0
1
1
1
0
0
0
1
Z
Z
Z
ON
ON
ON
Z
Z
Z
ON
Z
X X 0
1
1
1
0
0
1
0
Z
Z
Z
ON
ON
ON
Z
Z
ON
Z
Z
X X 0
1
1
1
0
0
1
1
Z
Z
Z
ON
ON
ON
Z
Z
ON
ON
Z
X X 0
1
1
1
0
1
0
0
Z
Z
Z
ON
ON
ON
Z
ON
Z
Z
Z
X X 0
1
1
1
0
1
0
1
Z
Z
Z
ON
ON
ON
Z
ON
Z
ON
Z
X X 0
1
1
1
0
1
1
0
Z
Z
Z
ON
ON
ON
Z
ON
ON
Z
Z
X X 0
1
1
1
0
1
1
1
Z
Z
Z
ON
ON
ON
Z
ON
ON
ON
Z
X X 0
1
1
1
1
0
0
0
Z
Z
Z
ON
ON
ON
ON
Z
Z
Z
Z
X X 0
1
1
1
1
0
0
1
Z
Z
Z
ON
ON
ON
ON
Z
Z
ON
Z
X X 0
1
1
1
1
0
1
0
Z
Z
Z
ON
ON
ON
ON
Z
ON
Z
Z
MC68HC05SB7
REV 2.1
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MOTOROLA
15-9
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 0
1
1
1
1
0
1
1
Z
Z
Z
ON
ON
ON
ON
Z
ON
ON
Z
X X 0
1
1
1
1
1
0
0
Z
Z
Z
ON
ON
ON
ON
ON
Z
Z
Z
X X 0
1
1
1
1
1
0
1
Z
Z
Z
ON
ON
ON
ON
ON
Z
ON
Z
X X 0
1
1
1
1
1
1
0
Z
Z
Z
ON
ON
ON
ON
ON
ON
Z
Z
X X 0
1
1
1
1
1
1
1
Z
Z
Z
ON
ON
ON
ON
ON
ON
ON
Z
X X 1
0
0
0
0
0
0
0
Z
Z
ON
Z
Z
Z
Z
Z
Z
Z
Z
X X 1
0
0
0
0
0
0
1
Z
Z
ON
Z
Z
Z
Z
Z
Z
ON
Z
X X 1
0
0
0
0
0
1
0
Z
Z
ON
Z
Z
Z
Z
Z
ON
Z
Z
X X 1
0
0
0
0
0
1
1
Z
Z
ON
Z
Z
Z
Z
Z
ON
ON
Z
X X 1
0
0
0
0
1
0
0
Z
Z
ON
Z
Z
Z
Z
ON
Z
Z
Z
X X 1
0
0
0
0
1
0
1
Z
Z
ON
Z
Z
Z
Z
ON
Z
ON
Z
X X 1
0
0
0
0
1
1
0
Z
Z
ON
Z
Z
Z
Z
ON
ON
Z
Z
X X 1
0
0
0
0
1
1
1
Z
Z
ON
Z
Z
Z
Z
ON
ON
ON
Z
X X 1
0
0
0
1
0
0
0
Z
Z
ON
Z
Z
Z
ON
Z
Z
Z
Z
X X 1
0
0
0
1
0
0
1
Z
Z
ON
Z
Z
Z
ON
Z
Z
ON
Z
X X 1
0
0
0
1
0
1
0
Z
Z
ON
Z
Z
Z
ON
Z
ON
Z
Z
X X 1
0
0
0
1
0
1
1
Z
Z
ON
Z
Z
Z
ON
Z
ON
ON
Z
X X 1
0
0
0
1
1
0
0
Z
Z
ON
Z
Z
Z
ON
ON
Z
Z
Z
X X 1
0
0
0
1
1
0
1
Z
Z
ON
Z
Z
Z
ON
ON
Z
ON
Z
X X 1
0
0
0
1
1
1
0
Z
Z
ON
Z
Z
Z
ON
ON
ON
Z
Z
X X 1
0
0
0
1
1
1
1
Z
Z
ON
Z
Z
Z
ON
ON
ON
ON
Z
X X 1
0
0
1
0
0
0
0
Z
Z
ON
Z
Z
ON
Z
Z
Z
Z
Z
X X 1
0
0
1
0
0
0
1
Z
Z
ON
Z
Z
ON
Z
Z
Z
ON
Z
X X 1
0
0
1
0
0
1
0
Z
Z
ON
Z
Z
ON
Z
Z
ON
Z
Z
X X 1
0
0
1
0
0
1
1
Z
Z
ON
Z
Z
ON
Z
Z
ON
ON
Z
X X 1
0
0
1
0
1
0
0
Z
Z
ON
Z
Z
ON
Z
ON
Z
Z
Z
X X 1
0
0
1
0
1
0
1
Z
Z
ON
Z
Z
ON
Z
ON
Z
ON
Z
X X 1
0
0
1
0
1
1
0
Z
Z
ON
Z
Z
ON
Z
ON
ON
Z
Z
X X 1
0
0
1
0
1
1
1
Z
Z
ON
Z
Z
ON
Z
ON
ON
ON
Z
X X 1
0
0
1
1
0
0
0
Z
Z
ON
Z
Z
ON
ON
Z
Z
Z
Z
X X 1
0
0
1
1
0
0
1
Z
Z
ON
Z
Z
ON
ON
Z
Z
ON
Z
MOTOROLA
15-10
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 1
0
0
1
1
0
1
0
Z
Z
ON
Z
Z
ON
ON
Z
ON
Z
Z
X X 1
0
0
1
1
0
1
1
Z
Z
ON
Z
Z
ON
ON
Z
ON
ON
Z
X X 1
0
0
1
1
1
0
0
Z
Z
ON
Z
Z
ON
ON
ON
Z
Z
Z
X X 1
0
0
1
1
1
0
1
Z
Z
ON
Z
Z
ON
ON
ON
Z
ON
Z
X X 1
0
0
1
1
1
1
0
Z
Z
ON
Z
Z
ON
ON
ON
ON
Z
Z
X X 1
0
0
1
1
1
1
1
Z
Z
ON
Z
Z
ON
ON
ON
ON
ON
Z
X X 1
0
1
0
0
0
0
0
Z
Z
ON
Z
ON
Z
Z
Z
Z
Z
Z
X X 1
0
1
0
0
0
0
1
Z
Z
ON
Z
ON
Z
Z
Z
Z
ON
Z
X X 1
0
1
0
0
0
1
0
Z
Z
ON
Z
ON
Z
Z
Z
ON
Z
Z
X X 1
0
1
0
0
0
1
1
Z
Z
ON
Z
ON
Z
Z
Z
ON
ON
Z
X X 1
0
1
0
0
1
0
0
Z
Z
ON
Z
ON
Z
Z
ON
Z
Z
Z
X X 1
0
1
0
0
1
0
1
Z
Z
ON
Z
ON
Z
Z
ON
Z
ON
Z
X X 1
0
1
0
0
1
1
0
Z
Z
ON
Z
ON
Z
Z
ON
ON
Z
Z
X X 1
0
1
0
0
1
1
1
Z
Z
ON
Z
ON
Z
Z
ON
ON
ON
Z
X X 1
0
1
0
1
0
0
0
Z
Z
ON
Z
ON
Z
ON
Z
Z
Z
Z
X X 1
0
1
0
1
0
0
1
Z
Z
ON
Z
ON
Z
ON
Z
Z
ON
Z
X X 1
0
1
0
1
0
1
0
Z
Z
ON
Z
ON
Z
ON
Z
ON
Z
Z
X X 1
0
1
0
1
0
1
1
Z
Z
ON
Z
ON
Z
ON
Z
ON
ON
Z
X X 1
0
1
0
1
1
0
0
Z
Z
ON
Z
ON
Z
ON
ON
Z
Z
Z
X X 1
0
1
0
1
1
0
1
Z
Z
ON
Z
ON
Z
ON
ON
Z
ON
Z
X X 1
0
1
0
1
1
1
0
Z
Z
ON
Z
ON
Z
ON
ON
ON
Z
Z
X X 1
0
1
0
1
1
1
1
Z
Z
ON
Z
ON
Z
ON
ON
ON
ON
Z
X X 1
0
1
1
0
0
0
0
Z
Z
ON
Z
ON
ON
Z
Z
Z
Z
Z
X X 1
0
1
1
0
0
0
1
Z
Z
ON
Z
ON
ON
Z
Z
Z
ON
Z
X X 1
0
1
1
0
0
1
0
Z
Z
ON
Z
ON
ON
Z
Z
ON
Z
Z
X X 1
0
1
1
0
0
1
1
Z
Z
ON
Z
ON
ON
Z
Z
ON
ON
Z
X X 1
0
1
1
0
1
0
0
Z
Z
ON
Z
ON
ON
Z
ON
Z
Z
Z
X X 1
0
1
1
0
1
0
1
Z
Z
ON
Z
ON
ON
Z
ON
Z
ON
Z
X X 1
0
1
1
0
1
1
0
Z
Z
ON
Z
ON
ON
Z
ON
ON
Z
Z
X X 1
0
1
1
0
1
1
1
Z
Z
ON
Z
ON
ON
Z
ON
ON
ON
Z
X X 1
0
1
1
1
0
0
0
Z
Z
ON
Z
ON
ON
ON
Z
Z
Z
Z
MC68HC05SB7
REV 2.1
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MOTOROLA
15-11
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 1
0
1
1
1
0
0
1
Z
Z
ON
Z
ON
ON
ON
Z
Z
ON
Z
X X 1
0
1
1
1
0
1
0
Z
Z
ON
Z
ON
ON
ON
Z
ON
Z
Z
X X 1
0
1
1
1
0
1
1
Z
Z
ON
Z
ON
ON
ON
Z
ON
ON
Z
X X 1
0
1
1
1
1
0
0
Z
Z
ON
Z
ON
ON
ON
ON
Z
Z
Z
X X 1
0
1
1
1
1
0
1
Z
Z
ON
Z
ON
ON
ON
ON
Z
ON
Z
X X 1
0
1
1
1
1
1
0
Z
Z
ON
Z
ON
ON
ON
ON
ON
Z
Z
X X 1
0
1
1
1
1
1
1
Z
Z
ON
Z
ON
ON
ON
ON
ON
ON
Z
X X 1
!
0
0
0
0
0
0
Z
Z
ON
ON
Z
Z
Z
Z
Z
Z
Z
X X 1
1
0
0
0
0
0
1
Z
Z
ON
ON
Z
Z
Z
Z
Z
ON
Z
X X 1
1
0
0
0
0
1
0
Z
Z
ON
ON
Z
Z
Z
Z
ON
Z
Z
X X 1
1
0
0
0
0
1
1
Z
Z
ON
ON
Z
Z
Z
Z
ON
ON
Z
X X 1
1
0
0
0
1
0
0
Z
Z
ON
ON
Z
Z
Z
ON
Z
Z
Z
X X 1
1
0
0
0
1
0
1
Z
Z
ON
ON
Z
Z
Z
ON
Z
ON
Z
X X 1
1
0
0
0
1
1
0
Z
Z
ON
ON
Z
Z
Z
ON
ON
Z
Z
X X 1
1
0
0
0
1
1
1
Z
Z
ON
ON
Z
Z
Z
ON
ON
ON
Z
X X 1
1
0
0
1
0
0
0
Z
Z
ON
ON
Z
Z
ON
Z
Z
Z
Z
X X 1
1
0
0
1
0
0
1
Z
Z
ON
ON
Z
Z
ON
Z
Z
ON
Z
X X 1
1
0
0
1
0
1
0
Z
Z
ON
ON
Z
Z
ON
Z
ON
Z
Z
X X 1
1
0
0
1
0
1
1
Z
Z
ON
ON
Z
Z
ON
Z
ON
ON
Z
X X 1
1
0
0
1
1
0
0
Z
Z
ON
ON
Z
Z
ON
ON
Z
Z
Z
X X 1
1
0
0
1
1
0
1
Z
Z
ON
ON
Z
Z
ON
ON
Z
ON
Z
X X 1
1
0
0
1
1
1
0
Z
Z
ON
ON
Z
Z
ON
ON
ON
Z
Z
X X 1
1
0
0
1
1
1
1
Z
Z
ON
ON
Z
Z
ON
ON
ON
ON
Z
X X 1
1
0
1
0
0
0
0
Z
Z
ON
ON
Z
ON
Z
Z
Z
Z
Z
X X 1
1
0
1
0
0
0
1
Z
Z
ON
ON
Z
ON
Z
Z
Z
ON
Z
X X 1
1
0
1
0
0
1
0
Z
Z
ON
ON
Z
ON
Z
Z
ON
Z
Z
X X 1
1
0
1
0
0
1
1
Z
Z
ON
ON
Z
ON
Z
Z
ON
ON
Z
X X 1
1
0
1
0
1
0
0
Z
Z
ON
ON
Z
ON
Z
ON
Z
Z
Z
X X 1
1
0
1
0
1
0
1
Z
Z
ON
ON
Z
ON
Z
ON
Z
ON
Z
X X 1
1
0
1
0
1
1
0
Z
Z
ON
ON
Z
ON
Z
ON
ON
Z
Z
X X 1
1
0
1
0
1
1
1
Z
Z
ON
ON
Z
ON
Z
ON
ON
ON
Z
MOTOROLA
15-12
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 1
1
0
1
1
0
0
0
Z
Z
ON
ON
Z
ON
ON
Z
Z
Z
Z
X X 1
1
0
1
1
0
0
1
Z
Z
ON
ON
Z
ON
ON
Z
Z
ON
Z
X X 1
1
0
1
1
0
1
0
Z
Z
ON
ON
Z
ON
ON
Z
ON
Z
Z
X X 1
1
0
1
1
0
1
1
Z
Z
ON
ON
Z
ON
ON
Z
ON
ON
Z
X X 1
1
0
1
1
1
0
0
Z
Z
ON
ON
Z
ON
ON
ON
Z
Z
Z
X X 1
1
0
1
1
1
0
1
Z
Z
ON
ON
Z
ON
ON
ON
Z
ON
Z
X X 1
1
0
1
1
1
1
0
Z
Z
ON
ON
Z
ON
ON
ON
ON
Z
Z
X X 1
1
0
1
1
1
1
1
Z
Z
ON
ON
Z
ON
ON
ON
ON
ON
Z
X X 1
1
1
0
0
0
0
0
Z
Z
ON
ON
ON
Z
Z
Z
Z
Z
Z
X X 1
1
1
0
0
0
0
1
Z
Z
ON
ON
ON
Z
Z
Z
Z
ON
Z
X X 1
1
1
0
0
0
1
0
Z
Z
ON
ON
ON
Z
Z
Z
ON
Z
Z
X X 1
1
1
0
0
0
1
1
Z
Z
ON
ON
ON
Z
Z
Z
ON
ON
Z
X X 1
1
1
0
0
1
0
0
Z
Z
ON
ON
ON
Z
Z
ON
Z
Z
Z
X X 1
1
1
0
0
1
0
1
Z
Z
ON
ON
ON
Z
Z
ON
Z
ON
Z
X X 1
1
1
0
0
1
1
0
Z
Z
ON
ON
ON
Z
Z
ON
ON
Z
Z
X X 1
1
1
0
0
1
1
1
Z
Z
ON
ON
ON
Z
Z
ON
ON
ON
Z
X X 1
1
1
0
1
0
0
0
Z
Z
ON
ON
ON
Z
ON
Z
Z
Z
Z
X X 1
1
1
0
1
0
0
1
Z
Z
ON
ON
ON
Z
ON
Z
Z
ON
Z
X X 1
1
1
0
1
0
1
0
Z
Z
ON
ON
ON
Z
ON
Z
ON
Z
Z
X X 1
1
1
0
1
0
1
1
Z
Z
ON
ON
ON
Z
ON
Z
ON
ON
Z
X X 1
1
1
0
1
1
0
0
Z
Z
ON
ON
ON
Z
ON
ON
Z
Z
Z
X X 1
1
1
0
1
1
0
1
Z
Z
ON
ON
ON
Z
ON
ON
Z
ON
Z
X X 1
1
1
0
1
1
1
0
Z
Z
ON
ON
ON
Z
ON
ON
ON
Z
Z
X X 1
1
1
0
1
1
1
1
Z
Z
ON
ON
ON
Z
ON
ON
ON
ON
Z
X X 1
1
1
1
0
0
0
0
Z
Z
ON
ON
ON
ON
Z
Z
Z
Z
Z
X X 1
1
1
1
0
0
0
1
Z
Z
ON
ON
ON
ON
Z
Z
Z
ON
Z
X X 1
1
1
1
0
0
1
0
Z
Z
ON
ON
ON
ON
Z
Z
ON
Z
Z
X X 1
1
1
1
0
0
1
1
Z
Z
ON
ON
ON
ON
Z
Z
ON
ON
Z
X X 1
1
1
1
0
1
0
0
Z
Z
ON
ON
ON
ON
Z
ON
Z
Z
Z
X X 1
1
1
1
0
1
0
1
Z
Z
ON
ON
ON
ON
Z
ON
Z
ON
Z
X X 1
1
1
1
0
1
1
0
Z
Z
ON
ON
ON
ON
Z
ON
ON
Z
Z
MC68HC05SB7
REV 2.1
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
ANALOG SUBSYSTEM
VSS
MOTOROLA
15-13
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
M M M
B
R
U U U
R
E
X X X
E
F
7 6 5
F
M
U
X
4
M
U
X
3
M
U
X
2
M
U
X
1
M
U
VDD
X
0
X X 1
1
1
1
0
1
1
1
Z
Z
ON
ON
ON
ON
Z
ON
ON
ON
Z
X X 1
1
1
1
1
0
0
0
Z
Z
ON
ON
ON
ON
ON
Z
Z
Z
Z
X X 1
1
1
1
1
0
0
1
Z
Z
ON
ON
ON
ON
ON
Z
Z
ON
Z
X X 1
1
1
1
1
0
1
0
Z
Z
ON
ON
ON
ON
ON
Z
ON
Z
Z
X X 1
1
1
1
1
0
1
1
Z
Z
ON
ON
ON
ON
ON
Z
ON
ON
Z
X X 1
1
1
1
1
1
0
0
Z
Z
ON
ON
ON
ON
ON
ON
Z
Z
Z
X X 1
1
1
1
1
1
0
1
Z
Z
ON
ON
ON
ON
ON
ON
Z
ON
Z
X X 1
1
1
1
1
1
1
0
Z
Z
ON
ON
ON
ON
ON
ON
ON
Z
Z
X X 1
1
1
1
1
1
1
1
Z
Z
ON
ON
ON
ON
ON
ON
ON
ON
Z
0
1
0
0
0
0
0
0
0
0
Z
ON
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
0
0
0
0
0
0
0
0
0
ON
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VIB
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
VSS
X = Don’t Care
Z = High Impedance
15.2
ANALOG CONTROL REGISTER
The Analog Control Register (ACR) controls the power up, interrupt and flag operation. The analog subsystem draws about 470 µA of current while it is operating.
The resulting power consumption can be reduced by powering down the analog
subsystem when not in use. This can be done by clearing two enable bits (ISEN
and CPEN) in the ACR at $001D. Since these bits are cleared following a reset,
the voltage comparator and the charge current source will be powered down following a reset of the device.
The control bits in the ACR are shown in Figure 15-2. All the bits in this register
are cleared by a reset of the device.
ACR
R
$001D
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
CHG
ATD2
ATD1
ICEN
CPIE
CPEN
0
0
0
0
0
0
BIT 1
BIT 0
ISEN
0
0
Figure 15-5. Analog Control Register (ACR)
MOTOROLA
15-14
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
CHG
The CHG enable bit allows direct control of the charge current source and the
discharge device; and also reflects the state of the discharge device. This bit is
cleared if the ISEN enable bit is also cleared. This bit is cleared by a reset of
the device.
1 = The charge current source is sourcing current out of the CAP pin.
Writing a logical one enables the charging current out of the CAP
pin, if the ISEN bit is also set.
0 = The discharge device is sinking current into the CAP pin. Writing a
logical zero disables the charging current and enables the
discharging current into the CAP pin.
ATD1:2
The ATD1:2 enable bits select one of the four operating modes used for making
A/D conversions via the single-slope method.These four modes are given in
Table 15-3. These bits have no effect if the ISEN enable bit is cleared. These
bits are cleared by a reset of the device; and thereby returning the analog subsystem to the manual A/D conversion method.
Table 15-3. A/D Conversion Options
A/D
Option
Mode
Charge
Control
Disabled
Current
Source and
Discharge
Disabled
0
A/D Options
ISEN
X
X
X
Current control disabled, no source or sink current.
1
0
0
0
Begin sinking current when the CHG bit is
cleared; and continue to sink current until the
CHG bit is set.
1
0
0
1
Begin sourcing current when the CHG bit is set;
and continue to source current until the CHG bit is
cleared.
0
Begin sinking current when the CHG bit is
cleared; and continue to sink current until the
CHG bit is set. (The CHG bit is cleared by writing
a logical zero to it; or when the CPF flag bit is
set.)
Manual
Charge and
Discharge
2
0
1
Manual
Charge and
Automatic
Discharge
Automatic
Charge and
Discharge
(TOF-ICF)
Synchronized
to Timer
MC68HC05SB7
REV 2.1
Current Flow To/From CAP
CHG
0
1
1
ATD2 ATD1
1
0
1
1
Begin sourcing current when the CHG bit is set;
and continue to source current until the CHG bit is
cleared. (The CHG bit is cleared by writing a logical zero to it; or when the CPF flag bit is set.)
1
1
0
0
The CHG bit remains cleared as long as current
is being sunk. Begin sourcing current when the
next Timer TOF occurs.
1
1
0
1
The CHG bit remains set as long as current is
being sourced. Begin sinking current when the
next Timer ICF occurs.
ANALOG SUBSYSTEM
MOTOROLA
15-15
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-3. A/D Conversion Options
A/D
Option
Mode
Charge
Control
3
Automatic
Charge and
Discharge
(OCF-ICF)
Synchronized
to Timer
A/D Options
ISEN
ATD2 ATD1
Current Flow To/From CAP
CHG
1
1
1
0
The CHG bit remains cleared as long as current
is being sunk. Begin sourcing current when the
next Timer OCF occurs.
1
1
1
1
The CHG bit remains set as long as current is
being sourced. Begin sinking current when the
next Timer ICF occurs.
ICEN
This is a read/write bit that enables a voltage comparison to trigger the input
capture register of the programmable Timer when the CPF flag bit is set. Therefore an A/D conversion could be started by receiving an OCF or TOF from the
programmable Timer; and then terminated when the voltage on the external
ramping capacitor reaches the level of the unknown voltage. The time of termination will be stored in the 16-bit buffer located at $0014 and $0015. This bit is
automatically set whenever Mode 2 or 3 is selected by setting the ATD2 control
bit. This bit is cleared by a reset of the device.
1 = Connects the CPF flag bit to the Timer input capture register.
0 = Connects the PB1/TCAP pin to the Timer input capture register.
NOTE
When the ICEN bit is set the input capture function of the programmable Timer is
not connected to the PB1/TCAP pin but is driven by the CPF output flag from the
comparator. To return to capturing times from external events, the ICEN bit must
first be cleared before the timed event occurs.
NOTE
The TCSEL bit in the Miscellaneous Control Register (bit 2 in $0B) must be
cleared for ICEN control. TCSEL=1 will select the SCL signal from the SMBus as
16-bit Timer Input Capture source, irrespective of ICEN setting.
CPIE
This is a read/write bit that enables an analog interrupt when the CPF flag bits
is set to a logical one. This bit is cleared by a reset of the device.
1 = Enables analog interrupt when comparator flag bit is set.
0 = Disables analog interrupt when comparator flag bit is set.
MOTOROLA
15-16
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
CPEN
The CPEN enable bit will power down voltage comparator in the analog subsystem. Powering down a comparator will drop the supply current by about
100µA. This bit is cleared by a reset of the device.
1 = Writing a logical one powers up voltage comparator.
0 = Writing a logical zero powers down voltage comparator
NOTE
The voltage comparator powers up slower than digital logic; and its output may go
through indeterminate states which might set the CPF flag. It is therefore
recommended to power up the charge current source first (ISEN); then to power
up the comparator, and finally clear the bit by writing a logic one to the CPFR bit in
the ACR.
ISEN
The ISEN enable bit will power down the charge current source and disable the
discharge device in the analog subsystem. Powering down the current source
will drop the supply current by about 200 µA. This bit is cleared by a reset of the
device.
1 = Writing a logical one powers up the ramping current source and
enables the discharge device on the CAP pin.
0 = Writing a logical zero powers down the ramping current source and
disables the discharge device on the CAP pin.
NOTE
The analog subsystem has support circuitry which draws about 70µA of current.
This current will be powered down if the comparator and the charge current
source are powered down (ISEN and CPEN all cleared). Powering up the
comparator or the charge current source will activate the support circuitry.
15.3
ANALOG STATUS REGISTER
The Analog Status Register (ASR) controls the interrupt and flag operation. The
control bits in the ASR are shown in Figure 15-2. All the bits in this register are
cleared by a reset of the device.
BIT 7
ASR
R
$001E
reset:
BIT 6
CPF
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
0
0
0
CPFR
W
0
0
0
Figure 15-6. Analog Status Register
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-17
GENERAL RELEASE SPECIFICATION
August 27, 1998
CPF
This read-only flag bit is set when the voltage on the positive input of comparator rises above the voltage on its negative input. This bit is reset by writing a
logical one to the CPFR reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = The voltage on positive input of comparator was above the voltage
on its negative input since CPF had been cleared.
0 = The voltage on positive input of comparator has not been above the
voltage on its negative input since CPF had been cleared.
CPFR
Writing a logical one to this write-only flag clears the CPF flag in the ASR. Writing a logical zero to this bit has no effect. Reading the CPFR bit will return a
logical zero. By default this bit looks cleared following a reset of the device.
1 = Clears the CPF flag bit.
0 = No effect.
NOTE
The CPFR bit should be written with a logical one following a power up of the
comparator. This will clear out any latched CPF flag bit which might have been set
during the slower power up sequence of the analog circuitry.
If both inputs to the comparator are above the maximum common-mode input
voltage (VDD –1.5V) the output of the comparator is indeterminate and may set the
comparator flag. Applying a reset to the device may only temporarily clear this flag
as long as both inputs of a comparator remain above the maximum commonmode input voltages.
MOTOROLA
15-18
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
15.4
GENERAL RELEASE SPECIFICATION
A/D CONVERSION METHODS
The control bits in the ACR provide various options to charge or discharge current
through the CAP pin in order to perform single-slope A/D conversions using an
external capacitor from the CAP pin to VSS as shown in Figure 15-7. The various
A/D conversion triggering options are given in Table 15-3.
VDD – 1.5 VDC
Charge Time = C x VX
I
UNKNOWN VOLTAGE ON (–) INPUT
VOLTAGE ON
CAPACITOR
CONNECTED
TO (+) INPUT
CHARGE TIME
TO MATCH UNKNOWN
DISCHARGE TIME
TO RESET CAPACITOR
MAXIMUM CHARGE TIME
TO VDD – 1.5 VDC
+5V
TM
Using VDD
as Voltage
Reference
VDD
PB7/AN0
UNKNOWN
SIGNALS
PB6/AN1
PB5/AN2
MC68HC05SB7
PB4/AN3
RAMP
CAP
CAP
VSS
+5V
TM
Using an
External Voltage
Reference
VDD
PB7/AN0
UNKNOWN
SIGNALS
PB6/AN1
PB5/AN2
REFERENCE
VOLTAGE
MC68HC05SB7
PB4/AN3
RAMP
CAP
CAP
VSS
Figure 15-7. Single-Slope A/D Conversion Method
The top three bits of the ACR control the charging and discharging current into or
out of the CAP pin. These three bits will have no affect on the CAP pin if the ISEN
enable bit is cleared. Any clearing of the ISEN bit will immediately disable both the
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-19
GENERAL RELEASE SPECIFICATION
August 27, 1998
charge current source and the discharge device. Since all these bits and the ISEN
bit are cleared when the device is reset, the MC68HC05SB7 starts with the
charge and discharge function disabled.
The length of time required to reach the maximum voltage to be measured will
determine the resolution of the reading. The time to ramp the external capacitor
voltage to match the maximum voltage is dependent on:
•
Desired resolution.
•
Clock rate for timing function.
•
Any prescaling of the clock to the timing function.
•
Charging current to external capacitor.
•
Value of the external capacitor.
The values of each parameter are related by the general equation:
C × V MAX
t CHG = ---------------------I CHG
Each parameter can also be expressed by the following equations:
P×N
t CHG = ------------f OSC
I CHG × P × N
V MAX = ----------------------------C × f OSC
V MAX × C × f OSC
N = -------------------------------------I CHG × P
I CHG × N × P
C = ----------------------------V MAX × f OSC
where the signal names and parameters used are given in Table 15-4.
NOTE
Noise on the system ground or the external ramping capacitor can cause the
comparator to trip prematurely. Therefore in any given application it is best to use
the fastest possible ramp rate (shortest possible time).
NOTE
The value of any capacitor connected directly to the CAP pin should be limited to
less than 2µF. Larger capacitances will create signal noise.
MOTOROLA
15-20
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
NOTE
Sufficient time should be allowed to discharge the external capacitor or
subsequent charge times will be shortened with resultant errors in timing
conversion.
NOTE
If the unknown voltage applied to the comparator is greater than its commonmode range (VDD –1.5 volts) the external capacitor will try to charge to the same
level. This will cause both comparator inputs to be above the common-mode
range and the output will be indeterminate. All A/D conversion software methods
should have a maximum time check to determine if this case is occurring.
Table 15-4. A/D Conversion Signals and Definitions
Name
Function
Conditions
ICHG
Charging current on external ramping capacitor
ICHG = 80 - 120 µA
IDIS
Discharge current on external ramping capacitor
IDIS > 1 mA
VCAP
VX
Voltage on external ramping capacitor
Voltage of unknown on (–) input of voltage comparator
VSS < VCAP < (VDD – 1.5)
VSS < VX < (VDD –1.5)
VMAX
Maximum voltage on external ramping capacitor
VMAX = VDD – 1.0
tCHG
TIme to charge external capacitor
∆t from VSS to VX
tDIS
Time to discharge external capacitor
C
Capacitance of external ramping capacitor
N
Number of counts for ICHG to charge C to VX
P
Prescaler into timing function
fOSC
Clock source frequency (excluding any prescaling)
∆t from VMAX to VSS
0.001 to 1.000 µF
0 to 65536
fOSC ÷ loop time for software timing
fOSC ÷ 8 for Core Timer
fOSC ÷ 8 for Programmable TImer
0 to 4.2 MHz
Table 15-5 gives examples of voltage ranges, resolution, ramp times and capacitor sizes for various conversion methods.
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-21
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-5. Sample Conversion Timing
Bits
Counts
VMAX
(VDC)
A/D Method
Clock Source
fOSC
(MHz)
tCHG
(µs)
C
(µF)
8
256
3.5
Software Loop (10 cycles)
Mode 0 (manual)
Ext Pin Oscillator
2.0
2560
0.073
VCO
0.5
4096
0.117
1.0
2048
0.059
2.0
1024
0.029
4.0
512
0.015
0.5
16384
0.468
1.0
8192
0.234
2.0
4096
0.117
4.0
2048
0.059
0.5
65536
1.872
1.0
32768
0.936
2.0
16384
0.468
4.0
8192
0.234
8
256
3.5
Programmable Timer,
Mode 1 (TOF to ICF)
Ext Pin Oscillator
VCO
10
1024
3.5
Programmable Timer,
Mode 1 (TOF to ICF)
Ext Pin Oscillator
VCO
12
4096
3.5
Programmable Timer,
Mode 1 (TOF to ICF)
Ext Pin Oscillator
The general architecture of the MC68HC05SB7 and mode selection bits in the
ACR allow four methods based on simple single-slope A/D conversion. Each of
these methods is shown in the following figures:
•
Manual start and stop (Mode 0) Figure 15-8.
•
Manual start and automatic discharge (Mode 1) Figure 15-9.
•
Automatic start and stop from TOF to ICF (Mode 2) Figure 15-10.
•
Automatic start and stop from OCF to ICF (Mode 3) Figure 15-11.
The description of the signals and parameters used in these figures are given in
Table 15-4.
MOTOROLA
15-22
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
tDIS
tDIS
tDIS
tMAX
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG X ICHG
CX
CHG
COMP
TOF
OCF
ICF
0
1
2
3
4
Software/Hardware Action
5
1
Point
Action
Dependent Variable(s)
0
Begin initial Discharge and select
Mode 0 by clearing the CHG, ATD2
and ATD1 control bits in the ACR.
Software write.
Software.
1
VCAP falls to VSS.
Wait out minimum tDIS time.
VMAX, IDIS, CX.
2
Stop Discharge and begin Charge
by setting CHG control bit in ACR.
Software write.
Software.
3
VCAP rises to VX and comparator
output trips, setting CPF.
Wait out tCHG time.
VX, ICHG, CX.
4
VCAP Reaches VMAX.
Wait out tCHG time.
VMAX, ICHG, CX.
5
Begin next Discharge by clearing
the CHG control bit in the ACR.
Software write.
Software.
Figure 15-8. A/D Conversion - Full Manual Control (Mode 0)
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-23
GENERAL RELEASE SPECIFICATION
August 27, 1998
tDIS
tDIS
tDIS
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG X ICHG
CX
CHG
COMP
TOF
OCF
ICF
0
1
2
3
1
Software/Hardware Action
2
Point
Action
Dependent Variable(s)
0
Begin initial Discharge and select
Mode 1 by clearing CHG and ATD2;
and setting ATD1 in the ACR.
Software write.
Software.
1
VCAP falls to VSS.
Wait out minimum tDIS time.
VMAX, IDIS, CX.
2
Stop Discharge and begin Charge
by setting CHG control bit in ACR.
Software write.
Software.
3
VCAP rises to VX and comparator
output trips, setting CPF which
clears CHG control bit in the ACR.
Wait out tCHG time.
CPF clears CHG control bit.
VX, ICHG, CX.
Figure 15-9. A/D Conversion - Manual/Auto Discharge Control (Mode 1)
MOTOROLA
15-24
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
tDIS
tDIS
tDIS
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG X ICHG
CX
CHG
COMP
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
Software/Hardware Action
2
Point
Action
Dependent Variable(s)
0
Begin initial Discharge and select
Mode 2 by clearing CHG and ATD1
and setting ATD2 in the ACR.
Software write.
(ICEN bit also set)
Software.
1
VCAP falls to VSS.
Wait out minimum tDIS time.
VMAX, IDIS, CX.
2
Stop Discharge and begin Charge
when the next TOF sets the CHG
control bit in ACR.
Timer TOF sets the CHG control bit
in the ACR.
Free-running Timer
counter overflow, fOSC, P.
3
VCAP rises to VX and comparator
output trips, setting CPF which
causes an ICF from the Timer and
clears the CHG control bit in ACR.
Wait out tCHG time.
Timer ICF clears the CHG control
bit in the ACR.
VX, ICHG, CX.
Figure 15-10. A/D Conversion - TOF/ICF Control (Mode 2)
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-25
GENERAL RELEASE SPECIFICATION
August 27, 1998
tDIS
tDIS
tDIS
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG X ICHG
CX
CHG
COMP
(TCAP)
TOF
OCF
ICF
0
Point
1
2
3
Action
1
Software/Hardware Action
3
Dependent Variable(s)
0
Begin initial Discharge and select
Mode 3 by clearing CHG and setting ATD2 and ATD1 in the ACR.
Software write.
(ICEN bit also set)
Software.
1
VCAP falls to VSS. Set Timer output
compare registers (OCRU, OCRL)
to desired charge start time.
Wait out minimum tDIS time.
Software write to OCRH, OCRL.
VMAX, IDIS, CX, Software.
2
Stop Discharge and begin Charge
when the next OCF sets the CHG
control bit in ACR.
Timer OCF sets the CHG control bit
in the ACR.
Free-running Timer
counter overflow, fOSC, P.
3
VCAP rises to VX and comparator
output trips, setting CPF which
causes an ICF from the Timer and
clears the CHG control bit in ACR.
Wait out tCHG time.
Timer ICF clears the CHG control
bit in the ACR.
VX, ICHG, CX.
Figure 15-11. A/D Conversion - OCF/ICF Control (Mode 3)
MOTOROLA
15-26
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
15.5
GENERAL RELEASE SPECIFICATION
VOLTAGE MEASUREMENT METHODS
The various methods for obtaining a voltage measurement can use software techniques to express these voltages as absolute or ratiometric readings.
NOTE
All A/D conversion methods should include a test for a maximum elapsed time in
order to detect error cases where the inputs may be outside of the design
specification.
15.5.1 Absolute Voltage Readings
The absolute value of a voltage measurement can be calculated in software by
first taking a reference reading from a fixed source and then comparing subsequent unknown voltages to that reading as a percentage of the reference voltage
multiplied times the known reference value.
The accuracy of absolute readings will depend on the error sources taken into
account using the features of the analog subsystem and appropriate software as
described in Table 15-6. As can be seen from this table, most of the errors can be
reduced by frequent comparisons to a known voltage, use of the inverted comparator inputs, and averaging of multiple samples.
Table 15-6. Absolute Voltage Reading Errors
Error Source
Accuracy Improvements Possible
In Hardware
In Software
Change in
Reference Voltage
Provide closer tolerance reference
Calibration and storage of
reference source over temperature
and supply voltage
Change in Magnitude of
Ramp Current Source
Not adjustable
Compare unknown with recent
measurement from reference
Non-Linearity of Ramp
Current Source vs. Voltage
Not adjustable
Calibration and storage of voltages
at 1/4, 1/2, 3/4 and FS
Change in Magnitude of
Ramp Capacitor
Provide closer tolerance ramp capacitor
Compare unknown with recent
measurement from reference
Frequency Shift in Internal
Low-Power Oscillator
Use external oscillator with crystal
Compare unknown with recent
measurement from reference
Frequency Shift in
External Oscillator
Provide closer tolerance crystal
Compare unknown with recent
measurement from reference
Sampling Capacitor
Leakage
Use faster conversion times
Compare unknown with recent
measurement from reference
Internal Voltage
Divider Ratio
Not adjustable
Compare unknown with recent
measurement from reference
OR avoid use of divided input
Noise internal to MCU
Close decoupling at VDD and VSS pins
and reduce supply source impedance
Average multiple readings on both the
reference and the unknown voltage
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-27
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-6. Absolute Voltage Reading Errors
Error Source
Noise external to MCU
Accuracy Improvements Possible
In Hardware
In Software
Close decoupling of power supply, low
source impedances, good board layout,
use of multi-layer board
Average multiple readings on both the
reference and the unknown voltage
Internal Absolute Reference
If a stable source of VDD is provided, the reference measurement point can be
internally selected. In this case the reference reading can be taken by setting the
VREF bit and clearing the MUX7:0 bits in the AMUX register. This connects the
channel selection bus to the VDD pin.
Alternatively, the internal bandgap voltage can be used as the reference
measurement point, by setting the IBREF bit in AMUX2 Register and TSEN bit in
the Miscellaneous Control Register.
External Absolute Reference
If a stable external source is provided, the reference measurement point can be
any one of the channel selected pins from PB4 through PB7. In this case the reference reading can be taken by setting the MUX bit in the AMUX which connects
channel selection bus to the pin connected to the external reference source.
15.5.2 Ratiometric Voltage Readings
The ratiometric value of a voltage measurement can be calculated in software by
first taking a reference reading from a reference source and then comparing subsequent unknown voltages to that reading as a percentage of the reference value.
The accuracy of ratiometric readings will depend on variety of sources, but will
generally be better than for absolute readings. Many of these error sources can be
taken into account using the features of the analog subsystem and appropriate
software as described in Table 15-7. As with absolute measurements most of the
errors can be reduced by frequent comparisons to the reference voltage, use of
the inverted comparator inputs, and averaging of multiple samples.
Internal Ratiometric Reference
If readings are to be ratiometric to VDD, the reference measurement point can be
internally selected. In this case the reference reading can be taken by setting the
VREF bit and clearing the MUX7:0 bits in the AMUX register which connects the
channel selection bus to the VDD pin.
Alternatively, the internal bandgap voltage can be used as the reference
measurement point, by setting the IBREF bit in AMUX2 Register and TSEN bit in
the Miscellaneous Control Register.
MOTOROLA
15-28
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
External Ratiometric Reference
If readings are to be ratiometric to some external source, the reference measurement point can be connected to any one of the channel selected pins from PB4
through PB7. In this case the reference reading can be taken by setting the MUX
bit in the AMUX which connects channel selection bus to the pin connected to the
external reference source.
Table 15-7. Ratiometric Voltage Reading Errors
Accuracy Improvements Possible
Error Source
In Hardware
In Software
Change in
Reference Voltage
Not required for ratiometric
Compare unknown with recent
measurement from reference
Change in Magnitude of
Ramp Current Source
Not required for ratiometric
Compare unknown with recent
measurement from reference
Non-Linearity of Ramp
Current Source vs. Voltage
Not adjustable
Calibration and storage of voltages
at 1/4, 1/2, 3/4 and FS
Change in Magnitude of
Ramp Capacitor
Not required for ratiometric
Compare unknown with recent
measurement from reference
Frequency Shift in Internal
Low-Power Oscillator
Not required for ratiometric
Compare unknown with recent
measurement from reference
Frequency Shift in
External Oscillator
Not required for ratiometric
Compare unknown with recent
measurement from reference
Sampling Capacitor
Leakage
Use faster conversion times
Compare unknown with recent
measurement from reference
Internal Voltage Divider
Ratio
Not required for ratiometric
Compare unknown with recent
measurement from reference
Noise internal to MCU
Close decoupling at
VDD and VSS pins and
reduce supply source impedance
Average multiple readings on both the
reference and the unknown voltage
Noise external to MCU
Close decoupling of power supply, low
source impedances, good board layout,
use of multi-layer board
Average multiple readings on both the
reference and the unknown voltage
15.6
VOLTAGE COMPARATOR FEATURES
The internal comparator can also be used as simple voltage comparator.
Voltage Comparator
Voltage comparator can be used as a simple comparator if its charge current
source and discharge device are disabled by clearing the ISEN bit in the ACR. If
ISEN bit is set the internal ramp discharge device connected to CAP may become
active and try to pulldown any voltage source that may be connected to that pin.
Also, since voltage comparator is always connected to two of the Port B I/O pins,
these pins should be configured as inputs and have their software programmable
pulldowns disabled. The required setup to use voltage comparator as a simple
comparator are shown in Table 15-8.
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-29
GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-8. Voltage Comparator Setup Conditions
15.7
Current
Source
Enable
Discharge
Device
Disable
Port B Pin
as Inputs
Prog. Timer
Input Capture
Source
ISEN = 0
ISEN = 0
DDRB4 = 0
DDRB5 = 0
ICEN = 0
CURRENT SOURCE FEATURES
The internal current source connected to the CAP pin supplies about 100 µA of
current when the ramp discharge device is disabled and the current source is
active. Therefore this current source can be used in an application if the ISEN
enable bit is set to power up the current source is enabled by setting the A/D conversion method to manual Mode 0 (ATD1 and ATD2 cleared) and the charge current enabled (CHG set).
15.8
SAMPLE AND HOLD
When using the internal sample capacitor to capture a voltage for later conversion, the HOLD and DHOLD bit must be cleared first before changing any channel
selection. If both the HOLD (or DHOLD) bit and the channel selection are
changed on the same write cycle, the sample may be corrupted during the switching transitions.
NOTE
The sample capacitor can be affected by excessive noise created with respect to
the device’s VSS pin such that it may appear to leak down or charge up depending
on the voltage level stored on the sample capacitor. It is recommended to avoid
switching large currents through the port pins while a voltage is to remain stored
on the same capacitor.
The additional option of adding an offset voltage to the bottom of the sample
capacitor allows unknown voltages near VSS to be sampled and then shifted up
past the comparator offset and the device offset caused by a single VSS return pin.
The offset also provides a means to measure the internal VSS level regardless of
the comparator offset in order to determine NOFF as described in Section 15.5.
15.9
PORT B INTERACTION WITH ANALOG INPUTS
The analog subsystem is connected directly to the Port B I/O pins without any
intervening gates. It is therefore possible to measure the voltages on Port B pins
set as inputs; or to have the analog voltage measurements corrupted by Port B
pins set as outputs.
MOTOROLA
15-30
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
15.9.1 Port B Pins As Inputs
All the Port B pins will power up as inputs or return to inputs following a reset of
the device since the bits in the Port B Data Direction register will be reset.
If any Port B pins are to be used for analog voltage measurements they should be
left as inputs. In this case, not only can the voltage on the pin be measured, but
the “logic” state of the Port B pins to be read from location $0002.
15.10 NOISE SENSITIVITY
In addition to the normal effects of electrical noise on the analog input signal there
can also be other noise related effects caused by the digital-to-analog interface.
Since there is only one VSS return for both the digital and the analog subsystems
on the device, currents in the digital section may affect the analog ground reference within the device. This can add voltage offsets to measured inputs or cause
channel-to-channel crosstalk.
In order to reduce the impact of these effects, there should be no switching of
heavy I/O currents to or from the device while there is a critical analog conversion
or voltage comparison in process. Limiting switched I/O currents to 2 to 4 mA during these times is recommended.
A noise reduction benefit can be gained with 0.1µF bypass capacitors from each
analog input (PB7:4) to the VSS pin. Also, try to keep all the digital power supply or
load currents from passing through any conductors which are the return paths for
an analog signal.
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-31
GENERAL RELEASE SPECIFICATION
MOTOROLA
15-32
August 27, 1998
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 16
PERSONALITY EPROM
This section describes how to program the 64-bit personality EPROM (PEPROM).
Figure 16-1 shows the structure of the bit programmable PEPROM subsystem.
INTERNAL DATA BUS
RESET
PEPRZF
0
0
0
0
0
PEPGM
SINGLE
SENSE
AMPLIFIER
PEDATA
PEPROM STATUS/CONTROL REGISTER
IRQ/VPP
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
COL 7
COL 6
COL 5
COL 4
COL 3
COL 2
8-TO-1 ROW DECODER
AND MULTIPLEXER
PEPROM SELECT REGISTER
VPP SWITCH
ROW ZERO
DECODER
PEB0
PEB1
PEB2
PEB3
PEB4
PEB5
0
8-TO-1 COLUMN DECODER
AND MULTIPLEXER
0
VPP SWITCH
COL 1
COL 0
ROW 7
RESET
INTERNAL DATA BUS
Figure 16-1. Personality EPROM
MC68HC05SB7
REV 2.1
PERSONALITY EPROM
MOTOROLA
16-1
GENERAL RELEASE SPECIFICATION
16.1
August 27, 1998
PEPROM REGISTERS
Two I/O registers control programming and reading of the PEPROM:
•
The PEPROM bit select register (PEBSR).
•
The PEPROM status and control register (PESCR).
16.1.1 PEPROM Bit Select Register (PEBSR)
The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM
array. Reset clears all the bits in the PEPROM bit select register.
PEBSR
R
$000E
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
Figure 16-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not connected to the PEPROM array
These read/write bits are available as storage locations. Reset clears PEB7
and PEB6.
PEB5–PEB0 — PEPROM Bit Select Bits
These read/write bits select one of 64 bits in the PEPROM as shown in
Table 16-1. Bits PEB2–0 select the PEPROM row, and bits PEB5–3 select the
PEPROM column. Reset clears PEB5–PEB0, selecting the PEPROM bit in row
zero, column zero.
16.1.2 PEPROM Status and Control Register (PESCR)
The PEPROM status and control register (PESCR) controls the PEPROM programming voltage. This register also transfers the PEPROM bits to the internal
data bus and contains a flag bit when row zero is selected.
BIT 7
PESCR
R
$000F
W
reset:
BIT 6
PEDATA
U
0
0
BIT 5
PEPGM
0
BIT 4
BIT 3
BIT 2
BIT 1
0
0
0
0
0
0
0
0
BIT 0
PEPRZF
1
U = UNAFFECTED BY RESET
Figure 16-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data
This read-only bit is the state of the PEPROM sense amplifier and shows the
state of the currently selected bit. Reset does not affect the PEDATA bit.
1 = PEPROM data is a logic one.
0 = PEPROM data is a logic zero.
MOTOROLA
16-2
PERSONALITY EPROM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
PEPGM — PEPROM Program Control
This read/write bit controls the switches that apply the programming voltage on
the IRQ/VPP pin to the selected PEPROM cell. Reset clears the PEPGM bit.
1 = Programming voltage applied to array bit.
0 = Programming voltage not applied to array bit.
PEPRZF — PEPROM Row Zero Flag
This read-only bit is set when the PEPROM bit select register selects the first
row (row zero) of the PEPROM array. Selecting any other row clears PEPRZF.
Monitoring PEPRZF can reduce the code needed to access one byte of eight
PEPROM locations. Reset clears the PEPROM bit select register thereby setting the PEPRZF bit by default.
1 = Row zero selected.
0 = Row zero not selected.
Table 16-1. PEPROM Bit Selection
PEBSR
16.2
PEPROM Bit Selected
$00 - $07
Row 0 - Row 7
Column 0
$08 - $0F
Row 0 - Row 7
Column 1
$10 - $17
Row 0 - Row 7
Column 2
$18 - $1F
Row 0 - Row 7
Column 3
$20 - $27
Row 0 - Row 7
Column 4
$28 - $2F
Row 0 - Row 7
Column 5
$30 - $37
Row 0 - Row 7
Column 6
$38 - $3F
Row 0 - Row 7
Column 7
PEPROM PROGRAMMING
The PEPROM can be programmed by user software with the VPP voltage level
applied to the IRQ/VPP pin. The following sequence shows how to program each
PEPROM bit:
1. Select a PEPROM bit by writing to the PEBSR.
2. Set the PEPGM bit in the PESCR.
3. Wait 3 milliseconds.
4. Clear the PEPGM bit.
5. Move to next PEPROM bit to be programmed in step 1.
MC68HC05SB7
REV 2.1
PERSONALITY EPROM
MOTOROLA
16-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
NOTE
While the PEPGM bit is set and the VPP voltage level is applied to the IRQ/VPP
pin, do not access bits that are to be left unprogrammed (erased).
To program the PEPROM, VDD must be greater than 4.5 Vdc.
16.3
PEPROM READING
The following sequence shows how to read the PEPROM:
1. Select a bit by writing to the PEBSR.
2. Read the PEDATA bit in the PESCR.
3. Store the PEDATA bit in RAM or in a register.
4. Select another bit by changing the PEBSR.
5. Continue reading and storing the PEDATA bits until the required
personality EPROM data is retrieved and stored.
Reading the PEPROM is easiest when each PEPROM column contains one byte.
Selecting a row 0 bit selects the first bit, and incrementing the PEPROM bit select
register (PEBSR) selects the next bit in row 1 from the same column. Incrementing PEBSR seven more times selects the remaining bits of the column and ends
up selecting the bit in row 0 of the next column, thereby setting the row 0 flag,
PEPRZF.
NOTE
A PEPROM byte that has been read can be transferred to the personality EPROM
bit select register (PEBSR) so that subsequent reads of the PEBSR quickly yield
that PEPROM byte.
16.4
PEPROM ERASING
MCUs with windowed packages permit PEPROM erasure with ultraviolet light.
Erase the PEPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of a PEPROM bit is a logic
zero.
MOTOROLA
16-4
PERSONALITY EPROM
MC68HC05SB7
REV 2.1
August 27, 1998
16.5
GENERAL RELEASE SPECIFICATION
PEPROM PREPROGRAMMED OPTIONS
The MC68HC05SB7 is available with a factory preprogrammed PEPROM. The following measured parameters are available:
•
The internal VCO minimum frequency: [programmed or left blank]
•
The internal VCO maximum frequency: [programmed or left blank]
•
The internal bandgap reference voltage: [programmed or left blank]
•
The internal temperature sensor voltage: [programmed or left blank]
Each parameter is stored as a 16-bit value in the PEPROM, as shown in the
Table 16-1. Unprogrammed bits are blank, and are available for user
programming.
Table 16-2. PEPROM Preprogrammed Option
PEBSR
(LSB - MSB)
DATA
$00 - $0F
VCO Minimum Frequency (fVCOMIN)
$10 - $1F
VCO Maximum Frequency (fVCOMAX)
$20 - $2F
Internal Bandgap Voltage (VIB)
$30 - $3F
Temperature Sensor Voltage1
Note: 1. measured at 80°C
16.5.1 Data Format in Preprogrammed PEPROM
The 16-bit value is a binary representation of the measured data (4 digits, with the
decimal point removed). Some examples are shown below.
For a measured data for fVCOMIN =1.500MHz, it is converted to 1500 or 5DC (hex)
and the hex data is programmed as 0000 0101 1101 1100.
For a measured data for fVCOMAX =5.800MHz, it is converted to 5800 or 16A8
(hex) and the hex data is programmed as 0001 0110 1010 1000.
For a measured data for VIB =1.211V, it is converted to 1211 or 4BB (hex) and the
hex data is programmed as 0000 0100 1011 1011.
For a measured data for VTEMP =836.0mV, it is converted to 8360 or 20A8 (hex)
and the hex data is programmed as 0010 0000 1010 1000.
MC68HC05SB7
REV 2.1
PERSONALITY EPROM
MOTOROLA
16-5
GENERAL RELEASE SPECIFICATION
MOTOROLA
16-6
August 27, 1998
PERSONALITY EPROM
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 17
INSTRUCTION SET
This section describes the addressing modes and instruction types.
17.1
ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, No Offset
•
Indexed, 8-Bit Offset
•
Indexed, 16-Bit Offset
•
Relative
17.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
17.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
MC68HC05SB7
REV 2.1
INSTRUCTION SET
MOTOROLA
17-1
GENERAL RELEASE SPECIFICATION
August 27, 1998
17.1.3 Direct
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
17.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
17.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
17.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
MOTOROLA
17-2
INSTRUCTION SET
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
17.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
17.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch
condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from
the address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
17.1.9 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
MC68HC05SB7
REV 2.1
INSTRUCTION SET
MOTOROLA
17-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
17.1.10 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 17-1 lists the register/memory instructions.
Table 17-1. Register/Memory Instructions
Instruction
MOTOROLA
17-4
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
INSTRUCTION SET
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
17.1.11 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 17-2 lists the
read-modify-write instructions.
Table 17-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left
ASL
Arithmetic Shift Right
ASR
Clear Bit in Memory
BCLR
Set Bit in Memory
BSET
Clear
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
17.1.12 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding the
MC68HC05SB7
REV 2.1
INSTRUCTION SET
MOTOROLA
17-5
GENERAL RELEASE SPECIFICATION
August 27, 1998
third byte to the program counter if the specified bit tests true. The bit to be tested
and its condition (set or clear) is part of the opcode. The span of branching is from
–128 to +127 from the address of the next location after the branch instruction.
The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 17-3 lists the jump and branch instructions.
Table 17-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
Branch Never
BRN
Branch if Bit Set
MOTOROLA
17-6
Mnemonic
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
INSTRUCTION SET
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
17.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 17-4 lists these instructions.
Table 17-4. Bit Manipulation Instructions
Instruction
Clear Bit
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
BSET
17.1.14 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 17-5, use inherent addressing.
Table 17-5. Control Instructions
Instruction
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
MC68HC05SB7
REV 2.1
Mnemonic
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
INSTRUCTION SET
MOTOROLA
17-7
GENERAL RELEASE SPECIFICATION
August 27, 1998
17.1.15 Instruction Set Summary
Table 17-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
F9
2
3
4
5
4
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
2
3
4
5
4
3
—
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
F4
2
3
4
5
4
3
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit
Clear
↕
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
↕
C
—
— —
0
b7
—
↕
↕
↕
↕
↕
↕
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
— —
↕
↕
↕
↕
b0
C
b7
— —
↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Source
Form
Operand
Table 17-6. Instruction Set Summary
— — — — —
ff
ff
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit
Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
MOTOROLA
17-8
INSTRUCTION SET
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Address
Mode
Opcode
Operand
Cycles
Table 17-6. Instruction Set Summary (Continued)
BHCC rel
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry
Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or
Same
BIH rel
BIL rel
Source
Form
Operation
Description
Effect on
CCR
H I N Z C
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Branch if IRQ Pin
High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— —
—
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
F5 p
2
3
4
5
4
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test
Accumulator with
Memory Byte
BLO rel
Branch if Lower
(Same as BCS)
BLS rel
Branch if Lower or
Same
BMC rel
Branch if Interrupt
Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt
Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
REL
21
rr
3
BRCLR n opr rel Branch if bit n clear
BRSET n opr rel Branch if Bit n Set
BRN rel
MC68HC05SB7
REV 2.1
Branch Never
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? Mn = 1
PC ← (PC) + 2 + rel ? 1 = 0
INSTRUCTION SET
↕
↕
— — — —
— — — —
— — — — —
MOTOROLA
17-9
GENERAL RELEASE SPECIFICATION
August 27, 1998
BSR rel
Branch to
Subroutine
CLC
Clear Carry Bit
CLI
Clear Interrupt Mask
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
MOTOROLA
17-10
Cycles
Set Bit n
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
C←0
— — — — 0
INH
98
I←0
— 0 — — —
INH
9A
— — 0 1 —
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
—
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
Description
Effect on
CCR
H I N Z C
BSET n opr
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operand
Operation
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
Mn ← 1
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
INSTRUCTION SET
— —
— —
— —
— —
— —
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
—
Address
Mode
Source
Form
Opcode
Table 17-6. Instruction Set Summary (Continued)
2
2
dd
ff
dd
ff
dd
ff
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
5
3
3
6
5
— — — — —
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
5
6
7
6
5
— —
—
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
F6
2
3
4
5
4
3
—
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
2
3
4
5
4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
Effect on
CCR
Description
H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Increment Byte
— —
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator
with Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
Logical Shift Right
MUL
Unsigned Multiply
X ← (M)
Negate Byte
(Two’s Complement)
NOP
No Operation
— —
C
0
b7
— —
↕
↕
↕
↕
↕
↕
↕
↕
—
b0
0
C
b7
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
MC68HC05SB7
REV 2.1
Cycles
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operand
INC opr
INCA
INCX
INC opr,X
INC ,X
Operation
Opcode
Source
Form
Address
Mode
Table 17-6. Instruction Set Summary (Continued)
— — 0
↕
↕
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— —
↕
↕
↕
— — — — —
INSTRUCTION SET
INH
42
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
ff
ff
ff
5
3
3
6
5
5
3
3
6
5
11
ii
ff
5
3
3
6
5
2
MOTOROLA
17-11
GENERAL RELEASE SPECIFICATION
August 27, 1998
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
—
IMM
DIR
EXT
IX2
IX1
IX
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
FA
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
INH
9C
2
INH
80
9
— — — — —
INH
81
6
— —
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
F2
2
3
4
5
4
3
Effect on
CCR
Description
H I N Z C
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
— —
C
— —
b7
↕
↕
↕
↕
b0
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right
through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
C
b7
— —
↕
↕
↕
b0
— — — — —
↕
↕
↕
↕
↕
ff
ff
Cycles
Opcode
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operation
Address
Mode
Source
Form
Operand
Table 17-6. Instruction Set Summary (Continued)
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory
Byte and Carry Bit
from Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— —
—
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7 ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF ff
FF
4
5
6
5
4
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in
Memory
STOP
Stop Oscillator and
Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
MOTOROLA
17-12
Store Index
Register In Memory
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
INSTRUCTION SET
↕
↕
↕
↕
↕
↕
—
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Subtract Memory
Byte from
Accumulator
Software Interrupt
TAX
Transfer
Accumulator to
Index Register
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte
for Negative or Zero
TXA
Transfer Index
Register to
Accumulator
WAIT
Stop CPU Clock and
Enable
Interrupts
A ← (A) – (M)
2
3
4
5
4
3
INH
83
10
— — — — —
INH
97
2
— —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
— —
↕
↕
↕
X ← (A)
(M) – $00
A ← (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
INSTRUCTION SET
↕
↕
—
dd
ff
Cycles
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
F0
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
MC68HC05SB7
REV 2.1
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
Description
H I N Z C
SWI
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Opcode
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Operation
Address
Mode
Source
Form
Operand
Table 17-6. Instruction Set Summary (Continued)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
MOTOROLA
17-13
MOTOROLA
17-14
INSTRUCTION SET
MC68HC05SB7
REV 2.1
5
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
5
DIR 2
BCLR7
DIR 2
5
BSET7
DIR 2
5
BCLR6
DIR 2
5
BSET6
DIR 2
5
BCLR5
DIR 2
5
BSET5
DIR 2
5
BCLR4
DIR 2
5
BSET4
DIR 2
5
BCLR3
DIR 2
5
BSET3
3
REL 2
3
BCC
REL 2
3
BLS
REL
3
BHI
REL
3
BRN
REL 2
3
BRA
2
REL
5
DIR 1
5
ASR
DIR 1
5
ROR
5
DIR 1
LSR
DIR 1
5
COM
1
3
INH 1
3
ASRA
INH 1
3
RORA
3
INH 1
LSRA
INH 1
3
COMA
INH
3
MUL
11
INH 1
NEGA
4
INH
3
3
INH 2
3
ASRX
INH 2
3
RORX
3
INH 2
LSRX
INH 2
3
COMX
INH 2
NEGX
5
INH
5
5
DIR 1
CLR
DIR 1
TST
DIR 1
4
INC
DIR 1
DEC
DIR 1
5
ROL
DIR 1
5
3
3
INH 1
CLRA
INH 1
TSTA
INH 1
3
INCA
INH 1
DECA
INH 1
3
ROLA
INH 1
3
INH 2
3
3
3
INH 2
CLRX
INH 2
TSTX
INH 2
3
INCX
INH 2
DECX
INH 2
3
ROLX
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
REL 2
BIH
REL
3
BIL
REL 2
3
BMS
REL 2
3
BMC
REL
3
BMI
REL 2
3
BPL
REL 2
3
BHCS
5
DIR 1
NEG
3
DIR
6
IX1 1
6
6
IX1 1
6
IX1 1
IX1 1
5
CLR
TST
INC
IX1 1
DEC
IX1 1
6
ROL
ASR
ROR
LSR
COM
NEG
7
IX
5
5
IX
5
IX
5
5
IX
IX 1
5
IX
IX
4
5
IX
IX
5
9
10
1
1
1
1
1
1
1
INH 1
WAIT
INH
2
STOP
2
INH
SWI
INH
RTS
INH
6
RTI
8
INH
2
2
2
2
2
2
2
2
INH
TXA
2
2
MSB
0
4
EXT 3
STX
EXT 3
5
LDX
EXT 3
4
JSR
EXT 3
6
JMP
EXT 3
3
ADD
EXT 3
4
ORA
EXT 3
4
ADC
EXT 3
4
EOR
EXT 3
4
STA
EXT 3
5
LDA
EXT 3
4
BIT
EXT 3
4
AND
EXT 3
4
CPX
EXT 3
4
SBC
EXT 3
4
CMP
EXT 3
4
SUB
C
EXT
3
IX2 2
5
IX2 2
6
STX
LDX
JSR
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
JMP
IX2 2
4
ADD
IX2 2
5
ORA
IX2 2
5
ADC
IX2 2
5
EOR
STA
LDA
IX2 2
5
IX2 2
5
AND
IX2 2
5
CPX
IX2 2
5
SBC
IX2 2
5
CMP
BIT
5
IX2 2
5
SUB
D
IX2
IX1 1
4
IX1 1
5
STX
LDX
JSR
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
JMP
IX1 1
3
ADD
IX1 1
4
ORA
IX1 1
4
ADC
IX1 1
4
EOR
STA
LDA
IX1 1
4
IX1 1
4
AND
IX1 1
4
CPX
IX1 1
4
SBC
IX1 1
4
CMP
BIT
5 Number of Cycles
DIR Number of Bytes/Addressing Mode
4
IX1 1
4
SUB
E
IX1
MSB of Opcode in Hexadecimal
DIR 3
STX
DIR 3
4
LDX
DIR 3
3
JSR
DIR 3
5
JMP
DIR 3
2
ADD
DIR 3
3
ORA
DIR 3
3
ADC
DIR 3
3
EOR
DIR 3
3
STA
DIR 3
4
LDA
DIR 3
3
DIR 3
3
AND
DIR 3
3
CPX
DIR 3
3
SBC
DIR 3
3
CMP
BIT
3
DIR 3
3
SUB
B
DIR
Register/Memory
BRSET0 Opcode Mnemonic
2
IMM 2
LDX
0
2
REL 2
2
BSR
6
IMM 2
ADD
IMM 2
2
ORA
IMM 2
2
ADC
IMM 2
2
EOR
2
IMM 2
LDA
IMM 2
2
BIT
IMM 2
2
AND
IMM 2
2
CPX
IMM 2
2
SBC
IMM 2
2
CMP
IMM 2
2
SUB
A
IMM
LSB
2
INH 2
NOP
INH
2
RSP
INH 2
2
SEI
INH 2
2
INH 2
2
SEC
INH 2
2
CLC
CLI
2
INH
2
TAX
9
INH
Control
LSB of Opcode in Hexadecimal
CLR
TST
INC
DEC
ROL
IX
5
1
IX 1
5
1
IX 1
ASL/LSL
IX1 1
6
ASR
IX1 1
6
ROR
6
IX1 1
IX1 1
6
COM
LSR
6
IX1 1
NEG
6
IX1
Read-Modify-Write
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL
REL 2
3
BHCC
REL 2
3
BEQ
REL 2
3
BNE
REL
3
BCS/BLO
DIR 2
5
BCLR2
DIR 2
5
BSET2
DIR 2
5
BCLR1
DIR 2
5
BSET1
DIR 2
5
BCLR0
DIR 2
5
BSET0
1
DIR
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
3
BRCLR7
3
BRSET7
3
BRCLR6
3
BRSET6
3
BRCLR5
3
BRSET5
3
BRCLR4
3
BRSET4
3
BRCLR3
3
BRSET3
3
BRCLR2
3
BRSET2
3
BRCLR1
3
BRSET1
3
BRCLR0
DIR 2
5
BRSET0
0
3
0
MSB
LSB
DIR
Bit Manipulation Branch
Table 17-7. Opcode Map
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 18
ELECTRICAL SPECIFICATIONS
This section describes the electrical and timing specifications of the
MC68HC05SB7.
18.1
MAXIMUM RATINGS
NOTE
Maximum ratings are the extreme limits the device can be exposed to without
causing permanent damage to the chip. The device is not intended to operate at
these conditions.
The MCU contains circuitry that protect the inputs against damage from high
static voltages; however, do not apply voltages higher than those shown in the
table below. Keep VIN and VOUT within the range from VSS ≤ (VIN or VOUT) ≤ VDD.
Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Bootloader Mode (IRQ/VPP Pin Only)
VIN
VSS – 0.3 to 17
V
I
25
mA
TJ
+150
°C
Tstg
–65 to +150
°C
Symbol
Value
Unit
TA
TL to TH
0 to +70
°C
Current Drain Per Pin Excluding VDD and VSS
Operating Junction Temperature
Storage Temperature Range
18.2
OPERATING TEMPERATURE RANGE
Characteristic
Operating Temperature Range
MC68HC05SB7 (Standard)
18.3
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
SOIC
SSOP
MC68HC05SB7
REV 2.1
Symbol
Value
Unit
θJA
θJA
60
60
°C/W
°C/W
ELECTRICAL SPECIFICATIONS
MOTOROLA
18-1
GENERAL RELEASE SPECIFICATION
18.4
August 27, 1998
SUPPLY CURRENT CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Unit
Run, All Analog and LVR enabled
Internal VCO at 2.5kHz
External Oscillator at 4.2MHz
IDD
IDD
—
—
3
4.8
5
8
mA
mA
Wait
Internal VCO at 2.5kHz
External Oscillator at 4.2 MHz
IDD
IDD
—
—
1
1.3
1.5
2
mA
mA
Stop - all clocks disabled
All Analog/LVR disabled and CSA enabled
All Analog and LVR disabled
All Analog disabled and LVR enabled
All Analog and LVR enabled
IDD
IDD
IDD
IDD
—
—
—
—
280
6
8
200
500
10
20
350
µA
µA
µA
µA
VDD = 4.5 to 5.5 Vdc
NOTES:
1.
2.
3.
4.
5.
6.
7.
18.5
VDD as indicated, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
All values shown reflect average measurements.
Typical values at midpoint of voltage range, 25°C only.
Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50pF on all
outputs, CL = 20pF on OSC2.
Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD – 0.2 VDC.
Stop IDD measured with OSC1 = VDD.
Wait IDD is affected linearly by the OSC2 capacitance.
PEPROM PROGRAMMING CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Unit
PEPROM Programming Voltage
VPP
—
13.7
—
V
PEPROM Programming Current
IPP
—
3
10
mA
tEPGM
2
—
—
ms
PEPROM Programming Time per Byte
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
MOTOROLA
18-2
ELECTRICAL SPECIFICATIONS
MC68HC05SB7
REV 2.1
August 27, 1998
18.6
GENERAL RELEASE SPECIFICATION
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
Iload = 10.0 µA
Iload = –10.0 µA
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
V
Output High Voltage
(Iload = –0.8 mA) PA0:7, PB1:7, PC4:7, RESET
VOH
VDD – 0.8
—
—
V
VOL
—
—
0.4
V
High Source Current (VOH = VDD – 0.5 to 1.0 Vdc)
Source current per pin, PA0:7, PB1:7, PC4:7
Source current total for all pins
IOH
IOH
—
—
—
—
4
—
mA
mA
High Sink Current (VOL = VSS + 1.5 Vdc)
Sink current per pin, PA0:7, PB1:7, PC4:7
Sink current total for all pins
IOL
IOL
—
—
—
—
12
—
mA
mA
High Source Current (VOH = VDD – 0.2Vdc)
Source current for pin, ESV
IOH
—
—
3
mA
Input High Voltage
PA0:7, PB1:7, PC4:7, RESET, OSC1, IRQ/VPP
VIH
0.7 X VDD
—
VDD
V
Input Low Voltage
PA0:7, PB1:7, PC4:7, RESET, OSC1, IRQ/VPP
VIL
VSS
—
0.3 x VDD
V
Input Current
PA0:7, PB1:7, PC4:7, RESET, OSC1, IRQ/VPP
IIN
—
—
±1
µA
I/O Ports High-Z Leakage Current
PA0:7, PB1:7, PC4:7
IOZ
—
—
±10
µA
Internal Bandgap Voltage
VBG
1.1
1.2
1.3
V
2.0
2.2
2.4
mV/°C
Output Low Voltage
(Iload = 1.6 mA) PA0:7, PB1:7, PC4:7, RESET
Internal Temperature Sensor Temperature Gradient
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25°C only.
MC68HC05SB7
REV 2.1
ELECTRICAL SPECIFICATIONS
MOTOROLA
18-3
GENERAL RELEASE SPECIFICATION
18.7
August 27, 1998
ANALOG SUBSYSTEM CHARACTERISTICS
Characteristic
Symbol
Min
Max
Unit
VIO
5
10
mV
Voltage Comparator Input Common-Mode Range
VCMR
—
VDD – 1.5
V
Voltage Comparator Supply Current
ICMP
—
150
µA
Voltage Comparator Input Divider Ratio
RDIV
0.49
0.51
ISOURCE
80
120
µA
Current Source Supply Current
IRAMP
—
220
µA
Source Current Linearity
IRAMP
—
1.0
%FS
Discharge Sink Current (VOUT = 0.4 V)
IDIS
0.8
—
mA
External Capacitor Voltage Range
VIN
VSS
VDD – 1.5
V
Comparator Input Impedance
Comparator
Used as comparator only (DHOLD =0)
Used as A/D function (DHOLD =1)
ZIN
ZIN
0.8
80
—
—
MΩ
kΩ
RMUX
4.5
7
kΩ
CSH
tSHCHG
4
20
60
6
—
—
pF
µs
µs
Voltage Comparator Input Offset Voltage
External Capacitor Current Source
Multiplexer Switch Resistance
Internal Sample & Hold Capacitor
Capacitance
Charge/Discharge Time (0 to 3.5 VDC, DHOLD =0)
Charge/Discharge Time (0 to 3.5 VDC, DHOLD =1)
tSHDCHG
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
MOTOROLA
18-4
ELECTRICAL SPECIFICATIONS
MC68HC05SB7
REV 2.1
August 27, 1998
18.8
GENERAL RELEASE SPECIFICATION
CONTROL TIMING
Characteristic
Symbol
Min
Max
Unit
Frequency of Oscillation (OSC)
Crystal Oscillator Option
External Clock Source
Internal VCO (SCLK = 0)2
Internal VCO (SCLK = 1)2
fOSC
fOSC
fOSC
fOSC
0.1
DC
1.5
0.5
4.2
4.2
5.8
4
MHz
MHz
MHz
kHz
Internal Operating Frequency, Crystal or External Clock (fOSC/2)
Crystal Oscillator Option
External Clock Source
fOP
fOP
0.05
DC
2.1
2.1
MHz
MHz
Cycle Time
Crystal Oscillator or External Clock source
tCYC
476
—
ns
tRESL
tTH, tTL
4.0
284
—
—
tCYC
ns
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
284
—
ns
Interrupt Pulse Period
tILIL
see note 3
—
tCYC
OSC1 Pulse Width (external clock input)
tOH,tOL
110
—
ns
Voltage Comparator Switching Time
(10 mV overdrive, either input)
tPROP
—
10
µs
Voltage Comparator Power Up Delay
(Bias Circuit already powered up)
tDELAY
—
100
µs
External Capacitor Switching Time (IDIS to IRAMP)
tPROP
—
10
µs
External Capacitor Current Source Power Up Delay
(Bias Circuit already powered up)
tDELAY
—
100
µs
Bias Circuit Power Up Delay
tDELAY
—
100
µs
Timer
Resolution
Input Capture (TCAP) pulse width
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
2. Due to process variations, operating voltages, and temperature requirements, the quoted VCO frequencies are typical limits, and should be treated as reference only. It is the user’s responsibility to
ensure that the resulting internal operating frequency meets user’s requirement by setting the appropriate value in the VCO Adjust Register.
3. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC.
MC68HC05SB7
REV 2.1
ELECTRICAL SPECIFICATIONS
MOTOROLA
18-5
GENERAL RELEASE SPECIFICATION
18.9
August 27, 1998
RESET CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Unit
Low Voltage Reset
Rising Recovery Voltage
Falling Reset Voltage
LVR Hysteresis
VLVRR
VLVRF
VLVRH
1.3
1.2
100
2.3
2.2
—
3.1
3.0
—
V
V
mV
POR Recovery Voltage2
VPOR
0
—
100
mV
SVDDR
SVDDF
0.1
0.05
—
—
—
—
V/µs
V/µs
tRL
1.5
—
—
tCYC
tRPD
3
—
4
tCYC
POR VDD Slew
Rising
Falling
Rate 2
RESET Pulse Width (when bus clock active)
RESET Pulldown Pulse Width (from internal reset)
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
2. By design, not tested.
OSC11
tRL
RESET
4096 tCYC2
Internal
Clock3
Internal
Address
Bus3
Internal
Data
Bus3
1FFE
NEW
PCH
1FFF
NEW PCH NEW PCL
NEW
PCL
Op
code
NOTES:
1. Represents the internal gating of the OSC1 pin.
2. Normal delay of 4064 tCYC.
3. Internal timing signal and data information not available externally.
Figure 18-1. Stop Recovery Timing Diagram
MOTOROLA
18-6
ELECTRICAL SPECIFICATIONS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
Internal
Reset1
RESET
Pin
tRPD
4096 tCYC2
Internal
Clock3
Internal
Address
Bus3
1FFE
Internal
Data
Bus3
1FFF
NEW
PCH
NEW PCH NEW PCL
NEW
PCL
NOTES:
1. Represents the internal reset from low voltage reset, illegal opcode fetch or COP Watchdog timeout.
2. Normal delay of 4064 tCYC.
3. Internal timing signal and data information not available externally.
Figure 18-2. Internal Reset Timing Diagram
VDD
VLVRL
VLVRH
Low
Voltage
Reset
RESET
Pin1
tRPD
4096 tCYC2
Internal
Clock3
Internal
Address
Bus3
1FFE
Internal
Data
Bus3
NEW
PCH
1FFF
NEW PCH NEW PCL
NEW
PCL
NOTES:
1. RESET pin pulled down be internal device.
2. Normal delay of 4064 tCYC.
3. Internal timing signal and data information not available externally.
Figure 18-3. Low Voltage Reset Timing Diagram
MC68HC05SB7
REV 2.1
ELECTRICAL SPECIFICATIONS
MOTOROLA
18-7
GENERAL RELEASE SPECIFICATION
August 27, 1998
18.10 SM-BUS DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Min
Max
Unit
LOW level input voltage
VIL
VSS
0.3 x VDD
V
HIGH level input voltage
VIH
0.7 x VDD
5.5
V
LOW level output voltage (open drain); at 2.86mA sink current
(RPULLUP=1.7kΩ and CLOAD=400pF)
VOL
VSS
0.135
V
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
2. For SM-Bus specification: logic "LOW"=0.6V or less; logic "HIGH"=1.4V or above.
18.11 SM-BUS CONTROL TIMING
18.11.1SM-Bus Interface Input Signal Timing
Parameter
Symbol
Min
Max
Unit
tHD.STA
2
—
tCYC
tLOW
4.7
—
tCYC
tR
—
1
µs
tHD.DAT
300
—
ns
SDA/SCL fall time
tF
—
300
ns
Clock high period
tHIGH
4
—
tCYC
Data set up time
tSU.DAT
250
—
ns
Start condition set up time (for repeated start condition only)
tSU.STA
2
—
tCYC
Stop condition set up time
tSU.STO
2
—
tCYC
Symbol
Min
Max
Unit
tHD.STA
8
—
tCYC
tLOW
11
—
tCYC
tR
—
1
µs
tHD.DAT
300
—
ns
SDA/SCL fall time
tF
—
300
ns
Clock high period
tHIGH
11
—
tCYC
Data set up time
tSU.DAT
tLOW–tCYC
—
ns
Start condition set up time (for repeated start condition only)
tSU.STA
10
—
tCYC
Stop condition set up time
tSU.STO
10
—
tCYC
Start condition hold time
Clock low period
SDA/SCL rise time
Data hold time
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
18.11.2SM-Bus Interface Output Signal Timing
Parameter
Start condition hold time
Clock low period
SDA/SCL rise time
Data hold time
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
MOTOROLA
18-8
ELECTRICAL SPECIFICATIONS
MC68HC05SB7
REV 2.1
August 27, 1998
tR
GENERAL RELEASE SPECIFICATION
tF
SDA
SCL
tHD.STA
tLOW
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
Figure 18-4. SM-Bus Timing Diagram
MC68HC05SB7
REV 2.1
ELECTRICAL SPECIFICATIONS
MOTOROLA
18-9
GENERAL RELEASE SPECIFICATION
MOTOROLA
18-10
August 27, 1998
ELECTRICAL SPECIFICATIONS
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 19
MECHANICAL SPECIFICATIONS
This section provides the mechanical dimensions for the 28-pin SOIC and
28-pin SSOP packages.
19.1
28-PIN SOIC (CASE 751F)
-A28
! ! %
! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
14X
-B1
P
14
28X D
!
M
R X 45°
C
-T26X
-T-
G
K
F
J
MC68HC05SB7
REV 2.1
MECHANICAL SPECIFICATIONS
°
°
°
°
MOTOROLA
19-1
GENERAL RELEASE SPECIFICATION
19.2
August 27, 1998
28-PIN SSOP
D/2
1.00
2.36
DIA. PIN
1.00 DIA.
3
2
1
H +
0.20
M E
M
E/2
I PP
I NE
HI L
1.00
S- P
N
6
TOP VIEW
BOTTOM VIEW
12-16°
+
e
0.12
M T
E
D
S
b 8
A2
A
-C3
-T-
0.076
C
7
-E-
A1
-D-
SEATING
PLANE
4
4
SEE
DETAIL "A"
SIDE VIEW
END VIEW
0.235 MIN
b1
WITH LEAD FINISH
0° MIN.
GAUGE PLANE
PARTING LINE
c
c1
R
G
0.25 BSC
8
M
b
BASE METAL
L
G
SECTION G-G
5
10
SEATING PLANE
L1
DETAIL 'A'
NOTES:
1. MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES).
2. DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982.
3. "T" IS A REFERENCE DATUM.
4. "D" & "E" ARE REFERENCE DATUMS AND DO NOT
INCLUDE MOLD FLASH OR PROTRUSIONS, BUT
DO INCLUDE MOLD MISMATCH AND ARE MEASURED
AT THE PARTING LINE, MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE.
5. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
6. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY.
7. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN
EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE
THAN 0.07mm AT LEAST MATERIAL CONDITION.
9. CONTROLLING DIMENSION: MILLIMETERS.
10. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS.
11. THIS PACKAGE OUTLINE DRAWING COMPLIES WITH
JEDEC SPECIFICATION NO. MO-150 FOR THE LEAD COUNTS SHOWN
MOTOROLA
19-2
S
Y
M
B
O
L
A
A1
A2
b
b1
c
c1
D
E
e
H
L
L1
N
M
R
DIMENSIONS IN MM
MIN.
MAX.
NOM.
1.73
0.05
1.68
0.25
0.25
0.09
0.09
10.07
5.20
7.65
0.63
0
0.09
1.86
0.13
1.73
—
0.30
—
0.15
10.20
5.30
0.65 BSC
7.80
0.75
1.25 REF.
28
4
0.15
MECHANICAL SPECIFICATIONS
DIMENSIONS IN INCH
MIN.
NOM.
MAX.
1.99
0.21
1.78
0.38
0.33
0.20
0.16
10.33
5.38
.068
.002
.066
.010
.010
.004
.004
.397
.205
7.90
0.95
.301
.025
8
0
.004
.073
.005
.068
—
.012
—
.006
.402
.209
.0256 BSC
.307
.030
.049 REF.
28
4
.006
N
O
T
E
.078
.008
.070
.015
.013
.008
.006
.407
.212
8,10
10
10
10
4
4
.311
.037
5
6
8
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
APPENDIX A
MC68HC705SB7
This appendix describes the MC68HC705SB7, the emulation part for
MC68HC05SB7. The entire MC68HC05SB7 data sheet applies to the
MC68HC705SB7, with exceptions outlined in this appendix.
A.1
INTRODUCTION
The MC68HC705SB7 is an EPROM version of the MC68HC05SB7, and is available for user system evaluation and debugging. The MC68HC705SB7 is functionally identical to the MC68HC05SB7 with the exception of the 6106 bytes user
ROM is replaced by 6106 bytes user EPROM. The mask option for the external
pin oscillator on the MC68HC05SB7 is controlled by the Mask Option Register at
$002F on the MC68HC705SB7. This device is available in 28-pin SOIC package.
A.2
MEMORY
The MC68HC705SB7 memory map is shown on Figure A-1.
$0000
$002F
$0030
$003F
I/O REGISTERS
48 BYTES
UNIMPLEMENTED
16 BYTES
$0040
USER RAM
224 BYTES
$011F
$0120
$05FF
STACK RAM
64 BYTES
$00C0
$00FF
UNIMPLEMENTED
1248 BYTES
$0600
USER EPROM
6144 BYTES
$1DFF
$1E00
$1FEF
$1FF0
$1FFF
BOOTLOADER ROM
496 BYTES
USER VECTORS
16 BYTES
Figure A-1. MC68HC705SB7 Memory Map
MC68HC05SB7
REV 2.1
MOTOROLA
A-1
GENERAL RELEASE SPECIFICATION
A.3
August 27, 1998
PERSONALITY EPROM (PEPROM)
The 64-bit PEPROM is left blank for user programming.
A.4
MASK OPTION REGISTER
The EPROM programmable Mask Option Register is used for setting EPROM
security and enabling the external pin oscillator.
BIT 7
MOR
R
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
-
-
-
-
-
-
EPMSEC
OSCS
reset:
U
U
U
U
U
U
U
U
erased:
0
0
-
-
-
-
-
-
$002F
W
U = UNAFFECTED BY RESET
Figure A-2. MC68HC705SB7 Mask Option Register (MOR)
EPMSEC — EPROM Security Bit
1 = Access to the EPROM array in non-user mode is denied.
0 = Access to the EPROM array in non-user mode is enabled.
This write-only bit controls the non-user mode access to the EPROM array on the
MCU. When programmed to “1”, any accesses of the EPROM locations will return
undefined results.
EPMSEC Programming
The state of the EPMSEC security bit should be programmed using a programmer
board (available from Motorola). In order to program the EPMSEC bit the desired
state must be written to the MOR address and then the MPGM bit in the EPROG
register must be used. The following sequence will program the EPMSEC bit:
1. Write the desired data to the EPMSEC bit in MOR.
2. Apply the programming voltage to the IRQ/VPP pin.
3. Set the MPGM bit in the EPROG.
4. Wait for the programming time (tMPGM).
5. Clear the MPGM bit in the EPROG.
6. Remove the programming voltage from the IRQ/VPP pin.
Once the EPMSEC bit has been programmed to a “1”, access to the contents of
the EPROM in the non-user mode will be denied. It is therefore recommended that
the User EPROM in the part first be programmed and fully verified before setting
the EPMSEC bit.
OSCS — Oscillator Select Bit
1 = External pin oscillator (EPO) enabled.
0 = External pin oscillator (EPO) disabled.
MOTOROLA
A-2
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
The OSCS bit enables the OSC1 and OSC2 pins for external oscillator connection. OSC1 replaces PB2/CS0 and OSC2 replaces PB3/CS1. This is selected by a
mask option on the MC68HC05SB7 device.
A.5
BOOTLOADER MODE
Bootloader mode is entered upon the rising edge of RESET if IRQ/VPP pin is at
VTST and PB1/TCAP at VDD. The Bootloader program is masked in the ROM area
from $1E00 to $1FEF. This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from
an external EPROM. The bootloader performs one programming pass at 1ms per
byte then does a verify pass.
A.6
EPROM PROGRAMMING
This section describes how to program the 6160-byte EPROM and the EPROM
security bit.
In packages with no quartz window, the EPROM functions as one-time programmable ROM (OTPROM)
Programming the on-chip EPROM is achieved by using the Program Control Register located at address $001E.
The programming software copies to the 6144-byte space located at EPROM
addresses $0600 – $1DFF and to the 16-byte space at addresses $1FF0 – $1FFF
which includes the mask option register (MOR) at address $002F.
Please contact Motorola for programming board availability.
A.6.1 EPROM Programming Register (EPROG)
The EPROM programming register shown in Figure A-3 contains the control bits
for programming the EPROM and MOR. In normal operation, the EPROM programming register is a read-only register that contains all logic zeros.
EPROG
R
$001C
W
reset:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
0
0
0
0
0
0
0
0
0
0
UNIMPLEMENTED
BIT 2
BIT 1
BIT 0
ELAT
MPGM
EPGM
0
0
0
RESERVED FOR TEST
Figure A-3. EPROM Programming Register (EPROG)
EPGM — EPROM Programming
This read/write bit applies the voltage from the IRQ/VPP pin to the EPROM. To
write the EPGM bit, the ELAT bit must already be set. Clearing the ELAT bit
also clears the EPGM bit. Reset clears EPGM.
1 = EPROM programming power switched on.
0 = EPROM programming power switched off.
MC68HC05SB7
REV 2.1
MOTOROLA
A-3
GENERAL RELEASE SPECIFICATION
August 27, 1998
MPGM — Mask Option Register (MOR) Programming
This read/write bit applies programming power from the IRQ/VPP pin to the
MOR. Reset clears MPGM.
1 = MOR programming power switched on.
0 = MOR programming power switched off.
ELAT — EPROM Bus Latch
This read/write bit configures address and data buses for programming the
EPROM array. EPROM data cannot be read when ELAT is set. Clearing the
ELAT bit also clears the EPGM bit. Reset clears ELAT.
1 = Address and data buses configured for EPROM programming of the
array. The address and data bus are latched in the EPROM array
when a subsequent write to the array is made. Data in the EPROM
array cannot be read.
0 = Address and data buses configured for normal operation.
Whenever the ELAT bit is cleared the EPGM bit is also cleared. Both the EPGM
and the ELAT bit cannot be set using the same write instruction. Any attempt to
set both the ELAT and EPGM bit on the same write instruction cycle will result in
the ELAT bit being set and the EPGM bit being cleared.
A.6.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified programming
time (tEPGM).
4. Clear the EPGM bit
5. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
CAUTION
It is important to remember that an external programming voltage
must be applied to the VPP pin while programming, but it should be
equal to VDD during normal operations.
Figure A-4 shows the flow required to successfully program the EPROM.
MOTOROLA
A-4
MC68HC05SB7
REV 2.1
August 27, 1998
GENERAL RELEASE SPECIFICATION
START
ELAT=1
Write EPROM byte
EPGM=1
Wait 1ms
EPGM=0
ELAT=0
Y
Write
additional
byte?
N
END
Figure A-4. EPROM Programming Sequence
A.7
EPROM ERASING
MCUs with windowed packages permit EPROM erasure with ultraviolet light.
Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of an EPROM bit is a logic
one.
MC68HC05SB7
REV 2.1
MOTOROLA
A-5
GENERAL RELEASE SPECIFICATION
A.8
August 27, 1998
EPROM PROGRAMMING SPECIFICATIONS
Characteristic
MOR Programming Time
Symbol
Min
Typ
Max
Unit
tMPGM
4
—
—
µs
13.7
V
EPROM Programming Voltage
VPP
EPROM Programming Current
IPP
—
3
5
mA
tEPGM
4
—
—
µs
EPROM Programming Time per Byte
NOTES:
1. VDD =5V ± 10%, VSS = 0 V, TL≤ TA ≤ TH, unless otherwise noted.
MOTOROLA
A-6
MC68HC05SB7
REV 2.1
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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© Motorola, Inc., 1998
HC05SB7GRS/H