FREESCALE MC68HC11ED0

68HC11M6
HC11M68HC
1M68HC11M
Freescale Semiconductor, Inc.
MC68HC11ED0TS/D
REV 1
MC68HC11ED0
Technical Summary
HCMOS
Microcontroller Unit
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
blank
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC68HC11ED0
Freescale Semiconductor, Inc...
Technical Summary
MC68HC11ED0 — Rev. 1.0
Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Technical Summary
Technical Summary
MC68HC11ED0 — Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Summary — MC68HC11ED0
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 15
Freescale Semiconductor, Inc...
Section 2. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 19
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 23
Section 4. Operating Modes and On-Chip Memory . . . . 43
Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 57
Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . . 65
Section 7. Serial Communications Interface (SCI) . . . . . 71
Section 8. Serial Peripheral Interface (SPI). . . . . . . . . . . 81
Section 9. Timing System. . . . . . . . . . . . . . . . . . . . . . . . . 87
MC68HC11ED0 — Rev. 1.0
Technical Summary
List of Sections
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
List of Sections
Technical Summary
MC68HC11ED0 — Rev. 1.0
List of Sections
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Summary — MC68HC11ED0
Table of Contents
Freescale Semiconductor, Inc...
Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Section 2. Pin Assignments
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
44-Pin Plastic-Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . .20
2.4
44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5
40-Pin Plastic Dual In-Line Package (DIP) . . . . . . . . . . . . . . . . 22
Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1
Accumulators A, B, and D . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2
Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3
Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MC68HC11ED0 — Rev. 1.0
Technical Summary
Table of Contents
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table of Contents
Freescale Semiconductor, Inc...
3.3.6
3.3.6.1
3.3.6.2
3.3.6.3
3.3.6.4
3.3.6.5
3.3.6.6
3.3.6.7
3.3.6.8
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 29
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I-Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
X-Interrupt Mask (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.1
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.2
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.3
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.4
Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.5
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.6
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Section 4. Operating Modes and On-Chip Memory
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.1
Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2
Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.3
Expanded Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5
On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5.1
Memory Map and Register Block . . . . . . . . . . . . . . . . . . . . . 49
4.5.2
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Technical Summary
MC68HC11ED0 — Rev. 1.0
Table of Contents
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table of Contents
Freescale Semiconductor, Inc...
Section 5. Resets and Interrupts
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4
System Configuration Options Register . . . . . . . . . . . . . . . . . . 60
5.5
Arm/Reset COP Timer Circuitry Register . . . . . . . . . . . . . . . . . 61
5.6
Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.7
Highest Priority I-Bit Interrupt and Miscellaneous Register . . . 63
Section 6. Parallel Input/Output (I/O) Ports
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3
Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4
Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . 67
6.5
Port D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6
Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . 69
Section 7. Serial Communications Interface (SCI)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.3.1
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.2
Serial Communications Control Register 1 . . . . . . . . . . . . . 77
7.3.3
Serial Communications Control Register 2 . . . . . . . . . . . . . 78
7.3.4
Serial Communication Status Register. . . . . . . . . . . . . . . . . 79
7.3.5
Serial Communications Data Register . . . . . . . . . . . . . . . . . 80
MC68HC11ED0 — Rev. 1.0
Technical Summary
Table of Contents
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table of Contents
Section 8. Serial Peripheral Interface (SPI)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Freescale Semiconductor, Inc...
8.3
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8.3.1
Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . .83
8.3.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . .85
8.3.3
Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . .86
Section 9. Timing System
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.3.1
Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . 91
9.3.2
Output Compare 1 Mask Register . . . . . . . . . . . . . . . . . . . . 92
9.3.3
Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . . 92
9.3.4
Timer Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.3.5
Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . 94
9.3.6
Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . . 95
9.3.7
Timer Input Capture 4/Output Compare 5 Register . . . . . . . 96
9.3.8
Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3.9
Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.10 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . 99
9.3.11 Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 100
9.3.12 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 100
9.3.13 Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . . 102
9.4
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.1
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 104
9.4.2
Pulse Accumulator Counter Register . . . . . . . . . . . . . . . . . 106
Technical Summary
MC68HC11ED0 — Rev. 1.0
Table of Contents
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Summary — MC68HC11ED0
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
Page
1-1
MC68HC11ED0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .17
2-1
2-2
2-3
Pin Assignments for 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . 20
Pin Assignments for 44-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Assignments for 40-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . .22
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Stacking Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4-1
4-2
Address and Data Demultiplexing . . . . . . . . . . . . . . . . . . . . . . 46
Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO) . . . . . . . . . . . . . . . . . 47
MC68HC11ED0 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 49
Register and Control Bit Assignments . . . . . . . . . . . . . . . . . . .50
RAM and Register Mapping Register (INIT) . . . . . . . . . . . . . . .56
4-3
4-4
4-5
5-1
5-2
5-3
5-4
System Configuration Options Register (OPTION) . . . . . . . . . 60
Arm/Reset COP Timer Circuitry Register (COPRST). . . . . . . . 61
System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . 62
Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO) . . . . . . . . . . . . . . . . . 63
6-1
6-2
6-3
6-4
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . 66
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . . . 67
Port D Data Register (PORTD). . . . . . . . . . . . . . . . . . . . . . . . . 68
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . . 69
7-1
7-2
SCI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .72
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MC68HC11ED0 — Rev. 1.0
Technical Summary
List of Figures
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
Page
7-3
7-4
7-5
7-6
7-7
7-8
Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SCI Baud Rate Generator Clock Diagram . . . . . . . . . . . . . . . . 76
Serial Communications Control Register 1 (SCCR1) . . . . . . . . 77
Serial Communications Control Register 2 (SCCR2) . . . . . . . . 78
Serial Communications Status Register (SCSR) . . . . . . . . . . . 79
Serial Communications Data Register (SCDR) . . . . . . . . . . . . 80
8-1
8-2
8-3
8-4
8-5
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Serial Peripheral Control Register (SPCR). . . . . . . . . . . . . . . . 83
SPI Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Serial Peripheral Status Register (SPSR) . . . . . . . . . . . . . . . . 85
Serial Peripheral Data I/O Register (SPDR) . . . . . . . . . . . . . . .86
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer Compare Force Register (CFORC) . . . . . . . . . . . . . . . . 91
Output Compare 1 Mask Register (OC1M) . . . . . . . . . . . . . . . 92
Output Compare 1 Data Register (OC1D) . . . . . . . . . . . . . . . . 92
Timer Count Register (TCNT). . . . . . . . . . . . . . . . . . . . . . . . . . 93
Timer Input Capture Register 1 (TIC1) . . . . . . . . . . . . . . . . . . . 94
Timer Input Capture Register 2 (TIC2) . . . . . . . . . . . . . . . . . . . 94
Timer Input Capture Register 3 (TIC3) . . . . . . . . . . . . . . . . . . . 94
Timer Output Compare Register 1 (TOC1). . . . . . . . . . . . . . . . 95
Timer Output Compare Register 2 (TOC2). . . . . . . . . . . . . . . . 95
Timer Output Compare Register 3 (TOC3). . . . . . . . . . . . . . . . 95
Timer Output Compare Register 4 (TOC4). . . . . . . . . . . . . . . . 96
Timer Input Capture4/Output Compare 5 Register (TI4/O5) . . 96
Timer Control Register 1 (TCTL1) . . . . . . . . . . . . . . . . . . . . . . 97
Timer Control Register 2 (TCTL2) . . . . . . . . . . . . . . . . . . . . . . 98
Timer Interrupt Mask 1 Register (TMSK1) . . . . . . . . . . . . . . . . 99
Timer Interrupt Flag 1 Register (TFLG1) . . . . . . . . . . . . . . . . 100
Timer Interrupt Mask 2 Register (TMSK2) . . . . . . . . . . . . . . . 100
Timer Interrupt Flag 2 Register (TFLG2) . . . . . . . . . . . . . . . . 102
Pulse Accumulator System Block Diagram . . . . . . . . . . . . . . 103
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . . 104
Pulse Accumulator Counter Register (PACNT) . . . . . . . . . . . 106
Technical Summary
MC68HC11ED0 — Rev. 1.0
List of Figures
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Summary — MC68HC11ED0
List of Tables
Freescale Semiconductor, Inc...
Table
Title
Page
1-1
Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3-1
3-2
Reset Vector Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5-1
5-2
5-3
Interrupt and Reset Vector Assignments . . . . . . . . . . . . . . . . . 59
COP Timer Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Highest Priority Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . 64
6-1
Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7-1
7-2
Prescaler Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8-1
SPI Clock Rate Selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9-1
9-2
9-3
9-4
9-5
9-6
9-7
Timer Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timer Output Compare Actions . . . . . . . . . . . . . . . . . . . . . . . .97
Timer Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Timer Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Pulse Accumulator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
RTI Rates (Period Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
RTI Rates (Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
MC68HC11ED0 — Rev. 1.0
Technical Summary
List of Tables
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
List of Tables
Technical Summary
MC68HC11ED0 — Rev. 1.0
List of Tables
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Summary — MC68HC11ED0
Section 1. General Description
Freescale Semiconductor, Inc...
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 Introduction
The MC68HC11ED0 is a low-cost member of the M68HC11 Family of
microcontrollers (MCU). This MCU has a multiplexed address/data bus
and is characterized by high speed and low-power consumption. The
fully static design allows operation at frequencies from 3 MHz to dc.
Pin count is minimized for cost-sensitive applications. Because there is
no on-chip read-only memory (ROM), this device is optimized for
expanded-bus systems. On-chip serial peripheral interface (SPI) and
serial communications interface (SCI) provide a convenient means or
transferring data to and from internal random-access memory (RAM).
Refer to Figure 1-1.
MC68HC11ED0 — Rev. 1.0
Technical Summary
General Description
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
General Description
1.3 Features
Freescale Semiconductor, Inc...
Features include:
•
M68HC11 CPU
•
Power-saving stop and wait modes
•
512 bytes of RAM
•
Multiplexed address and data buses
•
Enhanced 16-bit timer with 4-stage programmable prescaler
– Three input capture (IC) channels
– Four output compare (OC) channels
– One additional channel, selectable as fourth IC or fifth OC
•
8-bit pulse accumulator
•
Real-time interrupt circuit
•
Computer operating properly (COP) watchdog
•
Clock monitor
•
Enhanced asynchronous non-return-to-zero (NRZ) SCI
•
Enhanced SPI
•
Eight bidirectional input/output (I/O) lines
•
Three input-only lines
•
Three output-only lines (one output-only line in 40-pin package)
•
Packaging options:
– 44-pin plastic-leaded chip carrier (PLCC)
– 44-pin quad flat pack (QFP)
– 40-pin plastic dual in-line package (DIP)
Technical Summary
MC68HC11ED0 — Rev. 1.0
General Description
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
General Description
Structure
1.4 Structure
See Figure 1-1 for a block diagram of the MC68HC11ED0 MCU.
MODA/ MODB/
LIR
VSTBY
XTAL EXTAL
E
IRQ
OSC
RESET
INTERRUPT
LOGIC
MODE CONTROL
CLOCK LOGIC
PULSE ACCUMULATOR
COP TIMER
PAI
OC2
OC3
OC4
OC5/IC4/OC1
IC1
IC2
PERIODIC INTERRUPT
IC3
512 BYTES RAM
TIMER
SYSTEM
256 BYTES BOOTSTRAP ROM
M68HC11 CPU
SERIAL
COMMUNICATION
INTERFACE
SCI
TxD
RxD
LOW-ORDER
ADDRESS/DATA
SS
SCK
MOSI
MISO
HIGH-ORDER
ADDRESS
R/W
AS
SERIAL
PERIPHERAL
INTERFACE
SPI
CONTROL
PORT A
VDD
VSS
PD1/TxD
PD0/RxD
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
AS
R/W
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
PORT D
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
PA7/PAI/iOC1
PA6/OC2/OC1(1)
PA5/OC3/OC1
PA4/OC4/OC1(1)
PA3/IC4/OC5/OC1
PA2/IC1
PA1/IC2
PA0/IC3
Freescale Semiconductor, Inc...
XIRQ
Note 1. Not bonded in 40-pin package
Figure 1-1. MC68HC11ED0 Block Diagram
MC68HC11ED0 — Rev. 1.0
Technical Summary
General Description
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
General Description
1.5 Ordering Information
Table 1-1 provides ordering information for the MC68HC11ED0. Refer
to Section 2. Pin Assignments.
Table 1-1. Device Ordering Information
Package
Temperature
Description
Frequency
MC Order Number
2 MHz
MC68HC11ED0CFN2
3 MHz
MC68HC11ED0CFN3
2 MHz
MC68HC11ED0VFN2
3 MHz
MC68HC11ED0VFN3
2 MHz
MC68HC11ED0MFN2
3 MHz
MC68HC11ED0MFN3
2 MHz
MC68HC11ED0CFU2
3 MHz
MC68HC11ED0CFU3
2 MHz
MC68HC11ED0VFU2
3 MHz
MC68HC11ED0VFU3
2 MHz
MC68HC11ED0MFU2
3 MHz
MC68HC11ED0MFU3
2 MHz
MC68HC11ED0CP2
3 MHz
MC68HC11ED0CP3
2 MHz
MC68HC11ED0VP2
3 MHz
MC68HC11ED0VP3
2 MHz
MC68HC11ED0MP2
3 MHz
MC68HC11ED0MP3
Freescale Semiconductor, Inc...
–40°C to +85°C
44-pin PLCC
–40°C to +105°C
No ROM/EPROM
No EEPROM
512 bytes RAM
–40°C to +125°C
–40°C to +85°C
44-pin QFP
–40°C to +105°C
No ROM/EPROM
No EEPROM
512 bytes RAM
–40°C to +125°C
–40°C to +85°C
44-pin DIP
–40°C to +105°C
No ROM/EPROM
No EEPROM
512 bytes RAM
–40°C to +125°C
Technical Summary
MC68HC11ED0 — Rev. 1.0
General Description
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 2. Pin Assignments
Freescale Semiconductor, Inc...
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
44-Pin Plastic-Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . .20
2.4
44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5
40-Pin Plastic Dual In-Line Package (DIP) . . . . . . . . . . . . . . . . 22
2.2 Introduction
The MC68HC11ED0 pin assignments are shown here for these
packages:
•
44-pin plastic-leaded chip carrier (PLCC)
•
44-pin quad flat pack (QFP)
•
40-pin plastic dual in-line package (DIP)
MC68HC11ED0 — Rev. 1.0
Technical Summary
Pin Assignments
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin Assignments
2.3 44-Pin Plastic-Leaded Chip Carrier (PLCC)
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
VSS
EVSS(1)
XTAL
EXTAL
E
MODA/LIR
MODB/VSTBY
5
4
3
2
1
44
43
42
41
40
33
ADDR14
RESET
14
32
ADDR15
IRQ
15
31
NC
PD0/RxD
16
30
PA0/IC3
PD1/TxD
17
29
PA1/IC2
28
13
PA2/IC1
AS
27
ADDR13
PA3/IC4/OC5/OC1
R/W
34
26
ADDR12
12
25
XIRQ
35
PA4/OC4/OC1(1)
ADDR11
11
PA5/OC3/OC1
36
24
10
PA6/OC2/OC1(1)
ADDR7/DATA7
23
ADDR10
PA7/PAI/OC1
37
22
9
VDD
ADDR6/DATA6
21
ADDR9
PD5/SS
38
20
8
PD4/SCK
ADDR8
19
39
PD3/MOSI
ADDR5/DATA5
6
7
18
ADDR4/DATA4
PD2/MISO
Freescale Semiconductor, Inc...
Refer to Figure 2-1 for the 44-pin PLCC pin assignments.
Note 1. Not bonded in 40-pin package
Figure 2-1. Pin Assignments for 44-Pin PLCC
Technical Summary
MC68HC11ED0 — Rev. 1.0
Pin Assignments
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin Assignments
44-Pin Quad Flat Pack (QFP)
2.4 44-Pin Quad Flat Pack (QFP)
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
VSS
EVSS(1)
XTAL
EXTAL
E
MODA/LIR
MODB/VSTBY
43
42
41
40
39
38
37
36
35
34
28
ADDR13
AS
7
27
ADDR14
RESET
8
26
ADDR15
IRQ
9
25
NC
PD0/RxD
10
24
PA0/IC3
PD1/TxD
11
23
PA1/IC2
PA2/IC1
6
22
R/W
PA3/IC4/OC5/OC1
ADDR12
21
29
20
5
PA4/OC4/OC1(1)
XIRQ
19
ADDR11
PA5/OC3/OC1
30
18
4
PA6/OC2/OC1(1)
ADDR7/DATA7
17
ADDR10
PA7/PAI/OC1
31
16
3
VDD
ADDR6/DATA6
15
ADDR9
PD5/SS
32
14
2
PD4/SCK
ADDR8
13
33
PD3/MOSI
ADDR5/DATA5
44
1
12
ADDR4/DATA4
PD2/MISO
Freescale Semiconductor, Inc...
Refer to Figure 2-2 for the 44-pin QFP pin assignments.
Note 1. Not bonded in 40-pin package
Figure 2-2. Pin Assignments for 44-Pin QFP
MC68HC11ED0 — Rev. 1.0
Technical Summary
Pin Assignments
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin Assignments
2.5 40-Pin Plastic Dual In-Line Package (DIP)
Freescale Semiconductor, Inc...
Refer to Figure 2-3 for the 40-pin DIP pin assignments.
VSS
1
40
XTAL
ADDR0/DATA0
2
39
EXTAL
ADDR1/DATA1
3
38
E
ADDR2/DATA2
4
37
MODA/LIR
ADDR3/DATA3
5
36
MODB/VSTBY
ADDR4/DATA4
6
35
ADDR8
ADDR5/DATA5
7
34
ADDR9
ADDR6/DATA6
8
33
ADDR10
ADDR7/DATA7
9
32
ADDR11
XIRQ
10
31
ADDR12
R/W
11
30
ADDR13
AS
12
29
ADDR14
RESET
13
28
ADDR15
IRQ
14
27
PA0/IC3
PD0/RxD
15
26
PA1/IC2
PD1/TxD
16
25
PA2/IC1
PD2/MISO
17
24
PA3/IC4/OC5/OC1
PD3/MOSI
18
23
PA5/OC3/OC1
PD4/SCK
19
22
PA7/OC1
PD5/SS
20
21
VDD
Figure 2-3. Pin Assignments for 40-Pin DIP
Technical Summary
MC68HC11ED0 — Rev. 1.0
Pin Assignments
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 3. Central Processor Unit (CPU)
3.1 Contents
Freescale Semiconductor, Inc...
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1
Accumulators A, B, and D . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2
Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3
Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.3.6
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 29
3.3.6.1
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.6.2
Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.6.3
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.3.6.4
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.6.5
I-Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.6.6
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.3.6.7
X-Interrupt Mask (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.3.6.8
STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.1
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.2
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.3
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.4
Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.5
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.6
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
3.2 Introduction
Freescale Semiconductor, Inc...
This section presents information on M68HC11:
•
Central processor unit (CPU) architecture
•
Data types
•
Addressing modes
•
Instruction set
•
Special operations such as subroutine calls and interrupts
The CPU is designed to treat all peripheral, input/output (I/O), and
memory locations identically as addresses in the 64-Kbyte memory map.
This is referred to as memory-mapped I/O. I/O has no instructions
separate from those used by memory. This architecture also allows
accessing an operand from an external memory location with no
execution time penalty.
3.3 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not
addressed as if they were memory locations. The seven registers,
discussed in the following paragraphs, are shown in Figure 3-1.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
CPU Registers
7
15
A
0
7
B
0
0
D
IX
INDEX REGISTER X
IY
INDEX REGISTER Y
SP
STACK POINTER
PC
PROGRAM COUNTER
7
S
Freescale Semiconductor, Inc...
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
0
X
H
I
N
Z
V
C
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
Figure 3-1. Programming Model
3.3.1 Accumulators A, B, and D
Accumulators A and B are general-purpose 8-bit registers that hold
operands and results of arithmetic calculations or data manipulations.
For some instructions, these two accumulators are treated as a single
double-byte (16-bit) accumulator called accumulator D. Although most
instructions can use accumulators A or B interchangeably, these
exceptions apply:
•
The ABX and ABY instructions add the contents of 8-bit
accumulator B to the contents of 16-bit register X or Y, but there
are no equivalent instructions that use A instead of B.
•
The TAP and TPA instructions transfer data from accumulator A
to the condition code register or from the condition code register
to accumulator A. However, there are no equivalent instructions
that use B rather than A.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Central Processor Unit (CPU)
•
The decimal adjust accumulator A (DAA) instruction is used after
binary-coded decimal (BCD) arithmetic operations, but there is no
equivalent BCD instruction to adjust accumulator B.
•
The add, subtract, and compare instructions associated with both
A and B (ABA, SBA, and CBA) only operate in one direction,
making it important to plan ahead to ensure that the correct
operand is in the correct accumulator.
3.3.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the
8-bit offset provided in an instruction to create an effective address. The
IX register can also be used as a counter or as a temporary storage
register.
3.3.3 Index Register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that
of the IX register. However, most instructions using the IY register
require an extra byte of machine code and an extra cycle of execution
time because of the way the opcode map is implemented. Refer to
3.5 Opcodes and Operands for further information.
3.3.4 Stack Pointer (SP)
The M68HC11 CPU has an automatic program stack. This stack can be
located anywhere in the address space and can be any size up to the
amount of memory available in the system. Normally, the SP is initialized
by one of the first instructions in an application program. The stack is
configured as a data structure that grows downward from high memory
to low memory. Each time a new byte is pushed onto the stack, the SP
is decremented. Each time a byte is pulled from the stack, the SP is
incremented. At any given time, the SP holds the 16-bit address of the
next free location in the stack. Figure 3-2 is a summary of SP
operations.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
CPU Registers
JSR, JUMP TO SUBROUTINE
RTI, RETURN FROM INTERRUPT
MAIN PROGRAM
INTERRUPT ROUTINE
PC
PC
DIRECT
$9D = JSR
dd
RTN NEXT MAIN INSTR.
$3B = RTI
SP+2
SP+3
SP+4
PC
$AD = JSR
ff
RTN NEXT MAIN INSTR.
SP+5
7
SP–1
SP
PC
Freescale Semiconductor, Inc...
0
SP+6
➩ SP–2
MAIN PROGRAM
INDEXED, Y
STACK
$18 = PRE
$AD = JSR
RTN
ff
NEXT MAIN INSTR.
SP+7
SP+8
RTNH
RTNL
➩ SP+9
MAIN PROGRAM
PC
$3F = SWI
SP–6
WAI, WAIT FOR INTERRUPT
$8D = BSR
7
STACK
RTS, RETURN
FROM SUBROUTINE
MAIN PROGRAM
SP–3
$3E = WAI
SP–2
SP
STACK
SP
SP+1
CCR
ACCB
ACCA
IXH
IXL
IYH
IYL
RTNH
RTNL
LEGEND:
RTNH
RTNL
7
➩ SP+2
0
0
➩ SP–2
SP
$39 = RTS
SP–4
SP–1
SP–1
PC
SP–5
MAIN PROGRAM
BSR, BRANCH TO SUBROUTINE
STACK
➩ SP–9
SP–7
$BD = PRE
hh
RTN
ll
NEXT MAIN INSTR.
PC
PC
7
SP–8
MAIN PROGRAM
MAIN PROGRAM
0
SWI, SOFTWARE INTERRUPT
PC
INDEXED, Y
STACK
CCR
ACCB
ACCA
IXH
IXL
IYH
IYL
RTNH
RTNL
SP+1
MAIN PROGRAM
INDEXED, X
7
SP
RTNH
RTNL
0
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
BE EXECUTED UPON RETURN FROM SUBROUTINE
RTNH = MOST SIGNIFICANT BYTE OF RETURN ADDRESS
RTNL = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
➩ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
TO BE $00)
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
Figure 3-2. Stacking Operations
When a subroutine is called by a jump-to-subroutine (JSR) or branch-tosubroutine (BSR) instruction, the address of the instruction after the JSR
or BSR is automatically pushed onto the stack, least significant byte first.
When the subroutine is finished, a return-from-subroutine (RTS)
instruction is executed. The RTS pulls the previously stacked return
address from the stack and loads it into the program counter. Execution
then continues at this recovered return address.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
When an interrupt is recognized, the current instruction finishes
normally, the return address (the current value in the program counter)
is pushed onto the stack, all of the CPU registers are pushed onto the
stack, and execution continues at the address specified by the vector for
the interrupt.
Freescale Semiconductor, Inc...
At the end of the interrupt service routine, a return-from interrupt (RTI)
instruction is executed. The RTI instruction causes the saved registers
to be pulled off the stack in reverse order. Program execution resumes
at the return address.
Certain instructions push and pull the A and B accumulators and the X
and Y index registers and are often used to preserve program context.
For example, pushing accumulator A onto the stack when entering a
subroutine that uses accumulator A and then pulling accumulator A off
the stack just before leaving the subroutine ensures that the contents of
a register will be the same after returning from the subroutine as it was
before starting the subroutine.
3.3.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next
instruction to be executed. After reset, the program counter is initialized
from one of six possible vectors, depending on operating mode and the
cause of reset. See Table 3-1.
Table 3-1. Reset Vector Comparison
Mode
POR or RESET Pin
Clock Monitor
COP Watchdog
Normal
$FFFE, $FFFF
$FFFC, D
$FFFA, B
Test or boot
$BFFE, $BFFF
$BFFC, D
$BFFA, B
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
CPU Registers
3.3.6 Condition Code Register (CCR)
Freescale Semiconductor, Inc...
This 8-bit register contains:
•
Five condition code indicators (C, V, Z, N, and H),
•
Two interrupt masking bits (IRQ and XIRQ)
•
A stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by
most instructions. For example, load accumulator A (LDAA) and store
accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y
(ABY), and transfer/exchange instructions do not affect the condition
codes. Refer to Table 3-2, which shows what condition codes are
affected by a particular instruction.
3.3.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or
borrow during an arithmetic operation. The C bit also acts as an error flag
for multiply and divide operations. Shift and rotate instructions operate
with and through the carry bit to facilitate multiple-word shift operations.
3.3.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow.
Otherwise, the V bit is cleared.
3.3.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation
operation is 0. Otherwise, the Z bit is cleared. Compare instructions do
an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z bit and no other condition flags. For these
operations, only = and ≠ conditions can be determined.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
3.3.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result
is said to be negative if its most significant bit (MSB) is a 1. A quick way
to test whether the contents of a memory location has the MSB set is to
load it into an accumulator and then check the status of the N bit.
Freescale Semiconductor, Inc...
3.3.6.5 I-Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all
maskable interrupt sources. While the I bit is set, interrupts can become
pending, but the operation of the CPU continues uninterrupted until the
I bit is cleared. After any reset, the I bit is set by default and can be
cleared only by a software instruction. When an interrupt is recognized,
the I bit is set after the registers are stacked, but before the interrupt
vector is fetched. After the interrupt has been serviced, a
return-from-interrupt instruction is normally executed, restoring the
registers to the values that were present before the interrupt occurred.
Normally, the I bit is 0 after a return from interrupt is executed. Although
the I bit can be cleared within an interrupt service routine, "nesting"
interrupts in this way should be done only when there is a clear
understanding of latency and of the arbitration mechanism. Refer to
Section 5. Resets and Interrupts.
3.3.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H bit is cleared. Half carry is used during BCD operations.
3.3.6.7 X-Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any
reset, X is set by default and must be cleared by a software instruction.
When an XIRQ interrupt is recognized, the X and I bits are set after the
registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed,
causing the registers to be restored to the values that were present
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Data Types
before the interrupt occurred. The X interrupt mask bit is set only by
hardware (RESET or XIRQ acknowledge). X is cleared only by program
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6
of the value loaded into the CCR from the stack has been cleared).
There is no hardware action for clearing X.
Freescale Semiconductor, Inc...
3.3.6.8 STOP Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from
putting the M68HC11 into a low-power stop condition. If the STOP
instruction is encountered by the CPU while the S bit is set, it is treated
as a no-operation (NOP) instruction, and processing continues to the
next instruction. S is set by reset; STOP is disabled by default.
3.4 Data Types
The M68HC11 CPU supports four data types:
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. Because the M68HC11 is an 8-bit CPU,
there are no special requirements for alignment of instructions or
operands.
3.5 Opcodes and Operands
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each
opcode identifies a particular instruction and associated addressing
mode to the CPU. Several opcodes are required to provide each
instruction with a range of addressing capabilities. Only 256 opcodes
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
would be available if the range of values were restricted to the number
able to be expressed in 8-bit binary numbers.
Freescale Semiconductor, Inc...
A 4-page opcode map has been implemented to expand the number of
instructions. An additional byte, called a prebyte, directs the processor
from page 0 of the opcode map to one of the other three pages. As its
name implies, the additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero,
one, two, or three operands. The operands contain information the CPU
needs for executing the instruction. Complete instructions can be from
one to five bytes long.
3.6 Addressing Modes
Six addressing modes can be used to access memory:
•
Immediate
•
Direct
•
Extended
•
Indexed
•
Inherent
•
Relative
These modes are detailed in the following paragraphs. All modes except
inherent mode use an effective address. The effective address is the
memory address from which the argument is fetched or stored or the
address from which execution is to proceed. The effective address can
be specified within an instruction, or it can be calculated.
3.6.1 Immediate
In the immediate addressing mode, an argument is contained in the
byte(s) immediately following the opcode. The number of bytes following
the opcode matches the size of the register or memory location being
operated on. There are 2-, 3-, and 4- (if prebyte is required) byte
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Addressing Modes
immediate instructions. The effective address is the address of the byte
following the instruction.
Freescale Semiconductor, Inc...
3.6.2 Direct
In the direct addressing mode, the low-order byte of the operand
address is contained in a single byte following the opcode, and the
high-order byte of the address is assumed to be $00. Addresses
$00–$FF are thus accessed directly, using 2-byte instructions.
Execution time is reduced by eliminating the additional memory access
required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11
MCUs, the memory map can be configured for combinations of internal
registers, RAM, or external memory to occupy these addresses.
3.6.3 Extended
In the extended addressing mode, the effective address of the argument
is contained in two bytes following the opcode byte. These are 3-byte
instructions (or 4-byte instructions if a prebyte is required). One or two
bytes are needed for the opcode and two for the effective address.
3.6.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in
the instruction is added to the value contained in an index register (IX or
IY). The sum is the effective address. This addressing mode allows
referencing any memory location in the 64-Kbyte address space. These
are 2- to 5-byte instructions, depending on whether a prebyte is required.
3.6.5 Inherent
In the inherent addressing mode, all the information necessary to
execute the instruction is contained in the opcode. Operations that use
only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are
1- or 2-byte instructions.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
3.6.6 Relative
The relative addressing mode is used only for branch instructions. If the
branch condition is true, an 8-bit signed offset included in the instruction
is added to the contents of the program counter to form the effective
branch address. Otherwise, control proceeds to the next instruction.
These are usually 2-byte instructions.
Freescale Semiconductor, Inc...
3.7 Instruction Set
Refer to Table 3-2, which shows all the M68HC11 instructions in all
possible addressing modes. For each instruction, the table shows the
operand construction, the number of machine code bytes, and execution
time in CPU E-clock cycles.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 3-2. Instruction Set (Sheet 1 of 7)
Mnemonic
Operation
Description
ABA
Add
Accumulators
Add B to X
Add B to Y
Add with Carry
to A
A+B⇒A
Freescale Semiconductor, Inc...
ABX
ABY
ADCA (opr)
Addressing
Mode
INH
IX + (00 : B) ⇒ IX
IY + (00 : B) ⇒ IY
A+M+C⇒A
ADCB (opr)
Add with Carry
to B
B+M+C⇒B
ADDA (opr)
Add Memory to
A
A+M⇒A
ADDB (opr)
Add Memory to
B
B+M⇒B
ADDD (opr)
Add 16-Bit to D
D + (M : M + 1) ⇒ D
ANDA (opr)
AND A with
Memory
A•M⇒A
ANDB (opr)
AND B with
Memory
B•M⇒B
ASL (opr)
Arithmetic Shift
Left
C
ASLA
0
b0
b7
b0
b7
18
18
18
18
18
18
18
18
18
Instruction
Operand
—
3A
3A
89
99
B9
A9
A9
C9
D9
F9
E9
E9
8B
9B
BB
AB
AB
CB
DB
FB
EB
EB
C3
D3
F3
E3
E3
84
94
B4
A4
A4
C4
D4
F4
E4
E4
78
68
68
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
Cycles
2
S
—
X
—
Condition Codes
H
I
N
Z
∆
—
∆
∆
V
∆
C
∆
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
6
6
7
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
∆
—
—
∆
—
—
∆
—
—
∆
—
∆
∆
∆
∆
—
—
∆
—
∆
∆
∆
∆
—
—
∆
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
∆
∆
A
INH
48
—
2
—
—
—
—
∆
∆
∆
∆
B
INH
58
—
2
—
—
—
—
∆
∆
∆
∆
INH
05
—
3
—
—
—
—
∆
∆
∆
∆
77
67
67
47
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
∆
A
EXT
IND,X
IND,Y
INH
—
—
—
—
∆
∆
∆
∆
B
INH
57
—
2
—
—
—
—
∆
∆
∆
∆
REL
24
rr
3
—
—
—
—
—
—
—
—
DIR
IND,X
IND,Y
15
1D
1D
dd mm
ff mm
ff mm
6
7
8
—
—
—
—
∆
∆
0
—
0
Arithmetic Shift
Left B
C
ASLD
A
A
A
A
A
B
B
B
B
B
Arithmetic Shift
Left A
C
ASLB
b7
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
Opcode
1B
0
b0
Arithmetic Shift
Left D
0
C b7 A b0 b7 B b0
ASR
Arithmetic Shift
Right
ASRA
Arithmetic Shift
Right A
ASRB
Arithmetic Shift
Right B
BCC (rel)
Branch if Carry
Clear
Clear Bit(s)
b7
b7
b7
BCLR (opr)
(msk)
b0
b0
b0
C
18
C
C
?C=0
M • (mm) ⇒ M
18
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 3-2. Instruction Set (Sheet 2 of 7)
Mnemonic
Operation
Description
BCS (rel)
Branch if Carry
Set
Branch if = Zero
Branch if ∆ Zero
Branch if > Zero
Branch if
Higher
Branch if
Higher or Same
Bit(s) Test A
with Memory
?C=1
BEQ (rel)
BGE (rel)
BGT (rel)
BHI (rel)
BHS (rel)
Freescale Semiconductor, Inc...
BITA (opr)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
?C=0
REL
24
rr
3
—
—
—
—
—
—
—
—
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
REL
REL
REL
85
95
B5
A5
A5
C5
D5
F5
E5
E5
2F
25
23
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
rr
rr
2
3
4
4
5
2
3
4
4
5
3
3
3
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REL
REL
REL
2D
2B
26
rr
rr
rr
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REL
REL
DIR
IND,X
IND,Y
REL
DIR
IND,X
IND,Y
DIR
IND,X
IND,Y
REL
2A
20
13
1F
1F
21
12
1E
1E
14
1C
1C
8D
rr
rr
dd mm rr
ff mm rr
ff mm rr
rr
dd mm rr
ff mm rr
ff mm rr
dd mm
ff mm
ff mm
rr
3
3
6
7
8
3
6
7
8
6
7
8
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
A•M
A
A
A
A
A
B
B
B
B
B
Set Bit(s)
M + mm ⇒ M
Branch to
Subroutine
Branch if
Overflow Clear
Branch if
Overflow Set
Compare A to B
Clear Carry Bit
Clear Interrupt
Mask
Clear Memory
Byte
See Figure 3-2
Clear
Accumulator A
Clear
Accumulator B
Clear Overflow
Flag
Compare A to
Memory
0⇒A
0⇒B
CLRB
CLV
CMPA (opr)
C
—
—
—
—
—
?1=0
? (M) • mm = 0
CLRA
V
—
—
—
—
—
Branch Never
Branch if Bit(s)
Set
CLR (opr)
Condition Codes
H
I
N
Z
—
—
—
—
—
—
—
—
? Z + (N ⊕ V) = 1
?C=1
?C+Z=1
CBA
CLC
CLI
X
—
3
3
3
3
Branch if ∆ Zero
Branch if Lower
Branch if Lower
or Same
Branch if < Zero
Branch if Minus
Branch if not =
Zero
Branch if Plus
Branch Always
Branch if
Bit(s) Clear
BVS (rel)
S
—
rr
rr
rr
rr
BLE (rel)
BLO (rel)
BLS (rel)
BVC (rel)
Cycles
3
27
2C
2E
22
B•M
BSR (rel)
Instruction
Operand
rr
REL
REL
REL
REL
Bit(s) Test B
with Memory
BPL (rel)
BRA (rel)
BRCLR(opr)
(msk)
(rel)
BRN (rel)
BRSET(opr)
(msk)
(rel)
BSET (opr)
(msk)
Opcode
25
?Z=1
?N⊕V=0
? Z + (N ⊕ V) = 0
?C+Z=0
BITB (opr)
BLT (rel)
BMI (rel)
BNE (rel)
Addressing
Mode
REL
?N⊕V=1
?N=1
?Z=0
?N=0
?1=1
? M • mm = 0
18
18
18
18
18
?V=0
REL
28
rr
3
—
—
—
—
—
—
—
—
?V=1
REL
29
rr
3
—
—
—
—
—
—
—
—
A–B
0⇒C
0⇒I
INH
INH
INH
11
0C
0E
—
—
—
2
2
2
—
—
—
—
—
—
—
—
—
—
—
0
∆
—
—
∆
—
—
∆
—
—
∆
0
—
0⇒M
7F
6F
6F
4F
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
0
1
0
0
A
EXT
IND,X
IND,Y
INH
—
—
—
—
0
1
0
0
B
INH
5F
—
2
—
—
—
—
0
1
0
0
INH
0A
—
2
—
—
—
—
—
—
0
—
IMM
DIR
EXT
IND,X
IND,Y
81
91
B1
A1
A1
2
3
4
4
5
—
—
—
—
∆
∆
∆
∆
0⇒V
A–M
A
A
A
A
A
18
18
ii
dd
hh ll
ff
ff
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 3-2. Instruction Set (Sheet 3 of 7)
Mnemonic
Operation
Description
CMPB (opr)
Compare B to
Memory
B–M
COM (opr)
Ones
Complement
Memory Byte
Ones
Complement
A
Ones
Complement
B
Compare D to
Memory 16-Bit
$FF – M ⇒ M
COMA
Freescale Semiconductor, Inc...
COMB
CPD (opr)
B
B
B
B
B
$FF – A ⇒ A
A
$FF – B ⇒ B
B
D–M:M +1
Addressing
Mode
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
Cycles
2
3
4
4
5
6
6
7
2
S
—
X
—
Condition Codes
H
I
N
Z
∆
∆
—
—
—
—
—
—
∆
—
—
—
—
—
2
—
—
—
83
93
B3
A3
A3
8C
9C
BC
AC
AC
8C
9C
BC
AC
AC
19
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
—
5
6
7
7
7
4
5
6
6
7
5
6
7
7
7
2
—
—
—
7A
6A
6A
4A
hh ll
ff
ff
—
Opcode
C1
D1
F1
E1
18
E1
73
63
18
63
43
Instruction
Operand
ii
dd
hh ll
ff
ff
hh ll
ff
ff
—
53
1A
1A
1A
1A
CD
V
∆
C
∆
∆
0
1
∆
∆
0
1
—
∆
∆
0
1
—
—
∆
∆
∆
∆
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
6
6
7
2
—
—
—
—
∆
∆
∆
—
—
—
—
—
∆
∆
∆
—
CPX (opr)
Compare X to
Memory 16-Bit
IX – M : M + 1
CPY (opr)
Compare Y to
Memory 16-Bit
IY – M : M + 1
DAA
Decimal Adjust
A
Decrement
Memory Byte
Adjust Sum to BCD
Decrement
Accumulator
A
Decrement
Accumulator
B
Decrement
Stack Pointer
Decrement
Index Register
X
Decrement
Index Register
Y
Exclusive OR A
with Memory
A–1⇒A
A
EXT
IND,X
IND,Y
INH
B–1⇒B
B
INH
5A
—
2
—
—
—
—
∆
∆
∆
—
SP – 1 ⇒ SP
INH
34
—
3
—
—
—
—
—
—
—
—
IX – 1 ⇒ IX
INH
09
—
3
—
—
—
—
—
∆
—
—
IY – 1 ⇒ IY
INH
09
—
4
—
—
—
—
—
∆
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
—
2
3
4
4
5
2
3
4
4
5
41
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
∆
∆
∆
DEC (opr)
DECA
DECB
DES
DEX
DEY
M–1⇒M
A⊕M⇒A
18
18
EORB (opr)
Exclusive OR B
with Memory
B⊕M⇒B
FDIV
Fractional
Divide 16 by 16
Integer Divide
16 by 16
Increment
Memory Byte
D / IX ⇒ IX; r ⇒ D
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
D / IX ⇒ IX; r ⇒ D
INH
02
—
41
—
—
—
—
—
∆
0
∆
EXT
IND,X
IND,Y
INH
7C
6C
6C
4C
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
—
—
—
—
—
∆
∆
∆
—
EORA (opr)
IDIV
INC (opr)
INCA
Increment
Accumulator
A
A
A
A
A
A
B
B
B
B
B
CD
18
18
18
1A
18
M+1⇒M
A+1⇒A
A
18
18
18
88
98
B8
A8
A8
C8
D8
F8
E8
E8
03
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 3-2. Instruction Set (Sheet 4 of 7)
Mnemonic
Operation
Description
INCB
Increment
Accumulator
B
Increment
Stack Pointer
Increment
Index Register
X
Increment
Index Register
Y
Jump
B+1⇒B
INS
INX
INY
Freescale Semiconductor, Inc...
JMP (opr)
Addressing
Mode
B
INH
—
—
—
—
—
—
IX + 1 ⇒ IX
INH
08
—
3
—
—
—
—
—
∆
—
—
IY + 1 ⇒ IY
INH
08
—
4
—
—
—
—
—
∆
—
—
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
—
3
3
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
LDAB (opr)
Load
Accumulator
B
M⇒B
LDD (opr)
Load Double
Accumulator
D
M ⇒ A,M + 1 ⇒ B
LDS (opr)
Load Stack
Pointer
M : M + 1 ⇒ SP
LDX (opr)
Load Index
Register
X
M : M + 1 ⇒ IX
LDY (opr)
Load Index
Register
Y
M : M + 1 ⇒ IY
LSL (opr)
Logical Shift
Left
C
b7
b0
b7
b0
Logical Shift
Left B
C
b7
b0
B
INH
58
—
2
—
—
—
—
∆
∆
∆
∆
INH
05
—
3
—
—
—
—
∆
∆
∆
∆
EXT
IND,X
IND,Y
INH
74
64
64
44
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
0
∆
∆
∆
b0
—
—
—
—
0
∆
∆
∆
b7
b0
18
18
18
18
18
CD
18
18
18
1A
18
18
0
0
C
A
0
18
7E
6E
6E
9D
BD
AD
AD
86
96
B6
A6
A6
C6
D6
F6
E6
E6
CC
DC
FC
EC
EC
8E
9E
BE
AE
AE
CE
DE
FE
EE
EE
CE
DE
FE
EE
EE
78
68
68
48
0
b7 A b0 b7 B b0
b7
A
0
Logical Shift
Left Double
Logical Shift
Right A
18
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
A
A
A
A
A
B
B
B
B
B
Logical Shift
Left A
C
LSRA
C
—
—
M⇒A
0
V
∆
—
See Figure 3–2
C
Condition Codes
H
I
N
Z
—
—
∆
∆
3
Load
Accumulator
A
Logical Shift
Right
X
—
—
LDAA (opr)
LSR (opr)
S
—
31
See Figure 3–2
LSLD
Cycles
2
INH
Jump to
Subroutine
LSLB
Instruction
Operand
—
SP + 1 ⇒ SP
JSR (opr)
LSLA
Opcode
5C
18
C
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 3-2. Instruction Set (Sheet 5 of 7)
Mnemonic
Operation
LSRB
Logical Shift
Right B
LSRD
Logical Shift
Right Double
MUL
NEG (opr)
Freescale Semiconductor, Inc...
NEGA
NEGB
NOP
ORAA (opr)
Multiply 8 by 8
Two’s
Complement
Memory Byte
Two’s
Complement
A
Two’s
Complement
B
No operation
OR
Accumulator
A (Inclusive)
ORAB (opr)
OR
Accumulator
B (Inclusive)
PSHA
ROL (opr)
Push A onto
Stack
Push B onto
Stack
Push X onto
Stack (Lo
First)
Push Y onto
Stack (Lo
First)
Pull A from
Stack
Pull B from
Stack
Pull X From
Stack (Hi
First)
Pull Y from
Stack (Hi
First)
Rotate Left
ROLA
Rotate Left A
ROLB
Rotate Left B
ROR (opr)
Rotate Right
RORA
Rotate Right A
RORB
Rotate Right B
RTI
Return from
Interrupt
PSHB
PSHX
PSHY
PULA
PULB
PULX
PULY
Addressing
Mode
B
INH
Description
0
0
b7
b0
Opcode
54
Instruction
Operand
—
Cycles
2
S
—
X
—
Condition Codes
H
I
N
Z
—
—
0
∆
V
∆
C
∆
C
INH
04
—
3
—
—
—
—
0
∆
∆
∆
3D
70
60
60
40
—
hh ll
ff
ff
—
10
6
6
7
2
—
—
—
—
—
—
—
—
—
∆
—
∆
—
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
2
—
—
—
—
∆
∆
∆
∆
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
—
2
2
3
4
4
5
2
3
4
4
5
3
—
—
—
—
—
—
—
—
—
∆
—
∆
—
0
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
b7 A b0 b7 B b0 C
A∗B⇒D
0–M⇒M
0–A⇒A
A
INH
EXT
IND,X
IND,Y
INH
0–B⇒B
B
INH
50
A
A
A
A
A
B+M⇒B
B
B
B
B
B
A ⇒ Stk,SP = SP – 1 A
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
01
8A
9A
BA
AA
AA
CA
DA
FA
EA
EA
36
B ⇒ Stk,SP = SP – 1 B
INH
37
—
3
—
—
—
—
—
—
—
—
IX ⇒ Stk,SP = SP – 2
INH
3C
—
4
—
—
—
—
—
—
—
—
IY ⇒ Stk,SP = SP – 2
INH
3C
—
5
—
—
—
—
—
—
—
—
SP = SP + 1, A ⇐ Stk A
INH
32
—
4
—
—
—
—
—
—
—
—
SP = SP + 1, B ⇐ Stk B
INH
33
—
4
—
—
—
—
—
—
—
—
SP = SP + 2, IX ⇐ Stk
INH
38
—
5
—
—
—
—
—
—
—
—
SP = SP + 2, IY ⇐ Stk
INH
18
38
—
6
—
—
—
—
—
—
—
—
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
∆
18
79
69
69
49
—
—
—
—
∆
∆
∆
∆
No Operation
A+M⇒A
C
C
C
b7
b7
b7
b7
b7
b7
18
18
18
18
A
EXT
IND,X
IND,Y
INH
B
INH
59
—
2
—
—
—
—
∆
∆
∆
∆
76
66
66
46
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
∆
A
EXT
IND,X
IND,Y
INH
—
—
—
—
∆
∆
∆
∆
B
INH
56
—
2
—
—
—
—
∆
∆
∆
∆
INH
3B
—
12
∆
↓
∆
∆
∆
∆
∆
∆
b0
b0
b0
b0 C
18
b0 C
b0 C
See Figure 3–2
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 3-2. Instruction Set (Sheet 6 of 7)
Mnemonic
Operation
Description
RTS
Return from
Subroutine
Subtract B from
A
Subtract with
Carry from A
See Figure 3-2
SBCB (opr)
Subtract with
Carry from B
B–M–C⇒B
SEC
SEI
Set Carry
Set Interrupt
Mask
Set Overflow
Flag
Store
Accumulator
A
SBA
Freescale Semiconductor, Inc...
SBCA (opr)
SEV
STAA (opr)
A–B⇒A
Cycles
5
S
—
X
—
Condition Codes
H
I
N
Z
—
—
—
—
—
2
—
—
—
—
∆
—
—
—
—
V
—
C
—
∆
∆
∆
∆
∆
∆
∆
82
92
B2
A2
A2
C2
D2
F2
E2
E2
0D
0F
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
—
—
2
3
4
4
5
2
3
4
4
5
2
2
—
—
—
—
∆
∆
∆
∆
1⇒C
1⇒I
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
—
—
—
—
—
—
—
1
—
—
—
—
—
—
1
—
1⇒V
INH
0B
—
2
—
—
—
—
—
—
1
—
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
INH
97
B7
A7
A7
D7
F7
E7
E7
DD
FD
ED
ED
CF
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
—
3
4
4
5
3
4
4
5
4
5
5
6
2
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
9F
BF
AF
AF
DF
FF
EF
EF
DF
FF
EF
EF
80
90
B0
A0
A0
C0
D0
F0
E0
E0
83
93
B3
A3
A3
3F
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
—
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
14
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
1
—
—
—
—
A–M–C⇒A
A⇒M
B⇒M
STD (opr)
Store
Accumulator
D
A ⇒ M, B ⇒ M + 1
STOP
Stop Internal
Clocks
Store Stack
Pointer
—
A
A
A
A
A
B
B
B
B
B
A
A
A
A
B
B
B
B
SP ⇒ M : M + 1
STX (opr)
Store Index
Register X
IX ⇒ M : M + 1
STY (opr)
Store Index
Register Y
IY ⇒ M : M + 1
SUBA (opr)
Subtract
Memory from
A
A–M⇒A
SUBB (opr)
Subtract
Memory from
B
B–M⇒B
SUBD (opr)
Subtract
Memory from
D
D–M:M+1⇒D
SWI
Software
Interrupt
Transfer A to B
Transfer A to
CC Register
Transfer B to A
See Figure 3–2
TBA
Instruction
Operand
—
10
Store
Accumulator
B
TAB
TAP
Opcode
39
INH
STAB (opr)
STS (opr)
Addressing
Mode
INH
A
A
A
A
A
A
A
A
A
A
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
18
18
18
18
18
18
CD
18
18
1A
18
18
18
18
A⇒B
A ⇒ CCR
INH
INH
16
06
—
—
2
2
—
∆
—
↓
—
∆
—
∆
∆
∆
∆
∆
0
∆
—
∆
B⇒A
INH
17
—
2
—
—
—
—
∆
∆
0
—
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 3-2. Instruction Set (Sheet 7 of 7)
Mnemonic
Operation
Description
TEST
TEST (Only in
Test Modes)
Transfer CC
Register to A
Test for Zero or
Minus
Address Bus Counts
Test A for Zero
or Minus
Test B for Zero
or Minus
Transfer Stack
Pointer to X
Transfer Stack
Pointer to Y
Transfer X to
Stack Pointer
Transfer Y to
Stack Pointer
Wait for
Interrupt
Exchange D
with X
Exchange D
with Y
A–0
B–0
TPA
TST (opr)
TSTA
TSTB
Freescale Semiconductor, Inc...
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
Cycle
*
**
Addressing
Mode
INH
CCR ⇒ A
Opcode
00
Instruction
Operand
—
Cycles
*
S
—
X
—
Condition Codes
H
I
N
Z
—
—
—
—
V
—
C
—
INH
07
—
2
—
—
—
—
—
—
—
—
7D
6D
6D
4D
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
0
0
A
EXT
IND,X
IND,Y
INH
—
—
—
—
∆
∆
0
0
B
INH
5D
—
2
—
—
—
—
∆
∆
0
0
SP + 1 ⇒ IX
INH
30
—
3
—
—
—
—
—
—
—
—
SP + 1 ⇒ IY
INH
30
—
4
—
—
—
—
—
—
—
—
IX – 1 ⇒ SP
INH
35
—
3
—
—
—
—
—
—
—
—
IY – 1 ⇒ SP
INH
35
—
4
—
—
—
—
—
—
—
—
Stack Regs & WAIT
INH
3E
—
**
—
—
—
—
—
—
—
—
IX ⇒ D, D ⇒ IX
INH
8F
—
3
—
—
—
—
—
—
—
—
IY ⇒ D, D ⇒ IY
INH
8F
—
4
—
—
—
—
—
—
—
—
M–0
18
18
18
18
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
Operands
dd
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
ff
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh
= High-order byte of 16-bit extended address
ii
= One byte of immediate data
jj
= High-order byte of 16-bit immediate data
kk
= Low-order byte of 16-bit immediate data
ll
= Low-order byte of 16-bit extended address
mm
= 8-bit mask (set bits to be affected)
rr
= Signed relative offset $80 (–128) to $7F (+127)
(offset relative to address following machine code offset byte))
Operators
()
Contents of register shown inside parentheses
⇐
Is transferred to
⇑
Is pulled from stack
⇓
Is pushed onto stack
•
Boolean AND
+
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
⊕
Exclusive-OR
∗
Multiply
:
Concatenation
–
Arithmetic subtraction symbol or negation symbol (two’s complement)
Condition Codes
—
Bit not changed
0
Bit always cleared
1
Bit always set
∆
Bit cleared or set, depending on operation
↓
Bit can be cleared, cannot become set
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Central Processor Unit (CPU)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 4. Operating Modes and On-Chip Memory
4.1 Contents
Freescale Semiconductor, Inc...
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.1
Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2
Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.3
Expanded Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5
On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5.1
Memory Map and Register Block . . . . . . . . . . . . . . . . . . . . . 49
4.5.2
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.2 Introduction
The MC68HC11ED0 microcontroller (MCU) has three modes of
operation. For expanded and special test modes, there are no reset or
interrupt vectors contained in on-chip resources. An external memory
must be used to provide vectors at locations $FFC0–$FFFF. In
bootstrap mode, a small on-chip read-only memory (ROM) becomes
present in the memory map and provides the vectors for this mode.
Refer to Figure 4-3.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
4.3 Operating Modes
This subsection describes the three memory modes:
•
Bootstrap mode
•
Special test mode
•
Expanded operating mode
Freescale Semiconductor, Inc...
Refer to Figure 4-3.
4.3.1 Bootstrap Mode
Bootstrap mode allows special-purpose programs to be entered into
internal random-access memory (RAM). The MCU contains 256 bytes of
bootstrap ROM which is enabled and present in the memory map only
when the device is in bootstrap mode. The bootstrap ROM contains a
small program which initializes the serial communications interface (SCI)
and allows the user to download exactly 256 bytes of code into on-chip
RAM. After receiving the character for address $01FF, control passes to
the loaded program at $0100. Vectors are present on chip and located
at $BFC0–$BFFF.
4.3.2 Special Test Mode
Special test mode is used primarily for factory testing. In this operating
mode, vectors must be provided externally at $BFC0–$BFFF.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Operating Modes
4.3.3 Expanded Operating Mode
In expanded operating mode, the MCU has a 64-Kbyte address range
and, using the expansion bus, can access external resources within the
64-Kbyte space. This space includes:
•
On-chip memory addresses
•
Addressing capabilities for external peripheral and memory
devices
Freescale Semiconductor, Inc...
In expanded operating mode, high-order address bits are output on
ADDR[15:8] pins, low-order address bits and the data bus are
multiplexed on ADDR/DATA[7:0]. Refer to Figure 1-1. MC68HC11ED0
Block Diagram.
The read/write (R/W) and address strobe (AS) signals allow the
low-order address and the 8-bit data bus to be time-multiplexed on the
same pins.
•
During the first half of each bus cycle, address information is
present.
•
During the second half of each bus cycle, the pins become the
bidirectional data bus.
AS is an active-high latch enable signal for an external address latch.
Address information is allowed through the transparent latch while AS is
high and is latched when AS drives low. The address, R/W, and AS
signals are active and valid for all bus cycles including accesses to
internal memory locations.
The E clock is used to enable external devices to drive data onto the
internal data bus during the second half of a read bus cycle (E clock
high). R/W controls the direction of data transfers. R/W drives low when
data is being written to the external data bus. R/W will remain low during
consecutive data bus write cycles, such as when a double-byte store
occurs. Refer to Figure 4-1 for an example of address and data
multiplexing.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Freescale Semiconductor, Inc...
MCU
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
MC54/74HC373
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
AS
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
LE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q0
R/W
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
WE
E
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 4-1. Address and Data Demultiplexing
4.4 Mode Selection
Operating modes are selected by a combination of logic levels applied
to two input pins (MODA and MODB) during reset. The logic level
present (at the rising edge of reset) on these inputs is reflected in bits in
the highest priority I-bit interrupt and miscellaneous (HPRIO) register.
After reset, the operating mode may be changed as shown in Figure 4-2.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Mode Selection
Address:
$003C
Bit 7
Read:
6
RBOOT (1) SMOD(1)
5
4
3
2
1
Bit 0
MDA(1)
IRVNE(1)
PSEL3
PSEL2
PSEL1
PSEL0
1
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
Write:
Freescale Semiconductor, Inc...
Resets:
Expanded:
Bootstrap:
Special Test:
0
1
0
0
1
1
1. The reset values depend on the mode selected at power-up.
Figure 4-2. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
RBOOT — Read Bootstrap ROM Bit
Valid only when SMOD is set (bootstrap or special test mode); can be
written only in special modes
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BE00–$BFFF
SMOD and MDA — Special Mode Select and Mode Select A Bits
The initial value of SMOD is the inverse of the logic level present on
the MODB pin at the rising edge of reset. The initial value of MDA
equals the logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written any
time in special modes. MDA can be written only once in normal
modes. SMOD cannot be set once it has been cleared.
Input
Latched at Reset
Mode
MODB MODA
CAUTION:
SMOD
MDA
1
0
High-impedance state ADDR/DATA
(CPU held in reset)
0
0
1
1
Expanded
0
1
0
0
Bootstrap
1
0
0
1
Special test
1
1
Unlike other M68HC11 Family devices, the MC68HC11ED0 will not
function in single-chip operating mode. If MODA is pulled low and MODB
is pulled high at the rising edge of reset (the condition that causes most
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
M68HC11 devices to enter single-chip mode) the CPU will remain in
reset until the RESET pin is pulled low then released with appropriate
logic levels applied to MODA and MODB.
IRVNE — Internal Read Visibility/Not E Bit
Freescale Semiconductor, Inc...
IRVNE can be written once in any mode. In special test mode, IRVNE
is reset to 1. In all other modes, IRVNE is reset to 0.
In expanded test modes, IRVNE determines whether internal read
visibility (IRV) is on or off.
0 = No internal read visibility on external bus
1 = Data from internal reads driven out the external data bus
In bootstrap mode, IRVNE determines whether the E clock drives out
from the chip.
0 = E driven out from the chip
1 = E pin driven low
Mode
IRVNE Out E Clock Out IRV Out
IRVNE
IRVNE Can
of Reset
of Reset
of Reset Affects Only Be Written
Expanded
0
On
Off
IRV
Once
Bootstrap
0
On
Off
E
Once
Special test
1
On
On
IRV
Once
PSEL[3:0] — Priority Select Bits
Refer to Section 5. Resets and Interrupts.
4.5 On-Chip Memory
The MC68HC11ED0 contains 512 bytes of on-chip static RAM. There is
no on-chip ROM. Since the MC68HC11ED0 is intended for expanded
mode applications only, reset and interrupt vectors are not contained in
on-chip resources. An external memory must provide these at locations
$FFC0–$FFFF. Refer to Figure 4-3.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
On-Chip Memory
4.5.1 Memory Map and Register Block
Freescale Semiconductor, Inc...
The INIT register controls the location of the register block and RAM in
the 64-Kbyte central processor unit (CPU) address space. The 64-Kbyte
register block originates at $0000 after reset and can be placed at any
4-Kbyte boundary ($x000) by writing an appropriate value to the INIT
register. Since the RAM also begins at $0000 after reset, 64 bytes are
overlaid by the register block. Registers are a higher priority resource
than RAM. Therefore, the RAM which is overlaid by registers is
inaccessible. Either the registers or the RAM must be remapped to gain
access to all 512 bytes of the RAM. Refer to Figure 4-3 and Figure 4-4.
$0000
$0040
$0000
$003F
$0040
$01FF
$0200
$103F
EXT
64-BYTE REGISTER BLOCK(1)
CAN BE REMAPPED TO ANY
4-K PAGE BY THE INIT REGISTER
448 BYTES RAM(1)
CAN BE REMAPPED TO ANY
4-K PAGE BY THE INIT REGISTER
EXT
EXT
$BF00 BOOT
ROM
$BFFF
EXT
$BFC0 SPECIAL MODES
INTERRUPT
$BFFF VECTORS
EXT
$FFC0 NORMAL MODE
INTERRUPT VECTORS
$FFFF EXTERNAL
$FFC0
$FFFF
EXPANDED
BOOTSTRAP
SPECIAL
TEST
Note 1. To access the full 512 bytes of RAM, remap either the register block
or the RAM to any 4-K ($x000) boundary.
Figure 4-3. MC68HC11ED0 Memory Map
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
$0000
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
U
0
0
0
U
U
U
U
Reserved
R
R
R
R
R
R
R
R
Reserved
R
R
R
R
R
R
R
R
PD5
PD4
PD3
PD2
PD1
PD0
U
U
U
U
U
U
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read:
Port A Data Register
(PORTA) Write:
See page 66.
Reset:
$0001
↓
Freescale Semiconductor, Inc...
$0007
$0008
$0009
Port D Data Register Read:
(PORTD)
Write:
See page 68.
Reset:
Read:
Port D Data Direction
Register (DDRD) Write:
See page 69.
Reset:
$000A
$000B
$000C
$000D
$000E
Reserved
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
FOC2
FOC3
FOC4
FOC5
0
0
0
0
0
0
0
OC1M5
OC1M4
OC1M3
0
0
0
0
0
0
OC1D6
OC1D5
OC1D4
OC1D3
0
0
0
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
R
= Reserved
Read:
Timer Compare Force
FOC1
Register (CFORC) Write:
See page 91.
Reset:
0
Read:
Output Compare 1 Mask
OC1M7 OC1M6
Register (OC1M) Write:
See page 92.
Reset:
0
0
Read:
Output Compare 1 Data
OC1D7
Register (OC1D) Write:
See page 92.
Reset:
0
Read: Bit 15
Timer Count Register High
(TCNT) Write:
See page 93.
Reset:
0
= Unimplemented
U = Unaffected
Figure 4-4. Register and Control Bit Assignments (Sheet 1 of 6)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
On-Chip Memory
Addr.
$000F
Register Name
Read:
Timer Count Register Low
(TCNT) Write:
See page 93.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Freescale Semiconductor, Inc...
Read:
Timer Input Capture Register 1
Bit 15
$0010
High (TIC1) Write:
See page 94.
Reset:
Read:
Timer Input Capture Register 1
$0011
Low (TIC1) Write:
See page 94.
Reset:
Bit 7
Bit 7
$0016
$0017
Bit 7
Bit 4
Bit 3
Bit 14
Bit 13
Bit 12
Bit 11
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 14
Bit 13
Bit 12
Bit 11
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
Read:
Timer Output Compare
Bit 15
Register 1 High (TOC1) Write:
See page 95.
Reset:
1
Read:
Timer Output Compare
Register 1 Low (TOC1) Write:
See page 95.
Reset:
Bit 5
Unaffected by reset
Read:
Timer Input Capture Register 3
Bit 15
$0014
High (TIC3) Write:
See page 94.
Reset:
Read:
Timer Input Capture Register 3
$0015
Low (TIC3) Write:
See page 94.
Reset:
Bit 6
Unaffected by reset
Read:
Timer Input Capture Register 2
Bit 15
$0012
High (TIC2) Write:
See page 94.
Reset:
Read:
Timer Input Capture Register 2
$0013
Low (TIC2) Write:
See page 94.
Reset:
Unaffected by reset
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
R
= Reserved
= Unimplemented
U = Unaffected
Figure 4-4. Register and Control Bit Assignments (Sheet 2 of 6)
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
$0018
Freescale Semiconductor, Inc...
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0
0
0
0
0
0
0
0
R
= Reserved
Read:
Timer Output Compare
Bit 15
Register 2 High (TOC2) Write:
See page 95.
Reset:
1
Read:
Timer Output Compare
Register 2 Low (TOC2) Write:
See page 95.
Reset:
Read:
Timer Output Compare
Bit 15
Register 3 High (TOC3) Write:
See page 95.
Reset:
1
Read:
Timer Output Compare
Register 3 Low (TOC3) Write:
See page 95.
Reset:
Read:
Timer Output Compare
Bit 15
Register 4 High (TOC4) Write:
See page 96.
Reset:
1
Read:
Timer Output Compare
Register 4 Low (TOC4) Write:
See page 96.
Reset:
Read:
Timer Input Capture4/Output
Bit 15
Compare 5 High (TI4/O5) Write:
See page 96.
Reset:
1
Read:
Timer Input Capture4/Output
Compare 5 Low (TI4/O5) Write:
See page 96.
Reset:
Read:
Timer Control Register 1
(TCTL1) Write:
See page 97.
Reset:
= Unimplemented
U = Unaffected
Figure 4-4. Register and Control Bit Assignments (Sheet 3 of 6)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
On-Chip Memory
Addr.
$0021
Freescale Semiconductor, Inc...
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
0
0
0
0
0
0
0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
TOI
RTII
PAOVI
PAII
PR1
PR0
0
0
0
0
TOF
RTIF
PAOVF
PAIF
0
0
0
PAEN
Read:
Timer Control Register 2
EDG4B
(TCTL2) Write:
See page 98.
Reset:
0
Read:
Timer Interrupt Mask 1
Register (TMSK1) Write:
See page 99.
Reset:
Read:
Timer Interrupt Flag 1
OC1F
Register (TFLG1) Write:
See page 100.
Reset:
0
Read:
Timer Interrupt Mask 2
Register (TMSK2) Write:
See page 100.
Reset:
Read:
Timer Interrupt Flag 2
Register (TFLG2) Write:
See page 102.
Reset:
Read:
Pulse Accumulator Control
DDRA7
Register (PACTL) Write:
See page 104.
Reset:
0
Read:
Pulse Accumulator Counter
Register (PACNT) Write:
See page 106.
Reset:
Read:
Serial Peripheral Control
Register (SPCR) Write:
See page 83.
Reset:
Read:
Serial Peripheral Status
Register (SPSR) Write:
See page 85.
Reset:
Bit 7
0
0
0
0
0
0
0
0
0
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unaffected by reset
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
0
0
1
0
0
SPIF
WCOL
0
0
0
0
0
0
0
R
= Reserved
MODF
0
= Unimplemented
U = Unaffected
Figure 4-4. Register and Control Bit Assignments (Sheet 4 of 6)
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
$002A
Freescale Semiconductor, Inc...
$002B
$002C
$002D
$002E
$002F
Register Name
Read:
SPI Data Register I/O
(SPDR) Write:
See page 86.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Read:
Baud Rate Register
TCLR
(BAUD) Write:
See page 74.
Reset:
0
Read:
SCI Control Register 1
(SCCR1) Write:
See page 77.
Reset:
Read:
SCI Control Register 2
(SCCR2) Write:
See page 78.
Reset:
SCP0
RCKB
SCR2
SCR1
SCR0
0
0
0
U
U
U
M
WAKE
R8
T8
0
0
0
0
0
0
0
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
TC
RDRF
IDLE
OR
NF
FE
1
0
0
0
0
0
0
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Read:
SCI Status Register
TDRE
(SCSR) Write:
See page 79.
Reset:
1
Read:
SCI Data Register
R7/T7
(SCDR) Write:
See page 80.
Reset:
$0030
0
SCP1
Unaffected by reset
Reserved
R
R
R
R
R
R
R
R
Reserved
R
R
R
R
R
R
R
R
IRQE(1)
DLY(1)
CME
CR1(1)
CR0 (1)
0
1
0
0
0
↓
$0038
$0039
Read:
System Configuration Options
Register (OPTION) Write:
See page 60.
Reset:
0
0
0
Note 1. Can be written only once in the first 64 cycles out of reset in normal modes or at any time in special modes.
= Unimplemented
R
= Reserved
U = Unaffected
Figure 4-4. Register and Control Bit Assignments (Sheet 5 of 6)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
On-Chip Memory
Addr.
$003A
$003B
Freescale Semiconductor, Inc...
$003C
Register Name
Read:
Arm/Reset COP Timer
Circuitry Register (COPRST) Write:
See page 61.
Reset:
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
SMOD
MDA
IRVNE(1)
PSEL3
PSEL2
PSEL1
PSEL0
Note 1
Note 1
U
0
1
0
1
Highest Priority I-Bit Interrupt Read:
RBOOT
and Miscellaneous Register
Write:
(HPRIO)
See page 63. Reset: Note 1
Note 1. RBOOT, SMOD, and MDA reset depends on power-up initialization mode and can be written only in special mode.
$003D
$003E
RAM and Register Mapping Read:
RAM3
Register (INIT)
Write:
See page 56.
Reset:
0
Reserved
R
Read:
System Configuration Register
$003F
(CONFIG) Write:
See page 62.
Reset:
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
0
0
NOCOP
0
0
0
= Unimplemented
0
0
R
= Reserved
0
U = Unaffected
Figure 4-4. Register and Control Bit Assignments (Sheet 6 of 6)
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
4.5.2 RAM
Freescale Semiconductor, Inc...
The MC68HC11ED0 has 512 bytes of on-chip static RAM. The RAM can
be mapped to any 4-Kbyte boundary. Upon reset, the RAM is mapped at
$0000–$01FF. The register block also begins at $0000 and overlaps the
RAM space. Since registers have priority over RAM, this causes 64
bytes of RAM to be lost. However, the user can map either the RAM or
the register block to any 4-Kbyte boundary ($x000) and access the full
512 bytes of RAM. Remapping is accomplished by writing appropriate
values to the INIT register.
When power is removed form the MCU, RAM contents may be
preserved using the MODB/VSTBY pin. A 4-volt nominal power source
applied to this pin protects all 512 bytes of RAM.
Address:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 4-5. RAM and Register Mapping Register (INIT)
NOTE:
INIT can be written only once in the first 64-cycles out of reset in normal
modes or at any time in special modes.
RAM[3:0] — Internal RAM Map Position Bits
These bits determine the upper four bits of the RAM address. At reset
RAM is mapped to $0000 and includes the register block. Refer to
Figure 4-3.
REG[3:0] — 128-Byte Register Block Map Position Bits
These bits determine the upper four bits of the register space
address. At reset registers are mapped to $0000 and overwrite the
first 64 bytes of RAM. Refer to Figure 4-3.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 5. Resets and Interrupts
Freescale Semiconductor, Inc...
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4
System Configuration Options Register . . . . . . . . . . . . . . . . . . 60
5.5
Arm/Reset COP Timer Circuitry Register . . . . . . . . . . . . . . . . . 61
5.6
Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.7
Highest Priority I-Bit Interrupt
and Miscellaneous Register. . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Introduction
This section describes the MC68HC11ED0 reset and interrupt structure.
5.3 Resets
The MC68HC11ED0 has three reset vectors and 18 interrupt vectors.
The reset vectors are:
•
RESET or power-on reset
•
Clock monitor fail
•
Computer operating properly (COP) failure
MC68HC11ED0 — Rev. 1.0
Technical Summary
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
The 18 interrupt vectors service 22 interrupt sources (three
non-maskable, 19 maskable). The three non-maskable interrupt sources
are:
•
XIRQ pin (X-bit interrupt)
•
Illegal opcode trap
•
Software interrupt
Freescale Semiconductor, Inc...
On-chip peripheral systems generate maskable interrupts, which are
recognized only if the global interrupt mask bit (I) in the condition code
register (CCR) is clear. Maskable interrupts are prioritized according to
a default arrangement; however, any one source can be elevated to the
highest maskable priority position by a software-accessible control
register (HPRIO). HPRIO can be written at any time, provided bit I in the
CCR is set.
Nineteen interrupt sources in the MC68HC11ED0 are subject to
masking by the global interrupt mask bit (bit I in the CCR). In addition to
the global I bit, all of these sources, except the external interrupt (IRQ)
pin, are controlled by local enable bits in the control registers. Most
interrupt sources in M68HC11 devices have separate interrupt vectors;
therefore there is usually no need for software to poll control registers to
determine the cause of an interrupt.
For some interrupt sources, such as the serial communications interface
(SCI) interrupts, the flags are automatically cleared during the normal
course of responding to the interrupt requests. For example, the RDRF
flag in the SCI system is cleared by the automatic clearing mechanism
invoked by a read of the SCI status register while RDRF is set, followed
by a read of the SCI data register. The normal response to an RDRF
interrupt request would be to read the SCI status register to check for
receive errors, then to read the received data from the SCI data register.
These two steps satisfy the automatic clearing mechanism without
requiring any special instructions.
Refer to Table 5-1 for interrupt and reset vector assignments.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
Table 5-1. Interrupt and Reset Vector Assignments
Vector
Address
$FFC0, $FFC1 –
$FFD4, $FFD5
Freescale Semiconductor, Inc...
$FFD6, $FFD7
Interrupt
Source
Reserved
CCR
Mask Bit
Local
Mask
Priority
(1 = High)
—
—
—
RIE
RIE
TIE
TCIE
ILIE
19
20
21
22
23
SCI serial system:
• SCI receive data register full
• SCI receiver overrun
• SCI transmit data register empty
• SCI transmit complete
• SCI idle line detect
I
$FFD8, $FFD9
SPI serial transfer complete
I
SPIE
18
$FFDA, $FFDB
Pulse accumulator input edge
I
PAII
17
$FFDC, $FFDD
Pulse accumulator overflow
I
PAOVI
16
$FFDE, $FFDF
Timer overflow
I
TOI
15
$FFE0, $FFE1
Timer input capture 4/output compare 5
I
I4/O5I
14
$FFE2, $FFE3
Timer output compare 4
I
OC4I
13
$FFE4, $FFE5
Timer output compare 3
I
OC3I
12
$FFE6, $FFE7
Timer output compare 2
I
OC2I
11
$FFE8, $FFE9
Timer output compare 1
I
OC1I
10
$FFEA, $FFEB
Timer input capture 3
I
IC3I
9
$FFEC, $FFED
Timer input capture 2
I
IC2I
8
$FFEE, $FFEF
Timer input capture 1
I
IC1I
7
$FFF0, $FFF1
Real-time interrupt
I
RTII
6
$FFF2, $FFF3
IRQ (external pin)
I
None
5
$FFF4, $FFF5
XIRQ pin
X
None
4
$FFF6, $FFF7
Software interrupt
None
None
Note 1
$FFF8, $FFF9
Illegal opcode trap
None
None
Note 1
$FFFA, $FFFB
COP failure
None
NOCOP
3
$FFFC, $FFFD
Clock monitor fail
None
CME
2
$FFFE, $FFFF
RESET
None
None
1
1. Same level as an instruction
MC68HC11ED0 — Rev. 1.0
Technical Summary
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
5.4 System Configuration Options Register
Refer to Figure 5-1 for a description of the system configuration options
register (OPTION)
Address:
$0039
Bit 7
6
Read:
5
4
3
IRQE(1)
DLY(1)
CME
0
1
0
2
1
Bit 0
CR1(1)
CR0(1)
0
0
Freescale Semiconductor, Inc...
Write:
Reset:
0
0
0
Note 1. Can be written only once in the first 64 cycles out of reset in normal modes or at any
time
in special modes.
= Unimplemented
Figure 5-1. System Configuration Options Register (OPTION)
Bits [7:6] — Unimplemented
Always read as 0
IRQE — IRQ Select Edge Sensitive Only Bit
0 = Low level recognition
1 = Falling edge recognition
DLY — Enable Oscillator Startup Delay on Exit from Stop Mode Bit
0 = No stabilization delay on exit from stop mode
1 = Stabilization delay enabled on exit from stop mode
CME — Clock Monitor Enable Bit
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset.
Bit 2 — Unimplemented
Always reads 0
CR[1:0] — COP Timer Rate Select Bit
Refer to description of the NOCOP bit in 5.6 Configuration Control
Register.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
Arm/Reset COP Timer Circuitry Register
Freescale Semiconductor, Inc...
Table 5-2. COP Timer Rate Select
CR[1:0]
Rate
Selected
XTAL = 4.0 MHz
Timeout
– 0 ms,
+ 32.8 ms
XTAL = 8.0 MHz
Timeout
– 0 ms,
+ 16.4 ms
XTAL = 12.0 MHz
Timeout
– 0 ms,
+ 10.9 ms
00
215 ÷ E
32.768 ms
16.384 ms
10.923 ms
01
217 ÷ E
131.07 ms
65.536 ms
43.691 ms
10
219 ÷ E
524.29 ms
262.14 ms
174.76 ms
11
221 ÷ E
2.1 s
1.049 s
699.05 ms
E=
1.0 MHz
2.0 MHz
3.0 MHz
5.5 Arm/Reset COP Timer Circuitry Register
Refer to Figure 5-2 for a description of the arm/reset COP timer circuitry
register (COPRST).
Address:
$003A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 5-2. Arm/Reset COP Timer Circuitry Register (COPRST)
Write $55 to COPRST to arm COP watchdog clearing mechanism. Write
$AA to COPRST to reset COP watchdog. Refer to description of the
NOCOP bit in 5.6 Configuration Control Register.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
5.6 Configuration Control Register
In many M68HC11 devices the configuration control register (CONFIG)
is used to define various system functions. In the MC68HC11ED0,
CONFIG controls only one microcontroller (MCU) function. The
NOPCOP bit disables the COP watchdog circuit when it is set. Refer to
Table 5-2 and Figure 5-3.
Freescale Semiconductor, Inc...
Address:
$003F
Bit 7
6
5
4
3
Read:
2
1
Bit 0
0
0
0
0
0
0
NOCOP(1)
Write:
Reset States:
Expanded Mode
Special Test Mode
Bootstrap Mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1. NOCOP must be written during the first 64 cycles after reset in normal modes (SMOD = 0) or at any time in special
modes (SMOD = 1).
= Unimplemented
Figure 5-3. System Configuration Register (CONFIG)
Bits [7:3] — Unimplemented
Always read as 0
NOCOP — COP System Disable Bit
Resets to programmed value
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
Bits [1:0] — Unimplemented
Always read as 0
Technical Summary
MC68HC11ED0 — Rev. 1.0
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
Highest Priority I-Bit Interrupt and Miscellaneous Register
5.7 Highest Priority I-Bit Interrupt and Miscellaneous Register
Address:
$003C
Bit 7
Read:
6
RBOOT(1) SMOD(1)
5
4
3
2
1
Bit 0
MDA(1)
IRVNE
PSEL3
PSEL2
PSEL1
PSEL0
U
U
0
1
0
1
Write:
Reset:
U
U
Freescale Semiconductor, Inc...
1. RBOOT, SMOD, and MDA reset depends on power-up initialization mode and can only be
written only in special mode.
U = Undefined
Figure 5-4. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
RBOOT — Read Bootstrap ROM Bit
Refer to Section 4. Operating Modes and On-Chip Memory.
SMOD — Special Mode Select Bit
Refer to Section 4. Operating Modes and On-Chip Memory.
MDA — Mode Select A Bit
Refer to Section 4. Operating Modes and On-Chip Memory.
IRVNE — Internal Read Visibility/Not E Bit
Refer to Section 4. Operating Modes and On-Chip Memory.
PSEL[3:0] — Priority Select Bits
Can be written only while the I bit in the CCR is set (interrupts
disabled). These bits select one interrupt source to be elevated above
all other I bit related sources. See Table 5-3.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Resets and Interrupts
Table 5-3. Highest Priority Interrupt Selection
Freescale Semiconductor, Inc...
PSEL[3:0]
Interrupt Source Promoted
0000
Timer overflow
0001
Pulse accumulator overflow
0010
Pulse accumulator input edge
0011
SPI serial transfer complete
0100
SCI serial system
0101
Reserved (default to IRQ)
0110
IRQ (external pin)
0111
Real-time interrupt
1000
Timer input capture 1
1001
Timer input capture 2
1010
Timer input capture 3
1011
Timer output compare 1
1100
Timer output compare 2
1101
Timer output compare 3
1110
Timer output compare 4
1111
Timer input capture 4/output compare 5
Technical Summary
MC68HC11ED0 — Rev. 1.0
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 6. Parallel Input/Output (I/O) Ports
Freescale Semiconductor, Inc...
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3
Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4
Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . 67
6.5
Port D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6
Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2 Introduction
The MC68HC11ED0 has up to 14 input/output (I/O) lines. The
address/data bus of this microcontroller (MCU) is multiplexed and has
no I/O ports associated with it. Table 6-1 provides a summary of the
configuration and features of each port.
Table 6-1. Input/Output Ports
NOTE:
Port
Input
Pins
Output
Pins
Bidirectional
Pins
Port A
3
3
2
Timer
Port D
—
—
6
Serial communications interface
(SCI) and serial peripheral interface
(SPI)
Shared Functions
Do not confuse pin function with the electrical state of the pin at reset. All
general-purpose I/O pins configured as inputs at reset are in a
high-impedance state and the contents of port data registers is
undefined. In port descriptions, a U indicates this condition. The pin
function is mode dependent.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
6.3 Port A Data Register
Refer to Figure 6-1 for a description of the port A data register (PORTA).
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
U
0
0
0
U
U
U
U
PAI
OC1
OC2
OC1
OC3
OC1
OC4
OC1
IC4/OC5
OC1
IC1
—
IC2
—
IC3
—
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Alternate Function:
And/or:
U = Undefined
Figure 6-1. Port A Data Register (PORTA)
To enable PA3 as fourth input capture, set I4/O5 bit in the pulse
accumulator control register (PACTL). Otherwise, PA3 is configured as
a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit in PACTL is set (configuring PA3 as an output), and IC4 is
enabled, writes to PA3 cause edges on the pin to result in input captures.
Writing to I4/O5 has no effect when the I4/O5 register is acting as IC4.
PA7 drives the pulse accumulator input but also can be configured for
general-purpose I/O or output compare. DDRA7 bit in PACTL configures
PA7 for either input or output.
NOTE:
Even when PA7 is configured as an output, the pin still drives the pulse
accumulator input.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Pulse Accumulator Control Register
6.4 Pulse Accumulator Control Register
Refer to Figure 6-2 for a description of the pulse accumulator control
register (PACTL).
Address:
$0026
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
Figure 6-2. Pulse Accumulator Control Register (PACTL)
DDRA7 — Data Direction for Port A Bit 7
0 = Input
1 = Output
PAEN — Pulse Accumulator System Enable Bit
Refer to 9.4 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode Bit
Refer to 9.4 Pulse Accumulator.
PEDGE — Pulse Accumulator Edge Control Bit
Refer to 9.4 Pulse Accumulator.
DDRA3 — Data Direction for Port A Bit 3
This bit is overridden if an output compare function is configured to
control the PA3 pin.
0 = Input
1 = Output
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to Section 9. Timing System.
RTR[1:0] — Real-Time Interrupt (RTI) Rate Select Bits
Refer to 9.4 Pulse Accumulator.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
6.5 Port D Data Register
Refer to Figure 6-3 for a description of the port D data register (PORTD).
Address:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
PD5
PD4
PD3
PD2
PD1
PD0
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
0
0
U
U
U
U
U
U
Alternate Function:
—
—
SS
SCK
MOSI
MISO
TxD
RxD
= Unimplemented
U = Undefined
Figure 6-3. Port D Data Register (PORTD)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O) Ports
Port D Data Direction Register
6.6 Port D Data Direction Register
Refer to Figure 6-4 for a description of the port D data direction register
(DDRD)
Address:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
0
0
0
0
0
0
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
0
0
= Unimplemented
Figure 6-4. Port D Data Direction Register (DDRD)
Bits [7:6] — Unimplemented
Always read 0
DDD[5:0] — Port D Data Direction Bits
0 = Input
1 = Output
NOTE:
When the serial peripheral interface (SPI) system is in slave mode,
DDD5 has no meaning or effect. When the SPI system is in master
mode, DDD5 determines whether bit 5 of PORTD is an error detect input
(DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI system
is enabled and expects any of bits [4:2] to be an input, that bit will be an
input regardless of the state of the associated DDR bit. If any of bits [4:2]
are expected to be outputs, that bit will be an output only if the
associated DDR bit is set.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Parallel Input/Output (I/O) Ports
Technical Summary
MC68HC11ED0 — Rev. 1.0
Parallel Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 7. Serial Communications Interface (SCI)
7.1 Contents
Freescale Semiconductor, Inc...
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.3.1
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.2
Serial Communications Control Register 1 . . . . . . . . . . . . . 77
7.3.3
Serial Communications Control Register 2 . . . . . . . . . . . . . 78
7.3.4
Serial Communication Status Register. . . . . . . . . . . . . . . . . 79
7.3.5
Serial Communications Data Register . . . . . . . . . . . . . . . . . 80
7.2 Introduction
The serial communications interface (SCI) is a universal asynchronous
receiver transmitter (UART), one of two independent serial input/output
(I/O) subsystems in the MC68HC11ED0. It has a standard non-return to
zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit)
and several baud rates available. The SCI transmitter and receiver are
independent, but use the same data format and bit rate.
Refer to Figure 7-1 and Figure 7-2.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
WRITE ONLY
TRANSMITTER
BAUDRATE
CLOCK
SCDR Tx BUFFER
DDD1
10 (11) - BIT Tx SHIFT REGISTER
PIN BUFFER
ANDCONTROL
BREAK—JAM0s
PREAMBLE—JAM1s
JAMENABLE
SHIFT ENABLE
PD1
TxD
8
FORCE PIN
DIRECTION(OUT)
8
TDRE
TC
RDRF
IDLE
OR
NF
FE
M
WAKE
TRANSMITTER
CONTROL LOGIC
R8
T8
SCCR1 SCI CONTROL 1
SCSR INTERRUPT STATUS
8
TDRE
TIE
TC
TCIE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Freescale Semiconductor, Inc...
SIZE 8/9
TRANSFERTx BUFFER
H (8) 7 6 5 4 3 2 1 0 L
SCCR2 SCI CONTROL 2
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 7-1. SCI Transmitter Block Diagram
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Introduction
RECEIVER
BAUD RATE
CLOCK
DATA
RECOVERY
PIN BUFFER
AND CONTROL
PD0
RxD
10 (11) - BIT
Rx SHIFT REGISTER
STOP
÷16
START
DDD0
(8) 7
6
5
4
3
2
1
0
MSB
DISABLE
DRIVER
ALL 1s
M
WAKEUP
LOGIC
RWU
SCCR1 SCI CONTROL 1
FE
NF
OR
IDLE
RDRF
TC
TDRE
WAKE
M
T8
8
R8
SCSR SCI STATUS 1
SCDR Rx BUFFER
READ ONLY
8
RDRF
RIE
IDLE
ILIE
OR
SBK
RWU
RE
TE
ILIE
RIE
TCIE
RIE
TIE
Freescale Semiconductor, Inc...
RE
8
SCCR2 SCI CONTROL 2
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 7-2. SCI Receiver Block Diagram
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
7.3 SCI Registers
This subsection describes the SCI registers.
7.3.1 Baud Rate Register
Address:
$002B
Freescale Semiconductor, Inc...
Bit 7
6
5
4
3
2
1
Bit 0
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
0
0
0
U
U
U
Read:
TCLR
Write:
Reset:
0
0
= Unimplemented
U = Unaffected
Figure 7-3. Baud Rate Register (BAUD)
TCLR — Clear Baud Rate Counter Bit
TCLR can be set only in test modes.
1 = Clear baud rate counter chain for testing purposes
0 = Normal SCI operation
SCP[1:0] — SCI Baud Rate Prescaler Select Bits
Refer to Table 7-1 for the prescaler rates. The shaded boxes contain
the prescaler rates used in the Table 7-2.
Table 7-1. Prescaler Rates
Crystal Frequency in MHz
SCP[1:0]
Divide
E Clock By
00
4.0 MHz
(Baud)
8.0 MHz
(Baud)
12.0 MHz
(Baud)
1
62.50 k
125.0 k
187.5 k
01
3
20.83 k
41.67 k
62.5 k
10
4
15.625 k
31.25 k
46.88 k
11
13
4800
9600
14.4 k
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI Registers
RCKB — SCI Baud Rate Clock Check Bit
RCKB can be set only in test modes.
1 = Exclusive-OR of the RT clock driven out TxD pin for testing
purposes
0 = Normal SCI operation
SCR[2:0] — SCI Baud Rate Select Bits
Freescale Semiconductor, Inc...
These bits select receiver and transmitter bit rates based on output
from the baud rate prescaler stage. Refer to Table 7-2 and
Figure 7-4.
Table 7-2. Baud Rates
SCR[2:0]
Divide
Prescaler By
Baud Rate
(Prescaler output from Table 7-1)
4800
9600
14.4 k
000
1
4800
9600
14.4 k
001
2
2400
4800
7200
010
4
1200
2400
3600
011
8
600
1200
1800
100
16
300
600
1200
101
32
150
300
450
110
64
75
150
225
111
128
37.5
75
112.5
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
EXTAL
OSCILLATOR
AND
CLOCK GENERATOR
(÷4)
INTERNAL BUS CLOCK (PH2)
÷3
XTAL
÷4
÷ 13
SCP[1:0]
E
0:0
AS
0:1
1:0
1:1
Freescale Semiconductor, Inc...
SCR[2:0]
0:0:0
÷2
0:0:1
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷ 16
÷2
1:0:1
÷2
1:1:0
÷2
1:1:1
SCI
TRANSMIT
BAUD RATE
(1X)
SCI
RECEIVE
BAUD RATE
(16X)
Figure 7-4. SCI Baud Rate Generator Clock Diagram
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI Registers
7.3.2 Serial Communications Control Register 1
Address:
$002C
Bit 7
6
R8
T8
0
0
5
4
3
M
WAKE
0
0
2
1
Bit 0
0
0
0
Read:
Write:
Reset:
0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 7-5. Serial Communications Control Register 1 (SCCR1)
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
T8 — Transmit Data Bit 8
If M bit is set, T8 stores the ninth bit in the transmit data character.
Bit 5 — Unimplemented
Always reads 0
M — Mode Bit (select character format)
1 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
Bits [2:0] — Unimplemented
Always read 0
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
7.3.3 Serial Communications Control Register 2
Address:
Read:
$002D
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 7-6. Serial Communications Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE — Transmit Complete Interrupt Enable Bit
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE — Receiver Interrupt Enable Bit
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag
is set
ILIE — Idle-Line Interrupt Enable Bit
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable Bit
0 = Transmitter disabled
1 = Transmitter enabled
RE — Receiver Enable Bit
0 = Receiver disabled
1 = Receiver enabled
RWU — Receiver Wakeup Control Bit
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK — Send Break Bit
0 = Break generator off
1 = Break codes generated as long as SBK = 1
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI Registers
7.3.4 Serial Communication Status Register
Address:
$002E
Bit 7
6
5
4
3
2
1
TDRE
TC
RDRF
IDLE
OR
NF
FE
1
1
0
0
0
0
0
Bit 0
Read:
Write:
Reset:
0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 7-7. Serial Communications Status Register (SCSR)
TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading
SCSR and then writing to SCDR.
0 = SCDR busy
0 = SCDR empty
TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or
break transmission in progress). Clear the TC flag by reading SCSR
and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR.
Clear the RDRF flag by reading SCSR and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE — Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set
again until the RxD line has been active and becomes idle again. The
IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR
and then reading SCDR.
0 = RxD line active
1 = RxD line idle
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
OR — Overrun Error Flag
OR is set if a new character is received before a previously received
character is read from SCDR. Clear the OR flag by reading SCSR and
then reading SCDR.
0 = No overrun
1 = Overrun detected
Freescale Semiconductor, Inc...
NF — Noise Error Flag
NF is set if majority sample logic detects anything other than a
unanimous decision. Clear NF by reading SCSR and then reading
SCDR.
0 = Unanimous decision
1 = Noise detected
FE — Framing Error Flag
FE is set when a 0 is detected where a stop bit was expected. Clear
the FE flag by reading SCSR and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
Bit 0 — Unimplemented
Always reads 0
7.3.5 Serial Communications Data Register
Address:
$002F
Bit 7
6
5
4
3
2
1
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-8. Serial Communications Data Register (SCDR)
NOTE:
SCI receive and transmit data are double buffered. Reads of SCDR
access the receive data buffer and writes access the transmit data
buffer.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 8. Serial Peripheral Interface (SPI)
8.1 Contents
Freescale Semiconductor, Inc...
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8.3.1
Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . 83
8.3.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . 85
8.3.3
Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . .86
8.2 Introduction
The serial peripheral interface (SPI) allows the microcontroller unit
(MCU) to communicate synchronously with peripheral devices and other
microprocessors. When configured as a master, data transfer rates can
be as high as one-half the E clock rate (1.5 Mbits per second for a 3-MHz
bus frequency). When configured as a slave, data transfers can be as
fast as the E-clock rate (3 Mbits per second for a 3-MHz bus frequency).
When the SPI is enabled, all pins that are defined by the configuration
as inputs are inputs regardless of the state of the DDR bits of those pins.
All pins that are defined as outputs will be outputs only if the DDR bits for
those pins are set to 1. Any SPI output whose corresponding DDR bit is
cleared to 0 can be used as a general-purpose input. If the SPI system
is in master mode and DDRD bit 5 is set to 1, the port D bit 5 pin
becomes a general-purpose output instead of the SS input to the SPI
system. The MODF mode error flag function for which SS was used
becomes disabled to avoid interference between the general-purpose
output function and the SPI system.
Refer to Figure 8-1, which shows the SPI block diagram.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
S
MSB
LSB
8/16-BIT SHIFT REGISTER
DIVIDER
M
MISO
PD2
M
S
MOSI
PD3
PIN CONTROL LOGIC
INTERNAL
MCU CLOCK
READ DATA BUFFER
÷2 ÷4 ÷16 ÷32
CLOCK
SCK
PD4
SPR0
SPI STATUS REGISTER
SPE
DWOM
SPR0
SPR1
CPHA
CPOL
MSTR
DWOM
8
SPE
MSTR
SPE
MODE
WCOL
MSTR
SS
PD5
SPIE
SPR1
S
M
CLOCK
LOGIC
SPI CONTROL
SPIF
Freescale Semiconductor, Inc...
SELECT
SPI CONTROL REGISTER
8
SPI INTERRUPT
REQUEST
8
INTERNAL
DATA BUS
Figure 8-1. SPI Block Diagram
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI Registers
8.3 SPI Registers
This subsection describes the SPI registers.
8.3.1 Serial Peripheral Control Register
Address:
$0028
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
0
0
1
U
U
Freescale Semiconductor, Inc...
Read:
Write:
Reset:
U = Unaffected
Figure 8-2. Serial Peripheral Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPI interrupts disabled
1 = SPI interrupts enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Option Bit for Port D Pins PD[5:2]
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL and CPHA — Clock Polarity Bit and Clock Phase Bit
Refer to Figure 8-3.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
1
SCK CYCLE #
FOR REFERENCE
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT
Freescale Semiconductor, Inc...
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE)
Figure 8-3. SPI Transfer Format
SPR[1:0] — SPI Clock Rate Select Bits
Refer to Table 8-1.
Table 8-1. SPI Clock Rate Selects
SPR[1:0]
Divide
E Clock By
Frequency at
E = 1 MHz
Frequency at
E = 2 MHz
Frequency at
E = 3 MHz
00
2
500 kHz
1.0 MHz
1.5 MHz
01
4
250 kHz
500 kHz
750 kHz
10
16
125 kHz
125 kHz
375 kHz
11
32
62.5 kHz
62.5 kHz
187.5 kHz
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI Registers
8.3.2 Serial Peripheral Status Register
Address:
$0029
Bit 7
6
SPIF
WCOL
0
0
5
4
3
2
1
Bit 0
0
0
0
0
Read:
MODF
Write:
Reset:
0
0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 8-4. Serial Peripheral Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
This flag is set when an SPI transfer is complete (after eight SCK
cycles in a data transfer). Clear this flag by reading SPSR, then
access SPDR.
0 = No SPI transfer complete or SPI transfer still in progress
1 = SPI transfer complete
WCOL — Write Collision Error Flag
This flag is set if the MCU tries to write data into SPDR while an SPI
data transfer is in progress. Clear this flag by reading SPSR, then
access SPDR.
0 = No write collision error
1 = SPDR written while SPI transfer in progress
Bit 5 — Unimplemented
Always reads 0
MODF — Mode Fault Bit (mode fault terminates SPI operation)
Set when SS is pulled low while MSTR = 1. Cleared by SPSR read
followed by SPCR write.
0 = No mode fault error
1 = SS pulled low in master mode
Bits [3:0] — Unimplemented
Always read 0
MC68HC11ED0 — Rev. 1.0
Technical Summary
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
8.3.3 Serial Peripheral Data I/O Register
Address:
$002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Indeterminate after reset
Freescale Semiconductor, Inc...
Figure 8-5. Serial Peripheral Data I/O Register (SPDR)
SPI is double buffered in and single buffered out.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Technical Data — MC68HC11ED0
Section 9. Timing System
9.1 Contents
Freescale Semiconductor, Inc...
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.3.1
Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . 91
9.3.2
Output Compare 1 Mask Register . . . . . . . . . . . . . . . . . . . . 92
9.3.3
Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . . 92
9.3.4
Timer Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.3.5
Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . 94
9.3.6
Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . . 95
9.3.7
Timer Input Capture 4/Output Compare 5 Register . . . . . . . 96
9.3.8
Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3.9
Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.10 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . 99
9.3.11 Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 100
9.3.12 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 100
9.3.13 Timer Interrupt Flag Register 2 . . . . . . . . . . . . . . . . . . . . . 102
9.4
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.1
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 104
9.4.2
Pulse Accumulator Counter Register . . . . . . . . . . . . . . . . . 106
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.2 Introduction
The timing system is based on a free-running 16-bit counter with a
four-stage programmable prescaler. A timer overflow function allows
software to extend the system’s timing capability beyond the counter’s
16-bit range.
Freescale Semiconductor, Inc...
The timer has:
•
Three channels for input capture
•
Four channels for output compare
•
One channel that can be configured as a fourth input capture or a
fifth output compare
In addition, the timing system includes pulse accumulator and real-time
interrupt (RTI) functions, as well as a clock monitor function, which can
be used to detect clock failures that are not detected by the computer
operating properly (COP. Refer to 9.4 Pulse Accumulator for further
information about these functions.
Table 9-1 provides a summary of the crystal-related frequencies and
periods. A block diagram of the timer system is shown in Figure 9-1.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Introduction
Table 9-1. Timer Summary
Common System Frequencies
Control Bits
Freescale Semiconductor, Inc...
PR[1:0]
Definition
4.0 MHz
8.0 MHz
12.0 MHz
XTAL
1.0 MHz
2.0 MHz
3.0 MHz
E
Main Timer Count Rates (Period Length)
00
1 count —
overflow —
1000 ns
65.536 ms
500 ns
32.768 ms
333 ns
21.845 ms
1÷E
216 ÷ E
01
1 count —
overflow —
4.0 µs
262.14 ms
2.0 µs
131.07 ms
1.333 µs
87.381 ms
4÷E
218 ÷ E
10
1 count —
overflow —
8.0 µs
524.28 ms
4.0 µs
262.14 ms
2.667 µs
174.76 ms
8÷E
219 ÷ E
11
1 count —
overflow —
16.0 µs
1.049 s
8.0 µs
524.29 ms
5.333 µs
349.52 ms
16 ÷ E
220 ÷ E
RTR[1:0]
00
01
10
11
CR[1:0]
Periodic (RTI) Interrupt Rates (Period Length)
8.192 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
2.731 ms
5.461 ms
10. 923 ms
21.845 ms
213 ÷ E
214 ÷ E
215 ÷ E
216 ÷ E
COP Watchdog Timeout Rates (Period Length)
00
01
10
11
32.768 ms
131.072 ms
524.288 ms
2.098 s
16.384 ms
65.536 ms
262.14 ms
1.049 s
10.923 ms
43.691 ms
174.76 ms
699.05 ms
215 ÷ E
217 ÷ E
219 ÷ E
221 ÷ E
Timeout tolerance
(–0 ms/+...)
32.8 ms
16.4 ms
10.9 ms
215 ÷ E
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
MCU
E CLK
PRESCALER
DIVIDE BY
1, 4, 8, OR 16
PR1
TCNT (HI)
TCNT (LO)
TOI
16-BIT FREE-RUNNING
COUNTER
PR0
9
TOF
TAPS FOR RTI,
COP WATCHDOG, AND
PULSE ACCUMULATOR
16-BIT TIMER BUS
INTERRUPT REQUESTS
(FURTHER QUALIFIED BY
I BIT IN CCR)
TO PULSE
ACCUMULATOR
OC1I
16-BIT COMPARATOR =
Freescale Semiconductor, Inc...
TOC1 (HI)
OC1F
TOC1 (LO)
FOC1
OC2I
16-BIT COMPARATOR =
TOC2 (HI)
TOC2 (LO)
TOC3 (LO)
TOC4 (LO)
OC5
TI4/O5 (LO)
I4/O5F
CLK
TIC2 (HI)
CLK
IC1I
BIT 3
PA3/OC5/
IC4/OC1
BIT 2
PA2/IC1
BIT 1
PA1/IC2
BIT 0
PA0/IC3
3
IC1F
IC2I
2
IC2F
TIC2 (LO)
16-BIT LATCH
TIC3 (HI)
CLK
PA4/OC4/
OC1
4
FOC5
CFORC
FORCE OUTPUT
COMPARE
TIC1 (LO)
16-BIT LATCH
BIT 4
IC4
I4/O5
CLK
PA5/OC3/
OC1
5
FOC4
I4/O5I
16-BIT LATCH
BIT 5
OC4F
16-BIT COMPARATOR =
TIC1 (HI)
PA6/OC2/
OC1
6
FOC3
16-BIT COMPARATOR =
16-BIT LATCH
BIT 6
OC3F
OC4I
TI4/O5 (HI)
PA7/OC1/
PAI
7
FOC2
16-BIT COMPARATOR =
TOC4 (HI)
BIT 7
OC2F
OC3I
TOC3 (HI)
PIN
FUNCTIONS
8
IC3I
IC3F
1
TIC3 (LO)
TFLG 1
STATUS
FLAGS
TMSK 1
INTERRUPT
ENABLES
PORT A
PIN CONTROL
CAPTURE COMPARE BLOCK
Figure 9-1. Timer Block Diagram
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Timer Registers
9.3 Timer Registers
This subsection provides a description of the registers associated with
the timer system.
9.3.1 Timer Compare Force Register
Freescale Semiconductor, Inc...
Address:
$000B
Bit 7
6
5
4
3
FOC1
FOC2
FOC3
FOC4
FOC5
0
0
0
0
0
2
1
Bit 0
0
0
0
Read:
Write:
Reset:
= Unimplemented
Figure 9-2. Timer Compare Force Register (CFORC)
FOC[5:1] — Force Output Compare Bits
Write 1s to force compare(s)
0 = Not affected
1 = Output x action occurs
Bits [2:0] — Unimplemented
Always read 0
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.3.2 Output Compare 1 Mask Register
Address:
$000C
Bit 7
6
5
4
3
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
0
0
0
0
0
2
1
Bit 0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
= Unimplemented
Figure 9-3. Output Compare 1 Mask Register (OC1M)
OC1M[7:3] — Output Compare 1 Mask Bits
Set bit(s) to enable OC1 to control corresponding pin(s) of port A
Bits [2:0] — Unimplemented
Always read as 0
9.3.3 Output Compare 1 Data Register
Address:
$000D
Bit 7
6
5
4
3
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
0
0
0
0
0
2
1
Bit 0
0
0
0
Read:
Write:
Reset:
= Unimplemented
Figure 9-4. Output Compare 1 Data Register (OC1D)
OC1D[7:3] — Output Compare 1 Data Bits
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful
OC1 compares.
Bits [2:0] — Unimplemented
Always read 0
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Timer Registers
9.3.4 Timer Count Register
Address: $000E — High
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Freescale Semiconductor, Inc...
Address: $000F — Low
Read:
Write:
Reset:
= Unimplemented
Figure 9-5. Timer Count Register (TCNT)
The timer count register (TCNT) is read only in normal modes.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.3.5 Timer Input Capture Registers
Address: $0010 — High
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Address: $0011 — Low
Freescale Semiconductor, Inc...
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
Figure 9-6. Timer Input Capture Register 1 (TIC1)
Address: $0012 — High
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Address: $0013 — Low
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
Figure 9-7. Timer Input Capture Register 2 (TIC2)
Address: $0014 — High
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Address: $0015 — Low
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
Figure 9-8. Timer Input Capture Register 3 (TIC3)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Timer Registers
9.3.6 Timer Output Compare Registers
Address: $0016 — High
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $0017 — Low
Freescale Semiconductor, Inc...
Read:
Write:
Reset:
Figure 9-9. Timer Output Compare Register 1 (TOC1)
Address: $0018 — High
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $0019 — Low
Read:
Write:
Reset:
Figure 9-10. Timer Output Compare Register 2 (TOC2)
Address: $001A — High
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Address: $001B — Low
Read:
Write:
Reset:
Figure 9-11. Timer Output Compare Register 3 (TOC3)
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Address: $001C — High
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $001D — Low
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
Figure 9-12. Timer Output Compare Register 4 (TOC4)
9.3.7 Timer Input Capture 4/Output Compare 5 Register
Address: $001E — High
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Address: $001F — Low
Read:
Write:
Reset:
Figure 9-13. Timer Input Capture4/Output Compare 5 Register
(TI4/O5)
This is a shared register and is either input capture 4 or output
compare 5 depending on the state of bit I4/O5 in PACTL. Writes to
TI4/O5 have no effect when this register is configured as input capture 4.
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Timer Registers
9.3.8 Timer Control Register 1
Address: $0020
Bit 7
6
5
4
3
2
1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 9-14. Timer Control Register 1 (TCTL1)
OM[5:2] — Output Mode
OL[5:2] — Output Level
See Table 9-2.
Table 9-2. Timer Output Compare Actions
OMx
OLx
Action Taken on Successful Compare
0
0
Timer disconnected from output pin logic
0
1
Toggle OCx output line
1
0
Clear OCx output line to 0
1
1
Set OCx output line to 1
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.3.9 Timer Control Register 2
Address: $0021
Bit 7
6
5
4
3
2
1
Bit 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 9-15. Timer Control Register 2 (TCTL2)
Table 9-3. Timer Control Configuration
EDGxB
EDGxA
Configuration
0
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
1
Capture on any edge
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Timer Registers
9.3.10 Timer Interrupt Mask 1 Register
Address: $0022
Bit 7
6
5
4
3
2
1
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 9-16. Timer Interrupt Mask 1 Register (TMSK1)
OC1I–OC4I — Output Compare Interrupt Enable Bits
If the OCxF flag bit is set while the OCxI enable bit is set, a hardware
interrupt sequence is requested.
I4/OC5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt bit.
When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt
control bit.
IC1I–IC3I — Input Capture Interrupt Enable Bits
If the ICxF flag bit is set while the ICxI enable bit is set, a hardware
interrupt sequence is requested.
NOTE:
Control bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones
in TMSK1 enable the corresponding interrupt sources.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.3.11 Timer Interrupt Flag 1 Register
Address: $0023
Bit 7
6
5
4
3
2
1
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 9-17. Timer Interrupt Flag 1 Register (TFLG1)
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC4F — Output Compare x Flags
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by
I4/O5 of PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
9.3.12 Timer Interrupt Mask 2 Register
Address: $0024
Bit 7
6
5
4
TOI
RTII
PAOVI
PAII
0
0
0
0
3
2
1
Bit 0
PR1
PR0
0
0
Read:
Write:
Reset:
0
0
= Unimplemented
Figure 9-18. Timer Interrupt Mask 2 Register (TMSK2)
TOI — Timer Overflow Interrupt Enable Bit
0 = Timer overflow interrupt disabled
1 = Timer overflow interrupt enabled
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Timer Registers
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to 1
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 9.4 Pulse Accumulator.
PAII — Pulse Accumulator Interrupt Enable Bit
Freescale Semiconductor, Inc...
Refer to 9.4 Pulse Accumulator.
Bits [3:2] — Unimplemented
Always read as 0
PR[1:0] — Timer Prescaler Select Bits
In normal modes, PR1 and PR0 can be written only once, and the
writes must occur within 64 cycles after reset. Refer to Table 9-1 and
Table 9-4 for specific timing values.
Table 9-4. Timer Prescale
NOTE:
PR[1:0]
Prescaler
00
÷1
01
÷4
10
÷8
11
÷ 16
Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in
TFLG2. Logic 1s in TMSK2 enable the corresponding interrupt sources.
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.3.13 Timer Interrupt Flag Register 2
Address:
$0025
Bit 7
6
5
4
TOF
RTIF
PAOVF
PAIF
0
0
0
0
3
2
1
Bit 0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
= Unimplemented
Figure 9-19. Timer Interrupt Flag 2 Register (TFLG2)
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Set periodically. Refer to the description of bits RTR[1:0] in
Figure 9-21.
PAOVF — Pulse Accumulator Overflow Flag
Refer to 9.4 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Flag
Refer to 9.4 Pulse Accumulator.
Bits [3:0] — Unimplemented
Always read 0
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Pulse Accumulator
9.4 Pulse Accumulator
The MC68HC11ED0 has an 8-bit counter that can be configured as a
simple event counter or for gated time accumulation. The counter can be
read or written at any time.
Refer to Figure 9-1 and Table 9-5.
PAOVI
PAOVF
1
INTERRUPT
REQUESTS
PAII
TMSK2 INT ENABLES
2
PAIF
PAII
PAOVI
PAOVF
PAIF
E ÷ 64 CLOCK
FROM MAIN TIMER
TFLG2 INTERRUPT STATUS
PAI EDGE
DISABLE
FLAG SETTING
PAEN
OVERFLOW
MCU PIN
2:1
MUX
INPUT BUFFER
AND
EDGE DETECTOR
PA7/
PAI/
OC1
FROM
DDRA7
PACNT 8-BIT COUNTER
ENABLE
PEDGE
PAEN
PAMOD
FROM
MAIN TIMER
OC1
CLOCK
DATA
BUS
OUTPUT
BUFFER
PAEN
Freescale Semiconductor, Inc...
The port A bit 7 I/O pin can be configured to act as a clock in event
counting mode, or as a gate signal to enable a free-running clock (E
divided by 64) to the 8-bit counter in gated time accumulation mode.
PACTL CONTROL
INTERNAL
DATA BUS
Figure 9-20. Pulse Accumulator System Block Diagram
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Table 9-5. Pulse Accumulator Timing
Common XTAL Frequencies
4.0 MHz
8.0 MHz
12.0 MHz
CPU Clock
(E)
1.0 MHz
2.0 MHz
3.0 MHz
Cycle Time
(1 ÷ E)
1000 ns
500 ns
333 ns
Freescale Semiconductor, Inc...
Pulse Accumulator (Gated Mode)
1 Count
(26 ÷ E)
64.0 µs
32.0 µs
21.330 µs
Overflow
214 ÷ E)
16.384 ms
8.192 ms
5.491 ms
Pulse accumulator control bits are also located within two timer
registers, TMSK2 and TFLG2, as described in 9.4.1 Pulse
Accumulator Control Register.
9.4.1 Pulse Accumulator Control Register
Address:
$0026
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-21. Pulse Accumulator Control Register (PACTL)
DDRA7 — Data Direction for Port A Bit 7
Refer to Section 6. Parallel Input/Output (I/O) Ports.
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
Pulse Accumulator
PEDGE — Pulse Accumulator Edge Control Bit
0 = In event mode, falling edges increment counter. In gated
accumulation mode, high level enables accumulator and falling
edge sets PAIF.
1 = In event mode, rising edges increment counter. In gated
accumulation mode, low level enables accumulator and rising
edge sets PAIF.
DDRA3 — Data Direction for Port A Bit 3
Freescale Semiconductor, Inc...
Refer to Section 6. Parallel Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare Bit
Configure TI4/O5 for input capture or output compare
0 = OC5 enabled
1 = IC4 enabled
RTR[1:0] — RTI Interrupt Rate Select Bits
These two bits select the rate for periodic interrupts. Refer to
Table 9-6 and Table 9-7.
Table 9-6. RTI Rates (Period Length)
Period Length
RTR[1:0]
Period Length
Selected
E = 1.0 MHz
E = 2.0 MHz
E = 3.0 MHz
00
213 ÷ E
8.19 ms
4.096 ms
2.731 ms
01
214 ÷ E
16.38 ms
8.192 ms
5.461 ms
10
215 ÷ E
32.77 ms
16.384 ms
10.923 ms
11
216 ÷ E
65.54 ms
32.768 ms
21.845 ms
Table 9-7. RTI Rates (Frequency)
Frequency
RTR[1:0]
Rate Selected
00
E = 1.0 MHz
E = 2.0 MHz
E = 3.0 MHz
E ÷ 213
122.070 Hz
244.141 Hz
366.211 Hz
01
E ÷ 214
61.035 Hz
122.070 Hz
183.105 Hz
10
E ÷ 215
30.518 Hz
61.035 Hz
91.553 Hz
11
E ÷ 216
15.259 Hz
30.518 Hz
45.776 Hz
MC68HC11ED0 — Rev. 1.0
Technical Summary
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Timing System
9.4.2 Pulse Accumulator Counter Register
Refer to Figure 9-22 for a description of the pulse accumulator counter
register (PACNT).
Address:
$0027
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
Unaffected by reset
Figure 9-22. Pulse Accumulator Counter Register (PACNT)
Technical Summary
MC68HC11ED0 — Rev. 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
blank
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescale.s Environmental Products program, go to
http://www.freescale.com/epp.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
MC68HC11ED0TS/D
REV 1
M68H11E Series Technical Data
Home Page:
www.freescale.com
email:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
(800) 521-6274
480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 2666 8080
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
(800) 441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com