FREESCALE MC68SC302

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MC68SC302P/D
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MC68SC302
Product Brief
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The MC68SC302 Passive ISDN Protocol Engine (PIPE) is a communication controller optimized for ISDN
passive cards, with an ISA PNP interface and a PCMCIA slave interface. The MC68SC302 is a descendant of
the popular MC68302 Integrated Multiprotocol Processor. The microcoded RISC communications processor
from the 68302 was modified to form the core of the 68SC302. The 68000 core and many related system
integration features were removed to further optimize the device for passive ISDN card applications. The serial
communication channels (SCC) have been optimized for supporting a full ISDN basic rate interface. The three
SCCs support two 64kbit per second B-channels and one 16kbit per second D-channel. The 68SC302 connects
gluelessly to Motorola’s MC145572 U transceiver or MC145574 S/T transceiver and, as an added bonus,
eliminates the need for a second oscillator for the transceiver chip.
MC68SC302 KEY FEATURES
• ISA Bus Interface
ISA Plug and Play Interface
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Glueless Connections to ISA
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24mA Buffers for ISA Bus Pins
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Full Support of Plug and Play Standard
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All Chip Registers Accessed from ISA Bus.
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Support for 8- or 16-bit I/O or Memory ISA Cycles
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11 Selectable Interrupt Output Pins to ISA Bus.
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Additional Chip Select Allows Another Device to Be Accessed from the ISA Bus.
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Plug and Play Register Settings Stored in External Low Cost E2PROM.
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Passive ISDN Protocol Engine
• PCMCIA Interface
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PC Card 95 Compatible
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Two CIS Storage Options:
• CIS stored in Serial E2PROM and Downloaded At Runtime to Internal Dual Port RAM
• CIS Optionally Stored in Parallel E2PROM on the PC Card Bus with Dedicated Chip Select, Saving
Dual Port RAM Buffer Space and Always Available for PC Accesses.
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
 1996 All Rights Reserved.
Freescale Semiconductor, Inc.
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Memory Mode Accesses Supported (I/O Not Supported)
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Supports 8- or 16-bit Memory Cycles
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Supports Ring Detect through Status Change Pin
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Additional Chip Select Allows Another Device to be Address Mapped on the PC Card Bus.
Requires No External (Local) RAM
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Flexible Channel Handling
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RISC Processor Decreases CPU Load with Flexible Buffer Descriptor Structure and HDLC
Capability (UART Mode Not Supported).
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Totally Independent Programming for Rx/Tx for each of the B and D Channels
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Supports Any Sub-Channeling for Each of the B Channels
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Enables a Concatenation of 2 B Channels (or Any Selected Bits) to a Super-Channel
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HDLC with Retry Capability for the D Channel
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Allows Dynamic Connection/Disconnection for each of the B Channels
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Total 1536KB Dual Port RAM Divided into Parameter and Data Buffer RAM
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256 Byte Parameter RAM (As in PM302)
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1280 Byte Data RAM with Efficient FIFO Organization and Flexible Buffer Size
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Independent Programmable Channel FIFO Length, if Split Equally:
• 4 x 256 Bytes FIFO for B1 and B2 Channel (Rx/Tx)
• 2 x 64 Bytes FIFO for D Channel (Rx/Tx)
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• ISDN Communications Processor
1.
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Glueless Interface to Freescale and Other Popular ISDN S/T and U Interface Chips
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Supports Freescale Interchip Digital Link (IDL)
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Supports General Circuit Interface (GCI), Also Known as IOM-21
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Includes Serial Communication Port (SCP) for Synchronous Communication
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Includes one SMC That Can Support Both the C/I and Monitor Channel of GCI
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Two Strobes Support Time-Slot Assignment of Non-Intelligent Peripherals
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Only One Crystal Required for TA Application.
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Clock Output (CLKO) Generation from a Crystal. CLKO Can Be Connected to S/T XTAL Input.
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Clock Input for U-Chip (MC145572) can be Used to Drive SC302
IOM-2 is a trademark of Siemens AG
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• Other System Integration Features
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Gluelessly Connects to Serial E2PROM via SCP Port for PNP ISA ID and CIS Storage.
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25XXX Series or 93XX Series E2PROMs Supported.
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Flexible Pin Configuration Allows Trade-Offs between 16-Bit Wide ISA/PC Card Interface and Extra
I/O Pins.
• Up to 16 Parallel I/O Pins for Controlling Other Functions.
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On-Chip Interrupt Controller
2 Low-Power Modes
• Wait - Oscillator Keeps Running ~5 mA
• Stop - Oscillator Stops - <100uA
Operating Speed: 0-20.48 Mhz
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Operating Voltage: 5V
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100 pin TQFP (14mm x 14mm)
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MC68SC302 OVERVIEW
The block diagram for the MC68SC302 is shown in Figure 1. The MC68SC302 architecture is based on a
microcoded RISC communications processor that services the three main high speed serial channels (SCC),
two serial management channels (SMC) and a serial communications port (SCP). The three SCC channels
support simultaneous operation of the three channels specified by the ISDN basic rate interface (2B+D). Each
SCC can support onboard HDLC processing as well as totally transparent operation. The dual-port RAM
provides 1536 bytes of memory. A maximum of 1280 bytes can be allocated for serial channel buffer space,
which, when allocated evenly for a basic rate interface, allows 256 bytes per B channel per direction and 64
bytes per direction for the D channel. This provides 32msec worth of basic rate data to be stored in the buffers,
allowing ample interrupt latency time for host platform operating systems. The IDL or GCI interface provides
direct connection to the Freescale MC145572 U interface transceiver, the MC145574 S/T interface transceiver,
and other popular ISDN transceivers. A non-multiplexed serial interface (NMSI) is also provided for SCC2.
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• 8 Internal Interrupt Sources
• 7 External Pin Sources for External Devices.
The MC68SC302 has an ISA Plug and Play interface which supports the ISA Plug and Play specification
version 1.0a. The ISA bus interface can be configured for either I/O mode accesses or memory mode
accesses. The ISA interface can be either an 8- or 16-bit wide data bus allowing pin usage trade-offs to be
made. I/O mode accesses are based on a self-incrementing pointer, allowing the PC to write or read data from
a fixed ISA I/O address. Memory mode access allows the PC to write or read data into a predefined ISA
window. In addition to supporting access to the internal MC68SC302 register and memory map, an additional
chip-select is provided for an external device, and can be programmed for either memory or I/O and either 8
or 16 bit bus independent of internal space.
The MC68SC302 can also be configured to provide a PC Card interface based on the PC Card 95
specification. Either 8- or 16-bit wide memory cards can be implemented. There are two options available for
supporting the Card Information Structure (CIS): 1)The CIS can be stored in external serial EEPROM which is
downloaded on reset into the Dual Port RAM (DPRAM) space. 2) To save DPRAM space, the CIS can be
MC68SC302 PRODUCT INFORMATION
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stored in a parallel EEPROM on the external PCMCIA bus. An additional chip select is provided to support
access to an external device from the PC Card interface.
The MC68SC302 also has up to 12 general purpose I/O pins to connect to external circuits. Five external chip
interrupts can be brought in and routed through a built-in interrupt controller to any one of 11 ISA interrupts (or
to the PC Card interface interrupt). The MC68SC302 can be clocked at the same rate as the physical layer
transceiver clock which eliminates the need for a dedicated oscillator or crystal.
PIO AND INTERRUPT PINS
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1536 BYTE
RAM
ISA PnP
PCMCIA
ISA PnP/
PCMCIA
INTERFACE
INTERFACE
SCC1
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COMMUNICATIONS
PROCESSOR
SCC2
SCC3
2 SMCs
SCP
IDL/GCI INTERFACE
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PIO AND INT I/F
NMSI I/F
NMSI PINS
SCP/E2 PROM INTERFACE
IDL/GCI PINS
Figure 1. MC68SC302 Block Diagram
REFERENCE DESIGNS
Figure 2 shows the 68SC302 in an NT1 terminal adaptor (TA) application using the MC68SC302. The TA
supports a basic rate interface (BRI). The 68SC302 is connected gluelessly to the ISA bus connector and
performs the Plug and Play interface using the serial EEPROM for storage of non-volatile Plug and Play data.
Data and control accesses from the PC to the MC68SC302 can be selectively memory or I/O mapped. Only
one clock source (crystal or oscillator) is needed for a simple terminal adaptor.
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20.048 MHZ
SERIAL
EEPROM
IDL OR GCI BUS
MC68SC302
20.048 MHZ CLOCK
145572 U
I/F
LINE I/F
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Figure 2. Passive NT Terminal Adaptor Block Diagram
SERIAL
EEPROM
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Figure 3 shows a basic rate terminal adaptor with the 4-wire S/T interface. This architecture is almost identical
to the U interface TA with the exception that the TA clock source is provided to the S/T transceiver from the
MC68SC302.
MC68SC302
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ISA BUS
IDL OR GCI BUS
145574 S/T
15.36 MHZ CLOCK
I/F
LINE I/F
15.36 MHZ
ISA BUS
Figure 3. Passive TE Terminal Adaptor Block Diagram with S/T Interface
Figure 4 shows a more full featured terminal adaptor. The two added features are the “Plain Old Telephone”
(POTs) interface and a optional modem datapump. Up to two POTs interfaces can be added on the board to
support simultaneous B channel voice call. The ISA interface provides a separate chip select for an external
data pump which uses an MC145480 to produce an 8khz PCM output that can be directly connected to the
IDL or GCI bus.
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.
20.048 MHZ
SERIAL
EEPROM
20.048 MHZ CLOCK
145572 U
IDL OR GCI BUS
I/F
MC68SC302
PIO
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MC145480
ISA BUS
IN
Figure 4. NT Terminal Adaptor Block Diagram with POTS Interface and Datapump
SERIAL
EEPROM
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Figure 5 shows a PC Card terminal adaptor based on the SC302.
IDL OR GCI BUS
MC68SC302
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DATAPUMP
LINE I/F
POTS
I/F
PCMCIA
20.048 MHZ
145572 U
20.048 MHZ CLOCK
I/F
LINE I/F
Figure 5. PC Card Terminal Adaptor
ORDERING INFORMATION
PACKAGE TYPE
Surface Mount TQFP 100-Pin
(PU Suffix)
FREQUENCY
(MHZ)
TEMPERATURE
ORDER NUMBER
20.048
0°C to 70°C
MC68SC302PU20
RELATED DOCUMENTATION
DOCUMENT TITLE
MC68SC302 User’s Manual
ORDER NUMBER
CONTENT
MC68SC302UM/AD
Detailed technical information about the MC68SC302
MC68SC302 PRODUCT INFORMATION
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MC68SC302 APPLICATION DEVELOPMENT SYSTEM
The MC68SC302 Application Development System (ADS) is a platform for developing a passive terminal
adaptor using the MC68SC302. In addition to being an ISA half-card form factor plug-in card, the MC68SC302
can also be plugged into a PC card slot for development of PC card applications. The board includes both an
MC145572 U interface transceiver and an MC145574 S/T interface transceiver along with the associated line
interface circuitry. A 128-pin expansion connector is onboard for customer specific circuits such as a POTs
interface or a modem datapump. Logic analyzer connectors provide convenient access to ISA and PCMCIA
bus signals. Figure 6 shows the ADS block diagram.
CIS/PnP
EEPROM
ST95020
SOCKET
CIS/PnP
EEPROM
93C46
SOCKET
SCP
IDL/GCI
SCP
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FREESCALE MC145574
S/T INTERFACE,
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FREESCALE MC145572
U INTERFACE
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CIS/PnP
EEPROM
X25080
SOCKET
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4 WIRE
S/T INTERFACE
2 WIRE
U INTERFACE
128-PIN EXPANSION
CONNECTOR
LOGIC
ANALYZER
CONNECTORS
MC68SC302
PCMCIA BUS
CONNECTOR
Figure 6. ADS Block Diagram
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ISA BUS
CONNECTOR
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ADS FEATURES
• MC68SC302 operating at 20.48Mhz.
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• ISA half-card form factor modified with PCMCIA extender card.
• Host PC connection via either ISA Bus or PCMCIA bus.
• ISA Plug and Play Interface.
• Powered by the ISA or PCMCIA connectors with option to power from bench supply.
• The U interface transceiver MC145572 configurable to either NT or LT mode.
• The S/T interface transceiver MC145574 configurable to either TE or NT mode.
• Options to communicate with U and S/T transceivers via either the IDL/SCP bus or the GCI bus.
• 128-pin expansion connector providing access to the SC302 pins for customer daughter cards. This
includes access to the ISA/PCMCIA bus pins.
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• Options for three types of serial EEPROM for the PCMCIA or ISA Configuration.
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ADS ORDERING INFORMATION
DEVELOPMENT PLATFORM
ADS Board for M68SC302
ORDER NUMBER
M68SC302ADS
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• Logic analyzer connectors to probe MC68SC302 and ISA/PCMCIA bus activity.
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