GS880E18/32/36BT-xxxV 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • 1.8 V or 2.5 V +10%/–10% core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP package available Functional Description Applications The GS880E18/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. 250 MHz–150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. DCD Pipelined Reads The GS880E18/32/36BT is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS880E18/32/36BT operates on a 1.8 V or 2.5 V power supply. All input are 2.5 V and 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 2.5 V and 1.8 V compatible. Paramter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.00 6/2006 -250 -200 -150 Unit tKQ tCycle 3.0 4.0 3.0 5.0 3.8 6.7 ns ns Curr (x18) Curr (x32/x36) 200 230 170 195 140 160 mA mA tKQ tCycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 160 185 140 160 128 145 mA mA 1/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS880E18BT-xxxV 100-Pin TQFP Pinout (Package T) NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.00 6/2006 2/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS880E32BT-xxxV 100-Pin TQFP Pinout (Package T) NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A FT VDD NC VSS DQD DQD2 VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.00 6/2006 3/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS880E36BT-xxxV 100-Pin TQFP Pinout (Package T) DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.00 6/2006 4/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins NC — No Connect BW I Byte Write—Writes all enabled bytes; active low BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply Rev: 1.00 6/2006 5/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV GS880E18/32/36BT-xxxV Block Diagram Register A0–An D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ 0 Power Down DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.00 6/2006 6/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H or NC Low Drive (High Impedance) Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. There are pull-up devices on the ZQ, and SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.00 6/2006 7/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.00 6/2006 8/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D ADSP ADSC Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and and E3 = 0E3 = 0; E = F (False) if E2 = 0 or E3 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 6/2006 9/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.00 6/2006 10/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.00 6/2006 11/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage on VDDQ Pins –0.5 to VDD V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o TBIAS Temperature Under Bias –55 to 125 o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version) Parameter Symbol Min. Typ. Max. Unit 1.8 V Supply Voltage VDD1 1.7 1.8 2.0 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.7 1.8 VDD V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 VDD V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00 6/2006 12/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV VDDQ2 & VDDQ1 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Rev: 1.00 6/2006 13/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Figure 1 Output Load 1 DQ 30pF* 50Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA FT, SCD, ZQ, ZZ Input Current IIN VDD ≥ VIN ≥ 0 V –100 uA 100 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA DC Output Characteristics (1.8 V/2.5 V Version) Parameter Symbol Test Conditions Min Max 1.8 V Output High Voltage VOH1 IOH = –4 mA, VDDQ = 1.6 V VDDQ – 0.4 V — 2.5 V Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — 1.8 V Output Low Voltage VOL1 IOL = 4 mA — 0.4 V 2.5 V Output Low Voltage VOL2 IOL = 8 mA — 0.4 V Rev: 1.00 6/2006 14/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Operating Currents -250 Parameter Test Conditions Mode Symbol Operating Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL — — 0 –40 0 –40 to 70°C to 85°C to 70°C to 85°C Unit IDD IDDQ 200 30 220 30 170 25 190 25 140 20 160 20 mA Flow Through IDD IDDQ 160 25 180 25 140 20 160 20 130 15 150 15 mA Pipeline IDD IDDQ 185 15 205 15 155 15 175 15 130 10 150 10 mA Flow Through IDD IDDQ 145 15 165 15 130 10 150 10 120 8 140 8 mA Pipeline ISB 40 50 40 50 40 50 mA Flow Through ISB 40 50 40 50 40 50 mA Pipeline IDD 85 90 75 80 60 65 mA Flow Through IDD 60 65 50 55 50 55 mA (x18) Standby Current 0 to 70°C -150 Pipeline (x32/x36) Device Selected; All other inputs ≥VIH or ≤ VIL Output open -200 –40 to 85°C Notes: 1. IDD and IDDQ apply to any combination of VDD2, VDD1, VDDQ2, and VDDQ1 operation. 2. All parameters listed are worst case scenario. Rev: 1.00 6/2006 15/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time tKC -250 -200 -150 Unit Min Max Min Max Min Max 4.0 — 5.0 — 6.7 — ns Clock to Output Valid tKQ — 3.0 — 3.0 — 3.8 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ1 1.5 — 1.5 — 1.5 — ns Setup time tS 1.2 — 1.4 — 1.5 — ns Hold time tH 0.2 — 0.4 — 0.5 — ns Clock Cycle Time tKC 5.5 — 6.5 — 7.5 — ns Clock to Output Valid tKQ — 5.5 — 6.5 — 7.5 ns Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — ns 1 Clock to Output in Low-Z tLZ 2.0 — 2.0 — 2.0 — ns Setup time tS 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.5 — ns Clock LOW Time tKL 1.7 — 1.7 — 1.7 — ns Clock to Output in High-Z tHZ1 1.5 2.5 1.5 3.0 1.5 3.0 ns G to Output Valid tOE — 2.5 — 3.0 — 3.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.5 — 3.0 — 3.8 ns ZZ setup time tZZS2 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00 6/2006 16/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Pipeline Mode Timing (DCD) Begin Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect Deselect tKL tKH tKC CK ADSP tS ADSC initiated read tH ADSC tS tH ADV tS tH Ao–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 tS E2 and E3 only sampled with ADSC tH E2 tS tH E3 G tS tOE DQa–DQd Hi-Z Rev: 1.00 6/2006 tOHZ Q(A) tKQ tH D(B) tHZ tLZ tKQX Q(C) Q(C+1) 17/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+2) Q(C+3) © 2006, GSI Technology GS880E18/32/36BT-xxxV Flow Through Mode Timing (DCD) Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH ADSC initiated read ADSC tH tS tS tH ADV tS tH Ao–An A B C tS tH GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E1 masks ADSP E3 G tH tS tOE tKQ DQa–DQd tOHZ Q(A) tKQX tHZ tLZ D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Rev: 1.00 6/2006 18/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.00 6/2006 19/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV TQFP Package Drawing (Package T) L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle e D D1 Description c Pin 1 Symbol L1 θ b A1 A2 0.10 Y 0° — 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.00 6/2006 20/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Voltage Option Package Speed2 (MHz/ns) TA3 Status4 512K x 18 GS880E18BT-250V DCD 1.8 V or 2.5 V TQFP 250/5.5 C MP 512K x 18 GS880E18BT-200V DCD 1.8 V or 2.5 V TQFP 200/6.5 C MP 512K x 18 GS880E18BT-150V DCD 1.8 V or 2.5 V TQFP 150/7.5 C MP 256K x 32 GS880E32BT-250V DCD 1.8 V or 2.5 V TQFP 250/5.5 C MP 256K x 32 GS880E32BT-200V DCD 1.8 V or 2.5 V TQFP 200/6.5 C MP 256K x 32 GS880E32BT-150V DCD 1.8 V or 2.5 V TQFP 150/7.5 C MP 256K x 36 GS880E36BT-250V DCD 1.8 V or 2.5 V TQFP 250/5.5 C MP 256K x 36 GS880E36BT-200V DCD 1.8 V or 2.5 V TQFP 200/6.5 C MP 256K x 36 GS880E36BT-150V DCD 1.8 V or 2.5 V TQFP 150/7.5 C MP 512K x 18 GS880E18BT-250IV DCD 1.8 V or 2.5 V TQFP 250/5.5 I MP 512K x 18 GS880E18BT-200IV DCD 1.8 V or 2.5 V TQFP 200/6.5 I MP 512K x 18 GS880E18BT-150IV DCD 1.8 V or 2.5 V TQFP 150/7.5 I MP 256K x 32 GS880E32BT-250IV DCD 1.8 V or 2.5 V TQFP 250/5.5 I MP 256K x 32 GS880E32BT-200IV DCD 1.8 V or 2.5 V TQFP 200/6.5 I MP 256K x 32 GS880E32BT-150IV DCD 1.8 V or 2.5 V TQFP 150/7.5 I MP 256K x 36 GS880E36BT-250IV DCD 1.8 V or 2.5 V TQFP 250/5.5 I MP 256K x 36 GS880E36BT-200IV DCD 1.8 V or 2.5 V TQFP 200/6.5 I MP 256K x 36 GS880E36BT-150IV DCD 1.8 V or 2.5 V TQFP 150/7.5 I MP 512K x 18 GS880E18BGT-250V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 C PQ 512K x 18 GS880E18BGT-200V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C PQ 512K x 18 GS880E18BGT-150V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 C PQ 256K x 32 GS880E32BGT-250V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 C PQ 256K x 32 GS880E32BGT-200V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C PQ 256K x 32 GS880E32BGT-150V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 C PQ 256K x 36 GS880E36BGT-250V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 C PQ 256K x 36 GS880E36BGT-200V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 C PQ 256K x 36 GS880E36BGT-150V DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 C PQ 512K x 18 GS880E18BGT-250IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 I PQ 512K x 18 GS880E18BGT-200IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 I PQ Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18BT-200IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. MP = Mass Production. PQ = Pre-Qualification. 5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 6/2006 21/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Voltage Option Package Speed2 (MHz/ns) TA3 Status4 512K x 18 GS880E18BGT-150IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I PQ 256K x 32 GS880E32BGT-250IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 I PQ 256K x 32 GS880E32BGT-200IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 I PQ 256K x 32 GS880E32BGT-150IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I PQ 256K x 36 GS880E36BGT-250IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 I PQ 256K x 36 GS880E36BGT-200IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 I PQ 256K x 36 GS880E36BGT-150IV DCD 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 I PQ Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18BT-200IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. MP = Mass Production. PQ = Pre-Qualification. 5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 6/2006 22/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS880E18/32/36BT-xxxV 9Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 880ExxB_V_r1 Rev: 1.00 6/2006 Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet 23/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology