JDSU PLRXPL-VX-S43-23-N

COMMUNICATIONS MODULES & SUBSYSTEMS
10 G SFP+ 850 nm Limiting Transceiver,
10 Gigabit Ethernet Compatible
PLRXPL-Vx-S43-23-N Series
Key Features
• Compatible with 10 G links
• Uses a highly reliable, 850 nm oxide VCSEL
• Lead-free and RoHS 6/6-compliant, with allowed exemptions
• Commercial case operating temperature of 0 – 70°C
• Single 3.3 V power supply
• Low power consumption (typically 450 mW)
• Bit error rate < 1 x 10-12
• Hot pluggable
Applications
• Intra data center connectivity
- Switch and hub
- Mass storage systems
- Host bus adapters
• Enterprise access interconnect
• High-speed storage interconnect
• Disaster recovery/backup connectivity
• High-speed cluster/grid computing
aggregation
Compliance
•
•
•
•
•
•
•
•
SFF 8431 Revision 3.2
SFF 8432 Revision 5.0
SFF 8472 Revision 10.3
CDRH and IEC60825-1 Class 1 Laser
Eye Safety
FCC Class B
ESD Class 2 per MIL-STD 883
UL 94, V0
Reliability tested per Telcordia GR-468
NORTH AMERICA: 800 498-JDSU (5378)
The lead-free and RoHS-compliant small form factor pluggable (SFP+)
transceiver from JDSU improves the performance for 10 Gigabit Ethernet
(10 G) applications, and is ideal for high-speed campus and large data center
applications. This transceiver features a highly reliable, 850 nm, oxide, verticalcavity surface-emitting laser (VCSEL) coupled to an LC optical connector. The
transceiver is fully compatible with 10GBASE-SR, 10GBASE-SW and 10 G Fibre
Channel specifications at shorter link distances, with internal AC coupling on both
transmit and receive data signals. The all-metal housing design provides low EMI
emissions in demanding 10 G applications and conforms to IPF specifications.
An enhanced digital diagnostic feature set allows for real-time monitoring of
transceiver performance and system stability, and the serial ID allows for customer
and vendor system specific information to be stored in the transceiver. Transmit
disable, loss-of-signal, and transmitter fault functions are also provided. The small
size of the transceiver allows for high-density board designs that, in turn, enable
greater aggregate bandwidth.
WORLDWIDE: +800 5378-JDSU
WEBSITE: www.jdsu.com
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
2
Section 1
Functional Description
The PLRXPL-Vx-S43-23-N 10G SFP+ 850 nm optical transceiver is designed to
transmit and receive 10 G serial optical data over 50/125 µm or 62.5/125 µm multimode optical fiber.
Transmitter
The transmitter converts serial PECL or CML electrical data into serial optical data
compatible with the 10GBASE-SR, 10GBASE-SW or 10 G Fibre Channel standard.
Transmit data lines (TD+ and TD-) are internally AC coupled, with 100 Ω differential termination.
Transmitter rate select (RS1) pin 9 is assigned to control the SFP+ module transmitter rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal
on this pin does not affect the operation of the transmitter.
An open collector-compatible transmit disable (Tx_Disable) is provided. This pin
is internally terminated with a 10 kΩ resistor to Vcc,T. A logic “1,” or no connection, on this pin will disable the laser from transmitting. A logic “0” on this pin
provides normal operation.
The transmitter has an internal PIN monitor diode that ensures constant optical
power output, independent of supply voltage. It is also used to control the laser
output power over temperature to ensure reliability at high temperatures.
An open collector-compatible transmit fault (Tx_Fault) is provided. The Tx_
Fault signal must be pulled high on the host board for proper operation. A logic
“1” output from this pin indicates that a transmitter fault has occurred or that
the part is not fully seated and the transmitter is disabled. A logic “0” on this pin
indicates normal operation.
Receiver
The receiver converts serial optical data into serial PECL/CML electrical data. Receive data lines (RD+ and RD-) are internally AC coupled with 100 Ω differential
source impedance, and must be terminated with a 100 Ω differential load.
Receiver Rate Select (RS0) pin 7 is assigned to control the SFP+ module receiver
rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal on this
pin has no affect on the operation of the receiver.
An open collector compatible loss of signal (LOS) is provided. The LOS must be
pulled high on the host board for proper operation. A logic “0” indicates that light
has been detected at the input to the receiver (see Optical characteristics, Loss of
Signal Assert/Deassert Time). A logic “1” output indicates that insufficient light
has been detected for proper operation.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
3
16 Transmitter
Power Supply
10 kΩ
3 Transmitter
Disable In
VCC_TX TX_DIS
TOSA
100 Ω
Laser Driver
TX_GND
18 Transmitter
Positive Data
TD+
19 Transmitter
Negative Data
TD -
TX_FAULT
2 Transmitter
Fault Out
1, 17, 20 Transmitter
Signal Ground
5 SCL
Serial ID Clock
4 SDA
Serial ID Data
SCL
Management Processor
SDA
EEPROM
6 MOD_ABS
15 Receiver
Power Supply
VCC_RX
VCC_RX
RD -
50 Ω
12 Receiver
Negative Data Out
Receiver
ROSA
RD +
RX_GND
RX_GND
50 Ω
LOS
13 Receiver
Positive Data Out
8 Loss of Signal Out
9 RS1 TX Rate Select
Not Functional on
-N modules
30 kΩ
30 kΩ
7 RS0 RX Rate Select
Not Functional on
-N modules
10, 11, 14 Receiver
Signal Ground
Figure 1
SFP+ optical transceiver functional block diagram
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
4
Section 2
Application Schematic
Vcc
R1* 50 Ω
1 VeeT
Receiver (Tx Fault)
PECL Driver
(TX DATA)
Z* = 100 Ω
10 kΩ
VeeT 20
R2* 50 Ω
Vcc
Rp***
Open Collector
Bidirectional
SDA
2 Tx Fault
TD- 19
3 Tx Disable
TD+ 18
CMOS, TTL, or
Open Collector Driver
(Tx Disable)
Power Supply Filter
VccT 16
6 MOD_ABS
VccR 15
7 RS0
VeeR 14
8 LOS
RD+ 13
9 RS1
RD-
L2
C2
Vcc
C4
R5 ∗∗
Mod_ABS
CMOS or TTL Driver
(RS0 Rx Rate Select)
12
R3*
50 Ω
Vcc
R6 ∗∗
10 VeeR
VeeR 11
Receiver (LOS)
10 kΩ
C5
Ry
Z* = 100 Ω
Vcc
C1
Vcc
10 kΩ
5 SCL
***
Rq
Vcc +3.3V
Input
C6
C3
Open Collector
Bidirectional
SCL
L1
Vcc
Rx
VeeT 17
4 SDA
R4*
50 Ω
PECL Receiver
(RX DATA)
CMOS or TTL Driver
(RS1 Tx Rate Select)
Figure 2
Recommended application schematic for the 10 G SFP+ optical transceiver
Notes
Power supply filtering components should be placed as close to the Vcc pins of the host connector as possible for optimal performance.
PECL driver and receiver components will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are supported. Good impedance matching for the driver and receiver is required.
SDA and SCL should be bi-directional open collector connections in order to implement serial ID in JDSU SFP+ transceiver modules.
R1/R2 and R3/R4 are normally included in the output and input of the PHY. Please check the application notes for the IC in use.
* Transmission lines should be 100 Ω differential traces. Vias and other transmission line discontinuities should be avoided. In order to meet the host TP1 output jitter and
TP4 jitter tolerance requirements it is recommended that the PHY has both transmitter pre-emphasis to equalize the transmitter traces and receiver equalization to equalize the
receiver traces. With appropriate transmitter pre-emphasis and receiver equalization, up to 8 dB of loss at 5 GHz can be tolerated.
** R5 and R6 are required when an Open Collector driver is used in place of CMOS or TTL drivers. 5 kΩ value is appropriate.
*** The value of Rp and Rq depend on the capacitive loading of these lines and the two wire interface clock frequency. See SFF-8431. A value of 10 kΩ is appropriate for 80 pF
capacitive loading at 100 kHz clock frequency.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
5
Power supply filtering is recommended for both the transmitter and receiver. Filtering should be placed on the host assembly as close to the Vcc pins as possible for
optimal performance. Vcc,R and Vcc,T should have separate filters.
Power supply filter component values from Figure 2 are shown in the table below
for two different implementations.
Power Supply Filter Component Values
Component
Option A
Option B
Units
L1, L2
Rx, Ry
C1, C5
C2, C3, C4
C6
1.0
0.5*
10
0.1
Not required
4.7
0.5*
22
0.1
22
µH
Ω
µF
µF
µF
Notes:
Option A is recommended for use in applications with space constraints. Power supply noise must be less than 100 mVp-p.
Option B is used in the module compliance board in SFF-8431.
*If the total series resistance of L1+C6 and L2+C5 exceeds the values of Rx and Ry in the table, then Rx and Ry can be omitted.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
6
Section 3
Specifications
Technical specifications related to the SFP+ optical transceiver include:
• Section 3.1
• Section 3.2
• Section 3.3
• Section 3.4
• Section 3.5
• Section 3.6
• Section 3.7
• Section 3.8
• Section 3.9
• Section 3.10
• Section 3.11
3.1
TOWARD HOST
WITH DIRECTION
OF MODULE
INSERTION
Pin Function Definitions
Absolute Maximum Ratings
Operating Conditions
Electrical Characteristics
Optical Characteristics
Link Length
Regulatory Compliance
PCB Layout
Front Panel Opening
Module Outline
Transceiver Belly-to-belly Mounting
Pin Function Definitions
VEER
10
11
VEER
RS1
12
RD-
9
RX_LOS
13
RD+
8
RS0
14
VEER
7
MOD_ABS
15
VCCR
6
SCL
5
16
VCCT
17
VEET
18
TD+
19
TD-
20
VEET
Figure 3
SDA
4
TX_DISABLE
3
TX_FAULT
2
VEET
1
Host PCB SFP+ Pad assignment top view
TOWARD
BEZEL
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
7
SFP+ Optical Transceiver Pin Descriptions
Pin Number
Symbol
Name
Description
Receiver
8
LOS
Loss of Signal Out (OC)
10, 11, 14
VeeR
Receiver Signal Ground
12
RD-
Receiver Negative
DATA Out (PECL)
13
RD+
Receiver Positive
DATA Out (PECL)
15
VccR
Receiver Power Supply
7
RS0
RX Rate Select (LVTTL)
Sufficient optical signal for potential BER < 1x10-12 = Logic “0”
Insufficient signal for potential BER < 1x10-12 = Logic “1”
This pin is open collector compatible, and should be pulled up
to Host Vcc with a 10 kΩ resistor.
These pins should be connected to signal ground on the host board.
The VeeR and VeeT signals are connected together within the module
and are isolated from the module case.
Light on = Logic “0” Output
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
Light on = Logic “1” Output
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
This pin should be connected to a filtered +3.3 V power supply
on the host board. See Application schematics on page 4 for
filtering suggestions.
This pin has an internal 30 kΩ pull-down to ground. A signal
on this pin will not affect module performance.
Transmitter
3
TX_Disable
Transmitter Disable In (LVTTL)
1, 17, 20
VeeT
Transmitter Signal Ground
2
TX_Fault
Transmitter Fault Out (OC)
16
VccT
Transmitter Power Supply
18
TD+
Transmitter Positive
DATA In (PECL)
19
TD-
Transmitter Negative
DATA In (PECL)
9
RS1
TX Rate Select (LVTTL)
Module Definition
4
SDA
Two-wire Serial Data
5
SCL
Two-wire Serial Clock
6
MOD_ABS
Module Absent
Logic “1” Input (or no connection) = Laser off
Logic “0” Input = Laser on
This pin is internally pulled up to VccT with a 10 kΩ resistor.
These pins should be connected to signal ground on the host board.
The VeeR and VeeT signals are connected together within the module
and are isolated from the module case.
Logic “1” Output = Laser Fault (Laser off before t_fault)
This pin is open collector compatible, and should be pulled up
to Host Vcc with a 10 kΩ resistor.
This pin should be connected to a filtered +3.3 V power supply
on the host board. See Application schematics on page 4 for
filtering suggestions.
Logic “1” Input = Light on
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
Logic “0” Input = Light on
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
This pin has an internal 30 kΩ pulldown to ground. A signal
on this pin will not affect module performance.
Serial ID with SFF 8472 Diagnostics.
Module definition pins should be pulled up to Host Vcc with
appropriate resistors for the speed and capacitive loading of the
bus. See SFF8431.
Serial ID with SFF 8472 Diagnostics.
Module definition pins should be pulled up to Host Vcc with
appropriate resistors for the speed and capacitive loading of the
bus. See SFF8431.
Pin should be pulled up to Host Vcc with 10 kΩ resistor.
MOD_ABS is asserted “high” when the SFP+ module is
physically absent from the host slot.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
8
3.2
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Storage temperature
Operating case temperature
Relative humidity
Transmitter differential input voltage
Power supply voltage
TST
TC
RH
VD
VCC
-40 to +95
-40 to +85
5 – 95 (noncondensing)
2.5
0 to +4.0
˚C
˚C
%
V
VP-P
Note:
Absolute maximum ratings represent the damage threshold of the device.
Damage may occur if the device is subjected to conditions beyond the limits stated here.
3.3
Operating Conditions
Part Number
Temperature Rating
Unit
PLRXPL-VC-S43-23-N
0 – 70
˚C
Note:
Performance is not guaranteed and reliability is not implied for operation at any condition outside these limits.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
9
3.4
Electrical Characteristics
Parameter
Symbol
Min.
Typical
Max.
Unit
Notes
Supply voltage
Vcc
3.14
3.3
3.47
V
All electrical and optical specifications
valid within this range
Power consumption
Data rate
Transmitter
Supply current
Common mode voltage tolerance
Data dependent input jitter
Pdiss
480
10.3125
1000
10.52
mW
Gbps
100
mA
mVrms
UI
Data input uncorrelated jitter
Data input total jitter
Uj
TJ
0.023
0.28
Input data dependent pulse
width shrinkage
Eye mask
DDPWS
0.055
X1
X2
Y1
Y2
VIH
VIL
0.12
0.33
Transmit disable voltage levels
IccT
ΔV
DDJ
15
0.10
2.0
-0.3
Transmit disable/enable assert time TTD
TTEN
Transmit fault output levels
IOH
VOL
Transmit fault assert and reset times TFault
TReset
-50
-0.3
800
Vcc + 0.3
0.8
10
2
µs
ms
+37.5
0.4
µA
V
100
µs
µs
300
ms
120
7.5
0.42
mA
ps
mVrms
UI
0.70
UI
0.35
10
Initialization time
Receiver
Supply current
Data output rise/fall time
Output common mode voltage
99% jitter
IccR
tr/tf
Total jitter
TJ
Eye mask
X1
Y1
Y2
IOH
-50
425
+37.5
UI
mV
mV
µA
VOL
-0.3
0.4
V
TLOSA
100
µs
TLOSD
100
µs
Loss of signal levels
Loss of signal assert/deassert time
TINI
28
200
Note: All high frequency measurements are made with the module compliance board as described in SFF8431
29-1 pattern, TP1, at 10.3 Gbps
(Note 1)
UI (rms)
UI
231-1 pattern, TP1, BER < 1x10-12,
at 10.3 Gbps (Notes 1, 8)
UI
Reference SFF-8431 Revision 3.2
UI
UI
mV
mV
V
V
95
BER < 1x10-12
Reference SFF-8431 Revision 3.2,
Figure 22. 5 x 10-5 hit ratio
Laser output disabled after TTD if
input level is VIH; Laser output enabled
after TTEN if input level is VIL
Laser output disabled after TTD if
input level is VIH; Laser output enabled
after TTEN if input level is VIL
Fault level is IOH and Laser output
disabled TFault after laser fault. IOH is
measured with a 4.7 kΩ load to
Vcc host. VOL is measured at 0.7 mA.
Fault is VOL and Laser output restored
TINI after disable is asserted for TReset,
then disabled.
After hot plug or Vcc ≥ 2.97 V
20% – 80%, differential
RLOAD = 25 Ω, common mode
231-1 pattern, TP4, at 10.3 Gbps
(Notes 1, 4, 9)
231-1 pattern, TP4 , BER < 1x10-12,
at 10.3 Gbps (Notes 1, 4, 8)
Reference SFF-8431 Revision 3.2,
Figure 23. 5 x 10-5 hit ratio
LOS output level IOL TLOSD after light
input > LOSD (Note 2)
LOS output level VOH TLOSA after light
input < LOSA (Note 2)
LOS output level VOL TLOSD after light
input > LOSD (Note 2)
LOS output level VOH TLOSA after light
input < LOSA (Note 2)
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
10
3.5
Optical Characteristics
Parameter
Transmitter
Wavelength
RMS spectral width
Average optical power
Optical modulation amplitude
Transmitter dispersion penalty
Relative intensity noise
Receiver
Wavelength
Maximum input power
Sensitivity (OMA)
Stressed sensitivity (OMA)
Loss of signal assert/deassert level
Low frequency cutoff
Symbol
Min.
Typical
Max.
Unit
Notes
λp
840
850
PAVG
OMA
TDP
RIN12OMA
-8
*
860
0.45
Note 6
nm
nm
dBm
µW
dB
dB/Hz
(Note 3)
12 dB reflection
λ
Pmax
S
ISI = 2.8 dB
LOSD
LOSA
FC
840
+1
3.9
-128
850
860
-10.7
-7.8
-11
-30
0.3
nm
dBm
dBm
dBm
dBm
dBm
MHz
Exceeds IEEE 802.3 Clause 52
(Note 7)
Chatter-free operation; LOSD is
OMA, LOSA is average power
-3 dB, P<-16 dBm
Note:
* Tradeoffs between center wavelength, spectral width, and minimum OMA are used. Refer to the table on Minimum Optical Modulation Amplitude in dBm for details.
Minimum Optical Modulation Amplitude in dBm
Wavelength (nm)
840 – 845
845 – 850
850 – 855
855 – 860
<0.1
0.1 – 0.15
0.15 – 0.2
Spectral Width (nm)
0.2 – 0.25
0.25 – 0.30
0.3 – 0.35
0.35 – 0.4
0.4 – 0.45
-4.3
-4.3
-4.3
-4.3
-4.2
-4.2
-4.3
-4.3
-4.2
-4.2
-4.2
-4.2
-4.1
-4.2
-4.2
-4.2
-4.0
-4.0
-4.0
-4.1
-3.9
-3.9
-3.9
-4.0
-3.7
-3.8
-3.8
-3.9
Note:
* Tradeoffs between center wavelength, spectral width, and minimum OMA are used.
-4.1
-4.1
-4.1
-4.1
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
11
3.6
Link Length
Data Rate / Standard
Fiber Type
Modal Bandwidth at 850 nm (MHz*km)
Distance Range (m)
Notes
10.3 GBd
62.5/125 µm MMF
50/125 µm MMF
50/125 µm MMF
50/125 µm MMF
50/125 µm MMF
200
500
900
1500
2000
0.5 – 20
0.5 – 50
0.5 – 90
0.5 – 160
0.5 – 200
5
5
5
5
5
Specification Notes
1. UI (unit interval): one UI is equal to one bit period. For example, 10.3125 Gbps
corresponds to a UI of 96.97 ps.
2. For LOSA and LOSD definitions, see Loss of Signal Assert/Deassert Level in Optical Characteristics.
3. Transmitter dispersion penalty is measured using the methods specified in the
IEEE standard 802.3-2005 Clause 52 except that the transversal filter differential
delay is 33 ps.
4. Measured with stressed eye pattern as per IEEE standard 802.3-2005, Clause 52 except that the vertical eye opening penalty is as specified in Optical Characteristics.
5. Distances, shown in the “Link Length” table, are calculated for worst-case fiber
and transceiver characteristics based on the optical and electrical specifications
shown in this document using techniques specified in IEEE 802.3. In the nominal case, longer distances are achievable.
6. The maximum transmitter output power is the lesser of the Class 1 laser eye
safety limit and -1 dBm (the maximum receiver input power limit per the IEEE
802.3 Clause 52 specification).
7. Sensitivity is for informational purposes only.
8. The data pattern for the total jitter measurement is one of IEEE 802.3 Clause
52.9 Pattern 1, Pattern 3, or valid 64/66B data traffic.
9. 99% jitter is as defined in SFF-8431 Revision 3.2. 99% jitter has the same definition as “all but 1% for jitter” as used in IEEE 802.3 Clause 52.9.9 and is defined
as the time from the 0.5th to the 99.5th percentile of the jitter histogram.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
12
3.7 Regulatory Compliance
The PLRXPL-Vx-S43-23-N optical transceiver complies with international Electromagnetic Compatibility (EMC) and international safety requirements and
standards. EMC performance is dependent on the overall system design. Information included herein is intended as a figure of merit for designers to use as a basis
for design decisions.
The PLRXPL-Vx-S43-23-N optical transceiver is lead-free and RoHS-compliant
per Directive 2002/95/EC of the European Parliament and of the Council of 27
January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment.
Regulatory Compliance
Feature
Test Method
Performance
Component safety
UL 60950
UL 94, V0
IEC 60950
Directive 2002/95/EC
UL File E209897
RoHS-compliant
Laser eye safety1
Electromagnetic Compatibility
Electromagnetic emissions
EN 60825
U. S. 21CFR 1040.10
ESD immunity
EMC Directive 89/336/EEC
FCC CFR47 Part 15
IEC/CISPR 22
AS/NZS CISPR22
EN 55022
ICES-003, Issue 4
VCCI-03
EMC Directive 89/336/EEC
IEC/CISPR/24
EN 55024
EN 61000-4-2
Radiated immunity
EN 61000-4-3
Electromagnetic immunity
1. For further details, see Eye Safety
TUV Report/Certificate (CB scheme)
Compliant per the Directive 2002/95/EC of the European
Parliament and of the Council of 27 January 2003 on the
restriction of the use of certain hazardous substances in
electrical and electronic equipment.
TUV Certificate
CDRH compliant and Class 1 laser eye safe
Noise frequency range: 30 MHz to 40 GHz.
Good system EMI design practice required
to achieve Class B margins.
Exceeds requirements. Withstand discharges of 4 kV
contact and 8 kV air discharge to Criterion A, and 8 kV
contact and 25 kV air discharge to Criterion B.
Exceeds requirements. Field strength of 10 V/m RMS,
from 10 MHz to 1 GHz. No effect on transmitter/receiver
performance is detectable between these limits.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
13
3.8
PCB Layout
Figure 4
Board layout
ALL DIMENSIONS ARE IN MILLIMETERS
Figure 5
Detail layout
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
14
3.9
Front Panel Opening
Figure 6
3.10
Module Outline
ALL DIMENSIONS ARE IN MILLIMETERS
Figure 7
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
15
3.11 Transceiver Belly-to-belly Mounting
Figure 8
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
16
Section 4
Related Information
Other information related to the SFP+ optical transceiver includes:
• Section 4.1
• Section 4.2
• Section 4.3
• Section 4.4
4.1
Digital diagnostic monitoring and serial ID operation
Package and handling instructions
ESD discharge (ESD)
Eye safety
Digital Diagnostic Monitoring and Serial ID Operation
The PLRXPL-Vx-S43-23-N optical transceiver is equipped with a two-wire serial
EEPROM that is used to store specific information about the type and identification of the transceiver as well as real-time digitized information relating to
the transceiver’s performance. See the Small Form Factor Committee document
number SFF-8472 Revision 10.3, dated December 1, 2007 for memory/address
organization of the identification data and digital diagnostic data. The enhanced
digital diagnostics feature monitors five key transceiver parameters which are internally calibrated and should be read as absolute values and interpreted as follows:
Transceiver Temperature in degrees Celsius: Internally measured. Represented as
a 16-bit signed two’s complement value in increments of 1/256°C from -40 to
+70°C with LSB equal to 1/256°C. Accuracy is ± 3°C over the specified operating
temperature and voltage range.
Vcc/Supply Voltage in Volts: Internally measured. Represented as a 16-bit unsigned
integer with the voltage defined as the full 16-bit value(0 – 65535) with LSB equal
to 100 uV with a measurement range of 0 to +6.55 V. Accuracy is ± three percent
of nominal value over the specified operating temperature and voltage ranges.
TX Bias Current in mA: Represented as a 16-bit unsigned integer with current de-
fined as the full 16-bit value (0 – 65535) with LSB equal to 2 uA with a measurement range of 0 – 131 mA. Accuracy is ± 10 percent of nominal value over the
specified operating temperature and voltage ranges.
TX Output Power in mW: Represented as a 16-bit unsigned integer with the power
defined as the full 16-bit value (0 – 65535) with LSB equal to 0.1 uW. Accuracy is ±
2 dB over the specified temperature and voltage ranges over the range of -8.2 dBm
to 0.5 dBm. Data is not valid when transmitter is disabled.
RX Received Optical Power in mW: Represented as average power as a 16-bit un-
signed integer with the power defined as the full 16-bit value (0-65535) with LSB
equal to 0.1 uW. Accuracy is ± 3 dB over the specified temperature and voltage
ranges over the power range of -12 dBm to 0.5 dBm.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
17
Reading the data
The information is accessed through the SCL and SDA connector pins of the module. The SFF-8431 Revision 3.2 specification contains all the timing and addressing information required for accessing the data in the EEPROM.
The device address used to read the Serial ID data is 1010000X(A0h), and the address to read the diagnostic data is 1010001X(A2h). Any other device addresses
will be ignored.
MOD_ABS, pin 6 on the transceiver, is connected to Logic 0 (Ground) on the
transceiver.
SCL, pin 5 on the transceiver, is connected to the SCL pin of the EEPROM.
SDA, pin 4 on the transceiver, is connected to the SDA pin of the EEPROM.
The EEPROM Write Protect pin is internally tied to ground with no external access, allowing write access to the customer-writable field (bytes 128 – 247 of address 1010001X). Note: address bytes 0 – 127 are not write protected and may
cause diagnostic malfunctions if written over.
Decoding the data
The information stored in the EEPROM, including the organization and the digital diagnostic information, is defined in the Small Form Factor Committee document SFF-8472 Revision 10.3, dated December 1, 2007.
Data Field Descriptions
Address( 1010000X)(A0h)
Address( 1010001X)(A2h)
0
0
Serial ID Information;
Defined by SFP MSA
55
95
95
JDSU-Specific Information
127
119
127
Alarm and Warning Limits
Reserved for External
Calibration Constants
Real Time Diagnostic
Information
JDSU-Specific Information
Nonvolatile, customerwriteable, field-writeable
area
Reserved for SFP MSA
247
255
255
JDSU-Specific Information
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
18
Serial ID Data and Map
Memory Address
Value
Comments
0
1
2
3-10
11
12
13
14
15
16
17
18
19
20-35
36
37-39
40-55
56-59
60-61
62
63
64
03
04
07
0000000000000000
06
67
00
00
00
05
02
00
14
JDSU
00
00019C
PLRXPLVxS43xxN
SFP Transceiver
SFP with Serial ID
LC Connector
65
66
67
68-83
84-91
92
1A
00
00
93
F0
94
95
96-127
128-255
03
CC_EXT
0352
CC_BASE
00
68
64B/66B
Nominal Bit rate of 10.3 Gbps
Rate Identifier (for Rate-selectable modules)
Single-mode fiber not supported
Single-mode fiber not supported
50 meters of OM2 50/125 µm multimode fiber
20 meters of OM1 62.5/125 µm multimode fiber
Copper not supported
200 meters of OM3 50/125 µm multimode fiber
Vendor Name (ASCII)
Reserved
IEEE Company ID (ASCII)
Part Number (ASCII), x = part number variable
Revision of part number (ASCII)
Wavelength of laser in nm; 850
Unallocated
Check Code; Lower 8 bits of sum from byte 0 through 62
Conventional uncooled laser, Class 1 power level,
Conventional limiting receiver output
Tx_Disable, Tx Fault, Loss of Signal implemented
Serial Number (ASCII)
Date Code (ASCII)
Diagnostic monitoring implemented, internally calibrated,
Receiver Power Measurement type is Average Power
Alarms and Warnings, TX_Fault and Rx_LOS monitoring
implemented, TX_Disable Control and Monitoring.
SFF-8472 Revision 10.3 compliant
Check Code; Lower 8 bits of sum from byte 64 through 94
JDSU-specific EEPROM
Reserved for SFF-8079
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
19
Diagnostics Data Map
Memory Address
Value
Comments
00-01
02-03
04-05
06-07
08-09
10-11
12-13
14-15
16-17
18-19
20-21
22-23
24-25
26-27
28-29
30-31
32-33
34-35
36-37
38-39
40-55
56-59
60-63
64-67
68-71
72-75
76-77
78-79
80-81
82-83
84-85
86-87
88-89
90-91
92-94
95
96
97
98
99
100
Temp High Alarm
Temp Low Alarm
Temp High Warning
Temp Low Warning
Voltage High Alarm
Voltage Low Alarm
Voltage High Warning
Voltage Low Warning
Bias High Alarm
Bias Low Alarm
Bias High Warning
Bias Low Warning
TX Power High Alarm
TX Power Low Alarm
TX Power High Warning
TX Power Low Warning
RX Power High Alarm
RX Power Low Alarm
RX Power High Warning
RX Power Low Warning
Reserved
RP4
RP3
RP2
RP1
RP0
Islope
Ioffset
TPslope
TPoffset
Tslope
Toffset
Vslope
Voffset
Reserved
Checksum
Temperature MSB
Temperature LSB
Vcc MSB
Vcc LSB
TX Bias MSB (Note 1)
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
MSB at low address
For future monitoring quantities
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
External Calibration Constant
Reserved
Low order 8 bits of sum from 0 – 94
Internal temperature AD values
Internally measured supply voltage AD values
TX Bias Current AD values
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
20
Diagnostics Data Map
(continued)
Memory Address
Value
101
102
103
104
105
106
107
108
109
110-7
110-6
TX Bias LSB (Note 1)
TX Power MSB (Note 1)
TX Power LSB (Note 1)
RX Power MSB
RX Power LSB
Reserved MSB
Reserved LSB
Reserved MSB
Reserved LSB
Tx Disable State
Soft Tx Disable Control
110-5
110-4
110-3
110-2
110-1
110-0
111
112-119
120-127
128-247
248-255
Reserved
Rate Select State
Soft Rate Select Control
Tx Fault State
LOS State
Data Ready State
Reserved
Optional alarm & warning flag bits (Note 2)
Vendor specific
User/Customer EEPROM
Vendor specific
Comments
Measured TX output power AD values
Measured RX input power AD values
For 1st future definition of digitized analog input
For 2nd future definition of digitized analog input
Digital State of Tx Disable Pin
Writing “1” OR pulling the Tx_Disable pin will disable
the laser
Digital State of Rate Select Pin
Writing to this bit has no effect
Digital State
Digital State
Digital State; “1” until transceiver is ready
Reserved
Refer to SFF-8472 Revision 10.3
JDSU specific
Field writeable EEPROM
Vendor-specific control
Note :
1. During Tx disable, Tx bias and Tx power will not be monitored.
2. Alarm and warning are latched. The flag registers are cleared when the system Reads AND the alarm/warning condition no longer exists.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
21
4.2 Package and Handling Instructions
This product is not compatible with any aqueous wash process.
Process plug
The PLRXPL-Vx-S43-23-N optical transceiver is supplied with a process plug.
This plug protects the transceiver optics during standard manufacturing processes
by preventing contamination from air borne particles.
Note: It is recommended that the dust cover remain in the transceiver whenever an
optical fiber connector is not inserted.
Recommended cleaning and degreasing chemicals
JDSU recommends the use of methyl, isopropyl and isobutyl alcohols for cleaning.
Do not use halogenated hydrocarbons (trichloroethane, ketones such as acetone,
chloroform, ethyl acetate, MEK, methylene chloride, methylene dichloride, phenol,
N-methylpyrolldone).
Flammability
The housing is made of cast zinc and sheet metal.
4.3 Electrostatic Discharge (ESD)
Handling
Normal ESD precautions are required during the handling of this module. This
transceiver is shipped in ESD protective packaging. It should be removed from the
packaging and handled only in an ESD protected environment utilizing standard
grounded benches, floor mats, and wrist straps.
Test and operation
In most applications, the optical connector will protrude through the system chassis and be subjected to the same ESD environment as the system. Once properly
installed in the system, this transceiver should meet and exceed common ESD
testing practices and fulfill system ESD requirements.
Typical of optical transceivers, this module’s receiver contains a highly sensitive
optical detector and amplifier which may become temporarily saturated during
an ESD strike. This could result in a short burst of bit errors. Such an event may
require the application to reacquire synchronization at the higher layers (serializer/
deserializer chip).
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
4.4 Eye Safety
The PLRXPL-Vx-S43-23-N Optical Transceiver is a CLASS 1 LASER PRODUCT
as defined by the international standard IEC 60825-1 Second Edition 2007-03 and
by U.S.A. regulations for Class 1 products per CDRH 21 CFR 1040.10 and 1040.11.
Laser emissions from Class 1 laser products are not considered hazardous when
operated according to product specifications. Operating the product with a power
supply voltage exceeding 4.0 volts may compromise the reliability of the product,
and could result in laser emissions exceeding Class 1 limits.
Caution
Tampering with this laser based product or operating this product outside the
limits of this specification may be considered an act of “manufacturing,” and will
require, under law, recertification of the modified product with the U.S. Food and
Drug Administration (21 CFR 1040).
The use of optical instruments with this product will increase eye hazard.
Ordering Information
For more information on this or other products and their availability, please contact your local JDSU account manager or
JDSU directly at 1-800-498-JDSU (5378) in North America and +800-5378-JDSU worldwide, or via e-mail at
[email protected].
Sample: PLRXPL-VC-S43-23-N
Part Number
PLRXPL-VC-S43-23-N
Product Description
10 G SFP+ SR compatible, limiting electrical interface, 0 – 70˚C, ± 5% Vcc, no rate select, generic
NORTH AMERICA: 800 498-JDSU (5378)
WORLDWIDE: +800 5378-JDSU
Product specifications and descriptions in this document subject to change without notice. © 2008 JDS Uniphase Corporation 30162599 000 1208
WEBSITE: www.jdsu.com
PLRXPL-VX-S43-23-N.DS.CMS.AE
December 2008