LT6553 650MHz Gain of 2 Triple Video Amplifier U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 650MHz –3dB Small Signal Bandwidth 400MHz –3dB 2VP-P Large Signal Bandwidth 150MHz ±0.1dB Bandwidth High Slew Rate: 2500V/µs Fixed Gain of 2 Requires No External Resistors 75dB Channel Separation at 10MHz 50dB Channel Separation at 100MHz –82dBc 2nd Harmonic Distortion at 10MHz, 2VP-P –72dBc 3rd Harmonic Distortion at 10MHz, 2VP-P Low Supply Current: 8mA per Amplifier 6ns 0.1% Settling Time for 2V Step TTL Compatible Enable ISS ≤ 100µA when Disabled Differential Gain of 0.022%, Differential Phase of 0.006° Wide Supply Range: ±2.25V (4.5V) to ±6V (12V) Available in 16-Lead SSOP Package U APPLICATIO S ■ ■ ■ The LT®6553 is a high-speed triple video amplifier with an internally fixed gain of 2. The individual amplifiers are optimized for performance with a double terminated 75Ω video load and feature a 2VP–P full signal bandwidth of 400MHz, making them ideal for driving very high-resolution video signals. Separate power supply pins for each amplifier boost channel separation to 75dB, allowing the LT6553 to excel in many high-speed applications. While the performance of the LT6553 is optimized for dual supply operation, it can also be used on a single supply as small as 4.5V. Using dual 5V supplies, each amplifier draws only 8mA. When disabled, the amplifiers draw less than 100µA and the output pins become high impedance. Furthermore, the amplifiers are capable of turning on in less than 50ns, making them ideal for multiplexing and portable applications. The LT6553 is manufactured on Linear Technology’s proprietary low voltage complementary bipolar process and is available in the 16-lead SSOP package that fits in the same PCB area as an SO-8 package. RGB Amplifiers Coaxial Cable Drivers LCD Projectors , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Triple Video Line Driver 1 2 5V 16 LT6553 Large Signal Transient Response 15 1.5 + – 75Ω 370Ω 13 370Ω 5 GIN 75Ω 6 370Ω – 0.5 –5V 75Ω 12 370Ω 11 10 75Ω 5V –1.0 75Ω –1.5 + 75Ω 75Ω –5V 8 0 –0.5 + 370Ω – 7 BIN 75Ω 370Ω 4 VIN = 1VP–P VS = ±5V 1.0 RL = 15OΩ TA = 25°C 75Ω 14 OUTPUT (V) 3 RIN 9 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6553 TA01b –5V 6553 TA01a 6553f 1 LT6553 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Total Supply Voltage (V+ to V–) ............................ 13.2V Input Current (Note 2) ........................................ ±10mA Output Current (Continuous) ............................. ±70mA EN to DGND Voltage (Note 2) ................................. 5.5V Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Junction Temperature ........................................... 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW EN 1 16 V + DGND 2 15 V + INR 3 AGND 4 ING 5 AGND 6 INB 7 V– 8 G = +2 LT6553CGN LT6553IGN 14 OUTR 13 V – G = +2 12 OUTG GN PART MARKING 11 V + G = +2 10 OUTB 9 V– 6553 6553I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 135°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND = 0V. SYMBOL PARAMETER CONDITIONS VOS Input Referred Offset Voltage VIN = 0V, VOS = VOUT/2 MIN TYP MAX UNITS 3 ±10 ±20 mV mV –17 ±50 ● IIN Input Current RIN Input Resistance VIN = ±1V CIN Input Capacitance f = 100kHz PSRR Power Supply Rejection Ratio VS (Total) = 4.5V to 12V (Note 6) ● IPSRR Input Current Power Supply Rejection VS (Total) = 4.5V to 12V (Note 6) ● 1 ±4 AV ERR Gain Error VOUT = ±2V ● –1.2 ±5 AV MATCH Gain Matching Any One Channel to Another VOUT Maximum Output Voltage Swing ● ● ● IS 150 56 ±3.25 ±3.1 Supply Current, Per Amplifier kΩ 1 pF 62 IEN VEN = 4V VEN = Open ● ● Enable Pin Current VEN = 0.4V VEN = V+ ● ● ● ISC Output Short-Circuit Current RL = 0Ω, VIN = ±1V SR Slew Rate ±1V on ±2V Output Step (Note 9) –3dB BW Small Signal –3dB Bandwidth 0.1dB BW Gain Flatness ±0.1dB Bandwidth –200 dB µA/V % ±1 % ±3.5 V V 8 11 14 mA mA 22 0.5 100 100 µA µA –95 0.5 50 µA µA ● Supply Current, Disabled, Total µA 400 ±50 ±105 mA 1700 2500 V/µs VOUT = 200mVP-P 650 MHz VOUT = 200mVP-P 150 MHz 6553f 2 LT6553 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS FPBW Full Power Bandwidth 2V VOUT = 2VP-P (Note 7) 270 400 MHz FPBW Full Power Bandwidth 4V VOUT = 4VP-P (Note 7) 200 MHz All-Hostile Crosstalk f = 10MHz, VOUT = 2VP-P f = 100MHz, VOUT = 2VP-P –75 –50 dB dB tS Settling Time 0.1% of VFINAL, VSTEP = 2V 6 ns tR, tF Small-Signal Rise and Fall Time 10% to 90%, VOUT = 200mVP-P 550 ps dG Differential Gain (Note 8) 0.022 % dP Differential Phase (Note 8) 0.006 Deg HD2 2nd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –82 dBc HD3 3rd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –72 dBc Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It is not production tested. Note 3: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Depending on the supply voltage, a heat sink may be required. Note 4: The LT6553C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 5: The LT6553C is guaranteed to meet specified performance from 0°C to 70°C. The LT6553C is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6553I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: The two supply voltage settings for power supply rejection are shifted from the typical ±VS points for ease of testing. The first measurement is taken at V+ = 3V, V– = –1.5V to provide the required 3V headroom for the enable circuitry to function with EN, DGND, AGND and all inputs connected to 0V. The second measurement is taken at V+ = 8V, V– = –4V. Note 7: Full power bandwidth is calculated from the slew rate: FPBW = SR/(π • VP-P) Note 8: Differential gain and phase are measured using a Tektronix TSG120YC/NTSC signal generator and a Tektronix 1780R video measurement set. The resolution of this equipment is better than 0.05% and 0.05°. Nine identical amplifier stages were cascaded giving an effective resolution of better than 0.0056% and 0.0056%. Note 9: Slew rate is 100% production tested on the G channel. Slew rate of the R and B channels is guaranteed through design and characterization. 6553f 3 LT6553 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current per Amplifier vs Temperature SUPPLY CURRENT (mA) VEN = 0V 8 VEN = 0.4V 6 V– = –V+ VEN, VDGND, VIN = 0V 10 TA = 25°C 4 2 8 6 4 0 5 25 45 65 85 105 125 TEMPERATURE (°C) 1 0 2 VS = ±5V VIN = 0V VS = ±5V –2.5 –5.0 0 EN PIN CURRENT (µA) 0 TA = 125°C –20 TA = 25°C TA = –55°C –40 4.0 VS = ±5V VDGND = 0V –40 TA = 125°C –60 TA = –55°C –80 TA = 25°C –100 –120 –7.5 –10.0 –55 –35 –15 –60 –2.5 5 25 45 65 85 105 125 TEMPERATURE (°C) –1.5 0.5 1.5 –0.5 INPUT VOLTAGE (V) 6553 G04 VS = ±5V RL = 150Ω –140 2.5 0 5 0 –1 –2 TA = –55°C OUTPUT VOLTAGE (V) 0 TA = –55°C 3 TA = 25°C 2 TA = 125°C 1 –3 VS = ±5V VIN = –2V –1 OUTPUT VOLTAGE (V) 4 1 5 4 Output Voltage Swing vs ILOAD (Output Low) VS = ±5V VIN = 2V TA = 125°C TA = 25°C 3 2 EN PIN VOLTAGE (V) 6553 G06 Output Voltage Swing vs ILOAD (Output High) 3 2 1 6553 G05 Output Voltage vs Input Voltage OUTPUT VOLTAGE (V) 3.5 1.0 1.5 2.0 2.5 3.0 EN PIN VOLTAGE (V) 0.5 EN Pin Current vs EN Pin Voltage 0 –20 INPUT BIAS CURRENT (µA) OFFSET VOLTAGE (mV) 20 2.5 4 0 6553 G03 Input Bias Current vs Input Voltage 5.0 5 4 6553 G02 Input Referred Offset Voltage vs Temperature 7.5 TA = 125°C 6 0 3 4 5 6 7 8 9 10 11 12 TOTAL SUPPLY VOLTAGE (V) 6553 G01 10.0 TA = 25°C 8 2 2 0 –55 –35 –15 VS = ±5V VDGND = 0V VIN = 0V TA = –55°C 10 SUPPLY CURRENT (mA) 10 12 12 VS = ±5V RL = ∞ VIN = 0V SUPPLY CURRENT (mA) 12 Supply Current per Amplifier vs EN Pin Voltage Supply Current per Amplifier vs Supply Voltage TA = 25°C –2 TA = 125°C –3 TA = –55°C –4 –4 –5 –2.5 0 –1.5 0.5 1.5 –0.5 INPUT VOLTAGE (V) 2.5 6553 G07 –5 0 10 20 30 40 50 60 70 80 90 100 SOURCE CURRENT (mA) 6553 G08 0 10 20 30 40 50 60 70 80 90 100 SINK CURRENT (mA) 6553 G09 6553f 4 LT6553 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Noise Spectral Density Input Impedance vs Frequency 1000 VS = ±5V TA = 25°C en in 10 VS = ±5V VIN = 0V TA = 25°C 10 1 VS = ±5V TA = 25°C ±PSRR 60 50 –PSRR 40 +PSRR 30 20 10 1 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 0.1 0.01 100 0.1 1 10 FREQUENCY (MHz) 100 Frequency Response vs Output Amplitude 8 7 Gain Flatness vs Frequency 0.5 VS = ±5V RL = 150Ω TA = 25°C 0.4 VOUT = 2VP-P 0.3 AMPLITUDE (dB) 6 5 VOUT = 4VP-P 4 3 VOUT = 200mVP-P 0.2 G-CHANNEL – 0.2 – 0.4 1000 R-CHANNEL – 0.1 – 0.3 100 10 FREQUENCY (MHz) – 20 B-CHANNEL 0 1 1 0.1 1 FREQUENCY (MHz) 10 100 Crosstalk vs Frequency 0 VS = ±5V VOUT = 200mVP-P RL = 150Ω TA = 25°C TYPICAL PART 0.1 2 0 0.1 0.01 6553 G12 AMPLITUDE (dB) 9 0 0.001 1000 6553 G11 6553 G10 AMPLITUDE (dB) 70 REJECTION RATIO (dB) 100 PSRR vs Frequency 100 INPUT IMPEDANCE (kΩ) INPUT NOISE (nV/√Hz OR pA/√Hz) 1000 VS = ±5V VOUT = 2VP-P RL = 150Ω TA = 25°C ALLHOSTILE – 40 – 60 WORST ADJACENT – 80 – 100 – 0.5 0.1 1 100 10 FREQUENCY (MHz) 1000 – 120 1 0.1 10 100 FREQUENCY (MHz) 1000 6553 G15 6553 G14 6553 G13 Frequency Response with Capacitive Loads 14 AMPLITUDE (dB) 12 VS = ±5V VOUT = 2VP-P RL = 150Ω TA = 25°C – 10 CL = 10pF 10 CL = 4.7pF 8 6 4 – 20 – 30 CL = 0pF 2 – 50 – 60 –2 – 100 –4 – 110 10 100 FREQUENCY (MHz) 1000 6553 G16 HD3 – 80 – 90 1 DISABLED VEN = 4V – 40 0 –6 0.1 VS = ±5V VOUT = 2VP-P RL = 150Ω TA = 25°C – 70 – 120 0.01 HD2 0.1 Output Impedance vs Frequency 1000 OUTPUT IMPEDANCE (Ω) 16 Harmonic Distortion vs Frequency 0 DISTORTION (dBc) 18 1 10 FREQUENCY (MHz) 100 6553 G17 100 10 ENABLED VEN = 0.4V 1 0.1 0.01 0.1 10 1 FREQUENCY (MHz) VS = ±5V RL = 150Ω TA = 25°C 100 1000 6553 G18 6553f 5 LT6553 U W TYPICAL PERFOR A CE CHARACTERISTICS Video Amplitude Transient Response Small Signal Transient Response 4 VOUT = 700mVP–P 0.8 VS = ±5V RL = 150Ω 0.7 T = 25°C A VIN = 100mVP–P VS = ±5V 0.10 RL = 150Ω TA = 25°C 3 2 OUTPUT (V) 0 –0.05 OUTPUT (V) 0.6 0.05 OUTPUT (V) Large Signal Transient Response 0.9 0.15 0.5 0.4 0.3 0 –1 –2 0.1 –3 0 –0.1 2 4 6 8 10 12 14 16 18 20 TIME (ns) 0 2 4 6 Large Signal Transient Response PERCENT OF UNITS (%) 40 0 –0.5 6553 G21 Gain Error Distribution 45 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 TIME (ns) 6553 G20 1.5 VIN = 1VP–P VS = ±5V 1.0 RL = 150Ω TA = 25°C –4 8 10 12 14 16 18 20 TIME (ns) 35 Gain Error Matching Distribution 35 VS = ±5V VOUT = ±2V RL = 150Ω TA = 25°C 30 PERCENT OF UNITS (%) 0 6553 G19 OUTPUT (V) 1 0.2 –0.10 –0.15 VOUT = 5VP–P VS = ±5V RL = 150Ω TA = 25°C 30 25 20 15 VS = ±5V VOUT = ±2V RL = 150Ω TA = 25°C 25 20 15 10 10 –1.0 5 5 –1.5 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6553 G22 0 –3.0 –2.5 –2.0 –1.5 –1.0 – 0.5 0 0.5 1.0 1.5 GAIN ERROR–INDIVIDUAL CHANNEL (%) 6553 G23 0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 GAIN ERROR–BETWEEN CHANNELS (%) 6553 G24 6553f 6 LT6553 U U U PI FU CTIO S EN (Pin 1): Enable Control Pin. An internal pull-up resistor of 46k defines the pin’s impedance and will turn the part off if the pin is unconnected. When the pin is pulled low, the part is enabled. DGND (Pin 2): Digital Ground Reference for Enable Pin. This pin is normally connected to ground. INR (Pin 3): Red Channel Input. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND (Pin 4): Analog Ground for 370Ω Gain Resistor of Red Channel Amplifier. ING (Pin 5): Green Channel Input. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND (Pin 6): Analog Ground Shared for the 370Ω Gain Resistors of both Green and Blue Channel Amplifiers. Additional resistance at this pin will increase the crosstalk between the green and blue channels. INB (Pin 7): Blue Channel Input. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. V – (Pin 8): Negative Supply Voltage. V – pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. V – (Pin 9): Negative Supply Voltage for Blue Channel Output Stage. V – pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUTB (Pin 10): Blue Channel Output. It is twice the blue channel input, and performs optimally with a 150Ω load (a double terminated 75Ω cable). V + (Pin 11): Positive Supply Voltage for Output Stages of Amplifiers B and G. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUTG (Pin 12): Green Channel Output. It is twice the green channel input, and performs optimally with a 150Ω load (a double terminated 75Ω cable). V – (Pin 13): Negative Supply Voltage for Output Stage of Amplifiers G and R. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUTR (Pin 14): Red Channel Output. It is twice the red channel input, and performs optimally with a 150Ω load (a double terminated 75Ω cable). V + (Pin 15): Positive Supply Voltage for Output Stage R. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. V + (Pin 16): Positive Supply Voltage. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. 6553f 7 LT6553 U W U U APPLICATIO S I FOR ATIO Power Supplies The LT6553 is optimized for ±5V supplies but can be operated on as little as ±2.25V or a single 4.5V supply and as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation. Do not leave any supply pins disconnected or the part may not function correctly! Enable/Shutdown The LT6553 has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pull-up resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the DC output impedance will rise to approximately 700Ω through the internal feedback and gain resistors. Supply current into the amplifier in the disabled state will be primarily through V+ and approximately equal to (V+ – VEN)/46k. It is important that the two following constraints on the DGND pin and the EN pin are always followed: V+ – VDGND ≥ 3V VEN – VDGND ≤ 5.5V Split supplies of ±3V to ±5.5V will satisfy these requirements with DGND connected to 0V. In single supply applications above 5.5V, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to float. For example, on a 12V single supply, a 33k resistor would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. On dual ±2.25V supplies, connecting the EN and DGND pins to V– is the easiest way of ensuring that V+ – VDGND is more than 3V. The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to 10mA or less. The enable/disable times of the LT6553 are fast when driven with a logic input. Turn on (from 50% EN input to 50% output) typically occurs in less than 50ns. Turn off is slower, but is nonetheless below 300ns. Input Considerations The LT6553 input voltage range is from V– + 1V to V+ – 1V. Therefore, on split supplies the LT6553 input range is always larger than the output swing. On a single positive supply, however, the input range limits the output low swing to 2V (1V multiplied by the internal gain of 2). The inputs can be driven beyond the point at which the output clips so long as input currents are limited to below ±10mA. Continuing to drive the input beyond the output limit can result in increased current drive and slightly increased swing, but will also increase supply current and may result in delays in transient response at larger levels of overdrive. Layout and Grounding It is imperative that care is taken in PCB layout in order to utilize the very high speed and very low crosstalk of the LT6553. Separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. If input or output traces must be run over a distance of several centimeters, they should use a controlled impedance with matching series and shunt resistances (nominally 75Ω) to maintain signal fidelity. Series termination resistors should be placed as close to the output pins as possible to minimize output capacitance. See the Typical Performance Characteristics section for a plot of frequency response with various output capacitors—only 10pF of parasitic output capacitance causes 6dB of peaking in the frequency response! Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 4700pF ceramic capacitor is recommended for both V+ and V–. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional 1µF to 10µF tantalums should be added on each supply. The smallest value capacitors should be placed closest to the package. 6553f 8 LT6553 U W U U APPLICATIO S I FOR ATIO If the AGND pins are not connected directly to a low impedance ground plane, they must be carefully bypassed to maintain minimal impedance over frequency. Pin 6 is a shared connection of the gain resistors of both channel G and channel B, and any resistance external to this node can significantly decrease the isolation between those channels. Although crosstalk will be very dependent on the board layout, a recommended starting point for bypass capacitors would be 470pF as close as possible to each AGND pin with one 4700pF capacitor in parallel. plane or power supply traces. Vias between topside and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. ESD Protection The LT6553 has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may flow through these diodes. If the current is kept below 10mA, no damage to the devices will occur. To maintain the LT6553’s channel isolation, it is beneficial to shield parallel input and output traces using a ground U TYPICAL APPLICATIO RGB Buffer Demo Board terminations are connected as close to the part as possible. For ideal operation, a 75Ω load termination should be connected at the output. The LT6553’s gain of 2 will compensate for the resulting divider between the series and load termination resistors. The DC714 Demo Board illustrates optimal routing, bypassing and termination using the LT6553 as an RGB video buffer. The schematic is shown in Figure 1. All inputs and outputs are routed to have a characteristic impedance of 75Ω and 75Ω input shunt and output series E1 EN J1 50Ω BNC 1 EN JP1 CONTROL 1 2 ENABLE 5 4 3 2 V+ 3 EXT C1 4700pF JP2 DGND 1 2 3 AGND FLOAT INR ING INB 5 4 3 2 BNC × 3 1 E2 DGND 1 2 Z = 75 3 4 J5 5 4 3 2 1 Z = 75 5 6 J6 5 4 3 2 Z = 75 1 7 R4 75Ω J7 R5 75Ω R6 75Ω 8 LT6553 EN V+ 16 DGND V+ 15 INR OUTR V– AGND ING OUTG V+ AGND INB OUTB R1 75Ω 14 13 R2 75Ω 12 11 R3 75Ω 10 C2 470pF C3 4700pF V+ C4 J2 10µF, 16V BANANA 1210 JACK NOTE 5 BNC x3 1 Z = 75 Z = 75 OUTG J10 5 4 3 2 OUTB J11 5 4 3 2 1 Z = 75 1 9 V– V– OUTR J9 5 4 3 2 V– E3 AGND SINGLE 1 AGND CAL 5 4 3 2 J3 BANANA JACK 1 DUAL 2 3 JP3 SUPPLY C5 470pF C6 1000pF C7 470pF C8 4700pF V– J4 BANANA JACK C9 10µF, 16V 1210 Z = 75 J8 BNC 1 J12 BNC Figure 1. DC714 Demo Board Schematic 5 4 3 2 CAL 6553 F01 6553f 9 LT6553 U TYPICAL APPLICATIO S A fourth signal trace is provided at the bottom of the DC714 demo board with dimensions identical to the combined input and output of the other channels. This trace can be used for calibrating the effects of electrical delay and impedance mismatching and is not necessary in an end-user application. Several jumpers and additional connectors are also included to allow for testing of the enable feature and single supply operation. within the input and output common mode range of the part. On a 9V single supply, the input would sit at 2.2V DC, and the output would sit at 4.4V. Due to the 220µF coupling cap at the output, the only additional power dissipation due to the positive output voltage is through the feedback and gain resistors. Since those resistors are approximately 740Ω in series, the additional quiescent current is only 6mA per channel. Single Supply RGB Buffer Demo Board RGB Video Selector/Cable Driver The DC743A Demo Board uses the LT6553 in a single supply application with AC coupled inputs and outputs. It is nearly identical to the DC714 RGB Buffer Demo Board but has the additional components required for AC coupling and setting a DC bias point at the input. A schematic of a single channel is shown in Figure 2. AC performance of the LT6553 in the single supply application as shown is nearly identical to performance with dual supplies. A video multiplexer can be implemented using the EN pins of parallel LT6553s as shown in Figure 3. In this application, all outputs are connected together and one LT6553 is switched on while the other is switched off. A fast inverter provides a complementary signal to ensure that only one set of R, G and B channels is buffered at any time. As shown, the outputs are connected before the 75Ω series termination resistors in order to reduce any DC attenuation that may result from the non-infinite output impedance of the disabled LT6553. The 6.8k and 2.2k bias resistors at the input set up a nominal DC voltage at the input that keeps a video signal 7V TO 12V 22µF* 6.8k IN 80.6Ω 2.2k 1/3 LT6553 OUT 75Ω 220µF** + INPUT AGND * AVX 12066D226MAT ** SANYO 6TPB220ML 75Ω 6553 F02 Figure 2. Single Supply Configuration, One Channel Shown 6553f 10 LT6553 W W SI PLIFIED SCHE ATIC V+ V+ TO OTHER AMPLIFIERS BIAS AGND 370Ω V+ 46k 150Ω 1k EN 370Ω IN OUT V– DGND V– 6553 SS V– U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .053 – .068 (1.351 – 1.727) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 0502 6553f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT6553 U TYPICAL APPLICATIO 3.3V NC7SZ14 1 LT6553 3 R1 ×2 5 ×2 7 75Ω 75Ω 75Ω ×2 LT6553 3 ×2 G0 ×2 7 75Ω 75Ω 75Ω B 16 14 12 11 6 B0 75Ω 10 13 4 5 G 15 2 R0 75Ω 12 9 8 1 SEL R 11 6 B1 75Ω 14 13 4 G1 16 15 2 ×2 8 10 9 NOTE: POWER SUPPLY BYPASS CAPACITORS NOT SHOWN FOR CLARITY –3.3V 6553 F03 Figure 3. RGB Video Selector/Cable Driver RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1259/LT1260 Dual/Triple 130MHz Current Feedback Amplifiers Shutdown, Operates to ±15V LT1395/LT1396/LT1397 Single/Dual/Quad 400MHz Current Feedback Amplifiers 800V/µs Slew Rate LT1398/LT1399 Dual/Triple 300MHz Current Feedback Amplifiers 0.1dB Gain Flatness to 150MHz, Shutdown LT1675/LT1675-1 250MHz, Triple and Single RGB Multiplexer with Current Feedback Amplifiers 100MHz Pixel Switching, –3dB Bandwidth: 250MHz, 1100V/µs Slew Rate LT1809/LT1810 Single/Dual, 180MHz, Rail-to-Rail Input and Output Amplifiers 350V/µs Slew Rate, Shutdown, Low Distortion –90dBc at 5MHz LT6550/LT6551 3.3V Triple and Quad Video Buffers 110MHz Gain of 2 Buffers in MS Package 6553f 12 Linear Technology Corporation LT/TP 0304 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2004