LTC1909-8 Wide Operating Range, No RSENSETM Step-Down DC/DC Controller with SMBus Programming U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO SMBus/I2CTM Programmable Output Voltage: 1.3V to 3.5V No Sense Resistor Required 2% to 90% Duty Cycle at 200kHz tON(MIN) ≤ 100ns True Current Mode Control Stable with Ceramic COUT Power Good Output Voltage Monitor and 50µs Timer Wide VIN Range: 4V to 36V (Abs Max) Precision Resistor Divider and Reference Provide ±1.35% Output Voltage Accuracy Over Temperature Adjustable Switching Frequency and Current Limit Forced Continuous Control Pin Programmable Soft-Start Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Available in a 28-Lead SSOP Package U APPLICATIO S ■ Power Supplies for DSPs, ASICs, FPGAs and CPUs Voltage Margining Discontinuous mode operation provides high efficiency operation at light loads. A forced continuous control pin reduces noise and RF interference and can assist secondary winding regulation by disabling discontinuous mode operation when the main output is lightly loaded. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator and optional short-circuit shutdown timer. The LTC1909-8 is available in the 28-lead SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. U ■ The LTC®1909-8 is a synchronous step-down switching regulator controller with a digitally programmable output voltage. The output voltage is selected from one of two 5-bit settings programmed into internal registers via a 2-wire SMBus/I2C interface. The interface features safeguards against invalid output voltages and allows the microprocessor to turn the regulator on and off. Valley current control delivers very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. TYPICAL APPLICATIO 0.1µF 100k LTC1909-8 100k 1 100k 2 11k 39k 3 4 100pF 5 6 470pF 7 20k 8 9 SEL SDA SCL VRON 10 11 12 13 14 RUN/SS VON PGOOD VRNG FCB ITH SGND ION VFB SEL SDA SCL VRON PGTMR BOOST TG SW SENSE + PGND BG INTVCC VIN 28 27 0.22µF M1 26 VIN 5V TO 24V CIN 10µF 50V ×4 CMDSH-3 GND L1 1.8µH VOUT 2.5V OR 2.6V 10A (VOUT SET BY SEL) 25 24 23 M2 + 22 21 20 5V EXTVCC EXT 19 VCC 18 GND 17 FB 16 VOSENSE 15 CPUON 1Ω 0.1µF + 4.7µF 6.3V COUT1, 2 180µF 4V ×2 COUT3 22µF 6.3V X7R D1 GND RON 1.4M 1% 19098 F01 CIN: UNITED CHEMICON THCR60E1H106TZ COUT1, 2: CORNELL DUBILIER ESRE181ME04B/ PANASONIC EEFVEOG181R D1: DIODES INC. B340A L1: SUMIDA CEP125-1R8MC-H M1: Si4884 M2: Si4874 Figure 1. High Efficiency Step-Down Converter 19098f 1 LTC1909-8 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage VIN, ION ..................................................– 0.3V to 36V Boosted Topside Driver Supply Voltage BOOST .................................................. – 0.3V to 42V SW, SENSE + Voltages ................................. – 5V to 36V EXTVCC, (BOOST – SW), RUN/SS, PGOOD, INTVCC, SEL, SDA, SCL, VRON, PGTMR, VOSENSE, FB, CPUON, VCC Voltages .......................... – 0.3V to 7V FCB, VON, VRNG Voltages ....... – 0.3V to (INTVCC + 0.3V) ITH, VFB Voltages...................................... – 0.3V to 2.7V TG, BG, INTVCC, EXTVCC Peak Currents .................... 2A TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA Operating Ambient Temperature Range LTC1909-8EG (Note 2) ....................... – 40°C to 85°C Junction Temperature (Note 4) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUN/SS 1 28 BOOST VON 2 27 TG PGOOD 3 26 SW VRNG 4 25 FCB 5 24 PGND ITH 6 23 BG SGND 7 22 INTVCC ION 8 21 VIN VFB 9 20 EXTVCC SEL 10 19 VCC SDA 11 18 GND SCL 12 17 FB VRON 13 PGTMR 14 LTC1909-8EG SENSE + 16 VOSENSE 15 CPUON G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS (Switching Regulator Controller) The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 900 15 2000 30 µA µA 0.800 0.808 V Main Control Loop IQ Input DC Supply Current Normal Shutdown Supply Current VFB Feedback Reference Voltage ITH = 1.2V (Note 3) ∆VFB(LINEREG) Feedback Voltage Line Regulation VIN = 4V to 30V, ITH = 1.2V (Note 3) ∆VFB(LOADREG) Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) IFB Feedback Input Current VFB = 0.8V gm(EA) Error Amplifier Transconductance ITH = 1.2V (Note 3) VFCB Forced Continuous Threshold IFCB Forced Continuous Pin Current VFCB = 0.8V tON On-Time ION = 60µA, VON = 1.5V ION = 30µA, VON = 1.5V tON(MIN) Minimum On-Time ION = 180µA, VON = 0V tOFF(MIN) Minimum Off-Time ION = 60µA, VON = 1.5V VSENSE(MAX) Maximum Current Sense Threshold VPGND – VSENSE+ VRNG = 1V, VFB = 0.76V VRNG = 0V, VFB = 0.76V VRNG = INTVCC, VFB = 0.76V VSENSE(MIN) Minimum Current Sense Threshold VPGND – VSENSE+ VRNG = 1V, VFB = 0.84V VRNG = 0V, VFB = 0.84V VRNG = INTVCC, VFB = 0.84V ∆VFB(OV) Output Overvoltage Fault Threshold ● 0.792 0.002 ● %/V – 0.05 – 0.3 % –5 ±50 nA mS ● 1.4 1.7 2 ● 0.76 0.8 0.84 V –1 –2 µA 250 500 288 575 ns ns 50 100 ns 212 425 ● 113 79 158 250 400 ns 133 93 186 153 107 214 mV mV mV – 67 – 47 – 93 5.5 7.5 mV mV mV 9.5 % 19098f 2 LTC1909-8 ELECTRICAL CHARACTERISTICS (Switching Regulator Controller) The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ∆VFB(UV) Output Undervoltage Fault Threshold 520 600 680 mV VRUN/SS(ON) RUN Pin Start Threshold VRUN/SS(LE) RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising 0.8 1.5 2 V 4 4.5 V VRUN/SS(LT) RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 4.2 V IRUN/SS(C) Soft-Start Charge Current VRUN/SS = 0V IRUN/SS(D) Soft-Start Discharge Current VRUN/SS = 4.5V, VFB = 0V – 0.5 – 1.2 –3 µA 0.8 1.8 3 µA VIN(UVLO) Undervoltage Lockout VIN Falling VIN(UVLOR) Undervoltage Lockout Release VIN Rising ● 3.4 3.9 V ● 3.5 4 V TG RUP TG Driver Pull-Up On Resistance TG High 2 3 Ω TG RDOWN TG Driver Pull-Down On Resistance TG Low BG RUP BG Driver Pull-Up On Resistance BG High 2 3 Ω 3 4 Ω BG RDOWN BG Driver Pull-Down On Resistance BG Low 1 2 Ω TG tr TG Rise Time CLOAD = 3300pF, 20% to 80% of Swing 20 ns TG tf TG Fall Time CLOAD = 3300pF, 20% to 80% of Swing 20 ns BG tr BG Rise Time CLOAD = 3300pF, 20% to 80% of Swing 20 ns BG tf BG Fall Time CLOAD = 3300pF, 20% to 80% of Swing 20 ns ● Internal VCC Regulator VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V ∆VLDO(LOADREG) Internal VCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 4V VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, VEXTVCC Rising ∆VEXTVCC EXTVCC Switch Drop Voltage ICC = 20mA, VEXTVCC = 5V ∆VEXTVCC(HYS) EXTVCC Switchover Hysteresis ● ● 4.7 4.5 5 5.3 V – 0.1 ±2 % 4.7 150 V 300 200 mV mV PGOOD Output ∆VFBH PGOOD Upper Threshold VFB Rising 5.5 7.5 9.5 % ∆VFBL PGOOD Lower Threshold VFB Falling – 5.5 – 7.5 – 9.5 % ∆VFB(HYS) PGOOD Hysteresis VFB Returning 1 2 % VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V (SMBus VID Programmer) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.7V ≤ VCC ≤ 5.5V (Note 5) unless otherwise stated. SYMBOL PARAMETER VCC Operating Supply Voltage Range ICC Supply Current RFB-SENSE Resistance Between VOSENSE and FB DE Divider Error (Note 6) VIH CONDITIONS MIN TYP 2.7 CPUON, PGTMR Pins Are Open ● ● 14 ● – 0.35 SCL, SDA Input High Voltage ● 2.1 VIL SCL, SDA Input Low Voltage ● VIH SEL, VRON Input High Voltage VIL SEL, VRON Input Low Voltage VHYST SEL, VRON Hysteresis VOL SDA, CPUON PGTMR Output Low Voltage I = 3mA IIN SCL, SDA, SEL, VRON Input Current VOSENSE Programmed from 1.3V to 3.5V 20 SDA Not Acknowledging, 0 ≤ VPIN ≤ 5.5V, VPIN = 5.5V for VRON only 0.8 UNITS 5.5 V 350 µA 26 kΩ 0.35 % V 1.3 ● MAX 0.8 V 2 V 1.3 V ±50 mV ● 0.4 V ● ±10 µA 19098f 3 LTC1909-8 ELECTRICAL CHARACTERISTICS (SMBus VID Programmer) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.7V ≤ VCC ≤ 5.5V (Note 5) unless otherwise stated. SYMBOL PARAMETER CONDITIONS ISK1 SDA, PGTMR, CPUON Sink Current at VCC = 2.7V 0 ≤ VPIN ≤ 2.7V ISK2 SDA, PGTMR, CPUON Sink Current at VCC = 5.5V 0 ≤ VPIN ≤ 5.5V ILKG PGTMR, CPUON Leakage Current 0 ≤ VPIN ≤ 5.5V IPU VRON Pull-Up Current VPIN = 0 MIN TYP MAX ● 5 19 60 mA ● 35 65 150 mA ±0.2 µA –7 µA 100 KHz ● –1 – 2.5 UNITS Timing (Note 7) fSMB SMBus Operating Frequency ● 10 tBUF Bus Free Time Between Stop/Start ● 4.7 µs tHD:STA Hold Time After (Repeated) Start ● 4 µs tSU:STA Repeated Start Setup Time ● 4.7 µs tSU:STO Stop Condition Setup Time ● 4 µs tHD:DAT Data Hold Time ● 300 ns tSU:DAT Data Setup Time ● 250 ns tLOW Clock Low Period ● 4.7 µs tHIGH Clock High Period ● 4 µs tf SCL, SDA Fall Time 0.9VCC to 0.65V ● 300 ns tr SCL, SDA Rise Time 0.65V to 2.25V ● 1000 ns tSSH SEL to VOSENSE High (Note 8) Toggle SEL to Switch from 01111B to 10000B, VFB = 0.8V ● 500 ns tSSL SEL to VOSENSE Low (Note 8) Toggle SEL to Switch from 10000B to 01111B, VFB = 0.8V ● 500 ns tSPL SEL Toggling to PGTMR Low Toggle SEL to Select New Code CL = 100pF, 10kΩ Pull-Up, S2 in Test Circuit ● 160 500 ns tPH Stop Bit to CPUON High (Note 9) CL = 100pF, 10kΩ Pull-Up, S2 in Test Circuit ● 2 µs tPL Stop Bit to CPUON Low (Note 9) CL = 0.1µF, 10kΩ Pull-Up, S1 in Test Circuit ● 20 50 µs tPPL Stop Bit to PGTMR Low (Note 9) CL = 100pF, 10kΩ Pull-Up, S2 in Test Circuit ● 250 ns tVH VRON High to CPUON High CL = 100pF, 10kΩ Pull-Up, S2 in Test Circuit ● 2 µs tVL VRON Low to CPUON Low CL = 0.1µF, 10kΩ Pull-Up, S1 in Test Circuit ● 50 µs tVPL VRON Low to PGTMR Low CL = 100pF, 10kΩ Pull-Up, S2 in Test Circuit ● 130 500 ns tPGL PGTMR Low Duration CL = 100pF, 10kΩ Pull-Up, S2 in Test Circuit 50 70 µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1909-8E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC1909-8 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 4: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC1909-8E: TJ = TA + (PD • 130°C/W) 30 Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise noted. Note 6: The divider error is tested in a feedback loop that adjusts FB to 0.8V for each 5-bit code. Note 7: These parameters are guaranteed by design and are not tested in production. SMBus timing is referenced to VIL and VIH levels. Note 8: Dominated by the switching regulator. The delay due to the SMBus VID programmer is only 500ns typ. Note 9: Measured from the rising edge of SDA during Data High acknowledgment. 19098f 4 LTC1909-8 U W TYPICAL PERFOR A CE CHARACTERISTICS Transient Response (Discontinuous Mode) Transient Response Efficiency vs Load Current 100 VOUT 50mV/DIV IL 5A/DIV IL 5A/DIV 20µs LOAD STEP 0A TO 10A VIN = 15V VOUT = 2.5V FCB = 0V FIGURE 1 CIRCUIT DISCONTINUOUS MODE 90 EFFICIENCY (%) VOUT 50mV/DIV CONTINUOUS MODE 70 VIN = 10V VOUT = 2.5V EXTVCC = 5V FIGURE 1 CIRCUIT 60 20µs LOAD STEP 1A TO 10A VIN = 15V VOUT = 2.5V FCB = INTVCC FIGURE 1 CIRCUIT 19098 G16 80 19098 G17 50 0.001 0.1 0.01 1 LOAD CURRENT (A) 10 19098 G18 Efficiency vs Input Voltage Frequency vs Input Voltage 300 FCB = 5V FIGURE 1 CIRCUIT FREQUENCY (kHz) EFFICIENCY (%) FCB = 0V FIGURE 1 CIRCUIT 280 95 ILOAD = 1A 90 ILOAD = 10A Load Regulation 0 260 IOUT = 0A 240 FIGURE 1 CIRCUIT –0.1 IOUT = 10A ∆VOUT (%) 100 85 –0.2 –0.3 220 80 5 10 15 20 INPUT VOLTAGE (V) 25 200 30 10 5 15 300 CURRENT SENSE THRESHOLD (mV) ITH VOLTAGE (V) 1.5 CONTINUOUS MODE 1.0 DISCONTINUOUS MODE 15 19098 G22 1.4V 200 1V 0.7V 0.5V 100 0 –100 –200 10 5 LOAD CURRENT (A) 6 4 LOAD CURRENT (A) 8 0 0.5 1.0 1.5 2.0 ITH VOLTAGE (V) 10 Current Limit Foldback VRNG = 2V FIGURE 1 CIRCUIT 0 2 19098 G21 Current Sense Threshold vs ITH Voltage 2.0 0 0 19098 G20 ITH Voltage vs Load Current 0.5 25 INPUT VOLTAGE (V) 19098 G19 2.5 –0.4 20 MAXIMUM CURRENT SENSE THRESHOLD (mV) 0 2.5 3.0 19098 G23 150 125 100 75 50 25 0 0 0.2 0.4 VFB (V) 0.6 0.8 1778 G09 19098f 5 LTC1909-8 U W TYPICAL PERFOR A CE CHARACTERISTICS 250 200 150 100 50 0.5 0.75 1.0 1.25 1.5 VRNG VOLTAGE (V) 1.75 2.0 150 0.82 VRNG = 1V FEEDBACK REFERENCE VOLTAGE (V) 300 0 Feedback Reference Voltage vs Temperature Maximum Current Sense Threshold vs Temperature MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs VRNG Voltage 140 130 120 110 100 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 19098 G25 1.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 –0.25 6 4 2 50 25 0 75 TEMPERATURE (°C) 100 125 –1.50 –50 –25 0 PULL-UP CURRENT LATCHOFF ENABLE 4.0 3.5 LATCHOFF THRESHOLD 125 19098 G31 3.0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 Undervoltage Lockout Threshold vs Temperature 4.5 –1 100 50 25 75 0 TEMPERATURE (°C) 19098 G30 UNDERVOLTAGE LOCKOUT THRESHOLD (V) RUN/SS THRESHOLD (V) 1 50 25 0 75 TEMPERATURE (°C) –1.00 19098 G29 5.0 –25 –0.75 RUN/SS Latchoff Thresholds vs Temperature PULL-DOWN CURRENT –2 –50 –0.50 –1.25 19098 G28 3 125 FCB Pin Current vs Temperature 8 RUN/SS Pin Current vs Temperature 100 0 0 –50 –25 125 2 75 0 25 50 TEMPERATURE (°C) 19098 G27 FCB PIN CURRENT (µA) EXTVCC SWITCH RESISTANCE (Ω) gm (mS) 1.2 FCB PIN CURRENT (µA) 0.78 –50 –25 125 10 1.4 0.79 EXTVCC Switch Resistance vs Temperature 2.0 1.6 0.80 19098 G25 Error Amplifier gm vs Temperature 1.8 0.81 100 125 19098 G32 4.0 3.5 3.0 2.5 2.0 –50 –25 75 0 25 50 TEMPERATURE (C) 100 125 19098 G33 19098f 6 LTC1909-8 U W TYPICAL PERFOR A CE CHARACTERISTICS VCC Supply Current vs Supply Voltage 300 TA = 25°C 20.08 250 200 150 100 20.04 20.02 200 VCC = 2.7V 150 100 19.98 19.96 19.92 19.90 0 0 – 55 –35 –15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VCC (V) 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G01 INPUT LOW, VCC = 5.5V 1.25 INPUT HIGH, VCC = 2.7V 1.20 INPUT LOW, VCC = 2.7V 1.15 1.10 – 55 –35 –15 1.4 0.06 1.3 0.05 INPUT LOW 1.2 1.1 0.9 0.01 3.5 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) 6.5 0.25 OUTPUT LOW VOLTAGE (V) 0.08 0.07 0.06 0.05 0.04 0.03 0.02 3.5 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) 6.5 7 19098 G07 SCL, SDA, SEL Input Current vs Temperature IPIN = 3mA 0.20 VCC = 2.7V 0.15 0.10 VCC = 5.5V 0.05 0.01 3 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G06 SDA, CPUON, PGTMR Output Low Voltage vs Temperature TA = 25°C 0 2.5 0 – 55 –35 –15 7 19098 G05 SCL, SDA, SEL and VRON Hysteresis vs Supply Voltage 0.09 0.03 0.02 3 VCC = 2.7V 0.04 1.0 19098 G04 0.10 VCC = 5.5V INPUT HIGH 0.8 2.5 5 25 45 65 85 105 125 TEMPERATURE (°C) 0.07 TA = 25°C INPUT CURRENT (nA) 1.30 SCL, SDA, SEL and VRON Hysteresis vs Temperature HYSTERESIS (V) INPUT HIGH AND LOW VOLTAGE (V) 1.5 INPUT HIGH, VCC = 5.5V 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G03 SCL, SDA, SEL and VRON Input High and Low Voltage vs Supply Voltage 1.40 1.35 19.88 – 55 –35 –15 19098 G02 SCL, SDA, SEL and VRON Input High and Low Voltage vs Temperature INPUT HIGH AND LOW VOLTAGE (V) 20.00 19.94 50 50 VCC = 2.7V TO 5.5V 20.06 VCC = 5.5V 250 VCC SUPPLY CURRENT (µA) VCC SUPPLY CURRENT (µA) 300 HYSTERESIS (V) Resistance Between VOSENSE and FB Pins vs Temperature VCC Supply Current vs Temperature RSENSE (kΩ) 350 (SMBus VID Programmer) 0 – 55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G08 15 14 VCC = 5.5V VPIN = 5.5V 13 12 11 10 9 8 7 6 5 SCL PIN 4 3 2 SEL PIN 1 SDA PIN 0 – 55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G09 19098f 7 LTC1909-8 U W TYPICAL PERFOR A CE CHARACTERISTICS SDA, PGTMR, CPUON Sink Current vs Temperature PGTMR, CPUON Leakage Current vs Temperature 7 80 50 40 30 VCC = 2.7V, ISK1 20 2.50 2.45 VRON PULL-UP CURRENT (µA) 60 5 4 3 2 1 10 2.30 2.25 2.20 2.15 2.10 2.05 2.00 VCC = 2.7V 19098 G12 Power Good Timer Low Duration vs Temperature Resistor Divider Error vs Temperature 52.0 2.0 1.5 1.0 0.5 0 1.5 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V) 6.5 19098 G013 0.25 51.5 VCC = 5.5V 51.0 50.5 VCC = 2.7V (MINIMUM VCC) 0.20 DIVIDER ERROR (%) POWER GOOD TIMER LOW DURATION (µs) TA = 25°C VRON = 0V 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G11 VRON Pull-Up Current vs Supply Voltage VRON PULL-UP CURRENT (µA) VCC = 5.5V 2.35 1.90 – 55 –35 –15 0 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G10 2.5 2.40 1.95 0 – 55 –35 –15 3.0 VRON Pull-Up Current vs Temperature VPIN = 5.5V 6 VCC = 5.5V, ISK2 LEAKAGE CURRENT (nA) SINK CURRENT (mA) 70 (SMBus VID Programmer) VCC = 2.7V 50.0 0.15 CODE 15 0.10 CODE 31 0.05 CODE 0 0 –0.05 CODE 16 –0.10 49.5 –0.15 49.0 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 19098 G14 –0.20 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 19098 G15 19098f 8 LTC1909-8 U U U PI FU CTIO S RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/µF) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the device. VON (Pin 2): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.7V when the pin is grounded and 2.4V when the pin is tied to INTVCC. PGOOD (Pin 3): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. VRNG (Pin 4): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to INTVCC. FCB (Pin 5): Forced Continuous Input. Tie this pin to ground to force continuous synchronous operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. ITH (Pin 6): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). SGND (Pin 7): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. ION (Pin 8): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. VFB (Pin 9): Error Amplifier Feedback Input. This pin connects to the error amplifier input to the center tap of the SMBus programmable divider at the FB pin (Pin 17). SEL (Pin 10): Register Select Input. A TTL compatible logic input pin that is used to select 1 of 2 resistor divider settings. SEL selects the setting in Register 0 if pulled low and the setting in Register 1 if pulled high. SDA (Pin 11): SMBus Data Input/Output. SDA is a high impedance input when address, command or data bits are shifted into the SMBus interface. It is an open-drain N-channel output when acknowledging or sending data back to the microprocessor during read back. It requires a pull-up resistor or current source to VCC. SCL (Pin 12): SMBus Clock Input. Data at the SDA pin is latched into the LTC1909-8 SMBus interface at the rising edge of the clock and is shifted out of the SDA pin at the falling edge of the clock. SCL is a high impedance input pin. It is driven by the open collector output of a microprocessor and requires a pull-up resistor or current source to VCC. VRON (Pin 13): Global Control Input. This TTL compatible input pin is pulled up internally by a 2.5µA current source. Pulling VRON low forces the open-drain output pins (CPUON and PGTMR) to pull to ground. If the LTC1909-8 is programmed to turn on a DC/DC converter, pulling VRON high three-states the CPUON pin and allows the switching regulator to soft-start if CPUON is tied to the RUN/SS pin. PGTMR (Pin 14): Power Good Timer Output. This opendrain output is pulled low for 50µs each time the switching regulator is turned on or SEL is toggled to select a new code. PGTMR may be connected to the FCB pin to force the converter into continuous mode operation. This reduces the time needed for the converter output to settle to a lower output voltage under light load conditions if the SEL pin is toggled to select a lower output voltage. CPUON (Pin 15): CPU DC/DC Converter Control. Opendrain output, usually connected to the RUN/SS pin. It pulls low to shut down the converter or becomes high impedance to allow the converter to soft-start. VOSENSE (Pin 16): Sense Input. Upper terminal of the SMBus programmable resistor divider that is connected directly to the regulated output voltage node. 19098f 9 LTC1909-8 U U U PI FU CTIO S FB (Pin 17): Feedback Input. Center tap of the SMBus programmable divider that is connected to Pin 9. BG (Pin 23): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and INTVCC. GND (Pin 18): SMBus Programmer Ground. Connect to regulator signal ground at Pin 7. PGND (Pin 24): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (–) terminal of CVCC and the (–) terminal of CIN. VCC (Pin 19): Positive Supply of the SMBus VID Programmer. 2.7V ≤ VCC ≤ 5.5V. May be connected to the INTVCC pin. Bypass this pin to ground with a 0.1µF ceramic capacitor if using an external supply. EXTVCC (Pin 20): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC and shuts down the internal regulator so that controller and gate drive power is drawn from EXTVCC. Do not exceed 7V at this pin and ensure that EXTVCC < VIN. VIN (Pin 21): Main Input Supply. Decouple this pin to PGND with an RC filter (1Ω, 0.1µF). INTVCC (Pin 22): Internal 5V Regulator Output. The driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7µF low ESR tantalum or other low ESR capacitor. The internal 5V regulator is shut down when VRUN/SS <1.5V. SENSE + (Pin 25): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW pin unless using a sense resistor (see Applications Information). SW (Pin 26): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below ground up to VIN. TG (Pin 27): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. BOOST (Pin 28): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. TEST CIRCUIT SMBus VID Programmer Test Circuit 5V S1 10k VCC VCC SCL SCL SDA SDA SEL SEL CPUON OR PGTMR S2 0.8V VRON VRON GND FB VOSENSE 0.1µF 100pF + – 19098 TC 19098f 10 LTC1909-8 W FU CTIO AL DIAGRA U U RON VIN 2 VON 8 ION PGTMR* 14 SMBON* 0.7V 2.4V DCON* 5 FCB 21 VIN 20 EXTVCC + 4.7V 50µs TIMER* CIN 1µA + – 0.8V REF 1 0.8V + – F OST tON = 5V REG 28 VVON (10pF) IION R S Q FCNT SW 26 SENSE + SWITCH LOGIC IREV L1 DB 25 – – M1 27 + ICMP CB TG ON 20k + BOOST COUT VOSENSE* 22 SHDN 1.4V 16 CVCC BG OV M2 23 VRNG RFB1* PGND 4 × VOUT + INTVCC 24 PGOOD 0.7V VFB FB* 9 17 SGND GND* 7 18 3 3.3µA RFB2* VCC* POR* 1 240k + 1V Q2 Q4 + – – Q3 Q1 10:5 MUX* SCL* OV – ×4 SS + RUN SHDN 1.2µA DCON* * * + – 6 ITH SMBus INTERFACE* SMBON* RC CC1 0.6V CSS 1 RUN/SS SDA* 11 ON/OFF STATE MACHINE* 6V – + 0.6V 0.8V 0.84V * EA 12 REGISTER 1* – 0.8V 1.3V REGISTER 0* + Q5 + – 10 UV Q6 ITHB SEL* 19 0.76V VCC* 15 CPUON* + – *PART OF THE SMBus VID PROGRAMMER * VRON* 13 1.3V 19098 FD 19098f 11 S 1 1 1 1 0 4 5 6 SLAVE ADDRESS 0 3 2 0 1 7 1 8 X X X X VID0 VID1 VID3 VID2 R/W R/W X X X 9 DATA HIGH X X X DCON VID2 VID4 P X X X X X 1 1 1 0 0 0 1 0 0 0 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SLAVE COMMAND CODE DATA LOW DATA HIGH ADDRESS S SMBus READ WORD PROTOCOL, WITH SMBus ADDRESS = 1110001B, COMMAND BYTE = 010XXXXB, DATA LOW = 01001000B, DATA HIGH = 01011000B X VID4 NOTE 1: S = START CONDITION, P = STOP CONDITION NOTE 2: C7, C6, C5 = 001 FOR SETUP, 010 FOR READ-BACK, 000 FOR ON AND 011 FOR OFF SDA SCL 0 C7 C7 0 C6 C6 0 C5 C5 1 ACK ACK 1 VID4 ACK 1 ACK R/W SDA VID4 DATA LOW VID1 VID2 COMMAND CODE VID3 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VID0 VID1 9 VID2 VID3 8 DCON 7 VID0 4 5 6 SLAVE ADDRESS ACK 3 ACK 2 VID3 1 VID1 ACK ACK P VID0 S 19098 TD01 ACK SCL TI I G DIAGRA S UW W 12 SMBus WRITE WORD PROTOCOL, WITH SMBus ADDRESS = 1110001B, COMMAND BYTE = 001XXXXB, DATA LOW = 01001XXXB, DATA HIGH = 01011XXXB Operating Sequence LTC1909-8 19098f LTC1909-8 W UW TI I G DIAGRA S Timing for SMBus Interface t BUF SDA t HD:STA t HD:STA tf tr SCL t LOW STOP t HIGH START t SU:STO t SU:STA t HD:DAT t SU:DAT 19098 TD02 START STOP VRON, SEL, CPUON and PGTMR Timing P P SCL SDA 2nd ON PROTOCOL STOP SMBON 1.3V DCON 1.3V SEL 1.3V 2nd OFF PROTOCOL tPH CPU_ON tSPL tPL 1.3V tPGL PGTMR tVL tPGL tPPL tVH 0.7V tVPL tPGL VRON VOSENSE VMAX (VREF = 0.8V) VMIN 0V tSSL 10% tSSH 90% 0V NOTE: TIMING RELATIVE TO THE STOP BIT (P) IS MEASURED FROM THE RISING EDGE OF SDA SEE TABLE 1 FOR VMIN AND VMAX SENSE VOLTAGES 19098 TD03 19098f 13 LTC1909-8 U OPERATIO (Refer to Functional Diagram) The LTC1909-8 consists of two independent sections: a current mode controller for the DC/DC step-down converter and a SMBus VID voltage programmer. It simplifies the design of SMBus controlled power supplies. Current Mode Controller In normal operation, the top MOSFET of the current mode controller is turned on for a fixed interval determined by a one-shot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the PGND and SENSE + pins using either the bottom MOSFET on-resistance or a separate sense resistor. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal VFB from the output voltage with an internal 0.8V reference. The feedback voltage is derived from the output voltage by a resistive divider in the SMBus VID programmer. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. At low load currents, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV which then shuts off M2, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled by comparator F when the FCB pin is brought below 0.8V, forcing continuous synchronous operation. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±7.5% window around the regulation point. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down by clamp Q3 to a 1V level set by Q4 and Q6. This reduces the inductor valley current level to one sixth of its maximum value as VFB approaches 0V. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Releasing the pin allows an internal 1.2µA current source to charge up an external soft-start capacitor CSS. When this voltage reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately 0.6V below the RUN/SS voltage. As CSS continues to charge, the soft-start current limit is removed. Shorting the RUN/SS pin to the CPUON pin of the SMBus VID programmer puts the regulator under software control. The open-drain CPUON pin does not interfere with the soft-start cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode DB when the top MOSFET is turned off. When the EXTVCC pin is grounded and VRUN/SS >1.5V, an internal 5V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC rises above 4.7V, the internal regulator is turned off, and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source connected to EXTVCC, such as an external 5V supply or a secondary output from the converter, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive. If the input voltage is low and INTVCC drops below 3.5V, undervoltage lockout circuitry prevents the power switches from turning on. SMBus VID Voltage Programmer The SMBus interface is used to program the divider (to set the output voltage of the DC/DC converter) and to shut down the current mode controller or allow it to soft-start. 19098f 14 LTC1909-8 U OPERATIO (Refer to Functional Diagram) It uses two pins, SCL and SDA to communicate with a master device through the Read Word and Write Word protocols. The VIL and VIH logic threshold voltages of the SDA and SCL pins are 0.8V and 2.1V respectively, which comply with Rev 1.1 version of the Intel System Management Bus Specifications. Both pins require a resistor or active pull-up (see the LTC1694 data sheet) to VCC. Data is clocked out of the SDA pin at the falling edge and latched in at the rising edge of the SCL clock signal. The slave address of the interface for both Read and Write protocols is fixed at E2H. There are three types of Write Word protocols: Setup, On and Off and one Read Word protocol called Read-Back. The Setup Write Word protocol is used to set up two internal 5-bit registers (Register 0 and Register 1) with alternate resistor divider DAC settings. The On and Off Write Word protocols do not modify register contents but are used to shutdown the converter or to allow it to softstart. The Read Word protocol is used to verify the contents of the registers as well as to check whether the converter is operating or in shutdown from a status bit (DCON). Table 3 in the Applications Information section shows the data bits that identify each protocol as Setup, On, Off or Read-Back. Controller Control The VID programmer provides the VRON and CPUON pins for the purpose of shutting down or allowing the converter to soft-start. CPUON is an open-drain, N-channel output pin that is normally tied to the RUN/SS pin of the controller along with its soft-start capacitor. If the N-channel is turned off, the pin enters a high impedance state and the capacitor is allowed to charge up and soft-start the converter. When shutting down the converter, the N-channel FET at the CPUON pin will typically discharge a 0.1µF soft-start capacitor from 3V to 0.35V in 21µs with VCC = 2.7V. On power-up, the power-on reset (POR) circuit in the SMBus VID programmer turns on the N-channel to shut down the converter. The CPUON pin can also be controlled to clear overcurrent faults in the switching regulator (see SoftStart and Latchoff with the RUN/SS Pin section). The CPUON pin is under the control of an internal On/Off state machine that is accessed using the SMBus On/Off Write Word protocols and the VRON pin. The VRON pin has a trip point of 1.3V with ±50mV of hysteresis. It is TTL compatible and has a 2.5µA pull-up to VCC. Pulling VRON low will force CPUON low immediately, regardless of the On/Off state machine. Pulling VRON high or allowing it to float high hands control to the On/Off state machine. Table␣ 1 summarizes the function of the control pins. The SMBON control bit is explained in the next section. Table 1. DC/DC Converter Control Pins VRON SMBON DCON PGTMR CPUON 0 X 1 0 0 1 0 1 0 0 1 ↑ ↓ 0 for 50µs (Note 1) Z (Note 2) ↑ 1 ↓ 0 for 50µs (Note 1) Z (Note 2) Note 1: Also triggered by SEL pin toggling. Note 2: Z = High Impedance The LTC1909-8 provides safeguards against incorrect divider codes and the unintentional turn-on or turn-off of the DC/DC converter. Incorrect codes due to bus conflicts during Setup protocols can cause damage to circuits powered by the DC/DC converter. The safeguards built into the LTC1909-8 include Read-Back, repeated On and Off protocols, ignoring On protocols if the registers have not been set up (since power-up), locking out registers while the DC/DC converters are operating and latching in VID codes only in Setup protocols. After power-up, the microprocessor must set up the registers before the LTC1909-8 recognizes On protocols. This requirement ensures that the correct DC/DC converter output is programmed before the converters are turned on. After setup, Read-Back allows the contents of Registers 0 and 1 to be verified in case the VID codes were corrupted by noise or bus conflicts. In order to turn on the DC/DC converter, two On protocols must be sent to slave address E2H without any other (E2H) protocols in between. Protocols to other slave addresses are still allowed and are ignored. Similarly, two Off protocols must be sent to slave address E2H to turn the converters off. The On and Off protocols are monitored by an internal state machine. The output of the state machine, SMBON, is high after two On commands and low after two Off commands. Repeated On and Off protocols reduce the chances of bus conflicts and noise turning the converter 19098f 15 LTC1909-8 U OPERATIO (Refer to Functional Diagram) on or off accidentally. In both On and Off protocols, the LTC1909-8 does not latch in the Data Low and Data High bytes. This protects the settings that have already been loaded into the registers and verified by read-back. Once the converter is turned on (both SMBON and VRON are high) the contents of Registers 0 and 1 are protected and can only be altered with Setup protocols if VRON is pulled low or two Off protocols are sent to the LTC1909-8 (to force SMBON low). During Read-Back, the microprocessor can check the On or Off state of the controller by testing the DCON status bit that follows each 5-bit code. This bit is low only when both SMBON and VRON are high. Table 2. DC/DC Converter Output Voltage VID4 VID3 VID2 VID1 VID0 OUTPUT VOLTAGE 0 0 0 0 0 2.05V 0 0 0 0 1 2.00V 0 0 0 1 0 1.95V 0 0 0 1 1 1.90V 0 0 1 0 0 1.85V 0 0 1 0 1 1.80V 0 0 1 1 0 1.75V 0 0 1 1 1 1.70V 0 1 0 0 0 1.65V 0 1 0 0 1 1.60V Resistor Divider 0 1 0 1 0 1.55V The resistor divider settings comply with the Intel Desktop VRM8.4 VID Specifications. The divider consists of a fixed 20k (typical) resistor, RFB1, connected between the VOSENSE and FB pins and a variable resistor, RFB2, from FB to GND. The FB pin is connected to the VFB pin of the step-down controller to set the output voltage of the converter. Each resistor has a tolerance of ±30% but the divider ratio is accurate to ±0.35%. The error budget for the DC/DC converter output voltage must include the ±0.35% ratio tolerance and the ±1% tolerance in the 0.8V reference. The output of the DC/DC converter is given by: 0 1 0 1 1 1.50V 0 1 1 0 0 1.45V 0 1 1 0 1 1.40V 0 1 1 1 0 1.35V 0 1 1 1 1 1.30V 1 0 0 0 0 3.50V 1 0 0 0 1 3.40V 1 0 0 1 0 3.30V 1 0 0 1 1 3.20V 1 0 1 0 0 3.10V 1 0 1 0 1 3.00V 1 0 1 1 0 2.90V 1 0 1 1 1 2.80V 1 1 0 0 0 2.70V 1 1 0 0 1 2.60V 1 1 0 1 0 2.50V 1 1 0 1 1 2.40V 1 1 1 0 0 2.30V 1 1 1 0 1 2.20V 1 1 1 1 0 2.10V 1 1 1 1 1 2.00V VOUT = VREF • (RFB2 + RFB1)/RFB2 where VREF = 0.8V is the internal reference voltage of the converter. Table 2 shows the 32 possible converter output voltages. The microprocessor controls the SEL pin to select the contents of one of the registers as the active divider setting. The SEL pin has a trip point of 1.3V with ±50mV of hysteresis and is TTL compatible. It controls an internal 10:5 digital multiplexer and selects the contents of register 0 when pulled low and register 1 when pulled high. When SEL is toggled, and the new converter output is lower or greater by 7.5%, the overvoltage and undervoltage comparators of the controller may trip causing the PGOOD pin of the controller to go low. This condition will recover automatically as the converter charges up the output or allows the output to drop to the new voltage setting. Power Good Timer The PGTMR or “Power Good Timer” pin is also an opendrain, N-channel output. It pulls low if the DC/DC converter is in shutdown or on power-up. When the converter is turned on, an internal timer keeps PGTMR low for 50µs (typical) which allows time for the converters to enter regulation. Toggling the SEL pin while the converter is turned on also causes the PGTMR pin to pull low for 50µs. The PGTMR pin may be used to force continuous operation in the DC/DC converter. If the SEL pin is toggled to select a lower output voltage, if may take an unacceptably 19098f 16 LTC1909-8 U OPERATIO (Refer to Functional Diagram) long time for the output of the DC/DC converter to decrease to the new voltage under light load conditions. To reduce this time needed, the PGTMR pin can be connected to the FCB (force continuous bar) pin of the converter. When the SEL pin is toggled to select a new code, the FCB pin is forced low for 50µs. This forces the DC/DC converter out of Burst ModeTM operation and into continuous mode. The PGTMR pin may be tied to the same pull-up resistor as the PGOOD pin. SMBus Controller Supply If the EXTVCC pin is tied to ground, the VCC pin of the SMBus controller should be tied to an external 5V supply. It should not be tied to the INTVCC pin because the internal 5V regulator at the INTVCC pin is shut down while VRUN/SS is below 1.5V and the SMBus controller will not be powered up. If the EXTVCC pin is tied to an external 5V supply, the VCC pin can be tied to the same supply or to the INTVCC pin since the INTVCC pin is connected to the EXTVCC pin by an internal switch when VEXTVCC >4.7V. The EXTVCC and VCC voltages should be kept below the absolute maximum rating of 7V. Power-Up Reset On power-up, the internal POR circuit generates a low reset pulse, which stays low until VCC rises above approximately 2.2V. The reset pulse forces the SMBus interface into an idle state in which it listens for a start bit. At the same time the outputs of both Register 0 and Register 1 are set to 11111B. The DCON bit is pulled high so that the CPUON pin is pulled low to shut down the DC/DC converter. PGTMR is also pulled low as the converter is shut down and therefore not in regulation. Burst Mode is a trademark of Linear Technology Corporation. U W U U APPLICATIO S I FOR ATIO The basic LTC1909-8 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC1909-8 uses either an external sense resistor or the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the PGND and SENSE + pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately (0.133) • VRNG. The current mode control loop will not allow the inductor current valleys to exceed (0.133) • VRNG/RSENSE. In practice, one should allow some margin for variations in the LTC1909-8 and external component values and a good guide for selecting the sense resistance is: RSENSE = VRNG 10 • IOUT(MAX) An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.33 times this nominal value. Connecting the SENSE + Pin The LTC1909-8 can be used with or without a sense resistor. When using a sense resistor, it is placed between the source of the bottom MOSFET M2 and ground. Connect the SENSE + pin to the source of the bottom MOSFET so that the resistor appears between the SENSE + and PGND pins. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom MOSFET as the current sense element by simply connecting the SENSE + pin to the switch node SW at the drain of the bottom MOSFET. This improves efficiency, but 19098f 17 LTC1909-8 U W U U APPLICATIO S I FOR ATIO one must carefully choose the MOSFET on-resistance as discussed below. Power MOSFET Selection The LTC1909-8 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC1909-8 applications. If the input voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be considered. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX) = RSENSE ρT VOUT VIN V –V = IN OUT VIN DTOP = DBOT The resulting power dissipation in the MOSFETs at maximum output current are: PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX) + k VIN2 IOUT(MAX) CRSS f PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX) Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The constant K = 1.7A–1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. Operating Frequency The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C as shown in Figure 2. For a maximum temperature of 100°C, using a value ρT = 1.3 is reasonable. 2.0 ρT NORMALIZED ON-RESISTANCE The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC1909-8 is operating in continuous mode, the duty cycles for the MOSFETs are: The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC1909-8 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is set by the current into the ION pin according to: 1.5 1.0 tON = VVON (10pF) IION 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: 19098 F02 Figure 2. RDS(ON) vs. Temperature 19098f 18 LTC1909-8 U W U U APPLICATIO S I FOR ATIO f= VOUT VVON RON(10pF) Inductor Selection [Hz] To hold frequency constant during output voltage changes, tie the VON pin to VOUT. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the one-shot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. Because the voltage at the ION pin is about 0.7V, the current into this pin is not exactly inversely proportional to VIN, especially in applications with lower input voltages. To correct for this error, an additional resistor RON2 connected from the ION pin to the 5V INTVCC supply will further stabilize the frequency. RON2 = 5V RON 0.7 V Changes in the load current magnitude will also cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 25% of the voltage change at the ITH pin to the VON pin as shown in Figure 3a. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 3b. Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V V ∆IL = OUT 1 − OUT VIN fL Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: V V L = OUT 1− OUT f ∆IL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mµ® cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Kool Mµ is a registered trademark of Magnetics, Inc. RVON1 30k VOUT RVON1 3k CVON 0.01µF RVON2 100k VON LTC1909-8 RC ITH VOUT 10k INTVCC RVON2 CVON 0.01µF 10k VON LTC1909-8 RC ITH 2N5087 CC CC (3a) (3b) 19098 F03 Figure 3. Correcting Frequency Shift with Load Current Changes 19098f 19 LTC1909-8 U W U U APPLICATIO S I FOR ATIO Schottky Diode D1 Selection The Schottky diode D1 shown in Figure 1 conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS ≅ IOUT(MAX) VOUT VIN VIN –1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX) / 2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ∆VOUT is approximately bounded by: 1 ∆VOUT ≤ ∆IL ESR + 8 fCOUT Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. To dampen input voltage transients, add a small 5µF to 50µF aluminum electrolytic capacitor with an ESR in the range of 0.5Ω to 2Ω. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications a 0.1µF to 0.47µF X5R or X7R dielectric capacitor is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.8V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in VIN. Tying the FCB pin below the 19098f 20 LTC1909-8 U W U U APPLICATIO S I FOR ATIO 0.8V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. In addition to providing a logic input to force continuous operation, the FCB pin provides a means to maintain a flyback winding output when the primary is operating in discontinuous mode. The secondary output VSEC is normally set as shown in Figure 4 by the turns ratio N of the transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then VSEC will droop. An external resistor divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN) below which continuous operation is forced until VSEC has risen above its minimum. R4 VSEC(MIN) = 0.8 V 1 + R3 Fault Conditions: Current Limit and Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC1909-8, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX) 1 + ∆IL RDS(ON) ρT 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A VIN + CIN VIN OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V TG LTC1909-8 SW EXTVCC R4 FCB R3 SENSE + VSEC 1N4148 • + T1 1:N • + CSEC 1µF VOUT COUT BG SGND PGND 19098 F04 Figure 4. Secondary Output Loop and EXTVCC Connection reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. To further limit current in the event of a short circuit to ground, the LTC1909-8 includes foldback current limiting. If the output falls by more than 25%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. Minimum Off-time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC1909-8 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 300ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON INTVCC Regulator An internal P-channel low dropout regulator produces the 5V supply that powers the drivers and internal circuitry within the LTC1909-8. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7µF tantalum or other low ESR capacitor. Good bypassing is necessary to supply the high transient 19098f 21 LTC1909-8 U W U U APPLICATIO S I FOR ATIO currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of operation may cause the LTC1909-8 to exceed its maximum junction temperature rating or RMS current rating. Most of the supply current drives the MOSFET gates unless an external EXTVCC source is used. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics. For example, the LTC1909-8 is limited to less than 14mA from a 30V supply: TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C For larger currents, consider using an external supply with the EXTVCC pin. EXTVCC Connection The EXTVCC pin can be used to provide MOSFET gate drive and control power from the output or another external source during normal operation. Whenever the EXTVCC pin is above 4.7V the internal 5V regulator is shut off and an internal 50mA P-channel switch connects the EXTVCC pin to INTVCC. INTVCC power is supplied from EXTVCC until this pin drops below 4.5V. Do not apply more than 7V to the EXTVCC pin and ensure that EXTVCC ≤ VIN. The following list summarizes the possible connections for EXTVCC: 1. EXTVCC grounded. INTVCC is always powered from the internal 5V regulator. 2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive requirements (typically 5V) can improve overall efficiency. 3. EXTVCC connected to an output derived boost network. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. The system will start-up using the internal linear regulator until the boosted output supply is available. External Gate Drive Buffers The LTC1909-8 drivers are adequate for driving up to about 30nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. Alternately, the external buffer circuit shown in Figure 5 can be used. Note that the bipolar devices reduce the signal swing at the MOSFET gate and benefit from an increased EXTVCC voltage of about 6V. INTVCC BOOST Q3 FMMT619 Q1 FMMT619 10Ω 10Ω GATE OF M1 TG GATE OF M2 BG Q4 FMMT720 Q2 FMMT720 PGND SW 19098 F05 Figure 5. Optional External Gate Driver Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC1909-8 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 0.8V puts the LTC1909-8 into a low quiescent current shutdown (IQ < 30µA). Releasing the pin allows an internal 1.2µA current source to charge up the external timing capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about: tDELAY = ( ) 1.5V CSS = 1.3s/µF CSS 1.2µA When the voltage on RUN/SS reaches 1.5V, the LTC1909-8 begins operating with a clamp on ITH of approximately 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH is raised until its full 2.4V range is available. This takes an additional 1.3s/µF, during which the load current is folded back until the output reaches 75% of its final value. The pin can be driven from logic (Figures 6a or 6b) or from the CPUON pin (Figures 6c and 6d). Diode D1 reduces the start delay while allowing CSS to charge up slowly for the softstart function. After the controller has been started and given adequate time to charge up the output capacitor, CSS is used as a short-circuit timer. After the RUN/SS pin charges above 4V, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. A 1.8µA current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 3.5V, then the 19098f 22 LTC1909-8 U W U U APPLICATIO S I FOR ATIO INTVCC RSS* VIN 3.3V OR 5V RUN/SS RSS* D1 D2* RUN/SS CSS CSS shown in Figure 6a or 6c is simple, but slightly increases shutdown current. Connecting a resistor to INTVCC as shown in Figure 6b and 6d eliminates the additional shutdown current, but requires a diode to isolate CSS. Any pull-up network must be able to maintain RUN/SS above the 4.2V maximum latchoff threshold and overcome the 4µA maximum discharge current. *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (6a) (6b) Efficiency Considerations INTVCC VIN RSS* RUN/SS RSS* CPUON D2* RUN/SS CPUON CSS CSS 19098 F06 *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (6c) (6d) Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. If the RUN/SS pin is tied to the CPUON pin, this is achieved by pulling the VRON pin low or by sending two Off protocols to the SMBus VID programmer to force the CPUON pin low. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 – 4 [F/V s]) Generally 0.1µF is more than sufficient. Overcurrent latchoff operation is not always needed or desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff operation can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current greater than 5µA to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to VIN as The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC1909-8 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f 3. INTVCC current. This is the sum of the MOSFET driver and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high efficiency source, such as an output derived boost network or alternate supply if available. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and 19098f 23 LTC1909-8 U W U U APPLICATIO S I FOR ATIO sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 7 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. Design Example As a design example, take a supply with the following specifications: VIN = 7V to 24V (15V nominal), VOUT = 1.5V ±100mV, IOUT(MAX) = 15A, f = 300kHz. First, calculate the timing resistor with VON = VOUT: RON = 1 (300kHz)(10pF) = 330k and choose the inductor for about 40% ripple current at the maximum VIN: L= 1.5V 1.5V 1− = 0.8µH (300kHz)(0.4)(15A) 24V Selecting a standard value of 1µH results in a maximum ripple current of: ∆IL = 1.5V 1.5V 1– = 4.7 A (300kHz)(1µH) 24V Next, choose the synchronous MOSFET switch. Because of the narrow duty cycle and large current, a single SO-8 MOSFET will have difficulty dissipating the power lost in the switch. Choosing two IRF7811A (RDS(ON) = 0.013Ω, CRSS = 60pF, θJA = 40°C/W) yields a nominal sense voltage of: VSNS(NOM) = (15A)(0.5)(1.3)(0.012Ω) = 117mV Tying VRNG to INTVCC will set the current sense voltage range for a nominal value of 140mV with current limit occurring at 186mV. To check if the current limit is acceptable, assume a junction temperature of about 100°C above a 50°C ambient with ρ150°C = 1.6: ILIMIT ≥ (0.5)(1.6)(0.012Ω) ( ) 186mV + 1 4.7 A = 18 A 2 and double check the assumed TJ in the MOSFET: 2 PBOT 24V – 1.5V 21.7 A = (1.6 )(0.012 Ω) = 2.12 W 24V 2 TJ = 50°C + (2.12W)(50°C/W) = 156°C Because the top MOSFET is on for such a short time, a single IRF7811A will be sufficient. Checking its power dissipation at current limit with ρ90°C = 1.3: ) (1.3)(0.012Ω) + 2 (1.7)(24V) (21.7A)(60pF)(300kHz) PBOT = ( 1.5V 21.7 A 24V 2 = 0.46W + 0.38W = 0.84W TJ = 50°C + (0.84W)(50°C/W) = 92°C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 6A at temperature. The output capacitors are chosen for a low ESR of 0.005Ω to minimize output voltage changes due to 19098f 24 LTC1909-8 U W U U APPLICATIO S I FOR ATIO inductor ripple current and load steps. The ripple voltage will be only: in applications where rapid load steps are the main cause of error in the output voltage. By positioning the output voltage above the regulation point at zero load, and below the regulation point at full load, one can use more of the error budget for the load step. This allows one to reduce the number of output capacitors by relaxing the ESR requirement. ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (4.7A) (0.005Ω) = 24mV However, a 0A to 15A load step will cause an output change of up to: ∆VOUT(STEP) = ∆ILOAD (ESR) = (15A) (0.005Ω) = 75mV In the design example, Figure 7, five 0.025Ω capacitors are required in parallel to keep the output voltage within tolerance. Using active voltage positioning, the same specification can be met with only three capacitors. In this case, the load step will cause an output voltage change of: The complete circuit is shown in Figure 7. Active Voltage Positioning Active voltage positioning (also termed load “deregulation” or droop) describes a technique where the output voltage varies with load in a controlled manner. It is useful 1 ∆VOUT(STEP) = (15A ) (0.025Ω) = 125mV 3 CSS 0.1µF 1 2 RPG 100k 3 4 5 CC1 470pF RC 20k 6 CC2 100pF 7 8 CFB 100pF 9 10 SEL 11 SDA 12 SCL 13 VRON RON 330k 14 RUN/SS BOOST VON TG PGOOD SW VRNG FCB SENSE+ PGND ITH BG LTC1909-8 SGND ION INTVCC VIN VFB EXTVCC SEL VCC SDA GND SCL FB VRON PGTMR VOSENSE CPUON 28 CB 0.33µF 27 VIN 7V TO 24V CIN 22µF 50V ×3 DB CMDSH-3 M1 IRF7811A L1 1µH 26 VOUT 1.5V 15A 25 M2 IRF7811A ×2 24 D1 UPS840 + 23 22 CVCC 4.7µF 21 RF 1Ω 20 CF 0.1µF COUT 270µF 2V ×5 5V 19 18 17 16 C2 6.8nF 19098 F07 15 CIN: UNITED CHEMICON THCR70EIH226ZT COUT: CORNELL DUBILIER ESRE271M02B L1: SUMIDA CEP125-IR0MC-H Figure 7. CPU Core Voltage Regulator 1.5V, 15A at 300kHz 19098f 25 LTC1909-8 U W U U APPLICATIO S I FOR ATIO By positioning the output voltage 60mV above the regulation point at no load, it will only drop 65mV below the regulation point after the load step, well within the ±100mV tolerance. Implementing active voltage positioning requires setting a precise gain between the sensed current and the output voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active voltage positioning. In order to minimize power lost in this resistor, a low value is chosen of 0.003Ω. The nominal sense voltage will now be: of these resistors must equal RVP and their ratio determines nominal value of the ITH pin voltage when the error amplifier input is zero. To center the load line around the regulation point, the ITH pin voltage must be set to correspond to half the output current. The relation between ITH voltage and the output current is: 12V 1 ITH(NOM) = RSENSE IOUT – ∆IL + 0.8 V VRNG 2 1 12V = (0.003Ω) 7.5A – 4.7 A + 0.8 V 0.5V 2 = 1.17 V VSNS(NOM) = (0.003Ω)(15A) = 45mV To maintain a reasonable current limit, the voltage on the VRNG pin is reduced to its minimum value of 0.5V, corresponding to a 50mV nominal sense voltage. Next, the gain of the LTC1909-8 error amplifier must be determined. The change in ITH voltage for a corresponding change in the output current is: 12V ∆ITH = RSENSE ∆IOUT VRNG = (24)(0.003Ω)(15A ) = 1.08 V The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback divider. The LTC1909-8 error amplifier has a transconductance gm that is constant over both temperature and a wide ± 40mV input range. Thus, by connecting a load resistance RVP to the ITH pin, the error amplifier gain can be precisely set for accurate active voltage positioning. 0.8 V ∆ITH = gm RVP ∆VOUT VOUT Solving for this resistance value: RVP = = VOUT ∆ITH (0.8 V) gm ∆VOUT (1.5V)(1.08 V) = 9.53k (0.8 V)(1.7mS)(125mV) The gain setting resistance RVP is implemented with two resistors, RVP1 connected from ITH to ground and RVP2 connected from ITH to INTVCC. The parallel combination Solving for the required values of the resistors: RVP1 = 5V 5V 9.53k RVP = 5V – ITH(NOM) 5V – 1.17 V = 12.44k 5V 5V 9.53k = 40.73k RVP2 = RVP = 1.17 V ITH(NOM) The modified circuit is shown in Figure 8. Figures 9 and 10 show the transient response without and with active voltage positioning. Both circuits easily stay within ±100mV of the 1.5V output. However, the circuit with active voltage positioning accomplishes this with only three output capacitors rather than five. Refer to Design Solutions 10 for additional information about active voltage positioning. SMBus Protocols The Write Word and Read Word protocols (Figure 11) share three common features. First, the 7-bit slave address for both protocols is internally hardwired to 1110 001B = E2H. A single R/W bit follows the slave address. This bit is low for data transfer from the microprocessor to the LTC1909-8 and high for transfers in the opposite direction. Second, the LTC1909-8 decodes only the three most significant bits of the 8-bit command code. Table 3 shows the four valid combinations. All other combinations are ignored. 19098f 26 LTC1909-8 U W U U APPLICATIO S I FOR ATIO CSS 0.1µF 1 2 RRNG1 4.99k RRNG2 45.3k RPG 100k 3 4 5 RVP2 40.2k 6 RVP1 12.4k CC1 180pF 7 8 CFB 100pF 9 10 SEL 11 SDA 12 SCL 13 VRON RON 330k 14 RUN/SS BOOST VON TG PGOOD SW VRNG FCB SENSE+ PGND ITH BG LTC1909-8 SGND INTVCC ION VIN VFB EXTVCC SEL VCC SDA GND SCL FB VRON PGTMR VOSENSE CPUON 28 CB 0.33µF 27 VIN 7V TO 24V CIN 22µF 50V ×3 DB CMDSH-3 M1 IRF7811A L1 1µH 26 VOUT 1.5V 15A 25 M2 IRF7811A ×2 24 D1 B540 23 22 CVCC 4.7µF 21 RF 1Ω 20 CF 0.1µF + COUT 270µF 2V ×5 RSENSE 0.003Ω 5V 19 18 17 16 19098 F08 15 CIN: UNITED CHEMICON THCR70EIH226ZT COUT: CORNELL DUBILIER ESRE271M02B L1: SUMIDA CEP125-IR0MC-H Figure 8. CPU Core Voltage Regulator with Active Voltage Positioning 1.5V/15A at 300kHz VOUT 100mV/DIV 1.5V VOUT 100mV/DIV 1.5V IL 10A/DIV IL 10A/DIV COUT = 5 × 270µF VIN = 15V FIGURE 7 CIRCUIT 20µs/DIV 3711 F09 Figure 9. Normal Transient Response COUT = 3 × 270µF VIN = 15V FIGURE 8 CIRCUIT 20µs/DIV 3711 F10 Figure 10. Transient Response with Active Voltage Positioning 19098f 27 LTC1909-8 U W U U APPLICATIO S I FOR ATIO SLAVE ADDRESS ON COMMAND DATA LOW (REGISTER 0) S 1110001 R/W A 000XXXXX A DATA HIGH (REGISTER 1) DON’T CARE A DON’T CARE A P UPDATE DCON SLAVE ADDRESS OFF COMMAND DATA LOW (REGISTER 0) S 1110001 R/W A 011XXXXX A DATA HIGH (REGISTER 1) DON’T CARE A DON’T CARE A P UPDATE DCON SLAVE ADDRESS SETUP COMMAND DATA LOW (REGISTER 0) S 1110001 R/W A 001XXXXX A VID4 VID3 VID2 VID1 VID0 DATA HIGH (REGISTER 1) X X X A VID4 VID3 VID2 VID1 VID0 COMMAND LATCHED SLAVE ADDRESS XXX DATA LOW LATCHED READ-BACK COMMAND DATA HIGH LATCHED DATA LOW (REGISTER 0) S 1110001 R/W A 010XXXXX A S 1110010 RD A VID4 VID3 VID2 VID1 VID0 DCON COMMAND LATCHED DATA LOW LOADED A P UPDATE DCON DATA HIGH (REGISTER 1) 0 0 A VID4 VID3 VID2 VID1 VID0 DCON DATA HIGH LOADED 00 A P 19098 F11 STOP (IGNORED) Figure 11. Write Word and Read Word Protocols Third, the Data Low and Data High bytes correspond to Registers 0 and 1 respectively. In Write Word protocol with C7 = C6 = 0, C5 = 1, the five most significant bits (VID0VID4) of these bytes specify a resistor divider setting. Table 3. LTC1909-8 Command Bits C7 C6 C5 COMMAND PROTOCOL 0 0 0 On Write Word 0 1 1 Off Write Word 0 0 1 Setup Write Word 0 1 0 Read-Back Read Word Write Word Protocol Each Write Word protocol (Figure 11) begins with a start bit (S) and ends with a stop bit (P). As shown in the Timing Diagram the start and stop bits are defined as high-to-low and low-to-high SDA transitions respectively, while SCL is high. In between the start and stop bits, the microprocessor transmits four bytes to the LTC1909-8. These are the address byte, an 8-bit command code and two data bytes. The LTC1909-8 samples each bit at the rising edges of the SCL clock. When the microprocessor issues a start bit, all the slave devices on the bus, including the LTC1909-8 clock in the address byte, which consists of a 7-bit slave address and the R/W bit (set to 0). If the slave address from the microprocessor does not match the internal hardwired address, the LTC1909-8 returns to an idle state and waits for the next start bit. If the slave address matches, the LTC1909-8 acknowledges by pulling the SDA line low for one clock cycle after the address byte. After detecting the acknowledgment bit (A), the microprocessor transmits the second byte or command code. The command code identifies the type of Write Word protocol as Setup, On or Off (Table 3). The Setup protocol is used to load two resistor divider settings into Register 0 and 1. The On and Off protocols turn the converters on or off in conjunction with the VRON pin. Once all 8 bits of the command code are clocked in, the LTC1909-8 issues a second acknowledgment bit to the microprocessor. After detecting the acknowledgment bit, the microprocessor transmits two data bytes. 19098f 28 LTC1909-8 U W U U APPLICATIO S I FOR ATIO Each data byte is acknowledged in turn for all three Write Word protocols but is only latched into Register 0 or 1 in Setup protocol. This prevents previously loaded settings from accidentally being changed. The first or Data Low byte is loaded into Register 0. The second or Data High byte is loaded into Register 1. After issuing the final acknowledgment bit, the SMBus interface returns to an idle state and waits for the next start bit. Read Word Protocol The Read Word protocol starts off like Write Word protocol but after the command code acknowledgment, the microprocessor issues a second start bit (called a repeated start). This is followed by the slave address but with the R/W bit set high to indicate that data direction is now from the LTC1909-8 to the microprocessor. The LTC1909-8 then acknowledges the slave address and clocks the contents of Register 0 (Data Low byte) to the microprocessor. The Data Low byte is acknowledged by the microprocessor. On detecting the acknowledgment bit, the LTC1909-8 clocks out the contents of Register 1 (Data High byte). As defined in the SMBus specifications, the microprocessor does not acknowledge the last data byte. The LTC1909-8 enters an idle state to wait for the next start bit after clocking out the Data High byte. The five most significant bits (VID0-VID4) of the Data Low and High bytes are the resistor divider settings previously loaded using the Setup protocol. The next bit below the VID0VID4 bits is the status of the DCON signal. If this bit is low (high), the DC/DC converters are switched on (off). The two unused, least significant bits of the Data Low and Data High bytes are clocked out as zeros to eliminate the need to mask out these bits in software. Operating Sequence A typical control sequence for the LTC1909-8 is as follows: • On power up, the DCON bit is preset to a high state by the power-on reset (POR) circuit. The CPUON pin is pulled low to shut down the DC/DC converter. PGTMR and PGOOD pull low to indicate that the converters are not in regulation. • Pull VRON low as a precaution. Take SEL high or low to select the divider setting; e.g., one that suits the existing power source (battery or wall-pack) or intended CPU speed. • Use the Setup protocol to load the appropriate divider settings in Registers 0 and 1 and enable the On/Off state machine. • Use the Read-Back protocol to verify the contents of Registers 0 and 1. • Repeat the setup and read-back if the codes are incorrect (due to bus conflicts). • Send two On protocols in succession to clear the DCON bit. • Use the Read-Back protocol to verify that the DCON is low. A high state will indicate that an On command code was corrupted by bus conflicts. • Pull VRON high. Since DCON = 0, the CPUON pin enters a high impedance state, allowing the DC/DC converter to soft-start. PGTMR stays low for 50µs. PGOOD stays low until the regulator output rises above the –7.5% regulation limit. • To shut down the supply, send two Off protocols to set the DCON bit high or pull VRON low if immediate shutdown is required. 19098f 29 LTC1909-8 U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. • The ground layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 12. • Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. • Segregate the signal and power grounds. All smallsignal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. Tie the GND pin directly to SGND. • Place LTC1909-8 chip with Pins 20 to 28 facing the power components. Keep the components connected to Pins 16 to 18 close to LTC1909-8 (noise sensitive components). • Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. • Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. • Use an immediate via to connect the components to ground plane including SGND, GND and PGND of LTC1909-8. Use several bigger vias for power components. • Keep the high dV/dT SW, BOOST and TG nodes away from sensitive small-signal nodes. • Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. • Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and PGND pins. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. • Connect the VOSENSE, FB and GND pins of the resistor divider directly to the output of the DC/DC converter, the VFB pin and the SGND pin of the controller. • Connect the VIN pin decoupling capacitor CF closely to the VIN and PGND pins. 19098f 30 LTC1909-8 U W U U APPLICATIO S I FOR ATIO CB CSS 1 2 3 RUN/SS BOOST VON TG PGOOD SW 28 27 DB 26 + M1 4 VRNG 25 SENSE + D1 CIN VIN M2 5 CC1 RC 6 CC2 FCB PGND LTC1909-8 ITH BG 24 – 23 – CVCC 7 8 SGND INTVCC ION VIN VFB EXTVCC SEL VCC SDA GND SCL FB VOUT COUT 22 + CF RF 21 CFB 9 10 RON 11 12 13 14 VRON PGTMR VOSENSE CPUON 20 19 18 17 16 15 19098 F12 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 12. LTC1909-8 PCB Layout Diagram U PACKAGE DESCRIPTIO G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 9.90 – 10.50* (.390 – .413) 1.25 ±0.12 7.8 – 8.2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 5.3 – 5.7 0.42 ±0.03 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 2.0 (.079) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) 0.05 (.002) G28 SSOP 0802 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 19098f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC1909-8 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1380/LTC1393 Multiplexer with SMBus Interface Single-Ended 8-Channel/Differential 4-Channel Analog MUX LTC1622 550kHz Step-Down Controller 8-Pin MSOP, Synchronizable, Soft-Start; Current Mode LTC1623 SMBus Dual High Side Switch Controller Built-In Charge Pump Drives N-Channel MOSFETs, 8-Lead MSOP Package LTC1625/LTC1775 No RSENSE Current Mode Synchronous Step-Down Controller 97% Efficiency; No Sense Resistor; 16-Pin SSOP LTC1628-SYNC Dual, 2-Phase Synchronous Step-Down Controller Synchronizable 150kHz to 300kHz LTC1694/LTC1694-1 SMBus Accelerator ThinSOTTM, Active Pull-Up Improves Data Transmission and Reliability, Improves Low State Noise LTC1699-80 SMBus VID Programmer Compliant with Intel 5-Bit Mobile Specifications Precision ±0.35% Resistor Divider for Use with 0.8V Referenced Switching Regulators LTC1699-81 SMBus VID Programmer Compliant with Intel Desktop VRM8.4 Specifications Precision ±0.35% Resistor Divider for Use with 0.8V Referenced Switching Regulators LTC1699-82 SMBus VID Programmer Compliant with Intel Desktop VRM9.0 Specifications Precision ±0.35% Resistor Divider for Use with 0.8V Referenced Switching Regulators LTC1709-7 High Efficiency, 2-Phase Synchronous Step-Down Controller Up to 42A Output; 0.925V ≤ VOUT ≤ 2V LTC1709-8 High Efficiency, 2-Phase Synchronous Step-Down Controller Up to 42A Output; VRM 8.4, 1.3V ≤ VOUT ≤ 3.5V LTC1710 SMBus Dual Monolithic High Side Switch Two Integrated 0.4Ω/300mA N-Channel Switches LTC1735 High Efficiency, Synchronous Step-Down Controller Burst Mode Operation; 16-Pin Narrow SSOP; 3.5V ≤ VIN ≤ 36V LTC1759 SMBus Interfaced Smart Battery Charger Constant Current/Constant Voltage Battery Charger, Up to 8A Charge Current, High Efficiency Synchronous Charger LTC1772 ThinSOT Step-Down Controller Current Mode; 550kHz; Very Small Solution Size LTC1778 No RSENSE Synchronous Step-Down Controller No Sense Resistor Required, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9) VIN, GN16 LT®1786F SMBus Programmable CCFL Switching Regulator Precision 100µA Full-Scale DAC, Grounded Lamp or Floating Lamp Configurations LTC1876 2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator 3.5V ≤ VIN ≤ 36V, Power Good Output, 300kHz Operation LTC3701 Dual, Step-Down Controller Current Mode; 550kHz; Small 16-Pin SSOP, VIN < 9.8V LTC3711 5-Bit Adjustable, Wide Operating Range, No RSENSE Step-Down Controller GN24, Mobile VID, 0.925V ≤ VOUT ≤ 2V LTC3714 Intel Compatible, Wide Operating Range, Step-Down Controller with Internal Op Amp G28, 0.6V ≤ VOUT ≤ 1.75V, Programmable Output Offsets, 5-Bit VID ThinSOT is a trademark of Linear Technology Corporation. 19098f 32 Linear Technology Corporation LT/TP 0603 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001