LTC3407A-2 Dual Synchronous 800mA, 2.25MHz Step-Down DC/DC Regulator U FEATURES DESCRIPTIO ■ The LTC®3407A-2 is a dual, constant frequency, synchronous step-down DC/DC converter. Intended for low power applications, it operates from a 2.5V to 5.5V input voltage range and has a constant 2.25MHz switching frequency, enabling the use of tiny, low cost capacitors and inductors 1mm or less in height. Each output voltage is adjustable from 0.6V to 5V. Internal synchronous 0.35Ω, 1A power switches provide high efficiency without the need for external Schottky diodes. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Efficiency: Up to 95% Low Ripple (<35mVPK-PK) Burst Mode Operation; IQ = 40μA 2.25MHz Constant Frequency Operation No Schottky Diodes Required Low RDS(ON) Internal Switches: 0.35Ω Current Mode Operation for Excellent Line and Load Transient Response Short-Circuit Protected Low Dropout Operation: 100% Duty Cycle Ultralow Shutdown Current: IQ <1μA Output Voltages from 5V down to 0.6V Power-On Reset Output Externally Synchronizable Oscillator Optional External Soft-Start Small Thermally Enhanced MSOP and 3mm × 3mm DFN Packages U APPLICATIO S ■ ■ ■ To further maximize battery life, the P-channel MOSFETs are turned on continuously in dropout (100% duty cycle), and both channels draw a total quiescent current of only 40μA. In shutdown, the device draws <1μA. , LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. PDAs/Palmtop PCs Digital Cameras Cellular Phones Wireless and DSL Modems U ■ A user selectable mode input is provided to allow the user to trade-off ripple noise for low power efficiency. Burst Mode® operation provides the highest efficiency at light loads, while Pulse Skip Mode provides the lowest ripple noise at light loads. TYPICAL APPLICATIO Efficiency/Power Loss Curve 1mm High 2.5V/1.8V at 800mA Step-Down Regulators 1 100 VIN = 2.5V TO 5.5V RUN/SS2 VIN RUN/SS1 RESET LTC3407A-2 2.2μH 2.2μH SW2 0.1 70 POR SW1 22pF 22pF VOUT1 = 1.8V AT 800mA 60 0.01 50 40 30 0.001 20 10μF VFB1 VFB2 887k 280k GND VIN = 3.3V Burst Mode OPERATION NO LOAD ON OTHER CHANNEL 10 887k 442k 0 10μF POWER LOSS (W) MODE/SYNC 1.8V 80 100k EFFICIENCY (%) 10μF VOUT2 = 2.5V AT 800mA 2.5V 90 1 10 100 LOAD CURRENT (mA) 0.0001 1000 3407A2 TA02 3407A2 TA01 3407a2f 1 LTC3407A-2 U W W W ABSOLUTE AXI U RATI GS (Note 1) VIN Voltage ..................................................– 0.3V to 6V VFB1, VFB2 Voltages...................................– 0.3V to 1.5V RUN/SS1, RUN/SS2 Voltages ..................... – 0.3V to VIN MODE/SYNC Voltage .................................. – 0.3V to VIN SW1, SW2 Voltages ....................... – 0.3V to VIN + 0.3V POR Voltage ................................................– 0.3V to 6V Operating Temperature Range (Note 2) LTC3407AE-2 ..................................... – 40°C to 85°C LTC3407AI-2 .................................... – 40°C to 125°C Junction Temperature (Note 5) ............................. 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec) LTC3407AEMSE-2 ............................................ 300°C LTC3407AIMSE-2 ............................................. 300°C U U U PI CO FIGURATIO TOP VIEW VFB1 1 RUN/SS1 2 TOP VIEW 10 VFB2 9 RUN/SS2 11 VIN 3 SW1 4 7 SW2 GND 5 6 MODE/SYNC 8 POR DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND VFB1 RUN/SS1 VIN SW1 GND 1 2 3 4 5 11 10 9 8 7 6 VFB2 RUN/SS2 POR SW2 MODE/SYNC MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND U W U ORDER I FOR ATIO LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3407AEDD-2#PBF LTC3407AEDD-2#TRPBF LDDH 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3407AEMSE-2#PBF LTC3407AEMSE-2#TRPBF LTDDJ 10-Lead Plastic MSOP –40°C to 85°C LTC3407AIDD-2#PBF LTC3407AIDD-2#TRPBF LDDH 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3407AIMSE-2#PBF LTC3407AIMSE-2#TRPBF LTDDJ 10-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3407AEDD-2 LTC3407AEDD-2#TR LDDH 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3407AEMSE-2 LTC3407AEMSE-2#TR LTDDJ 10-Lead Plastic MSOP –40°C to 85°C LTC3407AIDD-2 LTC3407AIDD-2#TR LDDH 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3407AIMSE-2 LTC3407AIMSE-2#TR LTDDJ 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3407a2f 2 LTC3407A-2 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2) SYMBOL PARAMETER VIN Operating Voltage Range IFB Feedback Pin Input Current VFB Feedback Voltage (Note 3) CONDITIONS MIN ● TYP 2.5 ● 0°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 125°C (Note 2) ● 0.588 0.585 MAX UNITS 5.5 V 30 nA 0.6 0.6 0.612 0.612 V V 0.5 ΔVLINE REG Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 ΔVLOAD REG Output Voltage Load Regulation MODE/SYNC = 0V (Note 3) 0.5 IS Input DC Supply Current Active Mode Sleep Mode Shutdown (Note 4) VFB1 = VFB2 = 0.5V VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V 700 40 0.1 950 60 1 fOSC Oscillator Frequency VFBX = 0.6V 2.25 2.7 fSYNC Synchronization Frequency ILIM Peak Switch Current Limit VIN = 3V, VFBX = 0.5V, Duty Cycle <35% 1.2 1.6 A RDS(ON) Top Switch On-Resistance Bottom Switch On-Resistance (Note 6) (Note 6) 0.35 0.30 0.45 0.45 Ω Ω ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V, VFBX = 0V 0.01 1 μA POR Power-On Reset Threshold VFBX Ramping Up, MODE/SYNC = 0V VFBX Ramping Down, MODE/SYNC = 0V 8.5 –8.5 ● 1.8 % 2.25 1 Power-On Reset On-Resistance 100 Power-On Reset Delay %/V μA μA μA MHz MHz % % 200 65,536 Ω Cycles VRUN RUN/SS Threshold Low RUN/SS Threshold High ● ● IRUN RUN/SS Leakage Current ● VMODE MODE Threshold Low 0 MODE Threshold High VIN – 0.5 VIN V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3407AE-2 is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the – 40°C and 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3407AI-2 is guaranteed over the full –40°C to 125°C operating temperature range. 0.3 1 0.01 1.5 2 V V 1 μA 0.5 V Note 3: The LTC3407A-2 is tested in a proprietary test mode that connects VFB to the output of the error amplifier. Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA). Note 6: The DFN switch on-resistance is guaranteed by correlation to wafer level measurements. 3407a2f 3 LTC3407A-2 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise specified. Burst Mode Operation Pulse Skipping Mode SW 5V/DIV SW 5V/DIV VOUT 50mV/DIV VOUT 10mV/DIV IL 200mA/DIV IL 100mA/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 50mA CIRCUIT OF FIGURE 3 VIN = 3.6V VOUT = 1.8V ILOAD = 50mA CIRCUIT OF FIGURE 3 3407A2 G01 2μs/DIV Load Step 3407A2 G02 1μs/DIV Soft Start VOUT1 200mV/DIV VIN 2V/DIV VOUT2 100mV/DIV VOUT1 1V/DIV IL 500mA/DIV IL 500mA/DIV ILOAD 500mA/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 50mA TO 600mA CIRCUIT OF FIGURE 3 20μs/DIV Oscillator Frequency vs Temperature Efficiency vs Input Voltage 2.5 100mA 90 1mA 10mA 8 2.4 70 FREQUENCY (MHz) EFFICIENCY (%) 10 VIN = 3.6V 800mA 80 60 50 40 30 2.3 2.2 20 2.1 10 VOUT = 1.8V CIRCUIT OF FIGURE 3 0 4 3 2 5 INPUT VOLTAGE (V) 2.0 –50 –25 3407A2 G16 1ms/DIV Oscillator Frequency vs Supply Voltage FREQUENCY DEVIATION (%) 100 VIN = 3.6V VOUT = 1.8V ILOAD = 500mA CIRCUIT OF FIGURE 4 3407A2 G03 6 4 2 0 –2 –4 –6 –8 6 3407A2 G04 –10 50 25 75 0 TEMPERATURE (°C) 100 125 2 3 4 5 6 SUPPLY VOLTAGE (V) 3407A2 G05 3407A2 G06 3407a2f 4 LTC3407A-2 U W TYPICAL PERFOR A CE CHARACTERISTICS Reference Voltage vs Temperature TA = 25°C unless otherwise specified. RDS(ON) vs Input Voltage RDS(ON) vs Temperature 500 0.615 550 VIN = 3.6V 450 0.610 VIN = 4.2V 450 0.600 0.595 400 350 300 0.590 250 0.585 –50 –25 200 50 25 75 0 TEMPERATURE (°C) 100 2 3 4 VIN (V) 80 3.3V 5 50 40 Load Regulation Burst Mode OPERATION 3 2 60 PULSE SKIP MODE 50 40 30 30 20 20 10 VOUT = 2.5V Burst Mode OPERATION CIRCUIT OF FIGURE 3 0 1 10 100 LOAD CURRENT (mA) 10 VIN = 3.6V, VOUT = 1.8V NO LOAD ON OTHER CHANNEL 0 1 10 100 LOAD CURRENT (mA) 1000 Efficiency vs Load Current 3.3V –3 –4 1 1000 3.3V VOUT ERROR (%) EFFICIENCY (%) 40 20 20 10 10 10 100 LOAD CURRENT (mA) 0.3 4.2V 50 30 3407A2 G13 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 VOUT = 1.5V Burst Mode OPERATION 0 1000 VOUT = 1.8V IOUT = 200mA 0.4 60 30 VOUT = 1.2V Burst Mode OPERATION 1000 Line Regulation 2.7V 70 40 10 100 LOAD CURRENT (mA) 3407A2 G12 80 4.2V 50 VIN = 3.6V, VOUT = 1.8V NO LOAD ON OTHER CHANNEL 0.5 90 60 PULSE SKIP MODE –1 Efficiency vs Load Current 2.7V 1 0 –2 100 0 1 Burst Mode OPERATION 3407A2 G11 100 70 25 50 75 100 125 150 TEMPERATURE (°C) 3407A2 G09 0 3407A2 G08 VOUT ERROR(%) EFFICIENCY (%) 60 MAIN SWITCH SYNCHRONOUS SWITCH 4 3407A2 G10 EFFICIENCY (%) 7 6 70 80 250 100 –50 –25 80 70 90 300 Efficiency vs Load Current 90 4.2V 350 200 100 2.7V VIN = 3.6V 400 150 1 125 Efficiency vs Load Current EFFICIENCY (%) SYNCHRONOUS SWITCH 3407A2 G07 100 90 MAIN SWITCH RDS(ON) (mΩ) 0.605 RDS(ON) (mΩ) REFERENCE VOLTAGE (V) VIN = 2.7V 500 1 10 100 LOAD CURRENT (mA) 1000 –0.5 2 3 4 VIN (V) 5 6 3407A2 G15 3407A2 G14 3407a2f 5 LTC3407A-2 U U U PI FU CTIO S VFB1 (Pin 1): Output Feedback. Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.6V. be synchronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected. SW2 (Pin 7): Regulator 2 Switch Node Connection to the Inductor. This pin swings from VIN to GND. RUN/SS1 (Pin 2): Regulator 1 Enable and Soft-Start Input. Forcing this pin to VIN enables regulator 1, while forcing it to GND causes regulator 1 to shut down. Connect external RC-network with desired time-constant to enable softstart feature. This pin must be driven; do not float. POR (Pin 8): Power-On Reset. This common-drain logic output is pulled to GND when the output voltage is not within ±8.5% of regulation and goes high after 216 clock cycles when both channels are within regulation. VIN (Pin 3): Main Power Supply. Must be closely decoupled to GND. RUN/SS2 (Pin 9): Regulator 2 Enable and Soft-Start Input. Forcing this pin to VIN enables regulator 2, while forcing it to GND causes regulator 2 to shut down. Connect external RC-Network with desired time-constant to enable softstart feature. This pin must be driven; do not float. SW1 (Pin 4): Regulator 1 Switch Node Connection to the Inductor. This pin swings from VIN to GND. GND (Pin 5): Main Ground. Connect to the (–) terminal of COUT, and (–) terminal of CIN. VFB2 (Pin 10): Output Feedback. Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.6V. MODE/SYNC (Pin 6): Combination Mode Selection and Oscillator Synchronization. This pin controls the operation of the device. When tied to VIN or GND, Burst Mode operation or pulse skipping mode is selected, respectively. Do not float this pin. The oscillation frequency can Exposed Pad (GND) (Pin 11): Power Ground. Connect to the (–) terminal of COUT, and (–) terminal of CIN. Must be soldered to electrical ground on PCB. W BLOCK DIAGRA REGULATOR 1 MODE/SYNC 6 BURST CLAMP VIN SLOPE COMP 0.6V EA VFB1 SLEEP ITH – + 5Ω ICOMP + 0.65V – 1 EN – + BURST S 0.55V – UVDET Q RS LATCH R Q UV + SWITCHING LOGIC AND BLANKING CIRCUIT ANTI SHOOTTHRU 4 SW1 + – IRCMP – 0.65V OV + OVDET SHUTDOWN PGOOD1 11 GND VIN 3 VIN 8 POR RUN/SS1 2 0.6V REF POR COUNTER OSC RUN/SS2 9 OSC 5 GND PGOOD2 REGULATOR 2 (IDENTICAL TO REGULATOR 1) VFB2 10 7 SW2 3407A2 BD 3407a2f 6 LTC3407A-2 U OPERATIO The LTC3407A-2 uses a constant frequency, current mode architecture. The operating frequency is set at 2.25MHz and can be synchronized to an external oscillator. Both channels share the same clock and run in-phase. To suit a variety of applications, the selectable MODE/SYNC pin allows the user to trade-off noise for efficiency. The output voltage is set by an external divider returned to the VFB pins. An error amplifier compares the divided output voltage with a reference voltage of 0.6V and adjusts the peak inductor current accordingly. Overvoltage and undervoltage comparators will pull the POR output low if the output voltage is not within ±8.5%. The POR output will go high after 65,536 clock cycles (about 29ms in pulse skipping mode) of achieving regulation. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom switch (Nchannel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the internally compensated ITH voltage, which is the output of the error amplifier.This amplifier compares the VFB pin to the 0.6V reference. When the load current increases, the VFB voltage decreases slightly below the reference. This decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. automatically switches into Burst Mode operation in which the PMOS switch operates intermittently based on load demand with a fixed peak inductor current. By running cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. A voltage comparator trips when ITH is below 0.65V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH exceeds 0.65V, turning on the switch and the main control loop which starts another cycle. For lower ripple noise at low currents, the pulse skipping mode can be used. In this mode, the LTC3407A-2 continues to switch at a constant frequency down to very low currents, where it will begin skipping pulses. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. An important design consideration is that the RDS(ON) of the P-channel switch increases with decreasing input supply voltage (See Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3407A-2 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information Section). The main control loop is shut down by pulling the RUN/SS pin to ground. Low Supply Operation Low Current Operation The LTC3407A-2 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 1.65V to prevent unstable operation. Two modes are available to control the operation of the LTC3407A-2 at low currents. Both modes automatically switch from continuous operation to the selected mode when the load current is low. To optimize efficiency, the Burst Mode operation can be selected. When the load is relatively light, the LTC3407A-2 A general LTC3407A-2 application circuit is shown in Figure 1. External component selection is driven by the load requirement, and begins with the selection of the inductor L. Once the inductor is chosen, CIN and COUT can be selected. 3407a2f 7 LTC3407A-2 U W U U APPLICATIO S I FOR ATIO Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance and increases with higher VIN or VOUT: ΔIL = VOUT ⎛ VOUT ⎞ • 1– fO • L ⎜⎝ VIN ⎟⎠ Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. A reasonable starting point for setting ripple current is ΔIL = 0.3 • ILIM, where ILIM is the peak switch current limit. The largest ripple current ΔIL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: L= ⎞ VOUT ⎛ V • ⎜ 1– OUT ⎟ fO • ΔIL ⎝ VIN(MAX ) ⎠ The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this transition to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characterisitics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3407A-2 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3407A-2 applications. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/ VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ≈ IMAX VOUT ( VIN – VOUT ) VIN where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL/2. This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1μF to 1μF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER Taiyo Yuden CB2016T2R2M CB2012T2R2M CB2016T3R3M MAX DC VALUE CURRENT DCR 2.2μH 510mA 0.13Ω 2.2μH 530mA 0.33Ω 3.3μH 410mA 0.27Ω HEIGHT 1.6mm 1.25mm 1.6mm Panasonic ELT5KT4R7M 4.7μH 950mA 0.2Ω 1.2mm Sumida CDRH2D18/LD 4.7μH 630mA 0.086Ω 2mm Murata LQH32CN4R7M23 4.7μH 450mA 0.2Ω 2mm Taiyo Yuden NR30102R2M NR30104R7M 2.2μH 4.7μH 1100mA 750mA 0.1Ω 0.19Ω 1mm 1mm FDK FDKMIPF2520D FDKMIPF2520D FDKMIPF2520D 4.7μH 3.3μH 2.2μH 1100mA 1200mA 1300mA 0.11Ω 0.1Ω 0.08Ω 1mm 1mm 1mm TDK VLF3010AT4R7MR70 VLF3010AT3R3MR87 VLF3010AT2R2M1R0 4.7μH 700mA 0.28Ω 1mm 3.3μH 870mA 0.17Ω 1mm 2.2μH 1000mA 0.12Ω 1mm 3407a2f 8 LTC3407A-2 U W U U APPLICATIO S I FOR ATIO Output Capacitor (COUT) Selection The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is determined by: ⎛ ⎞ 1 ΔVOUT ≈ ΔIL ⎜ ESR + 8 fO COUT ⎟⎠ ⎝ where fO = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. With ΔIL = 0.3 • ILIM the output ripple will be less than 100mV at maximum VIN and fO = 2.25MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density. However, they also have a larger ESR and it is critical that they are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely costsensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost, but also have the lowest capacitance density, a high voltage and temperature coefficient, and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic Special Polymer (SP) capacitors. In most cases, 0.1μF to 1μF of ceramic capacitors should also be placed close to the LTC3407A-2 in parallel with the main capacitors for high frequency decoupling. VIN = 2.5V TO 5.5V CIN R7 VIN BURST* R6 PULSESKIP* MODE/SYNC R5 LTC3407A-2 RUN/SS2 RUN/SS1 L1 L2 VOUT2 POWER-ON RESET POR SW2 VOUT1 SW1 C2 C1 C4 C3 R4 COUT2 VFB1 VFB2 GND R3 R2 R1 *MODE/SYNC = 0V: PULSE SKIP MODE/SYNC = VIN: Burst Mode COUT1 3407A2 F01 Figure 1. LTC3407A-2 General Schematic Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective. Also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK, and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. 3407a2f 9 LTC3407A-2 U W U U APPLICATIO S I FOR ATIO At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3-4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: COUT ≈ 3 ΔIOUT fO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3407A-2 develops a 0.6V reference voltage between the feedback pin, VFB, and ground as shown in Figure 1. The output voltage is set by a resistive divider according to the following formula: ⎛ R2 ⎞ VOUT = 0.6 V ⎜ 1+ ⎟ ⎝ R1⎠ Keeping the current small (<5μA) in these resistors maximizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Power-On Reset The POR pin is an open-drain output which pulls low when either regulator is out of regulation. When both output voltages are within ±8.5% of regulation, a timer is started which releases POR after 216 clock cycles (about 29ms in pulse skipping mode). This delay can be significantly longer in Burst Mode operation with low load currents, since the clock cycles only occur during a burst and there could be milliseconds of time between bursts. This can be bypassed by tying the POR output to the MODE/SYNC input, to force pulse skipping mode during a reset. In addition, if the output voltage faults during Burst Mode sleep, POR could have a slight delay for an undervoltage output condition and may not respond to an overvoltage output. This can be avoided by using pulse skipping mode instead. When either channel is shut down, the POR output is pulled low, since one or both of the channels are not in regulation. Mode Selection & Frequency Synchronization The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. When this pin is connected to ground, pulse skipping operation is selected which provides the lowest output ripple, at the cost of low current efficiency. The LTC3407A-2 can also be synchronized to another LTC3407A-2 by the MODE/SYNC pin. During synchronization, the mode is set to pulse skipping and the top switch turn-on is synchronized to the rising edge of the external clock. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During 3407a2f 10 LTC3407A-2 U W U U APPLICATIO S I FOR ATIO this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard secondorder overshoot/DC ratio cannot be used to determine phase margin. In addition, a feed-forward capacitor can be added to improve the high frequency response, as shown in Figure 1. Capacitors C1 and C2 provide phase lead by creating high frequency zeros with R2 and R4 respectively, which improve the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (>1μF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot SwapTM controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and softstarting. Soft-Start The RUN/SS pins provide a means to separately run or shut down the two regulators. In addition, they can optionally be used to externally control the rate at which each regulator starts up and shuts down. Pulling the RUN/SS1 pin below 1V shuts down regulator 1 on the LTC3407A-2. Forcing this pin to VIN enables regulator 1. In order to control the rate at which each regulator turns on and off, connect a resistor and capacitor to the RUN/SS pins as shown in Figure 1. The soft-start duration can be calculated by using the following formula: ⎛ V −1 ⎞ (s) t SS = RSSCSSIn ⎜ IN ⎝ VIN − 1.6 ⎟⎠ For approximately a 1ms ramp time, use RSS = 4.7MΩ and CSS = 680pF at VIN = 3.3V. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in LTC3407A-2 circuits: 1)VIN quiescent current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the Electrical Characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L, but is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into Hot Swap is a registered trademark of Linear Technology Corporation. 3407a2f 11 LTC3407A-2 U W U U APPLICATIO S I FOR ATIO the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows: RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other ‘hidden’ losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3407A-2 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3407A-2 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To prevent the LTC3407A-2 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3407A-2 is in dropout on both channels at an input voltage of 2.7V with a load current of 800mA and an ambient temperature of 70°C. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the main switch is 0.425Ω. Therefore, power dissipated by each channel is: PD = I2 • RDS(ON) = 272mW The MS package junction-to-ambient thermal resistance, θJA, is 45°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: TJ = 2 • 0.272 • 45 + 70 = 94.5°C which is below the absolute maximum junction temperature of 125°C. Design Example As a design example, consider using the LTC3407A-2 in a portable application with a Li-Ion battery. The battery provides a VIN = 2.8V to 4.2V. The load requires a maximum of 800mA in active mode and 2mA in standby mode. The output voltage is VOUT = 2.5V. Since the load still needs power in standby, Burst Mode operation is selected for good low load efficiency. First, calculate the inductor value for about 30% ripple current at maximum VIN: L= 2.5V ⎛ 2.5V ⎞ • ⎜ 1– = 1.25μH 2.25MHz • 360mA ⎝ 4.2V ⎟⎠ 3407a2f 12 LTC3407A-2 U U W U APPLICATIO S I FOR ATIO Choosing the next highest standardized inductor value of 2.2μH, results in a maximum ripple current of: ΔIL = 2.5V ⎛ 2.5V ⎞ • ⎜ 1− = 204mA 2.25MHz • 2.2μH ⎝ 4.2V ⎟⎠ For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop: COUT ≈ 2.5 800mA = 7.1μF 2.25MHz • (5% • 2.5V) The closest standard value is 10μF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10μF. The output voltage can now be programmed by choosing the values of R1 and R2. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2μA with the 0.6V feedback voltage makes R1~300k. A close standard 1% resistor is 280k, and R2 is then 887k. The POR pin is a common drain output and requires a pullup resistor. A 100k resistor is used for adequate speed. Figure 3 shows the complete schematic for this design example. The specific passive components chosen allow for a 1mm height power supply that maintains a high efficiency across load. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3407A-2. These items are also illustrated graphically in the layout diagram of Figure 2. Check the following in your layout: 1. Does the capacitor CIN connect to the power VIN (Pin 3) and GND (exposed pad) as closely as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are COUT and L1 closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN. 3. The resistor divider formed by R1 and R2 must be connected between the (+) plate of COUT and a ground sense line terminated near GND (exposed pad). The feedback signals VFB1 and VFB2 should be routed away from noisy components and traces, such as the SW lines (Pins 4 and 7), and their traces should be minimized. 4. Keep sensitive components away from the SW pins. The input capacitor CIN and the resistors R1 to R4 should be routed away from the SW traces and the inductors. 5. A ground plane is preferred, but if not available keep the signal and power grounds segregated with small signal components returning to the GND pin at one point. Addtionally the two grounds should not share the high current paths of CIN or COUT. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND. VIN CIN RUN/SS2 VIN RUN/SS1 MODE/SYNC POR LTC3407A-2 L1 L2 VOUT2 SW1 SW2 C5 VFB1 VFB2 R4 COUT2 VOUT1 C4 GND R3 R2 R1 COUT1 3407A2 F02 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 2. LTC3407A-2 Layout Diagram (See Board Layout Checklist) 3407a2f 13 LTC3407A-2 U TYPICAL APPLICATIO S VIN = 2.5V TO 5.5V RUN/SS2 VIN RUN/SS1 LTC3407A-2 L2 2.2μH VOUT2 = 2.5V AT 800mA L1 2.2μH C5, 22pF R4 887k C3 10μF C4, 22pF VOUT1 = 1.8V AT 800mA VFB1 VFB2 R2 R1 604k 301k GND R3 280k 2.5V 90 1.8V 80 SW1 SW2 100 POWER-ON RESET POR MODE/SYNC Efficiency vs Load Current R5 100k C2 10μF 70 EFFICIENCY (%) C1 10μF 60 50 40 30 20 VIN = 3.3V Burst Mode OPERATION NO LOAD ON OTHER CHANNEL 10 C1, C2, C3: TAIYO YUDEN JMK316BJ106MD L1, L2: TDK VLF3010AT-2R2M1R0 3407A2 TA03 0 10 100 LOAD CURRENT (mA) 1 Figure 3. 1mm Height Core Supply 1000 3407A2 TA03b Efficiency vs Load Current VIN = 2.5V TO 5.5V 100 R7 100k VIN LTC3407A-2 POR RUN/SS2 VOUT2 = 2.5V AT 800mA R5 4.7MΩ POWER-ON RESET L1 4.7μH SW2 SW1 C2, 22pF C1, 22pF VOUT1 = 1.2V AT 800mA C4 680pF C3 680pF COUT2 10μF R4 887k VFB1 VFB2 R3 280k MODE/SYNC GND R1 604k R2 604k 2.5V 80 1.2V 70 RUN/SS1 L2 4.7μH 90 EFFICIENCY (%) CIN 10μF R6 4.7MΩ 60 50 40 30 20 VIN = 3.3V Burst Mode OPERATION NO LOAD ON OTHER CHANNEL 10 COUT1 10μF 0 1 CIN, COUT1, COUT2: TAIYO YUDEN JMK316BJ106ML L1, L2: TDK VLF3012AT-4R7M74 3407A2 TA04 10 100 LOAD CURRENT (mA) 1000 3407A2 TA04b Figure 4. Low Ripple Buck Regulators with Soft-Start 3407a2f 14 LTC3407A-2 U PACKAGE DESCRIPTIO DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 0.38 ± 0.10 6 10 5 1 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PACKAGE OUTLINE 0.25 ± 0.05 (DD) DFN 1103 0.75 ±0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1664) 2.794 ± 0.102 (.110 ± .004) 5.23 (.206) MIN 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 2.083 ± 0.102 3.20 – 3.45 (.082 ± .004) (.126 – .136) 0.254 (.010) DETAIL “A” 0° – 6° TYP BOTTOM VIEW OF EXPOSED PAD OPTION 1 2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) GAUGE PLANE 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 10 0.86 (.034) REF 1.10 (.043) MAX DETAIL “A” 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1 2 3 4 5 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MSE) 0603 3407a2f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3407A-2 U TYPICAL APPLICATIO 2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator VIN = 2.8V TO 4.2V C1 10μF RUN/SS2 VIN MODE/SYNC POWER-ON RESET POR LTC3407A-2 L2 10μH D1 VOUT2 = 3.3V AT 200mA R5 100k RUN/SS1 SW2 L1 2.2μH C4, 22pF M1 + C6 47μF C3 10μF R4 887k R3 196k VFB1 VFB2 C1, C2, C3: TAIYO YUDEN JMK316BJ106ML C6: SANYO 6TPB47M D1: PHILIPS PMEG2010 R2 R1 887k 442k GND C2 10μF L1: MURATA LQH32CN2R2M33 L2: TOKO A914BYW-100M (D52LC SERIES) M1: SILICONIX Si2302 Efficiency vs Load Current 3407A TA05 Efficiency vs Load Current 90 100 80 90 3.6V 2.8V 4.2V 3.6V 70 EFFICIENCY (%) 60 2.8V 80 4.2V 70 EFFICIENCY (%) VOUT1 = 1.8V AT 800mA SW1 50 40 30 60 50 40 30 20 20 VOUT = 3.3V Burst Mode OPERATION NO LOAD ON OTHER CHANNEL 10 0 1 10 100 LOAD CURRENT (mA) VOUT = 1.8V Burst Mode OPERATION NO LOAD ON OTHER CHANNEL 10 0 1000 1 3407A2 TA05a 10 100 LOAD CURRENT (mA) 1000 3407A2 TA05b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA, ISD <1μA, ThinSOT Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD <1μA, ThinSOT Package LTC3407/LTC3407-2 600mA/800mA (IOUT), 1.5MHz/2.25MHz, LTC3407-3/LTC3407-4/ Dual Synchronous Step-Down DC/DC Converter LTC3407A 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, MS10E Package, DFN Package LTC3410/LTC3410B 300mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter in SC70 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26μA, ISD <1μA, SC70 Package LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD <1μA, MSOP-10 Package LTC3412/LTC3412A 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD <1μA, TSSOP-16E Package LTC3414 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, ISD <1μA, TSSOP-28E Package LTC3440/LTC3441 600mA/1.2A (IOUT), 2MHz/1MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25μA, ISD <1μA, MSOP-10 Package/DFN Package LTC3548/ LTC3548-1/LTC3548-2 400mA/800mA (IOUT), 2.25MHz, Dual Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, MS10E Package/DFN Package 3407a2f 16 Linear Technology Corporation LT 0907 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007