LTM9001 16-Bit IF/Baseband Receiver Subsystem FEATURES DESCRIPTION n The LTM®9001 is an integrated System in a Package (SiP) that includes a high-speed 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It is designed for digitizing wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. The amplifier allows either AC- or DC-coupled input drive. A low-pass or bandpass filter network can be implemented with various bandwidths. Contact Linear Technology regarding semi-custom configurations. n n n n n n n n n n n Integrated 16-Bit, High-Speed ADC, Passive Filter and Fixed Gain Differential Amplifier Up to 300MHz IF Range Low-Pass and Bandpass Filter Versions Low Noise, Low Distortion Amplifiers Fixed Gain: 8dB, 14dB, 20dB or 26dB 50Ω, 200Ω or 400Ω Input Impedance 72dB SNR, 82dB SFDR (LTM9001-AA) Integrated Bypass Capacitance, No External Components Required Optional Internal Dither Optional Data Output Randomizer LVDS or CMOS Outputs 3.3V Single Supply Power Dissipation: 1.65W Clock Duty Cycle Stabilizer 11.25mm × 11.25mm × 2.32mm LGA Package APPLICATIONS n n n n Telecommunications High Sensitivity Receivers Cellular Base Stations Spectrum Analyzers The LTM9001 is perfect for IF receivers in demanding communications applications, with AC performance that includes 72dBFS noise floor and 82dB spurious free dynamic range (SFDR) at 162.5MHz (LTM9001-AA). The digital outputs can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V. The differential ENC+ and ENC– inputs may be driven with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Simplified IF Receiver Channel VCC SENSE 64k Point FFT, FIN = 162.4MHz, –1dBFS, PGA = 1 VDD = 3.3V 0 LTM9001 0VDD = 0.5V TO 3.6V IN– RF ANTI-ALIAS FILTER SAW LO 16-BIT 130Msps ADC IN+ • • • D0 CLKOUT OF DIFFERENTIAL FIXED GAIN AMPLIFIER 9001 TA01 ENC+ ENC– ADC CONTROL PINS –40 –60 HD3 –80 HD2 –100 OGND GND CMOS OR LVDS AMPLITUDE (dBFS) D15 –20 –120 0 12288 20480 28672 4096 FFT BIN NUMBER (32k TOTAL) 9001 TA01b 9001fa 1 LTM9001 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (VCC) ................................ –0.3V to 3.6V Supply Voltage (VDD) ................................... –0.3V to 4V Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V Analog Input Current (IN+, IN–) ............................±10mA Digital Input Voltage (Except AMPSHDN) ..................–0.3V to (VDD + 0.3V) Digital Input Voltage (AMPSHDN)..............................–0.3V to (VCC + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9001C................................................ 0°C to 70°C LTM9001I............................................. –40°C to 85°C Storage Temperature Range................... –45°C to 125°C Maximum Junction Temperature........................... 125°C ALL ELSE = GND TOP VIEW CONTROL 1 2 DATA 3 4 5 6 7 8 9 OGND J IN– H IN+ G OVDD F VCC E DNC D ENC+ C ENC– B A OGND VDD OGND OVDD CONTROL LGA PACKAGE TJMAX = 125°C, θJA = 15°C/W, θJC = 19°C/W θJA DERIVED FROM 60mm × 70mm PCB WITH 4 LAYERS WEIGHT = 0.71g ORDER INFORMATION LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM9001CV-AA#PBF LTM9001V-AA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C LTM9001IV-AA#PBF LTM9001V-AA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C LTM9001CV-BA#PBF LTM9001V-BA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C LTM9001IV-BA#PBF LTM9001V-BA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL GDIFF GTEMP PARAMETER Gain CONDITIONS MIN TYP MAX UNITS DC, LTM9001-AA fIN = 162.5MHz (Note 3) l 19.1 19.7 19 20.3 dB dB DC, LTM9001-BA fIN = 140MHz (Note 3) l 7.1 8.2 7.8 9.4 dB dB Gain Temperature Drift VIN = Maximum, (Note 3) VINCM Input Common Mode Voltage Range (IN+ + IN–)/2 VIN Input Voltage Range at –1dBFS LTM9001-AA at 162.5MHz LTM9001-BA at 140MHz 2 1.0–1.6 233 820 mdB/°C V mVP-P mVP-P 9001fa 2 LTM9001 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN RINDIFF Differential Input Impedance LTM9001-AA LTM9001-BA CINDIFF Differential Input Capacitance Includes Parasitic VOS Offset Error (Note 6) Including Amplifier and ADC (LTM9001-AA) Including Amplifier and ADC (LTM9001-BA) Offset Drift Including Amplifier and ADC ±10 μV/°C Full-Scale Drift Internal Reference External Reference ±30 ±15 ppm/°C ppm/°C 60 dB l l –8 –20 TYP MAX UNITS 200 400 Ω Ω 1 pF –3.2 –10 –0.5 –0.5 mV mV CMRR Common Mode Rejection Ratio ISENSE SENSE Input Leakage Current IMODE MODE Pin Pull-Down Current to GND 10 μA ILVDS LVDS Pin Pull-Down Current to GND 10 μA tAP Sample-and-Hold Acquisition Delay Time 1 ns tJITTER Sample-and-Hold Acquisition Delay Time Jitter 70 fsRMS 0V < SENSE < VDD l –3 3 μA CONVERTER CHARACTERISTICS The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS MIN l Resolution (No Missing Codes) TYP MAX UNITS 16 Bits Integral Linearity Error Differential Input LTM9001-AA (Notes 5, 7) Differential Input LTM9001-BA (Notes 5, 7) l l ±2.4 ±8 ±10 LSB LSB Differential Linearity Error Differential Input (Notes 5, 7) l ±0.3 ±1 LSB Transition Noise External Reference 1 LSBRMS DYNAMIC ACCURACY The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA SFDR Spurious Free Dynamic Range, 2nd or 3rd Harmonic 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA SFDR Spurious Free Dynamic Range 4th or Higher 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA MIN TYP MAX UNITS l 67.2 72 68.5 dBFS dBFS l 67 69.2 67.2 dBFS dBFS l 72 78 82 dBc dBc l 64 72 82 dBc dBc l 86 95 95 dBc dBc l 86 95 104 dBc dBc 9001fa 3 LTM9001 DYNAMIC ACCURACY The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS S/(N+D) Signal-to-Noise Plus Distortion Ratio 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA SFDR MIN TYP l 67 71.4 68 MAX UNITS dBFS dBFS l 64 67.5 66.4 dBFS dBFS Spurious Free Dynamic Range at –25dBFS, Dither “OFF” 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 90 93 dBFS dBFS Spurious Free Dynamic Range at –15dBFS, Dither “OFF” 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA 91 92 dBFS dBFS Spurious Free Dynamic Range at –25dBFS, Dither “ON” 162.5MHz Input (PGA = 0) LTM9001-AA 162.5MHz Input (PGA = 1) LTM9001-AA 95 100 dBFS dBFS Spurious Free Dynamic Range at –15dBFS, Dither “ON” 140MHz Input (PGA = 0) LTM9001-BA 140MHz Input (PGA = 1) LTM9001-BA 95 96 dBFS dBFS IMD3 Third Order Intermodulation Distortion; 1MHz Tone Spacing, 2 Tones at –7dBFS fIN = 162.5MHz LTM9001-AA fIN = 140MHz LTM9001-BA –78 –84 dB dB IIP3 Equivalent Third Order Input Intercept Point, 2 Tone fIN = 162.5MHz LTM9001-AA fIN = 140MHz LTM9001-BA 24 29.2 dBm dBm SFDR l 90 l 90 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Encode Inputs (ENC+, ENC–) VID Differential Input Voltage VICM Common Mode Input Voltage RIN Input Resistance CIN Input Capacitance l Internally Set Externally Set 0.2 V 1.6 1.2 (Note 7) 3.1 V V 100 Ω 3 pF Logic Inputs (DITH, PGA, ADCSHDN, RAND) VIH High Level Input Voltage VDD = 3.3V l VIL Low Level Input Voltage VDD = 3.3V l l IIN Input Current VIN = 0V to VDD CIN Input Capacitance (Note 7) 2 V 0.8 V ±10 μA 1.5 pF Logic Inputs (AMPSHDN) VIH High Level Input Voltage VCC = 3.3V l VIL Low Level Input Voltage VCC = 3.3V l IIH Input High Current VIN = 2V 1.3 μA IIL Input Low Current VIN = 0.8V 0.1 μA CIN Input Capacitance (Note 7) 1.5 pF 3.299 3.29 V V 2 V 0.8 V Logic Outputs (CMOS Mode) OVDD = 3.3V VOH VOL High Level Output Voltage Low Level Output Voltage VDD = 3.3V, IO = –10μA VDD = 3.3V, IO = –200μA l VDD = 3.3V, IO = 10μA VDD = 3.3V, IO = 1.6mA l 3.1 0.01 0.1 0.4 V V 9001fa 4 LTM9001 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ISOURCE Output Source Current VOUT = 0V –50 mA ISINK Output Sink Current VOUT = 3.3V 50 mA VOH High Level Output Voltage VDD = 3.3V, IO = –200μA 2.49 V VOL Low Level Output Voltage VDD = 3.3V, IO = 1.6mA 0.1 V VOH High Level Output Voltage VDD = 3.3V, IO = –200μA 1.79 V VOL Low Level Output Voltage VDD = 3.3V, IO = 1.6μA 0.1 V OVDD = 2.5V OVDD = 1.8V Logic Outputs (LVDS Mode) Standard LVDS VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 VOD Differential Output Voltage 100Ω Differential Load l 125 175 250 VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 mV V Low Power LVDS mV V POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VDD ADC Analog Supply Voltage (Note 9) VCC Amplifier Supply Voltage ICC Amplifier Supply Current PSHDN Total Shutdown Power l MIN TYP MAX UNITS 3.135 3.3 3.465 V 3.5 V 100 136 mA 2.85 l AMPSHDN = ADCSHDN = 3.3V 10 mW Standard LVDS Output Mode OVDD Output Supply Voltage IVDD Analog Supply Current IOVDD Output Supply Current PDISS Power Dissipation (Note 9) l LTM9001-AA LTM9001-BA l l 3 3.3 3.6 V 400 465 500 550 mA mA l 74 90 mA LTM9001-AA LTM9001-BA l l 1564 1779 1947 2112 mW mW 3.3 3.6 V Low Power LVDS Output Mode OVDD Output Supply Voltage (Note 9) l IVDD Analog Supply Current LTM9001-AA LTM9001-BA l l 400 465 500 550 mA mA IOVDD Output Supply Current l 41 50 mA PDISS Power Dissipation LTM9001-AA LTM9001-BA l l 1455 1670 1815 1980 mW mW 3.6 V 380 460 450 530 mA mA 3 CMOS Output Mode OVDD Output Supply Voltage (Note 9) l IVDD Analog Supply Current LTM9001-AA LTM9001-BA l l 0.5 9001fa 5 LTM9001 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS PDISS ADC Power Dissipation LTM9001-AA LTM9001-BA PDISS(TOTAL) Total Power Dissipation LTM9001-AA LTM9001-BA MIN l l TYP MAX UNITS 1320 1584 1650 1914 mW mW 1650 1914 mW mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 130 160 MHz MHz fS Sampling Frequency (Note 9) LTM9001-AA LTM9001-BA l l tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off (LTM9001-AA) Duty Cycle Stabilizer Off (LTM9001-BA) Duty Cycle Stabilizer On (LTM9001-AA) Duty Cycle Stabilizer On (LTM9001-BA) l l l l 3.65 2.97 2.6 2.1 3.846 3.125 3.846 3.125 1000 1000 1000 1000 ns ns ns ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off (LTM9001-AA) Duty Cycle Stabilizer Off (LTM9001-BA) Duty Cycle Stabilizer On (LTM9001-AA) Duty Cycle Stabilizer On (LTM9001-BA) l l l l 3.65 2.97 2.6 2.1 3.846 3.125 3.846 3.125 1000 1000 1000 1000 ns ns ns ns 1 1 LVDS Output Mode (Standard and Low Power) tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC – tD) (Note 7) l 4.3 10 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency 7 Cycles CMOS Output Mode tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC – tD) (Note 7) l 4.3 10 ns Data Latency Full Rate CMOS Demuxed Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: Gain is measured from IN+/IN– through the ADC. The amplifier provides approximately 20dB of gain and the filter has 1dB loss (LTM9001-AA). Note 4: VCC = VDD = 3.3V, fSAMPLE = maximum sample frequency, differential ENC+/ENC– = 2VP-P with 1.6V common mode, input range = –1dBFS with PGA = 0 with differential drive, AC-coupled inputs, unless otherwise noted. 7 7 Cycles Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the voltage applied between the IN+ and IN– pins required to make the output code flicker between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Amplifier dynamic performance tests are done from IN+/IN– through the DNC pins without using the ADC. Note 9: Recommended operating conditions. 9001fa 6 LTM9001 TIMING DIAGRAM LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL ENC – ENC+ tD N–7 D0-D15, OF N–6 N–5 N–4 N–3 tC CLKOUT+ CLKOUT – 9001 TD01 Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL ENC– ENC+ tD N–7 DA0-DA15, OFA N–6 N–5 N–4 N–3 tC CLKOUTA CLKOUTB DB0-DB15, OFB HIGH IMPEDANCE 9001 TD02 9001fa 7 LTM9001 TIMING DIAGRAM Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N N+4 N+2 N+3 tH tL – ENC ENC+ tD DA0-DA15, OFA N–8 N–6 N–4 N–7 N–5 N–3 tD DB0-DB15, OFB tC CLKOUTA CLKOUTB 9001 TD03 9001fa 8 LTM9001 TYPICAL PERFORMANCE CHARACTERISTICS 250 –2 –4 –6 –8 MAGNITUDE PHASE 0 8000 200 150 9000 –45 100 IMPEDANCE PHASE (deg) IMPEDANCE MAGNITUDE (Ω) 0 FILTER GAIN (dB) Shorted Inputs Histogram with 130k Samples Input Impedance vs Frequency 7000 6000 COUNT IF Frequency Response (LTM9001-AA) 5000 4000 3000 2000 1000 50 10 –10 120 130 140 150 160 170 180 190 200 FREQUENCY (MHz) –90 1000 100 FREQUENCY (MHz) 0.4 3 0.3 2 0.2 1 0 –1 –2 0 –20 0.1 0 –0.1 –0.2 –3 –0.3 –4 –0.4 –5 64k Point FFT, FIN = 162.4MHz, –1dBFS, PGA = 0 AMPLITUDE (dBFS) 4 DNL ERROR (LSB) 0.5 0 49152 16384 32768 ADC OUTPUT CODE 9001 G04 HD3 –80 –20 –20 AMPLITUDE (dBFS) 0 –40 –60 HD3 HD2 6553 –120 0 12288 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) HD2 –100 9001 G06 64k Point 2-Tone FFT, FIN = 161.5MHz, and 163.5MHz, –7dBFS, PGA = 0 0 –120 –60 9001 G05 64k Point FFT, FIN = 162.4MHz, –1dBFS, PGA = 1 –80 –40 –100 –0.5 65536 33544 9001 G03 Differential Non-Linearity (DNL) vs Output Code 5 AMPLITUDE (dBFS) INL ERROR (LSB) Best Fit Integral Non-Linearity (INL) vs Output Code 49152 16384 32768 ADC OUTPUT CODE 33524 33504 ADC OUTPUT CODE 9001 G02 9001 G01 0 0 33484 –40 –60 –80 –100 0 12288 20480 28672 4096 FFT BIN NUMBER (32k TOTAL) 9001 G07 –120 0 12288 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) 9001 G08 9001fa 9 LTM9001 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT, FIN = 162.4MHz, –15dBFS, PGA = 0, Dither “Off” 64k Point FFT, FIN = 162.4MHz, –15dBFS, PGA = 0, Dither “On” 0 0 –20 –20 –20 –40 –60 –80 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 64k Point 2-Tone FFT, FIN = 161.5MHz, and 163.5MHz, –15dBFS, PGA = 0 –40 –60 –80 –120 0 –120 12288 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) 0 140 40 84 SFDR (dBc) AND SNR (dBFS) SFDR (dBc AND dBFS) 60 12288 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) SFDR and SNR vs Sample Rate, FIN = 162.4MHz, –1dBFS, PGA = 0 SFDR dBc SFDR dBFS 120 80 0 9001 G11 SFDR vs Input Level, FIN = 162.4MHz, PGA = 0, Dither = “On” SFDR dBc SFDR dBFS 100 –80 9001 G10 SFDR vs Input Level, FIN = 162.4MHz, PGA = 0, Dither = “Off” 120 –60 –120 12288 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) 9001 G09 140 –40 –100 –100 –100 SFDR (dBc AND dBFS) (LTM9001-AA) 100 80 60 40 SNR SFDR 80 76 72 68 20 20 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 64 0 0 200 150 50 100 ADC SAMPLE RATE (Msps) 9001 G14 9001 G13 9001 G12 250 SFDR vs VCC Supply Voltage, FIN = 162.4MHz, –1dBFS, PGA = 0 SFDR vs Input Common-Mode Voltage, FIN = 162.4MHz, –1dBFS, PGA = 0 81.0 90 80.5 85 80.0 79.5 SFDR (dBc) SFDR (dBc) 80 75 70 79.0 78.5 78.0 77.5 77.0 65 76.5 60 0.5 75.5 2.8 76.0 2.5 2.0 1.0 1.5 INPUT COMMON-MODE VOLTAGE (V) 3.0 9001 G15 2.9 3.0 3.1 3.2 3.3 3.4 INPUT COMMON-MODE VOLTAGE (V) 3.5 9001 G16 9001fa 10 LTM9001 TYPICAL PERFORMANCE CHARACTERISTICS Differential Non-Linearity (DNL) vs Output Code Best Fit Integral Non-Linearity (INL) vs Output Code 0.8 0.4 DNL ERROR (LSB) DNL ERROR (LSB) 0.6 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 16384 49152 32768 OUTPUT CODE 65536 SNR vs Frequency 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 71 69 67 65 SNR (dB) 1.0 0 (LTM9001-BA) 63 61 59 57 55 53 0 16384 49152 32768 OUTPUT CODE 51 65536 1 10 100 IF FREQUENCY (MHz) 1000 9001 G19 9001 G17 9001 G18 Input Impedance vs Frequency IF Frequency Response 400 0 0 MAGNITUDE –5 –8 PHASE 250 200 –16 150 100 –24 AMPLITUDE (dBFS) 300 IMPEDANCE PHASE (°C) IMPEDANCE MAGNITUDE (Ω) 350 –15 –20 –25 50 0 –10 1 –30 –32 1000 10 100 FREQUENCY (MHz) 1 10 100 IF FREQUENCY (MHz) 1000 9001 G20 64k Point FFT, fIN = 250MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 64k Point 2-Tone FFT, fIN = 136MHz, –7dBFS Per Tone, PGA = 0, RAND “Off”, Dither “Off” 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 HD3 HD2 –80 AMPLITUDE (dBFS) 0 –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 64k Point FFT, fIN = 140MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 9001 G21 –40 HD3 –50 –60 HD2 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 50 20 30 40 FREQUENCY (MHz) 60 9001 G22 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 9001 G23 0 10 50 20 30 40 FREQUENCY (MHz) 60 9001 G24 9001fa 11 LTM9001 PIN FUNCTIONS Supply Pins VCC (Pins E1, E2): 3.3V Analog Supply Pin for Amplifier. The voltage on this pin provides power for the amplifier stage only and is internally bypassed to GND. VDD (Pins E5, D5): 3.3V Analog Supply Pin for ADC. This supply is internally bypassed to GND. OVDD (Pins A6, G9): Positive Supply for the ADC Output Drivers. This supply is internally bypassed to OGND. GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1, F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground. OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground. Analog Inputs IN+ (Pin G1): Positive (Non-Inverting) Amplifier Input. IN– (Pin H1): Negative (Inverting) Amplifier Input. DNC (Pins C3, D3): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They may be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. ENC+ (Pin C1): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. This input is internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. The Encode pins have a differential 100Ω input impedance. ENC– (Pin B1): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC–. This input is internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1μF capacitor for a single-ended Encode signal. The Encode pins have a differential 100Ω input impedance. Control Inputs SENSE (Pin J3): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set the maximum full scale input range. AMPSHDN (Pin H3): Power Shutdown Pin for Amplifier. This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down amplifier with typically 3mA amplifier supply current. MODE (Pin G3): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin F3): Digital Output Randomization Selection Pin. RAND = low results in normal operation. RAND = high selects D1 to D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin E3): Programmable Gain Amplifier Control Pin. PGA = low selects the normal (maximum) input voltage range. PGA = high selects a 3.5dB reduced input range for slightly better distortion performance at the expense of SNR. ADCSHDN (Pin B3): Power Shutdown Pin for ADC. ADCSHDN = low results in normal operation. ADCSHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin A3): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. LVDS (Pin F5): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. 9001fa 12 LTM9001 PIN FUNCTIONS Digital Outputs CLKOUTB (Pin E7): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. For CMOS Mode, Full Rate or Demultiplexed DA0 to DA15 (Pins E9 to H5): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. OFA (Pin G5): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under flow has occurred on the A bus. CLKOUTA (Pin E8): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. For LVDS Mode, STANDARD or LOW POWER D0–/D0+ to D15–/D15+ (Pins B5 to G6): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D15+/D15– is the MSB. OFB (Pin E6): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under flow has occurred on the B bus. OFB is in a high impedance state in full rate CMOS mode. CLKOUT–/CLKOUT+ (Pins E6, E7): LVDS Data Valid Output. Latch data on the rising edge of CLKOUT+, falling edge of CLKOUT–. DB0 to DB15 (Pins B5 to D9): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in a high impedance state in full rate CMOS mode. OF–/OF+ (Pins H5, G5): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred. Pin Configuration (LVDS Outputs/CMOS Outputs) 1 2 3 4 5 6 7 8 D14–/DA11 D12+/DA8 D12–/DA7 9 OGND J GND GND SENSE GND D14+/DA12 H IN– GND AMPSHDN GND OF–/DA15 D15–/DA13 D13–/DA9 D11–/DA5 D11+/DA6 G IN+ GND MODE GND OF+/OFA D15+/DA14 D13+/DA10 OGND OVDD D9–/DA1 D9+/DA2 D10–/DA3 D10+/DA4 F GND GND RAND GND LVDS E VCC VCC PGA GND VDD D GND GND DNC GND VDD D6–/DB12 D6+/DB13 D7–/DB14 D7+/DB15 C ENC+ GND DNC GND D0+/DB1 D4–/DB8 D4+/DB9 D5–/DB10 D5+/DB11 B ENC– GND ADCSHDN GND D0–/DB0 D1–/DB2 D1+/DB3 D3+/DB7 D3–/DB6 A GND GND DITH GND OGND OVDD D2–/DB4 D2+/DB5 OGND CLKOUT–/OFB CLKOUT+/CLKOUTB D8–/CLKOUTA D8+/DA0 9001fa 13 LTM9001 PIN FUNCTIONS Top View of LGA Pinout (Looking Through Component) ALL ELSE = GND TOP VIEW CONTROL 1 2 3 DATA 4 5 6 7 8 9 OGND J IN– H IN+ G OVDD F VCC E DNC D ENC+ C ENC– B A OGND CONTROL VDD OGND OVDD 9001 LGA01 9001fa 14 AMPSHDN SENSE AMPSHDN IN– IN + VCC PGA RANGE SELECT VOLTAGE REFERENCE INPUT AMPLIFIER PGA ANTI-ALIAS FILTER ADC REFERENCE DITHER SIGNAL GENERATOR INPUT S/H ENC+ 100Ω ENC– DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER INTERNAL CLOCK SIGNALS FIRST PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE ADCSHDN RAND MODE LVDS DITH CONTROL LOGIC SHIFT REGISTER AND ERROR CORRECTION SECOND PIPELINED ADC STAGE OGND 9001 BD OUTPUT DRIVERS FIFTH PIPELINED ADC STAGE OF– OF+ CLKOUT– CLKOUT+ D15± … D0± OVDD VDD LTM9001 FUNCTIONAL BLOCK DIAGRAM 9001fa 15 LTM9001 OPERATION DYNAMIC PERFORMANCE DEFINITIONS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is defined as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Aperture Delay Time Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = –20Log ⎛ (V22 + V32 + V42 + ...Vn2 )/V1⎞ ⎝ ⎠ where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. Aperture Delay is the time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) DESCRIPTION Intermodulation Distortion If the input signal consists of more than one spectral component, the transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the input, nonlinearities in the transfer function can create The LTM9001 is an integrated System in a Package (SiP) μModule™ receiver that includes a high-speed, sampling 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It is designed for digitizing high frequency, wide dynamic range signals with an Intermediate Frequency (IF) range up to 300MHz. μModule is a trademark of Linear Technology Corporation. 9001fa 16 LTM9001 OPERATION The following sections describe in further detail the functional operation of the LTM9001. The SiP technology allows the LTM9001 to be customized and this is described in the first section. The remaining outline follows the basic functional elements as shown in Figure 1. AMPLIFIER ADC INPUT NETWORK ADC 9001 F01 Figure 1. Basic Functional Elements SEMI-CUSTOM OPTIONS The μModule construction affords a new level of flexibility in application-specific standard products. Standard ADC and amplifier components can be integrated regardless of their process technology and matched with passive components to a particular application. The LTM9001-AA, as the first example, is configured with a 16-bit ADC sampling at rates up to 130Msps. The amplifier gain is 20dB with an input impedance of 200Ω and an input range of 250mVP-P. The matching network is designed to optimize the interface between the amplifier output and the ADC under these conditions. Additionally, there is a 2-pole band pass filter designed for 162.5MHz ±25MHz. However, other options are possible through Linear Technology’s semi-custom development program. Linear Technology has in place a program to deliver other speed, resolution, IF range, gain and filter configurations for a wide range of applications. See Table 1 for the LTM9001-AA configuration and potential options. These semi-custom designs are based on existing ADCs and amplifiers with an appropriately modified matching network. The final subsystem is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested and reliable solution. For more details on the semi-custom receiver subsystem program, contact Linear Technology. Note that not all combinations of options in Table 1 are possible at this time and specified performance may differ significantly from existing values. AMPLIFIER INFORMATION The amplifiers used in the LTM9001 are low noise and low distortion fully differential ADC drivers. The amplifiers are very flexible in terms of I/O coupling. They can be AC- or DC-coupled at the inputs. Users are advised to keep the input common mode voltage between 1V and 1.6V for proper operation. If the inputs are AC-coupled, the input common mode voltage is automatically biased. The input signal can be either single-ended or differential with almost no difference in distortion performance. Table 1. Semi-Custom Options AMPLIFIER IF AMPLIFIER INPUT AMPLIFIER GAIN RANGE IMPEDANCE 300MHz 200Ω 14dB 300MHz 400Ω 8dB Select Combination of Options from Columns Below DC-300MHz 50Ω 26dB DC-140MHz 200Ω 20dB DC-70MHz 200Ω 14dB DC-35MHz 400Ω 8dB 200Ω 6dB FILTER 162.5MHz BPF, 50MHz BW DC-300MHz LPF LPF TBD BPF TBD ADC SAMPLE RATE 130Msps 160Msps ADC RESOLUTION 16-bit 16-bit 160Msps 130Msps 105Msps 80Msps 65Msps 40Msps 25Msps 10Msps 16-bit 14-bit PART NUMBER LTM9001-AA LTM9001-BA 9001fa 17 LTM9001 OPERATION ADC INPUT NETWORK CONVERTER INFORMATION The passive network between the amplifier output stage and the ADC input stage can be configured for bandpass or low-pass response with different cut-off frequencies and bandwidths. The LTM9001-AA, for example, implements a 2-pole band-pass filter centered at 162.5MHz with 50MHz bandwidth. Note that the filter attenuates the signal at 162.5MHz by 1dB, making the overall gain of the subsystem 19dB. The analog-to-digital converter (ADC) is a CMOS pipelined multistep converter with a front-end PGA. As shown in the Functional Block Diagram, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The encode input is differential for improved common mode noise immunity. For production test purposes the filter is designed to allow DC inputs into the ADC. APPLICATIONS INFORMATION INPUT SPAN The LTM9001 is configured with a fixed input span and input impedance. With the amplifier gain and the ADC input network described above for LTM9001-AA, the full-scale input range of the driver circuit is 250mVP-P. The recommended ADC input span is achieved by tying the SENSE pin to VDD. However, the ADC input span can be changed by applying a DC voltage to the SENSE pin. 25Ω + – IN+ LTM9001 ZIN/2 RF ZIN/2 RF VIN RT 25Ω IN– Input Impedance and Matching 9001 F02 The differential input impedance of the LTM9001 can be 50Ω, 200Ω or 400Ω. In some applications the differential inputs may need to be terminated to a lower value impedance, e.g. 50Ω, in order to provide an impedance match for the source. Several choices are available. Figure 2. Input Termination for Differential 50Ω Input Impedance Using Shunt Resistor (See Table 2 for RT Values) LTM9001 One approach is to use a differential shunt resistor (Figure 2). Another approach is to employ a wide band transformer (Figure 3). Both methods provide a wide band match. The termination resistor or the transformer must be placed close to the input pins in order to minimize the reflection due to input mismatch. Table 2. Differential Amplifier Input Termination Values ZIN RT FIG 2 400Ω 57Ω 200Ω 66.5Ω 50Ω None 25Ω + – VIN 25Ω IN+ ZIN/2 RF IN– ZIN/2 RF • • 9001 F03 Figure 3. Input Termination for Differential 50Ω Input Impedance Using a Wideband Transformer 9001fa 18 LTM9001 APPLICATIONS INFORMATION Alternatively, one could apply a narrowband impedance match at the inputs for frequency selection and/or noise reduction. RS 50Ω + – Referring to Figure 4, amplifier inputs can be easily configured for single-ended input without a balun. The signal is fed to one of the inputs through a matching network while the other input is connected to the same impedance. In general, the single-ended input impedance and termination resistor RT are determined by the combination of RS, ZIN/2 and RF. LTM9001 IN+ ZIN/2 RF IN– ZIN/2 RF VIN RT 0.1μF RS/RT 0.1μF 9001 F04 Figure 4. Input Termination for Differential 50Ω Input Impedance Using Shunt Resistor Table 3. Single-Ended Amplifier Input Termination Values ZIN 0.1μF RT FIG 4 400Ω 59Ω 200Ω 68.5Ω 50Ω 150Ω Rs/2 The LTM9001 amplifier is stable with all source impedances. The overall differential gain is affected by the source impedance in Figure 5: + – IN+ LTM9001 ZIN/2 RF ZIN/2 RF VIN RT AV = | VOUT/VIN | = (1000/(RS + ZIN/2)) The noise performance of the amplifier also depends upon the source impedance and termination. For example, an input 1:4 transformer in Figure 3 improves the input noise figure by adding 6dB voltage gain at the inputs. Rs/2 IN– 9001 F05 Figure 5. Calculate Differential Gain Reference and SENSE Pin Operation Figure 6 shows the converter reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. There are three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in the maximum full scale range. RANGE SELECT AND GAIN CONTROL INTERNAL ADC REFERENCE SENSE PGA 2.5V BANDGAP REFERENCE 9001 F06 Figure 6. Reference Circuit 9001fa 19 LTM9001 APPLICATIONS INFORMATION PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = low selects the maximum input span; PGA = high selects a 3.5dB lower input span. The high input range has the best SNR. For applications with high linearity requirements, the low input range will have improved distortion; however, the SNR will be 1.8dB worse. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the converter can depend on the encode signal quality as much as the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use the largest amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. LTM9001 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. The encode clock inputs have a differential 100Ω input impedance. For 50Ω inputs e.g. signal generators, an additional 100Ω impedance will provide an impedance match, as shown in Figure 7b. Maximum and Minimum Encode Rates The maximum encode rate for the LTM9001-AA is 130Msps and 160Msps for LTM9001-BA. For the ADC to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 3.65ns (LTM9001-AA, or 2.97ns for LTM9001-BA) for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. VDD TO INTERNAL ADC CLOCK DRIVERS VDD 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 1.6V LTM9001 0.1μF ENC+ 6k T1 50Ω 100Ω • • + ENC 8.2pF 100Ω VDD 0.1μF 1.6V 50Ω 6k 0.1μF ENC– ENC– 9001 F07b T1 = M/A-COM ETC1-1-13 9001 F07a Figure 7a. Equivalent Encode Input Circuit Figure 7b. Transformer Driven Encode 9001fa 20 LTM9001 APPLICATIONS INFORMATION An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the sample rate is determined by the droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM9001 is 1Msps. ENC+ VTHRESHOLD = 1.6V 1.6V ENC– LTM9001 0.1μF 9001F8 Figure 8. Single-Ended ENC Drive, Not Recommended for Low Jitter DIGITAL OUTPUTS Digital Output Modes The LTM9001 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistive divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 4 shows the logic states for the LVDS pin. Table 4. LVDS Pin Function LVDS DIGITAL OUTPUT MODE 0V(GND) Full-Rate CMOS 1/3VDD Demultiplexed CMOS 2/3VDD Low Power LVDS VDD LVDS Digital Output Buffers (CMOS Modes) Figure 10 shows an equivalent circuit for a single output buffer in CMOS Mode, Full-Rate or Demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and eliminates the need for external damping resistors. LTM9001 OVDD VDD 3.3V MC100LVELT22 3.3V 261Ω Q0 261Ω LTM9001 OVDD ENC+ D0 DATA FROM LATCH 100Ω ENC– 0.5V TO 3.6V VDD PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT Q0 165Ω OGND 165Ω 9001 F09 9001 F10 Figure 9. ENC Drive Using a CMOS to PECL Translator Figure 10. Equivalent Circuit for a Digital Output Buffer 9001fa 21 LTM9001 APPLICATIONS INFORMATION As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTM9001 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43Ω on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Digital Output Buffers (LVDS Modes) In Low Power LVDS Mode 1.75mA is steered between the differential outputs, resulting in ±175mV at the LVDS receiver’s 100Ω termination resistor. The output common mode voltage is 1.2V, the same as standard LVDS Mode. Data Format The LTM9001 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistive divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 5 shows the logic states for the MODE pin. Table 5. MODE Pin Function Figure 11 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT– or vice versa, which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.2V. For proper operation each LVDS output pair must be terminated with an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER 0V(GND) Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF– pins indicates an overflow or underflow. LTM9001 OVDD 3.3V 3.5mA VDD VDD OVDD 43Ω DATA FROM LATCH PREDRIVER LOGIC 10k 10k OVDD 100Ω LVDS RECEIVER 43Ω 1.20V + – OGND 9001 F11 Figure 11. Equivalent Output Buffer in LVDS Mode 9001fa 22 LTM9001 APPLICATIONS INFORMATION Output Clock LTM9001 CLKOUT The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. OF OF D15 In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises. D15/D0 D14 In Full Rate CMOS Mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. CLKOUT D14/D0 • • • D2 D2/D0 D1 RAND = HIGH, RANDOMIZER ENABLED D1/D0 RAND D0 D0 Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. 9001 F12 Figure 12. Functional Equivalent of Digital Output Randomizer PC BOARD FPGA CLKOUT OF By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. D15 ⊕ D0 D15 D14 ⊕ D0 The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. D14 LTM9001 D2 ⊕ D0 • • • D2 D1 ⊕ D0 D1 D0 D0 9001 F13 Figure 13. Derandomizing a Randomized Digital Output 9001fa 23 LTM9001 APPLICATIONS INFORMATION For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In LVDS Mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND. Internal Dither The LTM9001 is a 16-bit receiver subsystem with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 14, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC will cause a small elevation in the noise floor of the ADC, as compared to the noise floor with dither off. For best noise performance with the dither signal on, the driving impedance connected across pins IN+/IN– should closely match that of the module (see Table 1). A source impedance that is resistive and matches that of the module within 10% will give the best results. Supply Sequencing The VCC pin provides the supply to the amplifier and the VDD pin provides the supply to the ADC. The amplifier and the ADC are separate integrated circuits within the LTM9001; however, there are no supply sequencing considerations beyond standard practice. It is recommended that the amplifier and ADC both use the same low noise, 3.3V supply, but the amplifier may be operated from a lower voltage level if desired. Both devices can operate from the same 3.3V linear regulator but place a ferrite bead between the VCC and VDD pins. Separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. LTM9001 IN + IN – 16-BIT PIPELINED ADC CORE S/H AMP CLOCK/DUTY CYCLE CONTROL PRECISION DAC DIGITAL SUMMATION CLKOUT OF D15 • • • D0 OUTPUT DRIVERS MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 9001 F14 ENC+ – DITH ENC DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit 9001fa 24 LTM9001 APPLICATIONS INFORMATION Grounding and Bypassing Recommended Layout The LTM9001 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTM9001 has been optimized for a flow-through layout so that the interaction between inputs and digital outputs is minimized. A continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The high integration of the LTM9001 makes the PC board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary, see Figures 15-18. The LTM9001 is internally bypassed with the amplifier (VCC) and ADC (VDD) supplies returning to a common ground (GND). The digital output supply (0VDD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is significant. The differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTM9001 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. • Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the LTM9001, but can be connected on the PCB underneath the part to provide a common return path. • Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. • Separate analog and digital traces as much as possible, using vias to create high-frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the LTM9001. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The LTM9001 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear. com/designtools/leadfree/mat_dec.jsp. 9001fa 25 LTM9001 APPLICATIONS INFORMATION Figure 15. Layer 1 Figure 16. Layer 2 Figure 17. Layer 3 Figure 18. Layer 4 9001fa 26 1.270 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5.080 3.810 2.540 1.270 0.000 0.9525 1.5875 2.540 3.810 1.5875 1.270 0.9525 SUGGESTED PCB LAYOUT TOP VIEW 0.000 PACKAGE TOP VIEW X 3.810 11.250 BSC Y aaa Z 1.90 – 2.10 DETAIL A MOLD CAP Z 0.27 – 0.37 SUBSTRATE LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A MARKED FEATURE SYMBOL TOLERANCE aaa 0.15 0.10 bbb 6. THE TOTAL NUMBER OF PADS: 81 1.27 BSC 3 PADS SEE NOTES 10.160 BSC 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 0.25 × 45° CHAMFER ×3 9 TRAY PIN 1 BEVEL COMPONENT PIN “A1” 0.605 – 0.665 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 DETAIL A PACKAGE SIDE VIEW 2.17 – 2.47 bbb Z aaa Z 5.080 4 1.270 PAD 1 CORNER 5.080 11.250 BSC 8 6 5 4 LTMXXXXXX μModule PACKAGE BOTTOM VIEW 3 2 LGA 81 1107 REV A PACKAGE IN TRAY LOADING ORIENTATION 7 10.160 BSC 0.605 – 0.665 1 PAD 1 A B C D E F G H J LTM9001 PACKAGE DESCRIPTION LGA Package 81-Lead (11.25mm × 11.25mm × 2.32mm) (Reference LTC DWG # 05-08-1809 Rev A) 9001fa 27 5.080 3.810 2.540 2.540 LTM9001 TYPICAL APPLICATIONS LTM9001 with Ground-Referenced Single-Ended Input 3.3V GROUND– REFERENCED SOURCE RS 50Ω 75Ω 75Ω IN+ LTM9001 + – 0V VCC IN– 51.1Ω 9001 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2202 16-Bit, 10Msps ADC 140mW, 81.6dB SNR, 100dB SFDR LTC2203 16-Bit, 25Msps ADC 220mW, 81.6dB SNR, 100dB SFDR LTC2204 16-Bit, 40Msps ADC 480mW, 79.1dB SNR, 100dB SFDR LTC2205 16-Bit, 65Msps ADC 610mW, 79dB SNR, 100dB SFDR LTC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR LTC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR LTC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR LTC2209 16-BIT, 160Msps ADC 1450mW, 77.1dB SNR, 100dB SFDR LTC6400-20/LTC6400-26 Low Noise, Low Distortion Differential Amplifier for 300MHz IF, Fixed Gain of 20dB or 26dB 3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF LTC6401-20/LTC6401-26 Low Noise, Low Distortion Differential Amplifier for 140MHz IF, Fixed Gain of 20dB or 26dB 3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF 9001fa 28 Linear Technology Corporation LT 1108 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008