MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE PS21964-4S INTEGRATED POWER FUNCTIONS 600V/15A low-loss 5th generation IGBT inverter bridge for three phase DC-to-AC power conversion. Open emitter type. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • • • • • For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply). Input interface : 3V, 5V line (High Active). UL Approved : Yellow Card No. E80276 APPLICATION AC100V~200V inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES Dimensions in mm 38 ±0.5 20×1.778(=35.56 ) 35 ±0.3 A 3.5 B 3 MIN 18 (3.5) 14.4 ±0.5 Lot No. 29.2 ±0.5 Code 33.7 ±0.5 Type name 18.9 ±0.5 12 QR 24 ±0.5 .6 R1 (3.3) 1 14.4 ±0.5 17 (1) 16-0.5 2- TERMINAL CODE 1.5 ±0.05 0.4 0.28 1.778 ±0.2 0.8 HEAT SINK SIDE 0.28 2.54 ±0.2 8-0.6 4-C1.2 14×2.54(=35.56) (2.656) (1.2) 0.5 5.5 ±0.5 HEAT SINK SIDE 2.5 MIN 0.5 9.5 ±0.5 0.5 (VNC) VUFB VVFB VWFB UP VP WP VP1 VNC * UN VN WN VN1 FO CIN VNC * NC NW NV NU W V U P NC 1.5m in (0°~5°) 0.5 0.4 25 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. (1.2) (2.756) DETAIL A DETAIL B *) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open. Mar. 2007 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Condition Applied between P-NU, NV, NW Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Ratings Applied between P-NU, NV, NW TC = 25°C TC = 25°C, less than 1ms TC = 25°C, per 1 chip (Note 1) 450 500 600 15 30 33.3 –20~+125 Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C). CONTROL (PROTECTION) PART Symbol Parameter VD VDB Control supply voltage Control supply voltage VIN Input voltage VFO IFO VSC Fault output supply voltage Fault output current Current sensing input voltage Condition Ratings Unit Applied between VP1-VNC, VN1-VNC Applied between VUFB-U, VVFB-V, VWFB-W Applied between UP, VP, WP, UN, VN, WN-VNC Applied between FO-VNC 20 20 V V –0.5~VD+0.5 V –0.5~VD+0.5 1 –0.5~VD+0.5 V mA V Ratings Unit 400 V –20~+100 –40~+125 °C 1500 Vrms Sink current at FO terminal Applied between CIN-VNC TOTAL SYSTEM Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2µs (Note 2) Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Storage temperature Viso 60Hz, Sinusoidal, 1 minute, Between pins and heat-sink plate Isolation voltage °C Note 2: TC measurement point Control terminals 11.6mm DIP-IPM 3mm IGBT chip position TC point FWD chip position Heat sink side Power terminals Mar. 2007 2 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Condition Parameter Junction to case thermal resistance (Note 3) Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Min. — — Limits Typ. — — Max. 3.0 3.9 Unit °C/W °C/W Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM and heat-sink. The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and the thermal conductivity is 1.0W/m·k. ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Condition Parameter Collector-emitter saturation voltage FWD forward voltage Switching times IC = 15A, Tj = 25°C VD = VDB = 15V VIN = 5V IC = 15A, Tj = 125°C Tj = 25°C, –IC = 15A, VIN = 0V VCC = 300V, VD = VDB = 15V IC = 15A, Tj = 125°C, VIN = 0 ↔ 5V Inductive load (upper-lower arm) Collector-emitter cut-off current Tj = 25°C VCE = VCES Tj = 125°C Min. — — — Limits Typ. 0.70 — — — — — — 1.70 1.80 1.70 1.30 0.30 0.50 1.60 0.50 — — Max. 2.20 2.30 2.20 1.90 — 0.75 2.20 0.80 1 10 Min. — — — — 4.9 — 0.43 0.70 10.0 10.5 10.3 10.8 20 — 0.8 Limits Typ. — — — — — — 0.48 1.00 — — — — — 2.1 1.3 Max. 2.80 0.55 2.80 0.55 — 0.95 0.53 1.50 12.0 12.5 12.5 13.0 — 2.6 — 0.35 0.65 — Unit V V µs µs µs µs µs mA CONTROL (PROTECTION) PART Symbol ID VFOH VFOL VSC(ref) IIN UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Vth(hys) Parameter Circuit current Fault output voltage Short circuit trip level Input current Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage ON/OFF threshold hysteresis voltage Condition VD = VDB = 15V Total of VP1-VNC, VN1-VNC VIN = 5V VUFB-U, VVFB-V, VWFB-W Total of VP1-VNC, VN1-VNC VD = VDB = 15V VIN = 0V VUFB-U, VVFB-V, VWFB-W VSC = 0V, FO terminal pull-up to 5V by 10kΩ VSC = 1V, IFO = 1mA Tj = 25°C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj ≤ 125°C Trip level Reset level (Note 5) Applied between UP, VP, WP, UN, VN, WN-VNC Unit mA V V V mA V V V V µs V V V Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. 5 : Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure. Mar. 2007 3 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Condition Parameter Mounting screw : M3 Recommended : 0.69 N·m (Note 6) Mounting torque Weight Heat-sink flatness Note 6 : Plain washers (ISO 7089~7094) are recommended. (Note 7) Min. Limits Typ. Max. 0.59 — 0.78 N·m — –50 10 — — 100 g µm Min. Limits Typ. Max. 0 13.5 13.0 –1 1.5 — 300 15.0 15.0 — — — 400 16.5 18.5 1 — 20 — — 7.5 — — 4.5 0.5 0.5 –5.0 — — — — — 5.0 Unit Note 7: Flatness measurement position Measurement position 4.6mm + – DIP-IPM Heat sink side – + Heat sink side RECOMMENDED OPERATION CONDITIONS Symbol Parameter VCC VD VDB ∆VD, ∆VDB tdead fPWM Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency IO Allowable r.m.s. current Condition Applied between P-NU, NV, NW Applied between VP1-VNC, VN1-VNC Applied between VUFB-U, VVFB-V, VWFB-W For each input signal, TC ≤ 100°C TC ≤ 100°C, Tj ≤ 125°C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal PWM, (Note 8) fPWM = 15kHz Tj ≤ 125°C, TC ≤ 100°C PWIN(on) Allowable minimum input PWIN(off) pulse width VNC variation VNC (Note 9) Unit V V V V/µs µs kHz Arms Between VNC-NU, NV, NW (including surge) Note 8 : The allowable r.m.s. current value depends on the actual application conditions. 9 : IPM might not make response if the input signal pulse width is less than the recommended minimum value. µs V Mar. 2007 4 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 THE DIP-IPM INTERNAL CIRCUIT DIP-IPM VUFB P HVIC VP1 VCC VUB UP UP UOUT VNC VVFB VP IGBT1 Di1 VUS COM U IGBT2 VVB Di2 VOUT VP VVS VWFB WP V VWB WP IGBT3 Di3 IGBT4 Di4 IGBT5 Di5 WOUT VWS W LVIC UOUT VN1 VCC NU VOUT UN UN VN VN WN WN Fo Fo NV IGBT6 Di6 WOUT CIN NW VNO VNC GND CIN Mar. 2007 5 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE Fig. 3 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO outputs (tFO(min) = 20µs). a6. Input “L” : IGBT OFF. a7. Input “H” : IGBT ON. a8. IGBT OFF in spite of input “H”. Lower-side control input a6 a7 Protection circuit state SET Internal IGBT gate RESET a3 a2 a1 SC a4 Output current Ic a8 SC reference voltage Sense voltage of the shunt resistor CR circuit time constant DELAY Error output Fo a5 [B] Under-Voltage Protection (Lower-side, UVD) b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO outputs (tFO ≥ 20µs and FO outputs continuously during UV period). b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VD RESET UVDr b1 SET UVDt b2 RESET b6 b3 b4 b7 Output current Ic Error output Fo b5 Mar. 2007 6 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (Upper-side, UVDB) c1. Control supply voltage rising : After the voltage level reaches UVDBr, the circuits start to operate when next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UVDBt). c4. IGBT OFF in spite of control input signal level, but there is no FO signal outputs. c5. Under voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET RESET SET UVDBr Control supply voltage VDB c1 UVDBt c2 c5 c3 c4 c6 Output current Ic High-level (no fault output) Error output Fo Fig. 4 RECOMMENDED MCU I/O INTERFACE CIRCUIT 5V line DIP-IPM 10kΩ UP,VP,WP,UN,VN,WN MCU 3.3kΩ (min) Fo VNC(Logic) Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the wiring impedance of the printed circuit board. The DIP-IPM input section integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage. Fig. 5 WIRING CONNECTION OF SHUNT RESISTOR DIP-IPM Each wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100µm, length=17mm VNC NU NV NW Shunt resistors Please make the GND wiring connection of shunt resistor to the VNC terminal as close as possible. Mar. 2007 7 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21964-4S TRANSFER-MOLD TYPE INSULATED TYPE Fig. 6 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT C1: Electrolytic capacitor with good temperature characteristics C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering C2 C1 C2 C1 C2 C1 Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. VUFB VVFB VWFB DIP-IPM P HVIC VP1 C3 UP VCC UP VUB UOUT U VUS VVB VP VP VOUT V VVS M VWB WP VNC WP COM WOUT W VWS MCU LVIC UOUT VN1 5V line NU VCC C3 VOUT UN VN WN Fo UN NV VN WN WOUT Fo CIN NW VNO VNC C Long wiring here might cause short-circuit. GND CIN 15V line Long wiring here might cause SC level fluctuation and malfunction. Long GND wiring here might generate noise to input and cause IGBT malfunction. Shunt resistors A B R1 + - Vref - Vref C4 B R1 + - C4 B R1 + OR Logic N1 Vref Comparator C4 External protection circuit Note 1 : Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage. 2 : Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 3 : FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ. 4 : To prevent erroneous protection, the wiring of A, B, C should be as short as possible. 5 : The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4. 6 : All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.) 7 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended. 8 : Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open. 9 : It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. 10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point. 11 : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V). 12 : OR logic output high level should exceed the maximum short circuit trip level (Vsc(ref): max.0.53V). Mar. 2007 8