UCC1895 UCC2895 UCC3895 application INFO available BiCMOS Advanced Phase Shift PWM Controller FEATURES DESCRIPTION • Programmable Output Turn-on Delay • • • • • • • The UCC3895 is a phase shift PWM controller that implements control of a full-bridge power stage by phase shifting the switching of one half-bridge Adaptive Delay Set with respect to the other. It allows constant frequency pulse-width modulaBidirectional Oscillator Synchronization tion in conjunction with resonant zero-voltage switching to provide high efficiency at high frequencies. The part can be used either as a voltage mode Capability for Voltage Mode or Current or current mode controller. Mode Control While the UCC3895 maintains the functionality of the UC3875/6/7/8 family Programmable Soft Start/Soft Stop and UC3879, it improves on that controller family with additional features and Chip Disable via a Single Pin such as enhanced control logic, adaptive delay set, and shutdown capability. Since it is built in BCDMOS, it operates with dramatically less supply 0% to 100% Duty Cycle Control current than it’s bipolar counterparts. The UCC3895 can operate with a 7MHz Error Amplifier maximum clock frequency of 1MHz. Operation to 1MHz The UCC3895 and UCC2895 are offered in the 20 pin SOIC (DW) pack- • Low Active Current Consumption (5mA Typical @ 500kHz) age, 20 pin PDIP (N) package, 20 pin TSSOP (PW) package, and 20 pin PLCC (Q). The UCC1895 is offered in the 20 pin CDIP (J) package, and 20 pin CLCC package (L). • Very Low Current Consumption During Undervoltage Lock-out (150mA typical) SIMPLIFIED APPLICATION DIAGRAM UCC3895 1 EAN 2 EAOUT 3 Q1 EAP 20 7 SS/DISB 19 RAMP OUTA 18 4 REF OUTB 17 5 GND PGND 16 6 SYNC VCC 15 7 CT OUTC 14 VOUT A VIN VBIAS B 8 RT OUTD 13 9 DELAB CS 12 10 DELCD ADS 11 C D UDG-98139 SLUS157B - DECEMBER 1999 - REVISED JANUARY 2001 UCC1895 UCC2895 UCC3895 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Supply Voltage (IDD < 10mA) . . . . . . . . . . . . . . . . . . . . . . . 17V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA REF current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Analog inputs (EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB) . . . . . . . . . . . –0.3V to REF+0.3V Power Dissipation at TA=+25°C (N Package). . . . . . . . . . . . 1W Power Dissipation at TA=+25°C (D Package) . . . . . . . . 650mW Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature (soldering, 10 sec). . . . . . . . . . . . . . +300°C DIL-20,c SOIC-20, TSSOP-20 (TOP VIEW) J or N Package, DW Package, PW Package TEMPERATURE & PACKAGE SELECTION TABLE TEMPERATURE RANGE –55°C to +125°C –40°C to +85°C 0°C to +70°C UCC1895 UCC2895 UCC3895 PACKAGE SUFFIX J, L DW, N, PW, Q DW, N, PW, Q 1 20 EAP EAOUT 2 19 SS/DISB RAMP 3 18 OUTA REF 4 17 OUTB GND 5 16 PGND SYNC 6 15 VDD CT 7 14 OUTC RT 8 13 OUTD DELAB 9 12 CS DELCD 10 11 ADS PLCC-20, CLCC-20 (TOP VIEW) Q Package, L Package EAN EAOUT RAMP ORDERING INFORMATION UCC EAN 895 EAP SS/DISB 3 PACKAGE SUFFIX TEMPERATURE RANGE 2 1 20 19 REF 4 18 OUTA GND 5 17 OUTB SYNC 6 16 PGND CT 7 15 VDD RT 8 14 OUTC 9 10 11 12 13 OUTD DELAB DELCD CS ADS ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kW, CT=220pF, RDELAB=10kW, RDELCD=10kW, CREF=0.1mF, CVDD=1.0mF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for UCC2895x, and –55°C to +125°C for UCC1895x. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Start Threshold 10.2 11 11.8 Stop Threshold 8.2 9 9.8 V Hysteresis 1.0 2.0 3.0 V 150 250 mA 5 6 mA 17.5 18.5 V UVLO Section V Supply Current Start-up Current VDD = 8V IDD Active VDD Clamp Voltage IDD = 10mA 16.5 2 UCC1895 UCC2895 UCC3895 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kW, CT=220pF, RDELAB=10kW, RDELCD=10kW, CREF=0.1mF, CVDD=1.0mF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for UCC2895x, and –55°C to +125°C for UCC1895x. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TJ = 25°C 4.94 5.00 5.06 V 10V < VDD < 17.5V, 0mA < IREF < 5mA, Temperature 4.85 5 5.15 V 10 20 Voltage Reference Section Output Voltage Short Circuit Current REF = 0V, TJ = 25°C mA Error Amplifier Section Common Mode Input Voltage Range Offset Voltage Input Bias Current (EAP, EAN) –0.1 3.6 V –7 7 mV 1 mA 4.0 4.5 5.0 V 0 0.2 0.4 1.0 1.5 mA 2.5 4.5 mA 75 85 dB –1 EAOUT VOH EAP–EAN = 500mV, IEAOUT= –0.5mA EAOUT VOL EAP–EAN = –500mV, IEAOUT= 0.5mA EAOUT Source Current EAP–EAN = 500mV, EAOUT= 2.5V EAOUT Sink Current EAP–EAN = –500mV, EAOUT= 2.5V, (Note 4) Open Loop DC Gain V Unity Gain Bandwidth (Note 3) 5.0 7.0 MHz Slew Rate EAN from 1V to 0V, EAP = 500mV, EAOUT from 0.5V to 3.0V, (Note 3) 1.5 2.2 V/ms 0.45 0.50 No Load Comparator Turn-Off Threshold 0.55 V No Load Comparator Turn-On Threshold 0.55 0.60 0.69 V No Load Comparator Hysteresis 0.035 0.100 0.165 V 473 500 527 kHz 2.5 5 % SYNC VIH 2.05 2.10 2.25 V SYNC VIL 1.85 1.90 1.95 V Oscillator Section Frequency TJ = 25°C Total Variation Line, Temperature (Note 3) SYNC VOH ISYNC = –400mA, CT = 2.6V 4.1 4.5 5.0 V SYNC VOL ISYNC = 100mA, CT = 0V 0.0 0.5 1.0 V SYNC Output Pulse Width SYNC Load = 3.9kW and 30pF in parallel RT Voltage CT Peak Voltage 85 135 ns 2.9 3 3.1 V 2.25 2.35 2.50 V CT Valley Voltage UCC2895, UCC3895 0.0 0.2 0.4 V CT Valley Voltage UCC1895 0.0 0.2 0.6 V PWM Comparator Section EAOUT to RAMP Input Offset Voltage RAMP = 0V, DELAB = DELCD = REF 0.72 0.85 1.05 V Minimum Phase Shift (OUTA to OUTC, OUTB to OUTD) RAMP = 0V, EAOUT = 650mV (Note 1) 0.00 0.85 1.40 % RAMP to OUTC/OUTD Delay RAMP from 0V to 2.5V, EAOUT = 1.2V, DELAB = DELCD = REF (Note 2) 70 120 ns RAMP Bias Current RAMP < 5V, CT < 2.2V –5 RAMP Sink Current RAMP = 5V, CT < 2.6V 12 5 19 mA mA Current Sense Section CS Bias Current 0 < CS , 2.5V, 0 < ADS < 2.5V –4.5 20 mA Peak Current Threshold 1.90 2.00 2.10 V Overcurrent Threshold 2.4 2.5 2.6 V 75 110 ns CS to Output Delay CS from 0 to 2.3V, DELAB = DELCD = REF 3 UCC1895 UCC2895 UCC3895 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kW, CT=220pF, RDELAB=10kW, RDELCD=10kW, CREF=0.1mF, CVDD=1.0mF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for UCC2895x, and –55°C to +125°C for UCC1895x. PARAMETER TEST CONDITIONS MIN TYP –40 –35 MAX UNITS Soft Start/Shutdown Section Soft Start Source Current SS/DISB = 3.0V, CS < 1.9V Soft Start Sink Current SS/DISB = 3.0V, CS > 2.6V Soft Start/Disable Comparator Threshold –30 mA 325 350 375 mA 0.44 0.50 0.56 V Delay Set Section DELAB/DELCD Output Voltage ADS = CS = 0V 0.45 0.50 0.55 V ADS = 0V, CS = 2.0V 1.9 2.0 2.1 V Output Delay ADS = CS = 0V (Notes 2 and 3) 450 525 600 ns ADS Bias Current 0V < ADS < 2.5V, 0V < CS < 2.5V –20 20 mA Output Section VOH (all outputs) IOUT = –10mA, VDD to Output 250 400 mV VOL (all outputs) IOUT = 10mA 150 250 mV Rise Time CLOAD = 100pF, (Note 3) 20 35 ns Fall Time CLOAD = 100pF, (Note 3) 20 35 ns Φ = 200 • Φ = 200 • tPERIOD t f ( OUTA ) − t f ( OUTC ) tPERIOD t f ( OUTB ) − t f ( OUTD ) OUTA tPERIOD tDELAY = tf(OUTA) - tf(OUTC) OUTC OUTA tDELAY = tf(OUTA) - tr(OUTB) OUTB 4 UCC1895 UCC2895 UCC3895 PIN DESCRIPTIONS ADS: Adaptive Delay Set. This function sets the ratio between the maximum and minimum programmed output delay dead time. When the ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2.0V (the Peak Current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by the following formula: DELAB, DELCD: Delay Programming Between Complementary Outputs. DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the external bridge. The UCC3895 allows the user to select the delay, in which the resonant switching of the external power stages takes place. Separate delays are provided for the two half-bridges to accommodate differences in resonant capacitor charging currents. The delay in each stage is set according to the following formula: VDEL = [0 .75 • ( VCS − VADS )] + 0 .5 V where VCS and VADS are in Volts. ADS must be limited to between 0V and 2.5V and must be less than or equal to CS. DELAB and DELCD also will be clamped to a minimum of 0.5V. tDELAY = ( 25 • 10 −12 ) • RDEL VDEL + 25 ns EAOUT: Error Amplifier Output. It is also connected internally to the non-inverting input of the PWM comparator and the no-load comparator. EAOUT is internally clamped to the soft start voltage. The no-load comparator shuts down the output stages when EAOUT falls below 500mV, and allows the outputs to turn-on again when EAOUT rises above 600mV. where VDEL is in Volts, and RDEL is in Ohms and tDELAY is in seconds. DELAB and DELCD can source about 1mA maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay can be defeated by tying DELAB and/or DELCD to REF. For an optimum performance keep stray capacitance on these pins at <10pF. CT: Oscillator Timing Capacitor. (Refer to Fig. 1, Oscillator Block Diagram) The UCC3895’s oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak voltage of 2.35V. The approximate oscillator period is calculated by the following formula: EAP: The non-inverting input to the error amplifier. t OSC = EAN: The inverting input to the error amplifier. GND: Chip ground for all circuits except the output stages. 5 • RT • CT + 120 ns 48 OUTA, OUTB, OUTC, OUTD: The 4 outputs are 100mA complementary MOS drivers, and are optimized to drive FET driver circuits. OUTA and OUTB are fully complementary, (assuming no programmed delay). They operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power stage. OUTC and OUTD will drive the other half-bridge and will have the same characteristics as OUTA and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB. Note that changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients. where CT is in Farads, and RT is in Ohms and tOSC is in seconds. CT can range from 100pF to 880pF. Please note that a large CT and a small RT combination will result in extended fall times on the CT waveform. The increased fall time will increase the SYNC pulse width, hence limiting the maximum phase shift between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum duty cycle of the converter. CS: Current Sense. This is the inverting input of the Current Sense comparator and the non-inverting input of the Over-current comparator, and the ADS amplifier. The current sense signal is used for cycle-by-cycle current limiting in peak current mode control, and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called “soft stop”, with full soft start. PGND: Output Stage Ground. To keep output switching noise from critical analog circuits, the UCC3895 has 2 different ground connections. PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied together closely near the IC. Also, since PGND carries high current, board traces must be low impedance. 5 UCC1895 UCC2895 UCC3895 PIN DESCRIPTIONS (cont.) After a fault or disable condition has passed, VDD is above the start threshold, and/or SS/DISB falls below 0.5V during a soft stop, SS/DISB will switch to a soft start mode. The pin will now source current, equal to IRT. A user-selected capacitor on SS/DISB determines the soft start (and soft-start) time. In addition, a resistor in parallel with the capacitor may be used, limiting the maximum voltage on SS/DISB. Note that SS/DISB will actively clamp the EAOUT pin voltage to approximately the SS/DISB pin voltage during both soft start, soft stop, and disable conditions. RAMP: The Inverting Input of the PWM Comparator. This pin receives either the CT waveform in voltage and average current mode controls, or the current signal (plus slope compensation) in peak current mode control. An internal discharge transistor is provided on RAMP, which is triggered during the oscillator dead time. RT: Oscillator Timing Resistor. (Refer to Fig. 1, Oscillator Block Diagram) The oscillator in the UCC3895 operates by charging an external timing capacitor, CT, with a fixed current programmed by RT. RT current is calculated as follows: IRT = SYNC: Oscillator Synchronization. (Refer to Fig. 1, Oscillator Block Diagram) This pin is bidirectional. When used as an output, SYNC can be used as a clock, which is the same as the chip’s internal clock. When used as an input, SYNC will override the chip’s internal oscillator and act as it’s clock signal. This bidirectional feature allows synchronization of multiple power supplies. The SYNC signal will also internally discharge the CT capacitor and any filter capacitors that are present on the RAMP pin. The internal SYNC circuitry is level sensitive, with an input low threshold of 1.9V, and an input high threshold of 2.1V. A resistor as small as 3.9kW may be tied between SYNC and GND to reduce the sync pulse width. 3.0 V RT where RT is in Ohms and IRT is in Amperes. RT can range from 40kW to 120kW Soft start charging and discharging current are also programmed by IRT . SS/DISB: Soft Start/Disable. This pin combines the two independent functions. : A rapid shutdown of the chip is accomplished by any one of the following: externally forcing SS/DISB below 0.5V, externally forcing REF below 4V, VDD dropping below the UNLO threshold, or an overcurrent fault is sensed (CS = 2.5V). VDD: Power Supply. VDD must be bypassed with a minimum of a 1.0mF low ESR, low ESL capacitor to ground. In the case of REF being pulled below 4V or an UVLO condition, SS/DISB is actively pulled to ground via an internal MOSFET switch. If an overcurrent is sensed, SS/DISB will sink a current of (10 • IRT) until SS/DISB falls below 0.5V. REF: 5V, ±1.2% voltage reference. The reference supplies power to internal circuitry, and can also supply up to 5mA to external loads. The reference is shut down during undervoltage lock-out but is operational during all other disable modes. For best performance, bypass with a 0.1mF low ESR, low ESL capacitor to ground. Note that if SS/DISB is externally forced below 0.5V the pin will start to source current equal to IRT. Also note that the only time the part switches into the low IDD current mode is when the part is in undervoltage lockout. APPLICATION INFORMATION Programming DELAB, DELCD, and the Adaptive Delay Set The UCC3895 allows the user to set the delay between switch commands within each leg of the full bridge power circuit according to the following formula from the data sheet: tDELAY UCC3895 ( 25 • 10 −12 ) • RDEL = + 25n sec VDEL 9 DELAB 10 DELCD CS 12 ADS 11 RDELAB For this equation VDEL is determined in conjunction with the desire to utilize (or not utilize) the adaptive delay set feature from the following formula: RDELCD VDEL = [0.75 • ( VCS − VADS )] + 0.5 V The following diagram illustrates the resistors needed to program the delay periods and the adaptive delay set function. 6 UCC1895 UCC2895 UCC3895 APPLICATION INFORMATION (CONT.) The Adaptive Delay Set feature (ADS) allows the user to vary the delay times between switch commands within each of the converter’s two legs. The delay time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive divider from CS to GND to set VADS. From the equation for VDEL above, if ADS is tied to GND then VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this condition the maximum value of VDEL is 2V. If ADS is connected to a resistive divider between CS and GND the term (VCS-VDS) becomes smaller, reducing the level of VDEL. This will decrease the amount of delay modulation. In the limit of ADS tied to CS, VDEL=0.5V and no delay modulation occurs. In the case with maximum delay modulation (ADS=GND), when the circuit goes from light load to heavy load the variation of VDEL is from 0.5V to 2V. This causes the delay times to vary by a 4:1 ratio as the load is changed. ing the UC3879. Implementing this adaptive feature is simplified in the UCC3895 controller, giving the user the ability to tailor the delay times to suit a particular application with a minimum of external parts. A = VADS/VCS RDELAY = 10kW A=1.0 DELAY TIME (ns) 500 400 A=0.8 300 A=0.6 200 100 0 0.5 1.0 1.5 A=0.4 A=0.2 A=0.1 2.0 2.5 CURRENT SENSE VOLTAGE (V) The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of the current flowing in the primary winding of the transformer, and can change by a factor of 10:1 or more as circuit loading changes. Reference [1] delves into the many interrelated factors for choosing the optimum delay times for the most efficient power conversion, and illustrates an external circuit to enable adaptive delay set us- [1] L. Balogh, Unitrode Power Supply Design Seminar Manual, Unitrode Corporation, 1996, Topic 2. CLOCK RAMP & COMP PWM SIGNAL OUTPUT A OUTPUT B OUTPUT C OUTPUT D UDG-98138 7 UCC1895 UCC2895 UCC3895 APPLICATION INFORMATION (cont.) IRT RT Q 8 8(IRT) CT 7 Q R SYNC 15 D S Q OSC Q D S Q 6 R Q DELAY B D S Q DELAY C PWM COMPARATOR RAMP 0.8 V EAOUT 20 EAN 1 ERROR AMP + CURRENT SENSE COMPARATOR 2V + NO LOAD COMPARATOR + R Q DELAB 17 OUTB 14 DELAY D 12 2.5 V IRT + HI=ON Q S DELCD 13 OUTD 16 PGND 11 ADS Q R 4 REF 5 GND 0.5V UVLO COMPARATOR + 11 V / 9 V DISABLE COMPARATOR REF 0.5 V REFERENCE OK COMPARATOR + 19 10 ADAPTIVE DELAY SET AMPLIFIER + REF OUTC 0.5 V / 0.6 V OVER CURRENT COMPARATOR SS 9 + 2 EAP CS OUTA + 3 18 DELAY A VDD + HI=ON 4V 10(IRT) UDG-98140 8 UCC1895 UCC2895 UCC3895 CIRCUIT DESCRIPTION REF 8IRT RT RT VREF IRT CT 2.5 V S Q CLOCK + CT + 0.2 V R SYNC CLOCK UDG-98141 REF 0.5 V 100 kΩ 75 kΩ TO DELAY A AND DELAY B BLOCKS + CS DELAB + 100 kΩ ADS 75 kΩ REF + TO DELAY C AND DELAY D BLOCKS DELCD UDG-98142 9 UCC1895 UCC2895 UCC3895 CIRCUIT DESCRIPTION (cont.) VREF BUSSED CURRENT FROM ADS CIRCUIT 3.5V DELAB/CD FROM PAD DELAYED CLOCK SIGNAL 2.5V CLOCK UDG-98143 TYPICAL CHARACTERISTIC Vcs=2V GAIN (dB) 1800 1400 200 80 160 GAIN (dB) OUTPUT DELAY (ns) 1600 PHASE MARGIN (°C) 100 1200 1000 800 60 120 40 80 20 40 600 400 PHASE MARGIN (DEGREES) Vcs=0V 2000 200 0 0 10 20 30 0 40 0 1 RDEL (kW) 100 RT=47K RT=62k 1000000 RT=82k RT=100k 1600 0.95 FREQUENCY (kHz) EAOUT TO RAMP OFFSET (V) 1 10000 FREQUENCY (Hz) 0.9 0.85 1400 1200 1000 800 600 400 200 0.8 -60 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 100 120 10 CT (pF) 1000 UCC1895 UCC2895 UCC3895 TYPICAL CHARACTERISTIC (cont.) Vdd=10V Vdd=12V Vdd=15V Vdd=10V Vdd=17V Vdd=12V Vdd=15V Vdd=17V 13 9 12 11 Idd (mA) Idd (mA) 8 7 6 10 9 8 7 6 5 5 4 4 0 400 800 1200 1600 0 OSCILLATOR FREQUENCY (kHz) 11 400 800 1200 OSCILLATOR FREQUENCY (kHz) 1600 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC1895J ACTIVE CDIP J 20 1 None UCC1895L ACTIVE LCCC FK 20 1 None Lead/Ball Finish A42 SNPB MSL Peak Temp (3) Level-NC-NC-NC POST-PLATE Level-NC-NC-NC UCC2895DW ACTIVE SOIC DW 20 25 None CU SNPB Level-2-220C-1 YEAR UCC2895DWTR ACTIVE SOIC DW 20 2000 None CU SNPB Level-2-220C-1 YEAR UCC2895N ACTIVE PDIP N 20 20 None CU SNPB Level-NA-NA-NA UCC2895PW ACTIVE TSSOP PW 20 70 None CU NIPDAU Level-2-220C-1 YEAR UCC2895PWTR ACTIVE TSSOP PW 20 2000 None CU NIPDAU Level-2-220C-1 YEAR UCC2895PWTRG4 PREVIEW TSSOP PW 20 2000 None Call TI Call TI UCC2895Q ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UCC2895QTR ACTIVE PLCC FN 20 1000 None CU SNPB Level-2-220C-1 YEAR UCC3895DW ACTIVE SOIC DW 20 25 None CU SNPB Level-2-220C-1 YEAR None CU SNPB Level-2-220C-1 YEAR CU NIPDAU Level-1-260C-UNLIM UCC3895DWTR ACTIVE SOIC DW 20 2000 UCC3895DWTRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) UCC3895N ACTIVE PDIP N 20 20 None CU SNPB Level-NA-NA-NA UCC3895PW ACTIVE TSSOP PW 20 70 None CU NIPDAU Level-2-220C-1 YEAR UCC3895PWTR ACTIVE TSSOP PW 20 2000 None CU NIPDAU Level-2-220C-1 YEAR UCC3895PWTRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3895Q ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UCC3895QTR ACTIVE PLCC FN 20 1000 None CU SNPB Level-2-220C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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