application INFO available UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A Current Mode PWM Controller FEATURES • Optimized for Off-line and DC to DC Converters • Low Start Up Current (<0.5mA) • Trimmed Oscillator Discharge Current • Automatic Feed Forward Compensation • Pulse-by-Pulse Current Limiting • Enhanced Load Response Characteristics • Under-Voltage Lockout With Hysteresis • Double Pulse Suppression • High Current Totem Pole Output • Internally Trimmed Bandgap Reference • 500kHz Operation • Low RO Error Amp DESCRIPTION The UC1842A/3A/4A/5A family of control ICs is a pin for pin compatible improved version of the UC3842/3/4/5 family. Providing the necessary features to control current mode switched mode power supplies, this family has the following improved features. Start up current is guaranteed to be less than 0.5mA. Oscillator discharge is trimmed to 8.3mA. During under voltage lockout, the output stage can sink at least 10mA at less than 1.2V for VCC over 5V. The difference between members of this family are shown in the table below. Maximum Duty Cycle Part # UVLO On UVLO Off UC1842A 16.0V 10.0V <100% UC1843A 8.5V 7.9V <100% UC1844A 16.0V 10.0V <50% UC1845A 8.5V 7.9V <50% BLOCK DIAGRAM Note 1: A/B A = DIL-8 Pin Number. B = SO-14 Pin Number. Note 2: Toggle flip flop used only in 1844A and 1845A. SLUS224A - SEPTEMBER 1994 - REVISED APRIL 2002 UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS (Note 1) PLCC-20, LCC-20 (TOP VIEW) Q, L Packages Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . 30V Supply Voltage (ICC mA) . . . . . . . . . . . . . . . . . . . . Self Limiting Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . . 5µJ Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . -0.3V to +6.3V Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . 10mA Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C Note 1. All voltages are with respect to Ground, Pin 5. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. Pin numbers refer to DIL package only. PACKAGE PIN FUNCTION FUNCTION PIN N/C 1 Comp 2 N/C 3-4 VFB 5 N/C 6 ISENSE 7 N/C 8-9 RT/CT 10 N/C 11 Pwr Gnd 12 Gnd 13 N/C 14 Output 15 N/C 16 VC 17 VCC 18 N/C 19 VREF 20 SOIC-14 (TOP VIEW) D Package DIL-8, SOIC-8 (TOP VIEW) J or N, D8 Package SOIC-WIDE16 (TOP VIEW) DW Package N/C 1 16 N/C N/C 2 15 VREF COMP 3 14 VCC VFB 4 13 VCC ISENSE 5 12 OUTPUT RT/CT 6 11 GND N/C 7 10 PWRGND N/C 8 9 N/C 2 UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –55°C ≤ TA ≤ 125°C for the UC184xA; –40°C ≤ TA ≤ 125°C for the UC284xAQ; –40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70°C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ; Pin numbers refer to DIL-8. PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Temp. Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit Oscillator Section Initial Accuracy Voltage Stability Temp. Stability Amplitude Discharge Current Error Amp Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current VOUT High VOUT Low Current Sense Section Gain Maximum Input Signal PSRR Input Bias Current Delay to Output Output Section Output Low Level Output High Level Rise Time Fall Time UVLO Saturation TEST CONDITIONS TJ = 25°C, IO = 1mA 12 ≤ VIN 25V 1 ≤ IO ≤ 20mA (Note 2, Note 7) Line, Load, Temp. 10Hz ≤ f ≤ 10kHz TJ = 25°C (Note 2) TA = 125°C, 1000Hrs. (Note 2) UC184xA\UC284xA MIN. TYP. MAX. MIN. 4.95 4.90 5.00 6 6 0.2 4.9 -30 TJ = 25°C (Note 6) 12 ≤ VCC ≤ 25V TMIN ≤ TA ≤ TMAX (Note 2) VPIN 4 peak to peak (Note 2) TJ = 25°C, VPIN 4 = 2V (Note 8) VPIN 4 = 2V (Note 8) 7.8 7.5 VPIN 1 = 2.5V 2.45 2 ≤ VO ≤ 4V TJ = 25°C (Note 2) 12 ≤ VCC ≤ 25V VPIN 2 = 2.7V, VPIN 1 = 1.1V VPIN 2 = 2.3V, VPIN 1 = 5V VPIN 2 = 2.3V, RL = 15k to ground VPIN 2 = 2.7V, RL = 15k to Pin 8 65 0.7 60 2 -0.5 5 (Note 3, Note 4) VPIN 1 = 5V (Note 3) 12 ≤ VCC ≤ 25V (Note 3) 2.85 0.9 -30 47 8.8 8.8 7.8 7.6 2.50 -0.3 90 1 70 6 -0.8 6 0.7 2.55 -1 2.42 3.15 1.1 VPIN 3 = 0 to 2V (Note 2) 3 1 70 -2 150 ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA TJ = 25°C, CL = 1nF (Note 2) TJ = 25°C, CL = 1nF (Note 2) VCC = 5V, ISINK = 10mA 0.1 15 13.5 13.5 50 50 0.7 0.4 2.2 13 12 52 0.2 5 1.7 8.3 25 -180 65 0.7 60 2 -0.5 5 1.1 2.85 0.9 -10 300 13 12 150 150 1.2 5.00 6 6 0.2 4.82 57 1 3 47 50 5 -100 5.05 20 25 0.4 5.1 UC384xA UNITS TYP. MAX. 50 5 -100 52 0.2 5 1.7 8.3 5.10 20 25 0.4 5.18 V mV mV mV/°C V 25 -180 µV mV mA 57 1 8.8 8.8 2.50 -0.3 90 1 70 6 -0.8 6 0.7 2.58 -2 3 1 70 -2 150 3.15 1.1 0.1 15 13.5 13.5 50 50 0.7 0.4 2.2 1.1 -10 300 150 150 1.2 kHz % % V mA mA V µA dB MHz dB mA mA V V V/V V dB µA ns V V V V ns ns V UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –55°C ≤ TA ≤ 125°C for the UC184xA; –40°C ≤ TA ≤ 125°C for the UC284xAQ; –40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70°C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ; Pin numbers refer to DIL-8. PARAMETER TEST CONDITIONS Under-Voltage Lockout Section Start Threshold Min. Operation Voltage After Turn On PWM Section Maximum Duty Cycle Minimum Duty Cycle Total Standby Current Start-Up Current Operating Supply Current VCC Zener Voltage UC184xA\UC284xA MIN. TYP. MAX. UC384xA UNITS MIN. TYP. MAX. x842A/4A x843A/5A x842A/4A x843A/5A 15 7.8 9 7.0 16 8.4 10 7.6 17 9.0 11 8.2 14.5 7.8 8.5 7.0 16 8.4 10 7.6 17.5 9.0 11.5 8.2 V V V V x842A/3A x844A/5A 94 47 96 48 100 50 0 94 47 96 48 100 50 0 % % % 0.5 17 30 0.3 11 34 0.5 17 30 0.3 11 34 mA mA V VPIN 2 = VPIN 3 = 0V ICC = 25mA Note 2: Ensured by design, but not 100% production tested. Note 3: Parameter measured at trip point of latch with VPIN2 = 0. ∆VPIN 1 ; 0 VPIN 3 0.8V. Note 4: Gain defined as: A = ∆VPIN 3 Note 5: Adjust VCC above the start threshold before setting at 15V. Note 6: Output frequency equals oscillator frequency for the UC1842A and UC1843A. Output frequency is one half oscillator frequency for the UC1844A and UC1845A. Note 7: “Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: VREF (max ) − VREF (min ) .VREF (max) and VREF (min) are the maximum & minimum reference voltTemp Stability = TJ (max ) − TJ (min ) age measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.” Note 8: This parameter is measured with RT = 10k to VREF.This contributes approximately 300 A of current to the measurement. The total current flowing into the RT/C pin will be approximately 300 A higher than the measured value. Error Amp Configuration Error Amp can Source and Sink up to 0.5mA, and Sink up to 2mA. 4 UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A Under-Voltage Lockout During UVLO, the Output is low. Current Sense Circuit Peak Current (IS) is Determined By The Formula 1.0V ISMAX ′ RS A small RC filter may be required to suppress switch transients. Output Saturation Characteristics Error Amplifier Open-Loop Frequency Response 5 UC1842A/3A/4A/5A UC2842A/3A/4A/5A APPLICATIONS DATA (cont.) Oscillator Section Oscillator Frequency vs Timing Resistance Maximum Duty Cycle vs Timing Resistor Open-Loop Laboratory Test Fixture High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Slope Compensation A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes. 6 UC1842A/3A/4A/5A UC2842A/3A/4A/5A UC3842A/3A/4A/5A APPLICATIONS DATA (cont.) Off-line Flyback Regulator 5. Output Voltage: A. +5V, ± 5%; 1A to 4A load Ripple voltage: 50mV P-P Max B. +12V, ± 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max C. -12V ,± 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max Power Supply Specifications 1. Input Voltage 2. Line Isolation 3. Switching Frequency 4. Efficiency Full Load 95VAC to 130VA (50 Hz/60Hz) 3750V 40kHz 70% 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-8670405PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670405VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670405VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8670405XA ACTIVE LCCC FK 20 1 None 5962-8670406PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670406VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670406VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8670406XA ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC POST-PLATE Level-NC-NC-NC 5962-8670407PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670407VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670407VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8670407XA ACTIVE LCCC FK 20 1 None 5962-8670408PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670408VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670408VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8670408XA ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC POST-PLATE Level-NC-NC-NC UC1842AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC1842AJ883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC1842AJQMLV ACTIVE CDIP JG 8 UC1842AL883B ACTIVE LCCC FK 20 UC1842ALQMLV ACTIVE LCCC FK 20 None 1 None Call TI Call TI POST-PLATE Level-NC-NC-NC None Call TI Call TI UC1843AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC1843AJ883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC1843AJQMLV ACTIVE CDIP JG 8 None Call TI UC1843AL883B ACTIVE LCCC FK 20 UC1843ALQMLV ACTIVE LCCC FK 20 UC1844AJ ACTIVE CDIP JG 8 1 None Call TI POST-PLATE Level-NC-NC-NC None Call TI 1 None A42 SNPB Call TI Level-NC-NC-NC 1 None A42 SNPB Level-NC-NC-NC None Call TI UC1844AJ883B ACTIVE CDIP JG 8 UC1844AJQMLV ACTIVE CDIP JG 8 UC1844AL883B ACTIVE LCCC FK 20 UC1844ALQMLV ACTIVE LCCC FK 20 None Call TI UC1845AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC1845AJ883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC1845AJQMLV ACTIVE CDIP JG 8 UC1845AL883B ACTIVE LCCC FK 20 UC1845ALQMLV ACTIVE LCCC FK 20 UC2842AD ACTIVE SOIC D 14 1 None None 1 None Call TI POST-PLATE Level-NC-NC-NC Call TI Call TI Call TI POST-PLATE Level-NC-NC-NC None Call TI 50 None CU NIPDAU Call TI Level-1-220C-UNLIM UC2842AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC2842AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC2842AD8TRG4 ACTIVE SOIC D 8 2500 None Call TI UC2842ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC2842ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR Addendum-Page 1 Call TI PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2005 Status (1) Package Type Package Drawing UC2842ADWTR ACTIVE SOIC DW 16 UC2842AJ OBSOLETE CDIP JG 8 UC2842AN ACTIVE PDIP P 8 Orderable Device Pins Package Eco Plan (2) Qty 2000 Lead/Ball Finish None CU NIPDAU None Call TI 50 Pb-Free (RoHS) CU SNPB MSL Peak Temp (3) Level-2-220C-1 YEAR Call TI Level-NC-NC-NC UC2843AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM UC2843AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC2843AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC2843ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC2843ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC2843ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC2843AJ OBSOLETE CDIP JG 8 None Call TI UC2843AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Level-NC-NC-NC UC2843AQ ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UC2844AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM Call TI UC2844AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC2844AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC2844AD8TRG4 PREVIEW SOIC D 8 2500 None Call TI UC2844ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM Call TI UC2844ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC2844ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC2844AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC2844AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Level-NC-NC-NC UC2844AQD ACTIVE SOIC D 14 50 None Call TI Level-1-220C-UNLIM UC2844AQD8 ACTIVE SOIC D 8 75 None Call TI Level-1-220C-UNLIM UC2844AQD8R ACTIVE SOIC D 8 2500 None Call TI Level-1-220C-UNLIM UC2844AQDR ACTIVE SOIC D 14 2500 None Call TI Level-1-220C-UNLIM UC2845AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM UC2845AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC2845AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC2845AD8TRG4 PREVIEW SOIC D 8 2500 None Call TI UC2845ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC2845ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC2845AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Call TI Level-NC-NC-NC UC3842AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM UC3842AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC3842AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC3842ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC3842ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC3842ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC3842AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC3842AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Level-NC-NC-NC Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UC3842ANG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-NA-NA-NA Lead/Ball Finish MSL Peak Temp (3) UC3843AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM UC3843AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC3843AD8G4 ACTIVE SOIC D 8 75 None Call TI UC3843AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC3843AD8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UC3843ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UC3843ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC3843AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC3843AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Level-NC-NC-NC UC3843ANG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-NA-NA-NA Call TI UC3844AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM UC3844AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC3844AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC3844AD8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UC3844ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC3844ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC3844ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC3844AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Level-NC-NC-NC UC3845AD ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM UC3845AD8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UC3845AD8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UC3845ADTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM UC3845ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC3845ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC3845AJ ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC UC3845AN ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU SNPB Level-NC-NC-NC UC3845ANG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2005 for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4