SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 D Complete Pulse-Width Modulation (PWM) D D D SG2524 . . . D OR N PACKAGE SG3524 . . . D, N, OR NS PACKAGE (TOP VIEW) Power-Control Circuitry Uncommitted Outputs for Single-Ended or Push-Pull Applications Low Standby Current . . . 8 mA Typ Interchangeable With Industry Standard SG2524 and SG3524 IN– IN+ OSC OUT CURR LIM+ CURR LIM– RT CT GND description/ordering information 1 16 2 15 3 14 4 13 5 12 6 11 7 10 REF OUT VCC EMIT 2 COL 2 COL 1 EMIT 1 SHUTDOWN COMP The SG2524 and SG3524 incorporate all the 9 8 functions required in the construction of a regulating power supply, inverter, or switching regulator on a single chip. They also can be used as the control element for high-power-output applications. The SG2524 and SG3524 were designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless voltage doublers, and polarity-converter applications employing fixed-frequency, pulse-width modulation (PWM) techniques. The complementary output allows either single-ended or push-pull application. Each device includes an on-chip regulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted pass transistors, a high-gain comparator, and current-limiting and shutdown circuitry. ORDERING INFORMATION TA INPUT REGULATION MAX (mV) PACKAGE† PDIP (N) 0°C to 70°C –25°C to 85°C 30 ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SG3524N Tube of 40 SG3524D Reel of 2500 SG3524DR SOP (NS) Reel of 2000 SG3524NSR SG3524 PDIP (N) Tube of 25 SG2524N SG2524N Tube of 40 SG2524D Reel of 2500 SG2524DR SOIC (D) 20 SOIC (D) SG3524N SG3524 SG2524 † Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ( $) (#" ! " !%$"" ! %$ *$ $! $+! ! #$ ! ! (( , -) (#" %"$!!. ($! $"$!!'- "'#($ $! . '' %$ $!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 functional block diagram VCC 15 16 Reference Regulator REF OUT Vref 12 Vref Vref RT Oscillator CURR LIM– SHUTDOWN Comparator 9 4 5 EMIT 2 OSC OUT – CURR LIM+ 2 + COMP 1 EMIT 1 COL 2 Vref Vref IN+ 14 3 6 CT 7 IN– 11 13 T COL 1 Error Amplifier Vref + – 10 1 kΩ 10 kΩ GND 8 NOTE A: Resistor values shown are nominal. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Collector output current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Reference output current, IO(ref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Current through CT terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 mA Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Package thermal impedance, θJA (see Notes 3 and 4): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. The reference regulator may be bypassed for operation from a fixed 5-V supply by connecting the VCC and reference output (REF OUT) pin both to the supply voltage. In this configuration, the maximum supply voltage is 6 V. 3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operation at the absolute maximum TJ of 150°C can impact reliability. 4. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 recommended operating conditions VCC MIN MAX Supply voltage 8 40 V Reference output current 0 50 mA –0.03 –2 mA Current through CT terminal RT CT Timing resistor 1.8 100 kΩ 0.001 0.1 µF SG2524 –25 85 SG3524 0 70 Timing capacitor TA Operating free-air free air temperature UNIT °C electrical characteristics over recommended operating free-air temperature range, VCC = 20 V, f = 20 kHz (unless otherwise noted) reference section PARAMETER TEST CONDITIONS† Output voltage SG2524 MIN TYP‡ 4.8 Input regulation Ripple rejection Output regulation Output voltage change with temperature Short-circuit output current§ MAX 5 5.2 VCC = 8 V to 40 V f = 120 Hz 10 20 IO = 0 mA to 20 mA TA = MIN to MAX 20 50 0.3% 1% SG3524 MIN TYP‡ 4.6 66 MAX 5 5.4 V 10 30 mV 20 50 mV 0.3% 1% 66 dB Vref = 0 100 100 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values, except for temperature coefficients, are at TA = 25°C § Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula: Ǹ UNIT mA ȍ (xn * X)2 s + N n+1 N*1 oscillator section PARAMETER fosc Oscillator frequency Standard deviation of frequency§ ∆fosc Frequency change with voltage Frequency change with temperature Output amplitude at OSC OUT TEST CONDITIONS† CT = 0.001 µF, RT = 2 kΩ All values of voltage, temperature, resistance, and capacitance constant VCC = 8 V to 40 V, TA = MIN to MAX MIN TYP‡ UNIT kHz 5% TA = 25°C 1% 2% 3.5 V tw Output pulse duration (width) at OSC OUT TA = 25°C 0.5 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values, except for temperature coefficients, are at TA = 25°C § Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula: µs Ǹ TA = 25°C CT = 0.01 µF, MAX 450 ȍ (xn * X)2 s + N n+1 N*1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 error amplifier section TEST CONDITIONS† PARAMETER VIO IIB Input offset voltage SG2524 MIN TYP‡ VIC = 2.5 V VIC = 2.5 V Input bias current Open-loop voltage amplification VICR Common-mode input voltage range CMMR Common-mode rejection ratio B1 Unity-gain bandwidth MAX 0.5 5 2 10 72 80 1.8 to 3.4 TA = 25°C SG3524 MIN TYP‡ 60 MAX UNIT 2 10 mV 2 10 µA 80 dB 1.8 to 3.4 V 70 70 3 3 Output swing TA = 25°C 0.5 3.8 0.5 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values, except for temperature coefficients, are at TA = 25°C dB MHz 3.8 V output section TEST CONDITIONS† PARAMETER V(BR)CE Collector-emitter breakdown voltage Collector-emitter saturation voltage tr tf Turn-off voltage rise time TYP‡ MAX 40 Collector off-state current Vsat VO MIN VCE = 40 V IC = 50 mA Emitter output voltage VC = 20 V, RC = 2 kΩ IE = –250 µA 17 UNIT V 0.01 50 µA 1 2 V 18 V 0.2 µs Turn-on voltage fall time RC = 2 kΩ 0.1 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values, except for temperature coefficients, are at TA = 25°C. µs comparator section TEST CONDITIONS† PARAMETER Maximum duty cycle, each output MIN MAX UNIT 45% Zero duty cycle VIT TYP‡ Inp t threshold voltage Input oltage at COMP 1 Maximum duty cycle V 3.5 µA IIB Input bias current –1 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values, except for temperature coefficients, are at TA = 25°C. current limiting section TEST CONDITIONS† PARAMETER VI V(SENSE) Input voltage range (either input) MIN TYP‡ MAX UNIT 200 225 mV –1 to1 Sense voltage at TA = 25°C Temperature coefficient of sense voltage V(IN+) mV, V(COMP) = 2 V (IN ) – V(IN (IN–)) ≥ 50 mV 175 V 0.2 mV/°C ‡ All typical values, except for temperature coefficients, are at TA = 25°C. total device PARAMETER Ist Standby current TEST CONDITIONS VCC = 40 V, IN–, CURR LIM+, CT, GND, COMP, EMIT 1, EMIT 2 grounded, IN+ at 2 V, All other inputs and outputs open ‡ All typical values, except for temperature coefficients, are at TA = 25°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP‡ MAX 8 10 UNIT mA SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION VREF 2 kΩ VCC = 8 V to 40 V 10 kΩ 15 VCC SG2524 or SG3524 2 kΩ 10 2 10 kΩ 1 9 4 1 kΩ 5 SHUTDOWN 3 OSC OUT IN+ 16 REF OUT IN– VREF 13 COL 2 CURR LIM+ CURR LIM– Outputs 12 COL 1 14 11 EMIT 1 CT RT 2 kΩ 1W 0.1 µF EMIT 2 6 2 kΩ 1W COMP 2 kΩ 7 (Open) CT RT GND 8 Figure 1. General Test Circuit VCC Circuit Under Test tf 2 kΩ tr ≈VCC Output 90% 90% Output 10% TEST CIRCUIT 10% ≈0 V VOLTAGE WAVEFORMS Figure 2. Switching Times POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 OPEN-LOOP VOLTAGE AMPLIFICATION OF ERROR AMPLIFIER vs FREQUENCY 90 OSCILLATOR FREQUENCY vs TIMING RESISTANCE 1M RL = ∞ VCC = 20 V TA = 25°C 80 ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ 70 60 RL = 1 MΩ 50 RL = 300 kΩ 40 RL = 100 kΩ 30 CT = 0 CT = 0.001 µF CT = 0.003 µF CT = 0.01 µF 400 k f osc – Oscillator Frequency – Hz Open-Loop Voltage Amplification of Error Amplifier – dB TYPICAL CHARACTERISTICS RL = 30 kΩ 20 10 100 k 40 k 10 k 4k CT = 0.03 µF 1k CT = 0.1 µF 400 0 VCC = 20 V TA = 25°C RL is resistance from COMP to ground –10 100 1k 10 k 100 k 1M 100 10 M 1 2 Frequency – Hz 4 Figure 4 OUTPUT DEAD TIME vs TIMING CAPACITANCE 10 4 Output Dead Time – µs 10 1 0.4 0.1 0.001 20 40 RT – Timing Resistance – kΩ Figure 3 0.01 0.004 0.04 CT – Timing Capacitance – µF Figure 5 6 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.1 70 100 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 PRINCIPLES OF OPERATION† The SG2524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulator operates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator, providing linear control of the output pulse duration (width) by the error amplifier. The SG2524 contains an onboard 5-V regulator that serves as a reference, as well as supplying the SG2524 internal regulator control circuitry. The internal reference voltage is divided externally by a resistor ladder network to provide a reference within the common-mode range of the error amplifier as shown in Figure 6, or an external reference can be used. The output is sensed by a second resistor divider network and the error signal is amplified. This voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator then is steered to the appropriate output pass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to ensure both outputs are never on simultaneously during the transition times. The duration of the blanking pulse is controlled by the value of CT. The outputs may be applied in a push-pull configuration in which their frequency is one-half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from either of these inputs. This common point is pinned out externally via the COMP pin, which can be employed to either control the gain of the error amplifier or to compensate it. In addition, the COMP pin can be used to provide additional control to the regulator. APPLICATION INFORMATION† oscillator The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4. f [ 1.30 R C T T where: RT is in kΩ CT is in µF f is in kHz Practical values of CT fall between 0.001 µF and 0.1 µF. Practical values of RT fall between 1.8 kΩ and 100 kΩ. This results in a frequency range typically from 130 Hz to 722 kHz. blanking The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled by the value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration can be maintained by applying a shunt capacitance from OSC OUT to ground. synchronous operation When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RTCT must be selected for a clock period slightly greater than that of the external clock. † Throughout these discussions, references to the SG2524 apply also to the SG3524. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† synchronous operation (continued) If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tied together. The oscillator programmed for the minimum clock period is the master from which all the other SG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a period approximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensure that the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave regulators. voltage reference The 5-V internal reference can be employed by use of an external resistor divider network to establish a reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 6), or an external reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal reference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In this configuration, however, the input voltage is limited to a maximum of 6 V. To Positive Output Voltage REF OUT 5 kΩ R2 5 kΩ REF OUT 2.5 V R1 2.5 V + + – 5 kΩ – 5 kΩ R1 R2 To Negative Output Voltage V O + 2.5 V R1 ) R2 R1 V O ǒ Ǔ + 2.5 V 1 * R2 R1 Figure 6. Error-Amplifier Bias Circuits error amplifier The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain control or ac phase compensation. The compensation node (COMP) is a high-impedance node (RL = 5 MΩ). The gain of the amplifier is AV = (0.002 Ω–1)RL and easily can be reduced from a nominal 10,000 by an external shunt resistance from COMP to ground. Refer to Figure 3 for data. compensation COMP, as previously discussed, is made available for compensation. Since most output filters introduce one or more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier, introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best with a series RC circuit from COMP to ground in the range of 50 kΩ and 0.001 µF. Other frequencies can be canceled by use of the formula f ≈ 1/RC. † Throughout these discussions, references to the SG2524 apply also to the SG3524. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† shutdown circuitry COMP also can be employed to introduce external control of the SG2524. Any circuit that can sink 200 µA can pull the compensation terminal to ground and, thus, disable the SG2524. In addition to constant-current limiting, CURR LIM+ and CURR LIM– also can be used in transformer-coupled circuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LIM– also can be grounded to convert CURR LIM+ into an additional shutdown terminal. current limiting A current-limiting sense amplifier is provided in the SG2524. The current-limiting sense amplifier exhibits a threshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is limited to 1 V to –1 V. Caution should be taken to ensure the –1-V limit is not exceeded by either input, otherwise, damage to the device may result. Foldback current limiting can be provided with the network shown in Figure 7. The current-limit schematic is shown in Figure 8. EMIT 1 EMIT 2 11 14 VO R1 I + O(max) 1 Rs ǒ 200 mV ) V Ǔ R2 O R1 ) R2 SG2524 R2 CURR LIM– CURR LIM+ 5 I Rs OS + 200 mV Rs 4 Figure 7. Foldback Current Limiting for Shorted Output Conditions CT COMP Comparator Error Amplifier CURR LIM– Constant-Current Source CURR LIM+ Figure 8. Current-Limit Schematic † Throughout these discussions, references to the SG2524 apply also to the SG3524. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† output circuitry The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA for fast response. general There are a wide variety of output configurations possible when considering the application of the SG2524 as a voltage-regulator control circuit. They can be segregated into three basic categories: D Capacitor-diode-coupled voltage multipliers D Inductor-capacitor-implemented single-ended circuits D Transformer-coupled circuits Examples of these categories are shown in Figures 9, 10, and 11, respectively. Detailed diagrams of specific applications are shown in Figures 12–15. D1 VO VI VI > VO D1 VO VI VI < VO D1 –VO VI | +VI | > | – VO | Figure 9. Capacitor-Diode-Coupled Voltage-Multiplier Output Stages † Throughout these discussions, references to the SG2524 apply also to the SG3524. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† VO VI VI > VO VO VI VI < VO –VO VI | +VI | < | – VO | Figure 10. Single-Ended Inductor Circuit VI ÏÏ VO VO VI Flyback Push-Pull Figure 11. Transformer-Coupled Outputs † Throughout these discussions, references to the SG2524 apply also to the SG3524. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† VCC = 15 V 15 15 kΩ 5 kΩ 0.1 µF 1 5 kΩ 5 kΩ 2 16 2 kΩ 6 SG2524 3 EMIT 1 COL 1 IN+ 12 20 µF COL 2 13 RT EMIT 2 14 CURR LIM+ . CURR LIM– OSC OUT COMP –5 V 20 mA 11 REF OUT 7 C T 10 SHUTDOWN 0.01 µF 1N916 VCC IN– 1N916 + 4 5 1N916 9 + 50 µF GND 8 Figure 12. Capacitor-Diode Output Circuit VCC = 5 V 1N916 15 V + 100 µF 25 kΩ 15 5 kΩ 1 5 kΩ 2 IN+ 5 kΩ 16 2 kΩ 0.02 µF IN– 300 Ω VCC SG2524 EMIT 1 COL 1 REF OUT COL 2 6 R T EMIT 2 200 Ω 20T 11 12 0.1 µF 1 MΩ 20 mA + –15 V 1N916 14 TIP29A 1N916 620 Ω 2N2222 510 Ω 0.001 µF 4.7 µF + Input Return Figure 13. Flyback Converter Circuit †Throughout these discussions, references to the SG2524 apply also to the SG3524. POST OFFICE BOX 655303 + 50T 13 4 7 C T CURR LIM+ 10 5 SHUTDOWN CURR LIM– 3 9 OSC OUT COMP GND 50 µF 50 µF 8 12 50T • DALLAS, TEXAS 75265 1Ω SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† VCC = 28 V 5 kΩ 5 kΩ IN+ 16 REF OUT 6 7 0.02 µF 11 EMIT 1 SG2524 12 COL 1 IN– 2 3 kΩ 5V 1A VCC 1 5 kΩ 0.9 mH 15 5 kΩ 0.1 µF TIP115 COL 2 RT EMIT 2 CT CURR LIM+ + 13 500 µF 1N3880 3 kΩ 14 4 10 5 SHUT CURR LIM– DOWN 3 9 OSC OUT COMP GND 0.001 µF 8 50 kΩ 0.1 Ω Input Return Figure 14. Single-Ended LC Circuit VCC = 28 V 15 1 kΩ 1W VCC 11 5 kΩ 5 kΩ 1 5 kΩ 0.1 µF 5 kΩ 2 kΩ 0.01 µF IN– 2 IN+ 16 6 1 kΩ 1W COL 2 RT EMIT 2 7 C T CURR LIM+ TIR101A + 1 mH EMIT 1 SG2524 12 COL 1 REF OUT TIP31A + 100 Ω 20T 5T 20T 5T 13 100 Ω 1500 µF 5V 5A – 14 4 10 SHUT 5 CURR LIM– DOWN 9 3 COMP OSC OUT GND TIP31A 0.001 µF 0.1 Ω + 8 20 kΩ 100 µF Figure 15. Push-Pull Transformer-Coupled Circuit †Throughout these discussions, references to the SG2524 apply also to the SG3524. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SG2524D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SG2524DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SG2524DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SG2524DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SG2524J OBSOLETE CDIP J 16 SG2524N ACTIVE PDIP N 16 SG2524NE4 ACTIVE PDIP N SG3524D ACTIVE SOIC SG3524DE4 ACTIVE SG3524DR Lead/Ball Finish MSL Peak Temp (3) TBD Call TI Call TI 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SG3524DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SG3524J OBSOLETE CDIP J 16 SG3524N ACTIVE PDIP N 16 SG3524NE4 ACTIVE PDIP N 16 SG3524NSR ACTIVE SO NS 16 SG3524NSRE4 ACTIVE SO NS 16 TBD Call TI Call TI 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2005 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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