TI SN75LBC184P

SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
D
D
D
D
D
D
D
D
D
D
D
D
Integrated Transient Voltage Suppression
ESD Protection for Bus Terminals:
– ± 15 kV Human Body Model
– ± 8 kV IEC1000-4-2, Contact Discharge
– ± 15 kV IEC1000-4-2, Air-Gap Discharge
Circuit Damage Protection of 400 W Peak
(Typical)
Controlled Driver Output-Voltage Slew
Rates Allows Longer Cable Stub Lengths
250-kbits/s in Electrically Noisy
Environments
Open-Circuit Fail-Safe Receiver Design
1/2 Unit Load Allows for 64 Devices
Connected on Bus
Thermal Shutdown Protection
Power-Up/-Down Glitch Protection
Each Transceiver Meets or Exceeds the
Requirements of EIA RS-485 and ISO/IEC
8482:1993(E) Standards
Low Disabled Supply Current 300 µA Max
Pin Compatible with SN75176
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
functional logic diagram (positive logic)
3
DE
4
D
description
The SN75LBC184 and SN65LBC184 are differential data line transceivers in the trade-standard
footprint of the SN75176 with built-in protection
against high-energy noise transients. This feature
provides a substantial increase in reliability for
better immunity to noise transients coupled to the
data cable over most existing devices. Use of
these circuits provides a reliable low-cost
direct-coupled (with no isolation transformer) data
line interface without requiring any external
components.
The SN75LBC184 and SN65LBC184 can withstand overvoltage transients of 400 W peak
(typical). The conventional combination wave
called out in CEI IEC 1000-4-5 simulates the
overvoltage transient and models a unidirectional
surge caused by overvoltages from switching and
secondary lightning transients.
2
RE
6
1
R
7
A
B
Bus
V
± VP
± 1/2 VP
1.2 µs
50 µs
t
Figure 1. Surge Waveform — Combination Wave
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
description (continued)
A biexponential function defined by separate rise and fall times for voltage and current simulates the
combination wave. The standard 1.2 µs/50 µs combination waveform is shown in Figure 1 and in the test
description in Figure 9.
The device also includes additional desirable features for party-line data buses in electrically noisy environment
applications including industrial process control. The differential-driver design incorporates slew-rate-controlled
outputs sufficient to transmit data up to 250 kbits/s. Slew-rate control allows longer unterminated cable runs and
longer stub lengths from the main backbone than possible with uncontrolled and faster voltage transitions. A
unique receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit).
The SN75LBC184 and SN65LBC184 receiver also includes a high input resistance equivalent to one-half unit
load allowing connection of up to 64 similar devices on the bus.
The SN75LBC184 is characterized for operation from 0°C to 70°C. The SN65LBC184 is characterized from
– 40°C to 85°C.
DRIVER FUNCTION TABLE
INPUT
ENABLE
D
DE
A
H
H
H
L
L
H
L
H
X
L
Z
Z
H = high level,
X = irrelevant,
OUTPUTS
B
L = low level,
? = indeterminate,
Z = high impedance (off)
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
A–B
RE
R
VID ≥ 0.2 V
– 0.2 V < VID < 0.2 V
L
H
L
?
VID ≤ – 0.2 V
X
L
L
H
Z
Open
L
H
H = high level,
L = low level,
? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic symbol†
DE
RE
D
3
2
EN1
EN2
1
4
1
R
1
6
7
A
B
2
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
POST OFFICE BOX 655303
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SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V to 15 V
Data input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Electrostatic discharge:
All Terminals (Class 3 A) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 kV
All Terminals (Class 3 B) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 V
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating free-air temperature range, TA: SN65LBC184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
SN75LBC184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. The driver shuts down at a junction temperature of approximately 160°C. To operate below this temperature, see the Dissipation
Rating Table.
3. GND and bus terminal ESD ratings are beyond readily available test equipment capabilities for MIL-STD-883C method 3015.3.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70_C
POWER RATING
TA = 85_C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
P
1150 mW
9.2 mW/°C
736 mW
598 mW
PACKAGE
recommended operating conditions
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
MIN
TYP
MAX
UNIT
4.75
– 7‡
5
5.25
V
12
V
2
Differential input voltage, |VID|
High level output current,
High-level
current IOH
Low level output current,
Low-level
current IOL
Operating
O
erating free-air tem
temperature
erature, TA
V
0.8
12
Driver
V
V
– 60
mA
Receiver
–8
mA
Driver
60
Receiver
4
SN75LBC184
0
70
mA
°C
SN65LBC184
85
°C
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for input voltage,
common-mode input voltage, common-mode output voltage, and free-air temperature levels only.
– 40‡
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3
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
DRIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
ALTERNATE
SYMBOLS
PARAMETER
ICC
IIH
IIL
Supply current
NA
High-level input current (D, DE, RE)
NA
Low-level input current (D, DE, RE)
NA
TEST CONDITIONS
MIN
Short circuit output current
Short-circuit
(see Note 5)
NA
IOZ
High-impedance output current
NA
MAX
DE = RE = 5 V,,
No Load
SN75LBC184
12
25
SN65LBC184
12
30
DE = 0 V,
RE = 5 V
V,
No Load
SN75LBC184
175
300
SN65LBC184
175
300
VI = 2.4 V
VI = 0.4 V
VO = –7 V
IOS
TYP†
–120
Output voltage
VOC(PP)
Peak-to-peak change in commonmode output voltage during state
transitions
Voa, Vob
VOC
Common-mode output voltage
|∆VOC(SS)|
Magnitude of change, commonmode steady-state output voltage
|VOD|
Magnitude
M
it d off diff
differential
ti l output
t t
voltage |VA – VB| (see Note 4)
∆|VOD|
Change in differential voltage magnitude between logic states
NA
µA
µA
– 250
250
IO= 0‡
0
See Figures 5 and 6
|Vos – Vos|
See Figure 5
||Vt| – |Vt||
RL = 54 Ω,,
See Figure 4
RL = 54 Ω
1.5
TA ≥ 0°C
TA < 0°C
mA
6
0.8
1
IO = 0
Vo
mA
250
See Receiver II
See Figure 4
µA
±100
VO = VCC
|Vos|
mA
±100
VO = 12 V
VO
UNIT
V
V
3
V
0.2
V
6
V
1.5
V
1
V
0.2
V
† All typical values are measured with TA = 25°C and VCC = 5 V.
‡ IO = Iia, Iib. Iia and Iib are alternate symbols for input voltage.
NOTES: 4. The minimum VOD specification of the SN75LBC184 and the SN65LBC184 may not fully comply with ANSI RS-485 at operating
temperature below 0°C. System designers should take the possibly lower output signal into account in determining the maximum
signal-transmission distance.
5. This parameter is measured with only one output being driven at a time.
4
POST OFFICE BOX 655303
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SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
DRIVER SECTION (CONTINUED)
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
td(DH)
Differential output delay time, low-to-highlevel output
td(DL)
Differential-output delay time, high-to-lowlevel output
tPLH
Propagation delay time, low-to-high-level
output
tPHL
Propagation delay time, high-to-low-level
output
tsk(p)
tr
Pulse skew (| td(DH) – td(DL) |)
tf
tPZH
Fall time, single ended
tPZL
tPHZ
tPLZ
Rise time, single ended
RL = 54 Ω,,
CL = 15 pF
MIN
TYP
MAX
UNIT
1.5
µs
1.5
µs
0.5
1.5
µs
0.5
1.5
µs
75
g
See Figure
5
225
ns
0.25
1.8
µs
0.25
1.8
µs
RL = 54 Ω
Ω,
pF
CL = 15 pF,
Output enable time to high level
RL = 110 Ω,
See Figure 2
3.5
µs
Output enable time to low level
RL = 110 Ω,
See Figure 3
3.5
µs
Output disable time from high level
RL = 110 Ω,
See Figure 2
2
µs
Output disable time from low level
RL = 110 Ω,
See Figure 3
2
µs
POST OFFICE BOX 655303
See Figure 5
• DALLAS, TEXAS 75265
5
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
TEST CONDITIONS
Supply current (total package)
DE = RE = 0 V,
No Load
RE = 5 V,
No Load
DE = 0 V,
II
Input current
Other input = 0 V
IOZ
Vhys
High-impedance-state output current
VO = 0.4 V to 2.4 V
VIT +
VIT–
Positive-going input threshold voltage
VI = 12 V
VI = 12 V,
VI = – 7 V
VI = – 7 V,
MIN
TYP†
MAX
UNIT
3.9
mA
300
µA
500
VCC = 0
500
– 400
VCC = 0
– 400
± 100
Input hysteresis voltage
70
µA
mV
200
– 200‡
Negative-going input threshold voltage
µA
mV
mV
VOH
High-level output voltage
IOH = – 8 mA
Figure 7
2.7
V
VOL
Low-level output voltage
IOL = 4 mA
Figure 7
0.5
V
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for input voltage,
common-mode input voltage, common-mode output voltage and free-air temperature levels only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
ns
300
ns
100
ns
tPLH
tPHL
Propagation delay time, low-to-high-level output
tsk(p)
tr
Pulse skew (| tpHL – tpLH |)
tf
tPZH
Fall time, single ended
Output enable time to high level
300
ns
tPZL
tPHZ
Output enable time to low level
300
ns
300
ns
tPLZ
Output disable time from low level
300
ns
6
Propagation delay time, high-to-low-level output
Rise time, single ended
CL = 50 pF,
pF
See Figure 7
See Figure 7
See Figure 8
Output disable time from high level
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
ns
20
ns
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
Output
3V
S1
Input
1.5 V
1.5 V
0 or 3 V
Generator
(see Note A)
RL = 110 Ω
CL = 50 pF
(see Note B)
50 Ω
0V
0.5 V
tPZH
VOH
Output
2.3 V
tPHZ
TEST CIRCUIT
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms
5V
S1
3V
Input
RL = 110 Ω
0V
Output
0 or 3 V
Generator
(see Note A)
1.5 V
1.5 V
tPZL
tPLZ
CL = 50 pF
(see Note B)
50 Ω
2.3 V
Output
5V
0.5 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms
A
D
Input
27 Ω
VOD
IO(A)
27 Ω
II
VO(A)
Output
B
VOC
IO(B)
CL
VO(B)
CL
NOTES: A. Resistance values are in ohms and are 1% tolerance.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit, Voltage, and Current Definitions
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7
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
3V
Input
50%
50%
0V
tPHL
tPLH
VO(A)
10%
90%
50%
90%
50%
tr
tf
tPHL
90%
VO(B)
50%
10%
10%
∼ 3.5 V
∼ 2.3 V
∼1V
tPLH
50%
10%
tr
td(DH)
90%
∼ 3.5 V
∼ 2.3 V
∼1V
tf
td(DL)
∼ 2.5 V
0V
∼ – 2.5 V
VOD
VOC
VOC(PP)
∆VOC(SS)
Figure 5. Driver Timing, Voltage and Current Waveforms
8
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SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
A
27 Ω
VOD
D
27 Ω
Output
B
Inputs
VOC
DE
CL
CL
3V
DE
0V
Inputs
3V
D
0V
Output
VOC(PP)
NOTES: A. Resistance values are in ohms and are 1% tolerance.
B. CL includes probe and jig capacitance (± 10%).
Figure 6. Driver VOC(PP) Test Circuit and Waveforms
II
A
Input
VI
B
1.5 V
Inputs
RE
50%
VO
50 pF
(see Note A)
Output
3V
1.5 V
0V
50%
tPLH
Output
IO
R
VID
tPHL
90%
10%
tr
NOTE A: This value includes probe and jig capacitance (± 10%).
90%
10%
VOH
50%
VOL
tf
Figure 7. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms
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9
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
5V
A
620 Ω
0 V or 3 V
R
1.5 V
B
620 Ω
RE
50 pF
(see Note A)
VO
Input
3V
A
0V
3V
Inputs
RE
3V
1.5 V
0V
tPHZ
Output
VO
tPZH
0.5 V
0V
tPLZ
0.5 V
tPZL
∼ 2.5 V
VOH
∼ 2.5 V
0.5 V
0.5 V
NOTE A: This value includes probe and jig capacitance (± 10%).
Figure 8. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VOL
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
APPLICATION INFORMATION
’LBC184 test description
The ’LBC184 is tested against the CEI IEC 1000–4–5 recommended transient identified as the combination
wave. The combination wave provides a 1.2-/50-µs open-circuit voltage waveform and a 8-/20-µs short-circuit
current waveform shown in Figure 9. The testing is performed with a combination/hybrid pulse generator with
an effective output impedance of 2 Ω. The setup for the overvoltage stress is shown in Figure 10 with all testing
performed with power applied to the ’LBC184 circuit.
NOTE
High voltage transient testing is done on a sampling basis.
VI(peak)
II(peak)
0.5 VP
0.5 IP
1.2 µs
8 µs
t
50 µs
20 µs
t
Figure 9. Short-Circuit Current Waveforms
The ’LBC184 is tested and evaluated for both maximum (single pulse) as well as life test (multiple pulse)
capabilities. The ’LBC184 is evaluated against transients of both positive and negative polarity and all testing
is performed with the worst-case transient polarity. Transient pulses are applied to the bus pins (A & B) across
ground as shown in Figure 10.
Key Tech
1.2/50 – 8/20
Combination Pulse
Generator
2-Ω Internal Impedance
High
IP
41.9 Ω
3Ω
Low
7
Current
Limiter
VP
5
B/A
SN75LBC184
GND
Figure 10. Overvoltage-Stress Test Circuit
An example waveform as seen by the ’LBC184 is shown in Figure 11. The bottom trace is current, the middle
trace shows the clamping voltage of the device and the top trace is power as calculated from the voltage and
current waveforms. This example shows a peak clamping voltage of 16 V, peak current of 33.6 A yielding an
absorbed peak power of 538 W.
NOTE
A circuit reset may be required to ensure normal data communications following a transient noise
pulse of greater than 250 W peak.
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11
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
APPLICATION INFORMATION
Power
538 W Peak
0
16 V Peak,
VI(peak)
Clamping Voltage
0
33.6 A Peak,
II(peak)
Input Current
0
0
20
40
80
60
100
120
140
160
180
t – 20 µs/Div
Figure 11. Typical Surge Waveform Measured At Terminals 5 and 7
12
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SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Four center pins are connected to die mount pad.
Falls within JEDEC MS-012
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13
SN65LBC184, SN75LBC184
DIFFERENTIAL TRANSCEIVER
WITH TRANSIENT VOLTAGE SUPPRESSION
SLLS236A – OCTOBER 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
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