FAIRCHILD SG6741A

SG6741A — Highly Integrated Green-Mode PWM
Controller
Features
Description
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The highly integrated SG6741A series of PWM
controllers provides several features to enhance the
performance of flyback converters.
High-voltage Startup
Low Operating Current: 4mA
Linearly Decreasing PWM Frequency to 18kHz
Frequency Hopping to Reduce EMI Emissions
Peak-current-mode Control
Cycle-by-cycle Current Limiting
Leading-edge Blanking (LEB)
Synchronized Slope Compensation
GATE Output Maximum Voltage Clamp: 18V
VDD Over-voltage Protection (Auto Restart)
VDD Under-voltage Lockout (UVLO)
Internal Open-loop Protection
Constant Power Limit (Full AC Input Range)
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
ƒ
ƒ
Power Adapters
Open-Frame SMPS
To minimize standby power consumption, a proprietary
green-mode function provides off-time modulation to
linearly decrease the switching frequency at light-load
conditions. To avoid acoustic-noise problems, the
minimum PWM frequency is set above 18KHz. This
green-mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss
due to bleeding resistors is eliminated. To further
reduce power consumption, SG6741A is manufactured
using the BiCMOS process, which allows an operating
current of only 4mA.
SG6741A integrates a frequency-hopping function
internally to reduce EMI emission of a power supply
with minimum line filters. A built-in synchronized slope
compensation achieves stable peak-current-mode
control. The proprietary internal line compensation
ensures constant output power limit over a wide AC
input voltages, from 90VAC to 264VAC.
SG6741A provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety when an
open-loop or output short-circuit failure occurs. PWM
output is disabled until VDD drops below the UVLO lower
limit, when the controller starts up again. As long as VDD
exceeds ~26V, the internal OVP circuit is triggered.
SG6741A is available in an 8-pin SOP package.
Ordering Information
Part Number
SG6741ASZ
Operating
Temperature Range
-20 to +85°C
Package
8-Lead Small Outline Package (SOP)
Packing Method
Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
www.fairchildsemi.com
SG6741A — Highly Integrated Green-Mode PWM Controller
April 2008
Figure 1. Typical Application
Block Diagram
SG6741A — Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 2. Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
www.fairchildsemi.com
2
SG6741A — Highly Integrated Green-Mode PWM Controller
Marking Information
T: S = SOP
P: Z =Lead Free
Null=regular package
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location
SG6741ATP
XXXXXXXXYWWV
Figure 3. Top Mark
Pin Configuration
GND
GATE
FB
VDD
NC
SENSE
HV
RI
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
GND
2
FB
Feedback. The signal from the external compensation circuit is fed into this pin. The PWM
duty cycle is determined in response to the signal on this pin and the current-sense signal on
SENSE pin.
3
NC
No Connection.
4
HV
Start-up Input. For start-up, this pin is pulled HIGH to the line input or bulk capacitor via
resistors.
5
RI
Reference Setting. A resistor connected from the RI pin to GND pin provides a constant
current source, which determines the center PWM frequency. Increasing the resistance
reduces PWM frequency. Using a 26KΩ resistor for RI results in a 65kHz center PWM
frequency.
6
SENSE
7
VDD
8
GATE
Ground.
Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds
the OVP trigger point.
Driver Output. The totem-pole output driver. Soft driving waveform is implemented for
improved EMI.
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are
given with respect to the ground pin.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage
30
VHV
Input Voltage to HV Pin
500
VL
Input Voltage to FB, SENSE, Pin
PD
Power Dissipation, TA < 50°C
400
mW
ΘJA
Thermal Resistance (Junction-to Air)
141
°C/W
TJ
TSTG
TL
ESD
-.3
7.0
Operating Junction Temperature
-40
+125
°C
Storage Temperature Range
-55
+150
°C
+260
°C
Lead Temperature (Wave Soldering or IR,
10 Seconds)
Human Body Model, JESD22-A114
3
Machine Model, JESD22-A115
250
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
Min.
Max.
Unit
-20
+85
°C
SG6741A — Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
4
VDD = 15V; TA = 25°, unless otherwise noted.
VDD Section
Symbol
Parameter
VDD-OP
Continuously Operating Voltage
VDD-ON
Start Threshold Voltage
VDD-OFF
Minimum Operating Voltage
Conditions
Min.
Typ.
Max.
Units
22
V
V
15.5
16.5
17.5
9.5
10.5
11.5
V
30
µA
4
5
mA
50
70
90
µA
6.5
7.5
8.0
V
IDD-ST
Startup Current
VDD-ON – 0.16V
IDD-OP
Operating Supply Current
VDD = 15V
GATE Open
IDD-OLP
Internal Sink Current
VDD-OLP +0.1V
VDD-OLP
IDD-OLP off Voltage
VDD-OVP
VDD Over-Voltage Protection
Auto Restart
25
26
27
V
tD-VDDOVP
VDD Over-Voltage Protection
Debounce Time
Auto Restart
100
180
260
µs
HV Electrical Characteristics
Symbol
IHV
IHV-LC
Parameter
Conditions
Typ.
Max.
Supply Current Drawn from HV Pin
VAC=90V (VDC=120V),
VDD=10µF
2
Leakage Current After Startup
HV=500V, VDD=VDD-OFF+1V
1
20
Min.
Typ.
Max.
62
65
68
±3.7
±4.2
±4.7
Units
mA
µA
Oscillator Section
Symbol
Parameter
fOSC
Frequency in Nominal Mode
tHOP
Hopping Period
fOSC-G
Conditions
Center Frequency
Hopping Range
4.4
Green-Mode Frequency
16
18
Units
kHz
ms
21
kHz
fDV
Frequency Variation vs. VDD Deviation VDD=11V to 22V
5
%
fDT
Frequency Variation vs. Temperature
Deviation
5
%
Max.
Units
TA=-20 to 85°C
SG6741A — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
Feedback Input Section
Symbol
Parameter
AV
Input Voltage to Current-Sense
Attenuation
ZFB
Input Impedance
Conditions
Min.
Typ.
1/3.75
1/3.20 1/2.75
4
7
kΩ
VFB-OPEN
FB Output High Voltage
VFB-OLP
FB Open-loop Trigger Level
3.7
4.0
4.3
V
tD-OLP
The Delay Time of FB Pin Open-Loop
RI=26kΩ
Protection
50
56
62
ms
VFB-N
Green-Mode Entry FB Voltage
1.9
2.1
2.3
V
VFB-G
Green-Mode Ending FB Voltage
VFB-ZDC
FB Pin Open
V/V
Zero Duty-Cycle Input Voltage
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
5.5
V
VFB-N 0.5
V
1
V
www.fairchildsemi.com
5
PWM Frequency
f OSC
f OSC-
V FB-ZDC V FB-G
V FB-N
VFB
Figure 5. PWM Frequency
Current-Sense Section
Symbol
Parameter
ZSENSE
Input Impedance
VSTHFL
Current Limit Flatten Threshold Voltage
VSTHVA
Current Limit Valley Threshold Voltage
tPD
Delay to Output
tLEB
Leading-Edge Blanking Time
Conditions
Min.
Typ.
Max.
12
VSTHFL–VSTHVA
Units
KΩ
0.87
0.90
0.93
V
0.18
0.22
0.26
V
100
200
ns
275
350
425
ns
Min.
Typ.
Max.
Units
60
65
70
%
1.5
V
SG6741A — Highly Integrated Green-Mode PWM Controller
PWM Frequency
Gate Section
Symbol
Parameter
DCYMAX
Maximum Duty Cycle
VGATE-L
Gate Low Voltage
Conditions
VDD=15V, IO=50mA
VGATE-H
Gate High Voltage
VDD=12.5V, IO=-50mA
tr
Gate Rising Time
VDD=15V, CL=1nF
150
250
350
ns
tf
Gate Falling Time
VDD=15V, CL=1nF
30
50
90
ns
IGATE-SOURCE Gate Source Current
VDD=15V, GATE=6V
250
VGATE-CLAMP Gate Output Clamping Voltage
VDD=22V
DCYMAX
Maximum Duty Cycle
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
8
60
V
mA
65
18
V
70
%
www.fairchildsemi.com
6
25
5.0
4.0
15
IDD -OP (mA)
IDD -ST (µA)
20
10
5
3.0
2.0
1.0
0.0
0
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
-25
-10
5
20.0
13.0
19.0
12.0
18.0
17.0
16.0
50
65
80
95
110
125
11.0
10.0
9.0
15.0
-40
-25
-10
5
20
35
50
65
80
95
110
8.0
125
-40
Temperature ( °C )
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (°C)
Figure 8. Start Threshold Voltage (VDD-ON)
vs. Temperature
Figure 9. Minimum Operating Voltage (VDD-OFF)
vs. Temperature
5.0
10
4.0
8
3.0
6
IHV-LC (µA)
IHV (mA)
35
Figure 7. Operating Supply Current (IDD-OP)
vs. Temperature
VDD -OFF (V)
VDD -ON (V)
Figure 6. Startup Current (IDD-ST) vs. Temperature
2.0
1.0
4
2
0.0
-40
-25
-10
5
20
35
50
65
80
95
110
0
125
-40
-25
-10
5
20
Temperature (°C)
35
50
65
80
95
110
125
Tem perature ( °C )
Figure 10. Supply Current Drawn from HV Pin (IHV)
vs. Temperature
Figure 11. Figure Caption
70
70.0
68
68.0
DCYM AX (%)
f OSC (kHz)
20
Temperature (°C )
Temperature (°C)
SG6741A — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
66
64
62
66.0
64.0
62.0
60.0
60
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
Temperature (°C )
-10
5
20
35
50
65
80
95
110
125
Temperature (°C )
Figure 12. Frequency in Nominal Mode (fOSC)
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
-25
Figure 13. Maximum Duty Cycle (DCYMAX)
vs. Temperature
www.fairchildsemi.com
7
Startup Current
Leading-Edge Blanking (LEB)
For start-up, the HV pin is connected to the line input or
bulk capacitor through an external resistor, RHV, which
is recommended as 100KΩ. Typical startup current
drawn from pin HV is 2mA and charges the hold-up
capacitor through the resistor RHV. When the VDD
capacitor level reaches VDD-ON, the startup current
switches off. At this moment, the VDD capacitor only
supplies the SG6741A to maintain VDD before the
auxiliary winding of the main transformer provides the
operating current.
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 10.5V. During startup, the hold-up
capacitor must be charged to 16.5V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 10.5V during startup. This
UVLO hysteresis window ensures that hold-up capacitor
is adequate to supply VDD during startup.
Operating Current
Operating current is around 4mA. The low operating
current enables a better efficiency and reduces the
requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides an offtime modulation to reduce the switching frequency in
the light-load and no-load conditions. The on-time is
limited for better abnormal or brownout protection. VFB,
which is derived from the voltage feedback loop, is
taken as the reference. Once VFB is lower than the
threshold voltage, switching frequency is continuously
decreased to the minimum green-mode frequency
around 18KHz (RI=26KΩ).
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction is avoided to minimize heat
dissipation, increase efficiency, and enhance reliability.
The output driver is clamped by an internal 18V Zener
diode to protect power MOSFET transistors against
undesirable gate over voltage. A soft driving waveform
is implemented to minimize EMI.
Built-in Slope Compensation
Oscillator Operation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability or prevents sub-harmonic oscillation. SG6741A
inserts a synchronized positive-going ramp at every
switching cycle.
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor RI results in a
corresponding 65KHz PWM frequency. The relationship
between Ri and the switching frequency is:
fPWM
=
1690
(KHz)
RI (KΩ )
Constant Output Power Limit
When the SENSE voltage, across the sense resistor Rs,
reaches the threshold voltage, around 0.9V, the output
GATE drive is turned off after a small delay, tPD. This
delay introduces an additional current proportional to tPD
• VIN / LP. Since the delay is nearly constant, regardless
of the input voltage VIN, higher input voltage results in a
larger additional current and the output power limit is
higher than that under low input line voltage. To
compensate this variation for wide AC input range, a
sawtooth power-limiter is designed to solve the unequal
power-limit problem. The power limiter is designed as a
positive ramp signal fed to the inverting input of the
OCP comparator. This results in a lower current limit at
high-line inputs than at low-line inputs.
(1)
The range of the PWM oscillation frequency is designed
as 47kHz ~ 109kHz.
Current Sensing and PWM Current
Limiting
Peak-current-mode control is utilized in SG6741A to
regulate output voltage and provide pulse-by-pulse
current limiting. The switch current is detected by a
sense resistor into the SENSE pin. The PWM duty cycle
is determined by this current sense signal and VFB, the
feedback voltage. When the voltage on the SENSE pin
reaches around VCOMP = (VFB–1.2)/3.2, a switch cycle
terminates immediately. VCOMP is internally clamped to a
variable voltage around 0.85V for output power limit.
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
SG6741A — Highly Integrated Green-Mode PWM Controller
Functional Description
www.fairchildsemi.com
8
VDD over-voltage protection has been built in to prevent
damage due to abnormal conditions. Once the VDD
voltage is over the VDD over-voltage protection voltage
(VDD-OVP) and lasts for tD-VDDOVP, the PWM pulses are
disabled until the VDD voltage drops below the UVLO,
then starts again. Over-voltage conditions are usually
caused by open feedback loops.
Noise Immunity
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the SG6741A, and increasing the
power MOS gate resistance improve performance.
Limited Power Control
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned off, the supply voltage VDD begins decreasing.
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
SG6741A — Highly Integrated Green-Mode PWM Controller
When VDD goes below the turn-off threshold (~10.5V)
the controller is totally shut down. VDD is charged up to
the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This
protection feature continues as long as the overloading
condition persists. This prevents the power supply from
overheating due to overloading conditions.
VDD Over-voltage Protection (OVP)
www.fairchildsemi.com
9
)
2
R2
T1
1
VZ1
1
2
3
C6
4
2
L1
4
2
BD1
CN1
C1
4
C2
1
4
T2
8
2
3
C5
Q1
1
L4
VO+
+
4
2
1
6
2
2
3
C4
C3
VO+
2
1
+
5
R1
2
1
1
3
2
3
CN1
L2
+
D1
C8
3
1
7
2
D2
1
1
1
C7
3
2
VO-
2
R3
R4
Q2
3
1
D3
2
2
1
+
U1
GND
GATE
C9
8
1
1
SG6741A
3
VDD
NC
SENSE
HV
RI
7
R5
6
5
R6
C10
R7
4
4
FB
R8
1
2
C12
U2
K 2
3
R9
VO+
R10
C11
R
U3
A
R11
Figure 14. Circuit (12V/5A)
SG6741A — Highly Integrated Green-Mode PWM Controller
Reference Circuit
BOM
Reference
BD1
Component
Reference
Component
BD 4A/600V
Q2
MOS 7A/600V
C1
XC 0.68µF/300V
R1
R 100KΩ 1/2W
C2
XC 0.1µF/300V
R2
R 47Ω 1/4W
C3
YC 222pF/Y1
R3
R 100KΩ 1/2W
C4
EC 120µF/400V
R4
R 20Ω 1/8W
C5
CC 0.01µF/500V
R5
R 100Ω 1/8W
C6
CC 102pF/100V
R6
R 33KΩ 1/8W
C7
EC 1000µF/25V
R7
R 0.3Ω 2W
C8
EC 470µF/25V
R8
R 680Ω m 1/8W
C9
EC 22µF/50V
R9
R 4.7KΩ 1/8W
C10
CC 470pF/50V
R10
R 150KΩ m 1/8W
C11
CC 222pF/50V
R11
C12
CC 103pF/50V
T1
10mH
D1
Zener Diode 15V 1/2W (option)
T2
600µH(PQ2620)
D2
BYV95C
U1
IC SG6741A
D3
FR103
U2
IC PC817
F1
FUSE 4A/250V
U3
IC TL431
L1
900µH
VZ1
VZ 9G
Q1
STP20-100CT
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
R 39KΩ 1/8W
www.fairchildsemi.com
10
)
SG6741A — Highly Integrated Green-Mode PWM Controller
Physical Dimensions
8
C
5
H
E
F
1
4
b
e
D
Θ
A1
L
A
Figure 15. 8-Lead Small Outline Package (SOP)
Dimensions
Millimeter
Inch
Symbol
Min.
A
A1
b
c
D
E
e
F
H
L
θ˚
Typ.
1.346
0.101
Max.
Min.
1.752
0.254
0.053
0.004
0.406
0.203
4.648
3.810
1.016
5.791
0.406
0°
1.270
0.381X45°
Typ.
Max.
0.069
0.010
0.016
0.008
4.978
3.987
1.524
0.183
0.150
0.040
6.197
1.270
8°
0.228
0.016
0°
0.050
0.015X45°
0.196
0.157
0.060
0.244
0.050
8°
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
www.fairchildsemi.com
11
)
SG6741A — Highly Integrated Green-Mode PWM Controller
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.0
www.fairchildsemi.com
12