www.fairchildsemi.com AN-9719 Applying Fairchild Power Switch (FPS™) FSL1x7 to Low- Power Supplies 1. Introduction The highly integrated FSL-series consists of an integrated current-mode Pulse Width Modulator (PWM) and an avalanche-rugged 700V SenseFET. It is specifically designed for high-performance offline Switched Mode Power Supplies (SMPS) with minimal external components. The features of the integrated PWM controller include a proprietary green-mode function providing off-time modulation to linearly decrease the switching frequency at light-load conditions to minimize standby power consumption. The PWM controller is manufactured using the BiCMOS process to further reduce power consumption. The green mode and burst mode functions with a low operating current (2mA in green mode) maximize light-load efficiency so that the power supply can meet stringent standby power regulations. The FSL-series has a built-in synchronized slope compensation to achieve stable peak-current-mode control. The proprietary external line compensation ensures constant output power limit over a wide AC input voltage range, 90VAC to 264VAC, and helps optimize the power stage. Many protection functions; such as open–loop / overload protection (OLP), over-voltage protection (OVP), and overtemperature protection (OTP); are fully integrated into FSLseries. These features improve the SMPS reliability without increasing system cost. Compared to a discrete MOSFET and controller or RCC switching converter solution, the FSL-series reduces total component count, converter size, and weight while increasing efficiency, productivity, and system reliability. These devices provide a basic platform for design of costeffective flyback converters. Figure 1. Typical Application Circuit © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com AN-9719 APPLICATION NOTE 2. Device Block Description 2.1 Startup Circuit 2.3 Green Mode Operation For startup, the HV pin is connected to the line input or bulk capacitor through external resistor RHV, as shown in Figure 2. Typical startup current is 3.5mA and it charges the VDD capacitor (CDD) through resistor RHV. The startup current turns off when the VDD capacitor voltage reaches VDD-ON. The VDD capacitor maintains VDD until the auxiliary winding of the transformer provides the operating current. The FSL-series uses feedback voltage (VFB) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 4, such that the switching frequency decreases as load decreases. In heavy-load conditions, the switching frequency is 100kHz. Once VFB decreases below VFB-N (2.5V), the PWM frequency starts to linearly decrease from 100kHz to 18kHz to reduce the switching losses. As VFB decreases below VFB-G (2.4V), the switching frequency is fixed at 18kHz and FSL-series enters “deep” green mode to reduce the standby power consumption. As VFB decreases below VFB-ZDC (2.1V), FSL-series enters into burst-mode operation. When VFB drops below VFB-ZDC, FSL-series stops switching and the output voltage starts to drop, which causes the feedback voltage to rise. Once VFB rises above VFB-ZDC, switching resumes. Burst mode alternately enables and disables switching, thereby reducing switching loss to improve power saving, as shown in Figure 5. Figure 2. Startup Circuit 2.2 Soft-Start The FSL-series has internal soft-start circuit that slowly increases the SenseFET current during startup. The typical soft-start time is 5ms, during which the VLimit level is increased in six steps to smoothly establish the required output voltage, as shown in Figure 3. It also helps prevent transformer saturation and reduce stress on the secondary diode during startup. Figure 4. PWM Frequency Figure 3. Soft-Start Function Figure 5. Bust-Mode Operation © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com 2 AN-9719 APPLICATION NOTE 2.4 Constant Power Control 2.5.3 Overload Protection (OLP) To constantly limit the output power of the converter, high / low line compensation is included. Sensing the converter input voltage through the VIN pin, the high / low line compensation function generates a line-voltage-dependent peak-current-limit threshold voltage for constant power control, as shown in Figure 6. When the upper branch of the voltage divider for the shunt regulator (KA431 shown) is open circuit, as shown in Figure 7, or an output over-current or short occurs; there is no current flowing through the opto-coupler transistor. VFB (feedback voltage) pulls up to 6V. When the feedback voltage is above 4.6V for longer than 56ms, OLP is triggered. This protection is also triggered when the SMPS output drops below the nominal value longer than 56ms due to the overload condition. Figure 6. Constant Power Control 2.5 Protection Functions The FSL-series provides full protection functions to prevent the power supply and the load from being damaged. The protection features is shown in Table 1. Table 1. Protection Functions OVP OTP OLP VIN-H VIN-L FSL127H FSL137H Latch Latch Auto Restart Latch Auto Restart Latch Latch Auto Restart Latch Auto Restart Figure 7. OLP Operator 2.5.1 VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents IC damage caused by over voltage on the VDD pin. The OVP is triggered when VDD reaches 28V. It has debounce time (typically 130µs) to prevent false trigger by switching noise. 2.5.2 Over-Temperature Protection (OTP) The SenseFET and the control IC integration make temperature detection of the SenseFET easier. When the junction temperature exceeds approximately 142°C, thermal shutdown is activated. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com 3 AN-9719 APPLICATION NOTE 3. Design Example [STEP-2] Determine Input Capacitor (CIN) and Input Voltage Range Flyback converters have two kinds of operation modes; Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). Each has its own advantages and disadvantages. In general, DCM generates lower stress for the rectifier diodes, since the diodes are operating at zero current just before becoming reverse biased and the reverse recovery loss is minimized. The transformer size can be reduced using DCM because the average energy storage is low compared to CCM. However, DCM causes high RMS current, which severely increases the conduction loss of the MOSFET for low line condition. For standby auxiliary power supply applications with low output voltage and minimal reverse recovery of Schottky diode, it is typical to design the converter such that the converter operates in CCM to maximize efficiency. It is typical to select the input capacitor as 2~3μF per watt of peak input power for the universal input range (85265VRMS) and 1μF per watt of peak input power for the European input range (195V-265VRMS). With the input capacitor chosen, the minimum input capacitor voltage at nominal-load condition is obtained as: · 1 2· (2) · where DCH is the input capacitor charging duty ratio defined in Figure 8, which is typically about 0.2. The maximum input capacitor voltage is given as: √2 (3) This section presents a design procedure using the Figure 1 schematic as a reference. An offline SMPS with 12W nominal output power has been selected as the example. [STEP-1] Define the System Specifications When designing a power supply, specifications should be determined first: the and V following Line Voltage Range (V Line Frequency (fL ) Nominal Output Power (PO ) Estimate Efficiencies for Nominal Load (η). The power conversion efficiency must be estimated to calculate the input power for nominal load condition. If no reference data is available, set η = 0.7~0.75 for lowvoltage output applications and η = 0.8~0.85 for highvoltage output applications. ) Figure 8. Input Capacitor Voltage Waveform (Design Example) By choosing 20μF for input capacitor, the minimum input voltage for nominal load is obtained as: 2 · 90 With the estimated efficiency, the input power for peak load condition is given by: · 15 · 1 20 · 10 0.2 · 60 79 The maximum input voltage is obtained as: (1) η · 1 2· √2 · √2 · 264 373 (Design Example) The specifications of the target system are: 90V V 264V V Line frequency (f ) = 60Hz Nominal output power (P ) = 12W (12V/1A) Estimated efficiency (η) = 0.8 η 12 0.8 [STEP-3] Determine the Reflected Output Voltage (VRO) When the MOSFET is turned off, the input voltage (VIN), together with the output voltage reflected to the primary (VRO), are imposed across the MOSFET, as shown in Figure 9. With a given VRO, the maximum duty cycle (DMAX) and the nominal MOSFET voltage (VDSNOM) are obtained as: 15 (4) (5) · © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 (6) www.fairchildsemi.com 4 AN-9719 APPLICATION NOTE (Design Example) As can be seen in Table 2, it is recommended to use rectifier diode with 100V voltage rating to maximize efficiency. Assuming that the nominal voltages of MOSFET and diode are less than 80% of their voltage rating, the reflected output voltage is given as: · 373 · 12 0.85 12 373 · 12 0.85 68 Î 0.8 · 100 70.5 0.8 · 700 560 Î 373 By determining 74 373 · 12 0.85 74 [STEP-4] Determine Inductance (LM) © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 447 the 12 76.8 Transformer Primary-Side The transformer primary-side inductance is determined for the minimum input voltage and nominal-load condition. With the DMAX from Step-3, the primary-side inductance (LM) of the transformer is obtained as: · · · (7) where fSW is the switching frequency and KRF is the ripple factor at minimum input voltage and nominal load condition, defined as shown in Figure 10. Voltage Ratings (3A Schottky Diode) 20V 30V 40V 50V 60V 80V 100V 74 · Table 2. Diode Forward-Voltage Drop for Different SB320 SB330 SB340 SB350 SB360 SB380 SB3100 0.48 79 373 2· VRRM 187 74 The actual drain voltage and diode voltage rise above the nominal voltage is due to the leakage inductance of the transformer as shown in Figure 9. It is typical to set VRO such that VDSNOM and VDONOM are 70~80% of voltage ratings of MOSFET and diode, respectively. Part Name 560 as 74V, Figure 9. Output Voltage Reflected to the Primary As can be seen in Equation 5, the voltage stress across MOSFET can be reduced by reducing VRO. However, this increases the voltage stresses on the rectifier diodes in the secondary side, as shown in Equation 6. Therefore, VRO should be determined by a balance between the voltage stresses of MOSFET and diode. Especially for low output voltage applications, the rectifier diode forward-voltage drop is a dominant factor determining the power supply efficiency. Therefore, the reflected output voltage should be determined such that rectifier diode forward voltage can be minimized. Table 2 shows the forward-voltage drop for Schottky diodes with different voltage rating. 80 VF For DCM operation, KRF = 1, and, for CCM operation, KRF < 1. The ripple factor is closely related to the transformer size and the RMS value of the MOSFET current. Even though the conduction loss in the MOSFET can be reduced by reducing the ripple factor, too small a ripple factor forces an increase in transformer size. When designing the flyback converter to operate in CCM, it is reasonable to set KRF = 0.25-0.5 for the universal input range and KRF = 0.4-0.8 for the European input range. 0.5V 0.74V 0.85V www.fairchildsemi.com 5 AN-9719 APPLICATION NOTE Once LM is calculated from equation (7) after choosing KRF, the peak and RMS current of the MOSFET for the minimum input voltage and nominal load condition are obtained as: ∆ (8) 2 ∆ 2 3 [STEP-5] Choose the Proper FPS Considering Input Power and Peak Drain Current With the resulting maximum peak drain current of the MOSFET (IDSPK) from Equation 8, choose the proper FPS for which the pulse-by-pulse current limit level (ILIM) is higher than IDSPK. Since FPS has ±10% tolerance of ILIM, there should be some margin when choosing the proper FPS device. The FSL-series lineup with proper power rating is summarized in Table 3. (9) 3 where: Table 3. Lineup of FSL1x7-Series with Power Rating (10) · Typ. Max. 85-265VAC Open Frame FSL127H 0.51A 0.61A 0.71A 16W FSL137H 0.74A 0.84A 0.94A 19W and · ∆ (11) · K RF = ΔI 2 I EDC (Design Example) 0.75 0.84 . FSL137H is selected. [STEP-6] Determine the Minimum Primary Turns ΔI With a given magnetic core, the minimum number of turns for the transformer primary side to avoid the core saturation is given by: · (12) 10 · where Ae is the cross-sectional area of the core in mm2, ILIM is the pulse-by-pulse current limit level, and BSAT is the saturation flux density in Tesla. I DS PK Figure 10. MOSFET Current and Ripple Factor (KRF) (Design Example) Choosing the ripple factor as 0.88, The pulse-by-pulse current limit level is included in Equation 12 because the inductor current reaches the pulseby-pulse current limit level during the load transient or overload condition. Figure 11 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (BSAT) decreases as temperature increases, the high-temperature characteristics should be considered. If there is no reference data, use BSAT =0.3 T. · 2· · · 79 · 0.48 2 · 15 · 100 10 · 0.88 540 15 79 · 0.48 · ∆ ILIM at VIN=1.2V Min. Product 79 · 0.48 10 · 100 · · 540 ∆ 2 3 3 0.4 0.4 0.4 0.35 ∆ 2 0.35 10 0.7 0.75 3 0.48 3 0.31 Figure 11. Typical B-H Characteristics of Ferrite Core (TDK/PC40) © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com 6 AN-9719 APPLICATION NOTE (Design Example) Assuming the diode forwardvoltage drop is 0.85V, the turn ratio is obtained as: (Design Example) EE-16 core is selected, whose effective cross-sectional area is 19.2mm2. Choosing the saturation flux density as 0.3T, the minimum number of turns for the primary-side is obtained as: · 12 10 · 540 10 · 0.8 0.3 · 19.2 74 0.85 5.8 Then determine the proper integer for NS such that the resulting NP is larger than NPMIN as: 10 75 13, 75 Setting as 12V, the number of turns for the auxiliary winding is obtained as: [STEP-7] Determine the Number of Turns for each Winding Figure 12 shows a simplified diagram of the transformer. First calculate the turn ratio (n) between the primary-side and the secondary-side from the reflected output voltage (VRO) determined in Step-3 as: 12 0.85 · 13 12 0.5 · 13 [STEP-8] Determine the Wire Diameter for Each Winding Based on the RMS Current of Winding (13) The maximum RMS current of the secondary winding is obtained as: where NP and NS are the number of turns for primary-side and secondary-side, respectively; VO is the output voltage; and VF is the output diode (DO) forward-voltage drop. 1 · Next, determine the proper integer for NS such that the resulting NP is larger than NPMIN obtained from Equation 12. (15) The current density is typically 3~5A/mm2 when the wire is long (>1m). When the wire is short with a small number of turns, a current density of 5~10A/mm2 is acceptable. Avoid using wire with a diameter larger than 1mm to avoid severe eddy current or ac losses. For high-current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect. The number of turns for the auxiliary winding for VDD supply is determined as: · · (14) where VDD is the supply voltage nominal value and VFA is the forward-voltage drop of DDD as defined in Figure 12. (Design Example) The RMS current of primary-side winding is obtained from Step-4 as 0.31A. The RMS current of secondary-side winding is calculated as: Since VDD increases as the output load increases, set VDD at 5~8V higher than VDD UVLO level (8V) to avoid the overvoltage protection condition during the peak-load operation. 1 · 5.8 · 0.31 1 0.48 0.48 1.87 0.3mm (5A/mm2) and 0.4mm (8A/mm2) diameter wires are selected for primary and secondary windings, respectively. [STEP-9] Choose the Rectifier Diode in the SecondarySide Based on the Voltage and Current Ratings The maximum reverse voltage and the RMS current of the rectifier diode are obtained as: (16) · Figure 12. Simplified Transformer Diagram © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 1 (17) www.fairchildsemi.com 7 AN-9719 APPLICATION NOTE Notice that there is a right-half-plane (RHP) zero (ωRZ) in the control-to-output transfer function of Equation 21. Because the RHP zero reduces the phase by 90 degrees, the crossover frequency should be placed below the RHP zero. The typical voltage and current margins for the rectifier diode are as follows: 1.2 · (18) 1.8 · (19) Figure 13 shows the variation of a CCM flyback converter control-to-output transfer function for different input voltages. This figure shows the system poles and zeros with the DC gain change for different input voltages. The gain is highest at the high input voltage condition and the RHP zero is lowest at the low input voltage condition. where VRRM is the maximum reverse voltage and IF is the current rating of the diode. (Design Example) The diode voltage and current are calculated as: 12 373 5.8 76.3 1 · 1 5.8 · 0.31 0.48 0.48 1.87 5A and 100V diodes in parallel are selected for the rectifier diode. [STEP-10] Feedback Circuit Configuration Figure 13. CCM Flyback Converter Control-to-Output Transfer Function Variation for Different Input Voltage Since FSL-series employs current-mode control, the feedback loop can be implemented with a one-pole and onezero compensation circuit. The current control factor of FPS, K, is defined as: Figure 14 shows the variation of a CCM flyback converter control-to-output transfer function for different loads. Note that the DC gain changes for different loads and the RHP zero is the lowest at the full-load condition. (20) 2.5 where ILIM is the pulse-by-pulse current limit and VFBSAT is the feedback saturation voltage, typically 2.5V. As described in Step-4, it is typical to design the flyback converter to operate in CCM for heavy-load condition. For CCM operation, the control-to-output transfer function of a flyback converter using current mode control is given by: (21) ⁄ · · · 2 ⁄ 1 1 1 ⁄ ⁄ Figure 14. CCM Flyback Converter Control-to-Output Transfer Function Variation for Different Loads where RL is the load resistance. The pole and zeros of Equation 21 are obtained as: 1 When the input voltage and the load current vary over a wide range, it is not easy to determine the worst case for the feedback loop design. The gain, together with zeros and poles, varies according to the operating conditions. Even though the converter is designed to operate in CCM or at the boundary of DCM and CCM in the minimum input voltage and full-load condition; the converter enters into DCM, changing the system transfer functions as the load current decreases and/or input voltage increases. 1 , 1 ⁄ (22) here D is the duty cycle of the FPS and RC is the ESR of CO. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com 8 AN-9719 APPLICATION NOTE One simple and practical way to address this problem is designing the feedback loop for low input voltage and fullload condition with enough phase and gain margin. When the converter operates in CCM, the RHP zero is lowest in low input voltage and full-load condition. The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. When the operating mode changes from CCM to DCM, the RHP zero disappears, making the system stable. Therefore, by designing the feedback loop with more than 45 degrees of phase margin in low input voltage and full-load condition, the stability over all the operating ranges can be guaranteed. (Design Example) Assuming CTR is 100%, · 12 1 10 10 1.2 2.5 1 10 8.3 Ω The minimum cathode current for KA431 is 1mA. 1.2 Ω. 1kΩ resistor is selected for RBIAS. Figure 15 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R1 and R2 form a voltage divider for output voltage regulation. RF and CF are for control-loop compensation. The maximum source current of the FB pin is about 1mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of RD, is determined by: · 1 The voltage divider resistors R1 and R2 should be designed to provide 2.5V to the reference pin of the KA431.The relationship between R1 and R2 is given as: 2.5 · 2.5 2.5 · 12 2.5 3.8 38.2kΩ and 10kΩ resistor are selected for R1, R2. (23) where VOPD is the forward-voltage drop of the photodiode (~1.2V); VKA is the minimum cathode-to-anode voltage of KA431 (2.5V); and CTR is the current transfer rate of the opto-coupler. [STEP-11] Design Input Voltage Sensing Circuit Figure 16 shows a resistive voltage divider with low-pass filter for line-voltage detection of the VIN pin. FSL-series devices start and enable the latch function when the VIN voltage reaches 1.03V. If latch protection is triggered, the VIN voltage is used for release latch protection as the VIN voltage drops below 0.7V. It is typical to use 100:1 voltage divider for VIN level. 6V + - Figure 16. Input Voltage Sensing Figure 15. Feedback Circuit The feedback compensation network transfer function of Figure 15 is obtained as: · 1 1 ⁄ ⁄ (24) where , 1 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 1 (25) www.fairchildsemi.com 9 AN-9719 APPLICATION NOTE 4. Printed Circuit Board Layout To get better EMI performance and reduce line-frequency ripple, the output of the bridge rectifier should be connected to capacitor CDC first, then to the switching circuits. GND2→3→1 are suggestions for ESD tests where the earth ground is not available on the power supply. In the ESD discharge path, the charge goes from the secondary, through the transformer stray capacitance, to GND3, then GND1, and back to mains. It should be noted that control circuits should not be placed on the discharge path. Point discharge for common-mode choke (see Figure 17) can decrease high-frequency impedance and increase ESD immunity. The high-frequency current loop is in CDC – Transformer – Drain pin – CDC. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 2→1 in Figure 17) short, direct, and wide. High-voltage traces related the drain and RCD snubber should be kept far away from control circuits to prevent unnecessary interference. Should a Y-cap between primary and secondary be required, connect this Y-cap to the positive terminal of CDC. If this Y-cap is connected to primary ground, it should be connected to the negative terminal of CDC (GND1) directly. Point discharge of this Y-cap also helps for ESD. In addition, the creepage distance between these two pointed ends should be at least 5mm according to safety requirements. High-frequency switching current / voltage makes printed circuit board layout a very important design task. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge/ESD tests. 4.1 Guidelines As indicated by 2, the ground of control circuits should be connected first, then route other traces. As indicated by 3, the area enclosed by the transformer auxiliary winding, DDD and CDD should also be kept small. Place CDD close to the controller for good decoupling. Figure 17. Layout Considerations © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com 10 AN-9719 APPLICATION NOTE 5. Design Summary 5.1 Schematic Figure 18 shows the final schematic of the 12W power supply of the design example. Figure 18. Design Example 5.2 Transformer Specification Figure 19. Transformer Specification 2 Core: EEL-16 (Ae=19.2mm ) Bobbin: EEL-16 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 www.fairchildsemi.com 11 AN-9719 APPLICATION NOTE Na Pin (S → F) Wire Turns 5→4 0.3φ×1 13 0.26φ×1 75 COPPER SHIELD 1.2 0.35φ×1 13 Insulation : Polyester Tape t = 0.025mm, 2 Layers Np 2→1 Insulation : Polyester Tape t = 0.025mm, 2 Layers - 4→- Insulation : Polyester Tape t = 0.025mm, 2 Layers Ns 8 → 10 Insulation : Polyester Tape t = 0.025mm, 3 Layers Pin Specification Remark Inductance 1－2 600μH ± 10% 100kHz, 1V Leakage 1－2 < 30 μH Maximum Short All Other Pins Related Datasheets FSL127H — Green Mode Fairchild Power Switch (FPS™) FSL137H— Green Mode Fairchild Power Switch (FPS™) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 • 11/2/10 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12

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