TI UC3845

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
Current Mode PWM Controller
FEATURES
DESCRIPTION
•
Optimized For Off-line And DC
To DC Converters
•
Low Start Up Current (<1mA)
•
Automatic Feed Forward
Compensation
•
Pulse-by-pulse Current Limiting
•
The UC1842/3/4/5 family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes
with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched
operation, a PWM comparator which also provides current limit control, and a
totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N Channel MOSFETs, is low in the off state.
Enhanced Load Response
Characteristics
•
Under-voltage Lockout With
Hysteresis
•
Double Pulse Suppression
•
High Current Totem Pole
Output
•
Internally Trimmed Bandgap
Reference
•
500khz Operation
•
Low RO Error Amp
Differences between members of this family are the under-voltage lockout
thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have
UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are 8.4V
and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching
100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the
addition of an internal toggle flip flop which blanks the output off every other
clock cycle.
BLOCK DIAGRAM
Note 1: A/B A = DIL-8 Pin Number. B = SO-14 Pin Number.
Note 2: Toggle flip flop used only in 1844 and 1845.
4/97
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Supply Voltage (ICC <30mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Limiting
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A
Output Energy (Capacitive Load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5µJ
Analog Inputs (Pins 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.3V
Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Power Dissipation at TA ≤ 25°C (SOIC-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725mW
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Note 1: All voltages are with respect to Pin 5.
All currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal limitations and considerations
of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, D8 Package
PLCC-20 (TOP VIEW)
Q Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
COMP
N/C
N/C
VFB
N/C
ISENSE
N/C
N/C
RT/CT
N/C
PWR GND
GROUND
N/C
OUTPUT
N/C
VC
VCC
N/C
VREF
SOIC-14 (TOP VIEW)
D Package
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the
UC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC =
15V (Note 5); RT = 10k; CT =3.3nF, TA=TJ.
PARAMETER
UC1842/3/4/5
UC2842/3/4/5
TEST CONDITIONS
UC3842/3/4/5
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
4.95
5.00
5.05
4.90
5.00
5.10
V
6
20
6
20
mV
Reference Section
Output Voltage
TJ = 25°C, IO = 1mA
Line Regulation
12 ≤ VIN ≤ 25V
Load Regulation
1 ≤ I0 ≤ 20mA
Temp. Stability
(Note 2) (Note 7)
Total Output Variation
Line, Load, Temp. (Note 2)
Output Noise Voltage
10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2)
50
Long Term Stability
TA = 125°C, 1000Hrs. (Note 2)
5
25
-100
-180
-30
52
57
47
0.2
1
6
25
6
25
mV
0.2
0.4
0.2
0.4
mV/°C
4.9
Output Short Circuit
-30
5.1
4.82
5.18
V
µV
50
5
25
mV
-100
-180
mA
52
57
kHz
0.2
1
%
Oscillator Section
Initial Accuracy
TJ = 25°C (Note 6)
Voltage Stability
12 ≤ VCC ≤ 25V
Temp. Stability
TMIN ≤ TA ≤ TMAX (Note 2)
Amplitude
VPIN 4 peak to peak (Note 2)
47
5
5
%
1.7
1.7
V
Error Amp Section
Input Voltage
VPIN 1 = 2.5V
2.45
Input Bias Current
2 ≤ VO ≤ 4V
65
Unity Gain Bandwidth
(Note 2) TJ = 25°C
PSRR
12 ≤ VCC ≤ 25V
AVOL
Output Sink Current
VPIN 2 = 2.7V, VPIN 1 = 1.1V
Output Source Current
VPIN 2 = 2.3V, VPIN 1 = 5V
VOUT High
VPIN 2 = 2.3V, RL = 15k to ground
VOUT Low
VPIN 2 = 2.7V, RL = 15k to Pin 8
2.50
2.55
-0.3
-1
2.42
90
65
0.7
1
60
70
2.50
2.58
V
-0.3
-2
µA
90
dB
0.7
1
MHz
60
70
dB
2
6
2
6
mA
-0.5
-0.8
-0.5
-0.8
mA
5
6
5
0.7
1.1
3
3.15
2.85
1
1.1
0.9
6
V
0.7
1.1
V
3
3.15
V/V
1
1.1
Current Sense Section
Gain
(Notes 3 and 4)
2.85
Maximum Input Signal
VPIN 1 = 5V (Note 3)
0.9
PSRR
12 ≤ VCC ≤ 25V (Note 3) (Note 2)
70
-2
-10
-2
-10
µA
VPIN 3 = 0 to 2V (Note 2)
150
300
150
300
ns
Input Bias Current
Delay to Output
70
Note 2: These parameters, although guaranteed, are not 100% tested in production.
Note 3: Parameter measured at trip point of latch with VPIN 2 = 0.
Note 4: Gain defined as
∆ VPIN 1
A=
, 0 ≤ VPIN 3 ≤ 0.8V
∆ VPIN 3
Note 5: Adjust VCC above the start threshold before setting at 15V.
Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
Note 7: Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
VREF (max) − VREF (min)
Temp Stability =
TJ (max) − TJ (min)
VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate
temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
3
V
dB
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for the
UC184X; −40°C≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC =
15V (Note 5); RT = 10k; CT =3.3nF, TA=TJ.
PARAMETER
UC1842/3/4/5
UC2842/3/4/5
TEST CONDITION
MIN
UC3842/3/4/5
TYP
MAX
ISINK = 20mA
0.1
ISINK = 200mA
1.5
MIN
UNITS
TYP
MAX
0.4
0.1
0.4
V
2.2
1.5
2.2
V
Output Section
Output Low Level
Output High Level
ISOURCE = 20mA
13
13.5
13
13.5
V
ISOURCE = 200mA
12
13.5
12
13.5
V
Rise Time
TJ = 25°C, CL = 1nF (Note 2)
50
150
50
150
ns
Fall Time
TJ = 25°C, CL = 1nF (Note 2)
50
150
50
150
ns
Under-voltage Lockout Section
Start Threshold
Min. Operating Voltage
After Turn On
X842/4
15
16
17
14.5
16
17.5
V
X843/5
7.8
8.4
9.0
7.8
8.4
9.0
V
X842/4
9
10
11
8.5
10
11.5
V
X843/5
7.0
7.6
8.2
7.0
7.6
8.2
V
X842/3
95
97
100
95
97
100
%
X844/5
46
48
50
47
48
50
%
0
%
0.5
1
mA
11
17
mA
PWM Section
Maximum Duty Cycle
Minimum Duty Cycle
0
Total Standby Current
Start-Up Current
Operating Supply Current
VPIN 2 = VPIN 3 = 0V
0.5
1
11
17
ICC = 25mA
30
34
VCC Zener Voltage
Note 2: These parameters, although guaranteed, are not 100% tested in production.
Note 3: Parameter measured at trip point of latch with VPIN 2 = 0.
Note 4: Gain defined as:
∆ VPIN 1
A=
; 0 ≤ VPIN 3 ≤ 0.8V.
∆ VPIN 3
Note 5: Adjust VCC above the start threshold before setting at 15V.
Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA
4
30
34
V
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output driver is biased to
sink minor amounts of current. Pin 6 should be shunted to
ground with a bleeder resistor to prevent activating the power
switch with extraneous leakage currents.
CURRENT SENSE CIRCUIT
Peak Current (IS) is Determined By The Formula
1.0V
ISMAX ≈
RS
A small RC filter may be required to suppress switch transients.
OSCILLATOR SECTION
5
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
OUTPUT SATURATION CHARACTERISTICS
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to
pin 3.
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage
two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram).
The PWM latch is reset dominant so that the output will remain
low until the next clock cycle after the shutdown condition at
pin 1 and/or 3 is removed. In one example, an externally
latched shutdown may be accomplished by adding an SCR
which will be reset by cycling VCC below the lower UVLO
threshold. At this point the reference turns off, allowing the
SCR to reset.
6
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
OFFLINE FLYBACK REGULATOR
5. Output Voltage:
A. +5V, ±5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
B. +12V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
C. -12V ,±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
Power Supply Specifications
1. Input Voltage
2. Line Isolation
3. Switching Frequency
4. Efficiency @ Full Load
95VAC to 130VA
(50 Hz/60Hz)
3750V
40kHz
70%
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over
50%.
Note that capacitor, C forms a filter with R2 to suppress
the leading edge switch spikes.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
7
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