Revised August 1999 74F845 8-Bit Transparent Latch General Description Features The 74F845 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. ■ 3-STATE outputs ■ Direct replacement for AMD’s Am29845 The 74F845 is functionally- and pin-compatible with AMD’s Am29845. Ordering Code: Order Number Package Number Package Description 74F845SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F845SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009601 www.fairchildsemi.com 74F845 8-Bit Transparent Latch April 1988 74F845 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D0–D7 Data Inputs 1.0/1.0 20 µA/−0.6 mA O0–O7 Data Outputs 150/40 −3.0 µA/24 mA OE1–OE3 Output Enables 1.0/1.0 20 µA/−0.6 mA LE Latch Enable 1.0/1.0 20 µA/−0.6 mA CLR Clear 1.0/1.0 20 µA/−0.6 mA PRE Preset 1.0/1.0 20 µA/−0.6 mA Function Table Functional Description The 74F845 consists of eight D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Inputs Internal Output Function CLR PRE OE LE D Q O H H H X X X Z H H H H L L Z High Z High Z H H H H H H Z High Z H H H L X NC Z Latched H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC H L L X X H H Preset L H L X X L L Clear Latched L L L X X H H Preset L H H L X L Z Latched H L H L X H Z Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 IOH = −1 mA Voltage 10% VCC 2.4 IOH = −3 mA 5% VCC 2.7 5% VCC 2.7 Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current V Conditions Input HIGH Voltage VOL 2.0 Units VIH Output HIGH Leakage Current VID Input Leakage Test IOD Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCZ Power Supply Current IIN = −18 mA V Min 0.5 V Min IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Recognized as a LOW Signal Min IOH = −1 mA IOH = −3 mA 10% VCC Breakdown Test ICEX Recognized as a HIGH Signal −60 63 3 IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 85 mA Max VO = HIGH Z www.fairchildsemi.com 74F845 Absolute Maximum Ratings(Note 1) 74F845 AC Electrical Characteristics Symbol Parameter TA = +25°C TA= 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 2.5 4.8 8.0 2.0 9.0 tPHL Dn to On 1.5 3.6 6.5 1.5 7.0 Units ns tPLH Propagation Delay 5.0 8.1 12.0 4.5 13.5 tPHL LE to On 2.0 4.4 7.5 2.0 8.0 tPLH Propagation Delay 3.0 5.9 10.0 2.5 11.0 ns ns PRE to On tPHL Propagation Delay 3.0 6.5 10.0 2.5 11.0 tPZH Output Enable Time 2.5 5.8 9.5 2.0 10.5 tPZL OE to On 2.5 7.6 12.0 2.0 13.0 tPHZ Output Disable Time 1.0 3.1 7.5 1.0 8.5 tPLZ OE to On 1.0 2.8 6.5 1.0 7.5 CLR to On ns ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA= 0°C to +70°C VCC = +5.0V Min Units Max tS(H) Setup Time, HIGH or LOW 2.0 2.5 tS(L) Dn to LE 2.0 2.5 tH(H) Hold Time, HIGH or LOW 2.5 3.0 tH(L) Dn to LE 3.0 3.5 tW(H) LE Pulse Width, HIGH 4.0 4.0 ns tW(L) PRE Pulse Width, LOW 5.0 5.0 ns ns ns tW(L) CLR Pulse Width, LOW 5.0 5.0 ns tREC PRE Recovery Time 10.0 10.0 ns tREC CLR Recovery Time 12.0 13.0 ns www.fairchildsemi.com 4 74F845 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F845 8-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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