24C02C 2K 5.0V I2C™ Serial EEPROM Features: • Single-supply with operation from 4.5 to 5.5V • Low-power CMOS technology: - Read current 1 mA, typical - Standby current 10 μA, typical • 2-wire serial interface, I2C compatible • Cascadable up to eight devices • Schmitt Trigger inputs for noise suppression • Output slope control to eliminate ground bounce • 100 kHz and 400 kHz clock compatibility • Fast Page or Byte write time 1 ms, typical • Self-timed erase/write cycle • 16-byte page write buffer • Hardware write-protect for upper half of the array (80h-FFh) • ESD protection >4,000V • More than 1 million erase/write cycles • Data retention >200 years • Factory programming available • Packages include 8-lead PDIP, SOIC, TSSOP, DFN and MSOP • Pb-free and RoHS compliant • Temperature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C Package Types A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA DFN A0 1 A1 2 A2 3 VSS 4 The Microchip Technology Inc. 24C02C is a 2K bit Serial Electrically Erasable PROM with a voltage range of 4.5V to 5.5V. The device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low-current design permits operation with typical standby and active currents of only 10 μA and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data and has fast write cycle times of only 1 ms for both byte and page writes. Functional address lines allow the connection of up to eight 24C02C devices on the same bus for up to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm), 8-pin 2x3 DFN, 8-pin MSOP and TSSOP packages. 8 VCC 7 WP 6 SCL 5 SDA Block Diagram A0 A1 A2 WP HV Generator I/O Control Logic Memory Control Logic XDEC EEPROM Array SDA SCL Vcc Description: SOIC, TSSOP PDIP, MSOP Vss Write-Protect Circuitry YDEC Sense Amp. R/W Control I2C is a trademark of Philips Corporation. © 2007 Microchip Technology Inc. DS21202G-page 1 24C02C 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ...................................................................................................................................... ≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS All parameters apply across the specified operating ranges unless otherwise noted. Parameter VCC = +4.5V to +5.5V Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Symbol SCL and SDA pins: High-level input voltage VIH Low-level input voltage VIL Hysteresis of Schmitt Trigger inputs VHYS Low-level output voltage Min. Max. Units 0.7 VCC — V Conditions — 0.3 VCC V 0.05 VCC — V (Note) VOL — 0.40 V IOL = 3.0 mA, VCC = 4.5V Input leakage current ILI — ±1 μA VIN = VSS or VCC, WP = Vss Output leakage current ILO — ±1 μA VOUT = VSS or VCC Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note) TA = 25°C, f = 1 MHz Operating current ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz Standby current Note: ICC Write — 3 mA VCC = 5.5V ICCS — 50 μA VCC = 5.5V, SDA = SCL = VCC WP = VSS This parameter is periodically sampled and not 100% tested. DS21202G-page 2 © 2007 Microchip Technology Inc. 24C02C TABLE 1-2: AC CHARACTERISTICS All parameters apply across the specified operating ranges unless otherwise noted. Parameter Symbol VCC = +4.5V to +5.5V Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C TA > +85°C -40°C ≤ TA ≤ +85°C Min. Max. Min. Max. Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns Start condition setup time TSU:STA 4700 — 600 — ns Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns — 250 20 + 0.1 CB 250 ns (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB ≤ 100 pF — 50 — 50 ns (Note 3) — 1M 1.5 — — 1M 1 — TOF Output fall time from VIH minimum to VIL maximum Input filter spike suppression TSP (SDA and SCL pins) Write cycle time TWR Endurance Note 1: 2: 3: 4: BUS TIMING DATA THIGH TF TR TSU:STA TLOW SDA IN ms Byte or Page mode cycles 25°C, VCC = 5.0V, Block mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: SCL (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition (Note 2) TSP THD:DAT TSU:DAT TSU:STO THD:STA TAA TBUF SDA OUT © 2007 Microchip Technology Inc. DS21202G-page 3 24C02C 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PIN FUNCTION TABLE PDIP SOIC TSSOP DFN MSOP Description A0 1 1 1 1 1 Address Pin A0 A1 2 2 2 2 2 Address Pin A1 A2 3 3 3 3 3 Address Pin A2 VSS 4 4 4 4 4 Ground SDA 5 5 5 5 5 Serial Address/Data I/O SCL 6 6 6 6 6 Serial Clock WP 7 7 7 7 7 Write-Protect Input VCC 8 8 8 8 8 +4.5 to 5.5V Power Supply 2.1 SDA Serial Data This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 SCL Serial Clock 3.0 FUNCTIONAL DESCRIPTIONS The 24C02C supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions, while the 24C02C works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. This input is used to synchronize the data transfer from and to the device. 2.3 A0, A1, A2 The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24C02C devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. 2.4 WP This is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to Vcc, the hardware write protection is enabled. If the WP pin is tied to Vss the hardware write protection is disabled. 2.5 Noise Protection The 24C02C employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 3.8 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS21202G-page 4 © 2007 Microchip Technology Inc. 24C02C 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in firstout fashion. 4.1 4.5 Bus Not Busy (A) Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Note: A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: SCL (A) The 24C02C does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2). Stop Data Transfer (C) 4.4 Acknowledge DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS (B) (C) Start Condition Address or Acknowledge Valid (D) (C) (A) SDA FIGURE 4-2: Stop Condition Data Allowed to Change ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 SDA 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. © 2007 Microchip Technology Inc. 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. DS21202G-page 5 24C02C 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a four bit control code; for the 24C02C this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24C02C devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is selected. Following the Start condition, the 24C02C monitors the SDA bus checking the control byte being transmitted. Upon receiving a ‘1010’ code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C02C will select a read or write operation. DS21202G-page 6 FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1, A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24C02C devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9, and A2 as address bit A10. It is not possible to write or read across device boundaries. © 2007 Microchip Technology Inc. 24C02C 6.0 WRITE OPERATIONS 6.1 Byte Write As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if the write protection is enabled. Following the Start signal from the master, the device code(4 bits), the Chip Select bits (3 bits) and the R/W bit, which is a logic low, is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24C02C. After receiving another Acknowledge signal from the 24C02C the master device will transmit the data word to be written into the addressed memory location. The 24C02C acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24C02C will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if the write protection is enabled. 6.2 Note: Page Write The write control byte, word address and the first data byte are transmitted to the 24C02C in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 15 additional data bytes to the 24C02C which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the four lower order Address Pointer bits are internally incremented by one. The higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. FIGURE 6-1: S T A R T SDA Line S The WP pin must be tied to VCC or VSS. If tied to VCC, the upper half of the array (080-0FF) will be writeprotected. If the WP pin is tied to VSS, then write operations to all address locations are allowed. Control Byte Word Address S T O P Data P A C K Bus Activity FIGURE 6-2: SDA Line Write Protection BYTE WRITE Bus Activity Master Bus Activity Master 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. A C K A C K PAGE WRITE S T A R T Control Byte Word Address (n) Data n Data n +1 S T O P Data n + 15 S Bus Activity © 2007 Microchip Technology Inc. P A C K A C K A C K A C K A C K DS21202G-page 7 24C02C 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW 8.0 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 8.1 Send Start Send Control Byte with R/W = 0 Yes Next Operation Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C02C as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C02C will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24C02C discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. Send Stop Condition to Initiate Write Cycle Did Device Acknowledge (ACK = 0)? Current Address Read The 24C02C contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24C02C issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24C02C discontinues transmission (Figure 8-1). 8.2 Send Write Command READ OPERATIONS No 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24C02C transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24C02C to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads, the 24C02C contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address FF to address 00. DS21202G-page 8 © 2007 Microchip Technology Inc. 24C02C FIGURE 8-1: CURRENT READ ADDRESS Bus Activity Master S T A R T SDA line S Control Byte P A C K Bus Activity FIGURE 8-2: S T A R T Control Byte S T A R T Word Address (n) S SDA line Control Byte S T O P Data (n) P S A C K A C K Bus Activity Bus Activity Master N O A C K RANDOM READ Bus Activity Master FIGURE 8-3: S T O P Data A C K N O A C K SEQUENTIAL READ Control Byte Data n Data n + 1 Data n + 2 S T O P Data n + X P SDA line Bus Activity © 2007 Microchip Technology Inc. A C K A C K A C K A C K N O A C K DS21202G-page 9 24C02C 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN 8-Lead TSSOP Example: 24C02CI SN e3 0527 13F Example: 4C2C TYWW I527 NNN 13F XXXXT YWWNNN 8-Lead 2x3 DFN DS21202G-page 10 24C02C I/P e3 13F 0527 XXXX 8-Lead MSOP XXX YWW NN Example: Example: 4C2CI 52713F Example: 2P7 527 13 © 2007 Microchip Technology Inc. 24C02C 1st Line Marking Codes Part Number DFN TSSOP 24C02C Note: MSOP 4C2C 4C2CT I Temp. E Temp. 2P7 2P8 T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 Note: Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. © 2007 Microchip Technology Inc. DS21202G-page 11 24C02C 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B DS21202G-page 12 © 2007 Microchip Technology Inc. 24C02C 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC 1.75 6.00 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B © 2007 Microchip Technology Inc. DS21202G-page 13 24C02C 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.20 Overall Width E Molded Package Width E1 4.30 6.40 BSC 4.40 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 4.50 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-086B DS21202G-page 14 © 2007 Microchip Technology Inc. 24C02C 8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.75 0.85 0.95 Standoff A1 0.00 – 0.15 Overall Width E Molded Package Width E1 3.00 BSC Overall Length D 3.00 BSC Foot Length L Footprint L1 1.10 4.90 BSC 0.40 0.60 0.80 0.95 REF Foot Angle φ 0° – 8° Lead Thickness c 0.08 – 0.23 Lead Width b 0.22 – 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-111B © 2007 Microchip Technology Inc. DS21202G-page 15 24C02C 8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 NOTE 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 2.00 BSC Overall Width E Exposed Pad Length D2 1.30 – Exposed Pad Width E2 1.50 – 1.90 b 0.18 0.25 0.30 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 0.50 BSC 3.00 BSC 1.75 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-123B DS21202G-page 16 © 2007 Microchip Technology Inc. 24C02C APPENDIX A: REVISION HISTORY Revision D Corrections to Section 1.0, Electrical Characteristics. Revision E Added DFN package. Revision F (02/2007) Revised Features section; Section 1.0 revised Ambient temperature; Revised Tables 1-1, 1-2, (removed commercial temp); Revised Table 2-1; Replaced On-line Support page; Replaced Package Drawings; Revised Product ID section. Revision G (03/2007) Replaced Package Drawings (Rev. AM). © 2007 Microchip Technology Inc. DS21202G-page 17 24C02C NOTES: DS21202G-page 18 © 2007 Microchip Technology Inc. 24C02C THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. DS21202G-page 19 24C02C READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: 24C02C Y N Literature Number: DS21202G Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21202G-page 20 © 2007 Microchip Technology Inc. 24C02C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: 24C02C 2K I2C™ Serial EEPROM 24C02CT 2K I2C™ Serial EEPROM (Tape and Reel) Temperature Range: I E = -40°C to +85°C = -40°C to +125°C Package: P SN ST MS MC = = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC, (3.90 mm Body), 8-lead TSSOP (4.4 mm Body), 8-lead Plastic Micro Small Outline (MSOP), 8-lead 2x3 DFN, 8-lead © 2007 Microchip Technology Inc. DS21202G-page 21 24C02C NOTES: DS21202G-page 22 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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