PIC12C5XX
8-Pin, 8-Bit CMOS Microcontroller
Devices included in this Data Sheet:
CMOS Technology:
PIC12C508 and PIC12C509 are 8-bit microcontrollers
packaged in 8-lead packages. They are based on the
Enhanced PIC16C5X family.
• Low power, high speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.5V to 5.5V
- Industrial: 2.5V to 5.5V
• Low power consumption
- < 2 mA @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 KHz
- < 1 µA typical standby current
High-Performance RISC CPU:
• Only 33 single word instructions to learn
• All instructions are single cycle (1 µs) except for
program branches which are two-cycle
• Operating speed: DC - 4 MHz clock input
DC - 1 µs instruction cycle
Device
EPROM
RAM
Pin Diagram
PDIP, SOIC
VDD
GP5/OSC1/CLKIN
GP4/OSC2
GP3/MCLR/VPP
1
2
3
4
PIC12C508
PIC12C509
PIC12C508
512 x 12
25
PIC12C509
1024 x 12
41
• 12-bit wide instructions
• 8-bit wide data path
• Seven special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
• Internal 4 MHz RC oscillator with programmable
calibration
• In-circuit serial programming
8
7
6
5
VSS
GP0
GP1
GP2/T0CKI
Peripheral Features:
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Wake-up from SLEEP on pin change
• Internal pull-ups on I/O pins
• Selectable oscillator options:
- INTRC: Internal 4 MHz RC oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- LP:
Power saving, low frequency crystal
• Internal pull-up on MCLR pin
1996 Microchip Technology Inc.
Advance Information
This document was created with FrameMaker 4 0 4
DS40139A-page 1
PIC12C5XX
TABLE OF CONTENTS
1.0
General Description ..........................................................................................................................................3
2.0
PIC12C5XX Device Varieties............................................................................................................................5
3.0
Architectural Overview ......................................................................................................................................7
4.0
Memory Organization......................................................................................................................................11
5.0
I/O Port............................................................................................................................................................19
6.0
Timer0 Module and TMR0 Register................................................................................................................21
7.0
Special Features of the CPU ..........................................................................................................................25
8.0
Instruction Set Summary.................................................................................................................................37
9.0
Development Support .....................................................................................................................................49
10.0
Electrical Characteristics - PIC12C5XX ..........................................................................................................53
11.0
Packaging Information ....................................................................................................................................65
Appendix A:PIC16/17 Microcontrollers..........................................................................................................................69
Index..............................................................................................................................................................................79
PIC12C5XX Product Identification System ...................................................................................................................83
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
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DS40139A-page 2
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
1.0
GENERAL DESCRIPTION
The PIC12C5XX from Microchip Technology is a family
of low-cost, high performance, 8-bit, fully static,
EPROM/ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single word/
single cycle instructions. All instructions are single
cycle (1 µs) except for program branches which take
two cycles. The PIC12C5XX delivers performance an
order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC12C5XX products are equipped with special
features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset
Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to
choose from, including INTRC internal oscillator mode
and the power-saving LP (Low Power) oscillator.
Power saving SLEEP mode, Watchdog Timer and code
protection features improve system cost, power and
reliability.
1.1
Applications
The PIC12C5XX series fits perfectly in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The EPROM technology makes customizing application programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or
surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost,
low-power, high performance, ease of use and I/O flexibility make the PIC12C5XX series very versatile even
in areas where no microcontroller use has been
considered before (e.g., timer functions, replacement
of “glue” logic and PLD’s in larger systems, coprocessor applications).
The PIC12C5XX are available in the cost-effective
One-Time-Programmable (OTP) versions which are
suitable for production in any volume. The customer
can take full advantage of Microchip’s price leadership
in OTP microcontrollers while benefiting from the
OTP’s flexibility.
The PIC12C5XX products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, fuzzy logic support tools,
a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM
PC and compatible machines.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 3
DS40139A-page 4
4
4
M
y
or
em
on
n
pi
a
ch
e
ng
Features
512
1024
25
41
TMR0
TMR0
m
ra
Yes
Yes
5
5
1
1
Yes
Yes
2.5-5.5
2.5-5.5
Yes
Yes
33
33
8-pin PDIP, 8-pin SOIC
8-pin PDIP, 8-pin SOIC
All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect
and high I/O current capability.
All PIC12C5XX devices use serial programming with data pin GP0 and clock pin GP1.
PIC12C508
PIC12C509
(M
Peripherals
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TABLE 1-1:
)
Hz
Clock
PIC12C5XX
PIC12C5XX FAMILY OF DEVICES
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
2.0
PIC12C5XX DEVICE VARIETIES
A variety of packaging options are available.
Depending
on
application
and
production
requirements, the proper device option can be
selected using the information in this section. When
placing orders, please use the PIC12C5XX Product
Identification System at the back of this data sheet to
specify the correct part number.
1996 Microchip Technology Inc.
2.1
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages,
permit the user to program them once. In addition to
the program memory, the configuration bits must be
programmed.
Advance Information
DS40139A-page 5
PIC12C5XX
NOTES:
DS40139A-page 6
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12C5XX family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12C5XX uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution
of
instructions.
Consequently,
all
instructions (33) execute in a single cycle (1µs @
4MHz) except for program branches.
The PIC12C508 address 512 x 12 of program
memory, the PIC12C509 addresses 1K x 12 of
program memory. All program memory is internal.
The PIC12C5XX can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC12C5XX has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC12C5XX simple yet efficient.
In addition, the learning curve is reduced significantly.
1996 Microchip Technology Inc.
The PIC12C5XX device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
Advance Information
DS40139A-page 7
PIC12C5XX
FIGURE 3-1:
PIC12C5XX BLOCK DIAGRAM
12
EPROM
512 x 12 or
1024 x 12
Program
Memory
12
RAM Addr (1)
GPIO
GP0
GP1
GP2/T0CKI
GP3/MCLR/Vpp
GP4/OSC2
GP5/OSC1/CLKIN
RAM
25 x 8 or
41 x 8
File
Registers
STACK1
STACK2
Program
Bus
8
Data Bus
Program Counter
9
Addr MUX
Instruction reg
Direct Addr
5
5-7
Indirect
Addr
FSR reg
STATUS reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2
Timing
Generation
Power-on
Reset
Watchdog
Timer
On-Chip OSC
ALU
8
W reg
Timer0
MCLR
VDD, VSS
DS40139A-page 8
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
TABLE 3-1:
PIC12C5XX PINOUT DESCRIPTION
DIP
Pin #
SOIC
Pin #
I/O/P
Type
GP0
7
7
I/O
TTL/ST Bi-directional I/O port/ serial programming clock. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP1
6
6
I/O
TTL/ST Bi-directional I/O port/ serial programming data. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP2/T0CKI
5
5
I/O
ST
Bi-directional I/O port. Can be configured as T0CKI.
GP3/MCLR/VPP
4
4
I
TTL
Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. Weak pullup always on if configured as MCLR
GP4/OSC2
3
3
I/O
TTL
Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, GPIO in other modes).
GP5/OSC1/CLKIN
2
2
I/O
VDD
1
1
P
—
Positive supply for logic and I/O pins
VSS
8
8
P
—
Ground reference for logic and I/O pins
Name
Buffer
Type
Description
TTL/ST Bidirectional IO port oscillator crystal input/external
clock source input (GPIO in Internal RC mode only,
OSC1 in all other oscillator modes).
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 9
PIC12C5XX
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2
(RC mode)
EXAMPLE 3-1:
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
SUB_1
4. BSF
GPIO, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40139A-page 10
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
4.0
MEMORY ORGANIZATION
PIC12C5XX memory is organized into program memory and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one STATUS register bit. For the PIC12C509 with a data memory register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12C5XX
PC<11:0>
12
CALL, RETLW
Stack Level 1
Stack Level 2
Reset Vector (note 1)
The PIC12C508 and PIC12C509 each have a 12-bit
Program Counter (PC) capable of addressing a 2K x
12 program memory space.
On-chip Program
Memory
Only the first 512 x 12 (0000h-01FFh) for the
PIC12C508 and 1K x 12 (0000h-03FFh) for the
PIC12C509 are physically implemented. Refer to
Figure 4-1. Accessing a location above these
boundaries will cause a wrap-around within the first
512 x 12 space (PIC12C508) or 1K x 12 space
(PIC12C509). The reset vector is at 0000h. Location
01FFh (PIC12C508) or location 03FFh (PIC12C509)
contains the internal clock oscillator calibration value.
This value should never be overwritten.
User Memory
Space
Program Memory Organization
4.1
512 Word (PIC12C508)
0000h
01FFh
0200h
On-chip Program
Memory
1024 Word (PIC12C509)
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the effective reset vector. Location 01FFh
(PIC12C508) or location 03FFh
(PIC12C509) contains the MOVLW
XX clock calibration value.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 11
PIC12C5XX
4.2
Data Memory Organization
FIGURE 4-2:
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
PIC12C508 REGISTER FILE
MAP
File Address
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
The general purpose registers are used for data and
control information under command of the instructions.
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
07h
For the PIC12C508, the register file is composed of 7
special function registers and 25 general purpose
registers (Figure 4-2).
General
Purpose
Registers
For the PIC12C509, the register file is composed of 7
special function registers, 25 general purpose
registers, and 16 general purpose registers that may
be addressed using a banking scheme (Figure 4-3).
4.2.1
1Fh
GENERAL PURPOSE REGISTER FILE
Note 1:
Not a physical register. See Section 4.7
The general purpose register file is accessed either
directly or indirectly through the file select register
FSR (Section 4.7).
FIGURE 4-3:
PIC12C509 REGISTER FILE MAP
FSR<6:5>
00
01
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
20h
Addresses map
back to
addresses
in Bank 0.
07h
General
Purpose
Registers
2Fh
0Fh
10h
30h
General
Purpose
Registers
1Fh
3Fh
Bank 0
Note 1:
DS40139A-page 12
General
Purpose
Registers
Bank 1
Not a physical register. See Section 4.7
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
4.2.2
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions to control the
operation of the device (Table 4-1).
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Value on
Wake-up on
Pin Change
N/A
TRIS
I/O control registers
--11 1111
--11 1111
--11 1111
N/A
OPTION
Contains control bits to configure Timer0, Timer0/WDT
prescaler, interrupt on change, and weak pull-ups
1111 1111
1111 1111
1111 1111
00h
INDF
Uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
uuuu uuuu
uuuu uuuu
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
uuuu uuuu
02h(1)
PCL
Low order 8 bits of PC
1111 1111
1111 1111
1111 1111
0001 1xxx
000q quuu
100q quuu
GPWUF
—
03h
STATUS
04h
FSR
(12C508)
Indirect data memory address pointer
111x xxxx
111u uuuu
111u uuuu
04h
FSR
(12C509)
Indirect data memory address pointer
110x xxxx
11uu uuuu
11uu uuuu
04h
FSR
Indirect data memory address pointer
1xxx xxxx
1uuu uuuu
1uuu uuuu
05h
OSCCAL
06h
GPIO
PA0
TO
PD
Z
DC
C
CAL7
CAL6
CAL5
CAL4
—
—
—
—
0111 ----
uuuu ----
uuuu ----
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
--uu uuuu
Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as '0' (if applicable)
x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5
for an explanation of how to access these bits.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 13
PIC12C5XX
4.3
STATUS Register
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bit for
program memories larger than 512 words.
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see Table 82, Instruction Set Summary.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-4:
R/W-0
GPWUF
bit7
STATUS REGISTER (ADDRESS:03h)
R/W-0
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
6
5
4
3
2
1
R/W-x
C
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
GPWUF: GPIO reset bit
1 = Reset from wake-up from SLEEP on pin change
0 = After power up or other reset
bit 6:
Unimplemented
bit 5:
PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh) - PIC12C509
0 = Page 0 (000h - 1FFh) - PIC12C508 and PIC12C509
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF
SUBWF
1 = A carry occurred
1 = A borrow did not occur
0 = A carry did not occur
0 = A borrow occurred
DS40139A-page 14
Advance Information
RRF or RLF
Load bit with LSB or MSB, respectively
1996 Microchip Technology Inc.
PIC12C5XX
4.4
OPTION Register
Note that TRIS overrides OPTION control if GPPU is
enabled and GPWU is disabled.
The OPTION register is a 8-bit wide, write-only
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
Note:
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<7:0> bits.
If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin.
Note:
If the TOCS bit is set to ‘1’, GP2 is forced
to be an input even if TRIS GP2 = ‘0’
FIGURE 4-5:
W-1
GPWU
bit7
OPTION REGISTER
W-1
GPPU
6
W-1
T0CS
5
W-1
T0SE
4
W-1
PSA
3
W-1
PS2
2
bit 7:
GPWU: Enable wake-up on pin change (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6:
GPPU: Enable weak pull-ups (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5:
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Transition on internal instruction cycle clock, Fosc/4
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0:
PS2:PS0: Prescaler rate select bits
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1996 Microchip Technology Inc.
W-1
PS1
1
Advance Information
W-1
PS0
bit0
W = Writable bit
U = Unimplemented bit
- n = Value at POR reset
Reference Table 4-1 for
other resets.
DS40139A-page 15
PIC12C5XX
4.5
Program Counter
4.5.1
EFFECTS OF RESET
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the oscillator calibration instruction. After
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 46).
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is preselected.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-6).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.
Note:
Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any program memory page (512 words long).
FIGURE 4-6:
LOADING OF PC
BRANCH INSTRUCTIONS PIC12C508/C509
GOTO Instruction
11 10
9
8 7
0
PC
Therefore, upon a RESET, a GOTO instruction will
automatically cause the program to jump to page 0
until the value of the page bits is altered.
4.6
Stack
PIC12C5XX devices have a 12-bit wide hardware
push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1.
If more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
PCL
Instruction Word
PA0
7
0
STATUS
CALL or Modify PCL Instruction
11 10
9
8 7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
STATUS
DS40139A-page 16
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
4.7
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2:
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 4-1:
INDIRECT ADDRESSING
NEXT
movlw
movwf
clrf
incf
btfsc
goto
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
•
•
•
•
Register file 07 contains the value 10h
Register file 08 contains the value 0Ah
Load the value 07 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 08)
• A read of the INDR register now will return the
value of 0Ah.
:
;YES, continue
The FSR is a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
PIC12C508: Does not use banking. FSR<6:5> are
unimplemented and read as '1's.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
PIC12C509: Uses FSR<5>. Selects between bank 0
and bank 1. FSR<6> is unimplemented, read as '1’ .
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
6 5
4
bank select
location select
Indirect Addressing
(opcode)
0
6
5
4
bank
00
(FSR)
0
location select
01
00h
Addresses
map back to
addresses
in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
3Fh
Bank 1(2)
Note 1: For register map detail see Section 4.2.
Note 2: PIC12C509 only
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 17
PIC12C5XX
NOTES:
DS40139A-page 18
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
5.0
I/O PORT
5.3
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF GPIO,W) always read the
I/O pins independent of the pin’s input/output modes.
On RESET, all I/O ports are defined as input (inputs
are at hi-impedance) since the I/O control registers are
all set. GP0 and GP1 can be programmed in software
with weak pull-ups.
5.1
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output
operations. For input operations these ports are nonlatching. Any input must be present until read by an
input instruction (e.g., MOVF GPIO,W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pullup is always on and wake-up on change for this pin is
not set.
5.2
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
VDD
Q
CK
P
N
W
Reg
TRIS Register
Q
Data
Latch
WR
Port
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see
Section 4.4.
Note:
I/O Interfacing
D
Q
TRIS
Latch
TRIS ‘f’
I/O
pin(1)
VSS
Q
CK
Reset
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 5-1:
Address
N/A
SUMMARY OF PORT REGISTERS
Name
TRIS
Bit 7
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Value on
Wake-up on
Pin Change
--11 1111
--11 1111
--11 1111
GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
I/O control registers
N/A
OPTION
1111 1111
1111 1111
03H
STATUS GPWUF
GPWU
—
PA0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
100q quuu
06h
GPIO
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
--uu uuuu
—
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
q = see tables in Section 7.7 for possible values.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 19
PIC12C5XX
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit5 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wiredand”). The resulting high output currents may damage
the chip.
FIGURE 5-2:
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;GPIO<6> have external pull-ups and are
;not connected to other circuitry
;
;
GPIO latch GPIO pins
;
---------- ---------BCF
GPIO, 5
;--01 -ppp
--11 pppp
BCF
GPIO, 4
;--10 -ppp
--11 pppp
MOVLW 007h
;
TRIS GPIO
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP4 to be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF GPIO
PC + 1
MOVF GPIO,W
PC + 2
PC + 3
NOP
NOP
GP5:GP0
Port pin
written here
Instruction
executed
DS40139A-page 20
MOVWF GPIO
(Write to
GPIO)
Port pin
sampled here
MOVF GPIO,W
(Read
GPIO)
This example shows a write to GPIO followed
by a read from GPIO.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
NOP
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
6.0
TIMER0 MODULE AND
TMR0 REGISTER
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of
1:2, 1:4,..., 1:256 are selectable. Section 6.2 details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
Data bus
GP2/T0CKI
Pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler(2)
0
T0SE
8
Sync with
Internal
Clocks
TMR0 reg
PSout
(2 cycle delay) Sync
3
T0CS(1)
PS2, PS1, PS0(1)
PSA(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 21
PIC12C5XX
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
MOVWF TMR0
T0
Timer0
T0+1
Instruction
Executed
FIGURE 6-3:
PC+2
PC+3
PC+4
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+5
MOVF TMR0,W
NT0
NT0+1
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+2
Read TMR0
reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
MOVWF TMR0
Instruction
Fetch
PC+1
Instruction
Execute
PC+3
PC+4
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC+5
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
TABLE 6-1:
PC+2
T0+1
T0
Timer0
Address
PC+1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h
TMR0
Timer0 - 8-bit real-time clock/counter
N/A
OPTION GPWU GPPU T0CS T0SE PSA PS2
N/A
TRIS
Value on
Power-On
Reset
Value on
Value on
MCLR and Wake-up on
WDT Reset Pin Change
xxxx xxxx uuuu uuuu uuuu uuuu
PS1
PS0 1111 1111 1111 1111 1111 1111
I/O control registers
--11 1111 --11 1111 --11 1111
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged,
DS40139A-page 22
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
6.1
Using Timer0 with an External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
6.1.3
OPTION REGISTER EFFECT ON GP2 TRIS
If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of the TRIS register setting.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 23
PIC12C5XX
6.2
Prescaler
EXAMPLE 6-1:
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 7.6). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
CLRF
CLRWDT
TMR0
MOVLW
OPTION
'xxxx1xxx'
;Clear TMR0
;Clears WDT and
;prescaler
;Select new prescale
;value
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before switching
the prescaler.
The PSA and PS2:PS0 bits (OPTION<3:0>)
determine prescaler assignment and prescale ratio.
EXAMPLE 6-2:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT. The prescaler is neither
readable nor writable. On a RESET, the prescaler
contains all '0's.
6.2.1
CHANGING PRESCALER
(TIMER0→WDT)
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
MOVLW
'xxxx0xxx'
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
0
GP2/T0CKI
Pin
1
8
M
U
X
1
M
U
X
0
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Sync
2
Cycles
TMR0 reg
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40139A-page 24
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
7.0
SPECIAL FEATURES OF THE
CPU
The PIC12C5XX has a Watchdog Timer which can be
shut off only through configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
XT or LP selectable oscillator options, there is always
an 18 ms delay provided by the Device Reset Timer
(DRT), intended to keep the chip in reset until the
crystal oscillator is stable. If using INTRC or EXTRC
there is an 18 ms delay only on VDD power-up. With
this timer on-chip, most applications need no external
reset circuitry.
What sets a microcontroller apart from other
processors are special circuits to deal with the needs
of real-time applications. The PIC12C5XX family of
microcontrollers has a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRL RC oscillator option saves system cost
while the LP crystal option saves power. A set of
configuration bits are used to select various options.
• Oscillator selection
• Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit Serial Programming
7.1
Configuration Bits
The PIC12C5XX configuration word consists of 5 bits.
Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.
One bit is the code protection bit (Figure 7-1).
OTP devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see “Product Identification System” on
the inside back cover).
FIGURE 7-1:
CONFIGURATION WORD FOR PIC12C508 OR PIC12C509
—
—
—
—
—
—
—
MCLRE
CP
bit11
10
9
8
7
6
5
4
3
WDTE FOSC1 FOSC0
2
1
bit0
Register:
Address(1):
CONFIG
FFFh
bit 11-5: Unimplemented
bit 4:
MCLRE: MCLR enable bit.
1 = MCLR enabled
0 = MCLR disabled
bit 3:
CP: Code protection bit.
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator selection bits
11 = EXTRC - external RC oscillator
10 = INTRC - internal RC oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the
configuration word. This register is not user addressable during device operation.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 25
PIC12C5XX
7.2
Oscillator Configurations
7.2.1
OSCILLATOR TYPES
TABLE 7-1:
The PIC12C5XX can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1:FOSC0) to select one of
these four modes:
•
•
•
•
LP:
XT:
INTRC:
EXTRC:
7.2.2
Low Power Crystal
Crystal/Resonator
Internal 4 MHz Oscillator
External Resistor/Capacitor
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT or LP modes, a crystal or ceramic resonator is
connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 7-2). The
PIC12C5XX oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in XT or LP modes, the device
can have an external clock source drive the GP5/
OSC1/CLKIN pin (Figure 7-3).
FIGURE 7-2:
CRYSTAL OPERATION (OR
CERAMIC RESONATOR) (XT
OR LP OSC
CONFIGURATION)
C1(1)
OSC1
PIC12C5XX
SLEEP
XTAL
RS(2)
RF(3)
OSC2
To internal
logic
Osc
Type
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C5XX
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
XT
455 kHz
68-100 pF
68-100 pF
2.0 MHz
15-33 pF
15-33 pF
4.0 MHz
10-22 pF
10-22 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 7-2:
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC12C5XX
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
15 pF
15 pF
32 kHz(1)
200-300 pF
15-30 pF
100 kHz
100-200 pF
15-30 pF
200 kHz
15-100 pF
15-30 pF
455 kHz
15-30 pF
15-30 pF
1 MHz
15 pF
15 pF
2 MHz
15 pF
15 pF
4 MHz
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
LP
XT
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
FIGURE 7-3:
EXTERNAL CLOCK INPUT
OPERATION (XT OR LP OSC
CONFIGURATION)
OSC1
PIC12C5XX
Clock from
ext. system
Open
DS40139A-page 26
OSC2
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-4 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 7-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC12C5XX
CLKIN
10k
XTAL
10k
20 pF
20 pF
Figure 7-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 7-5:
7.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Figure 7-6 shows how the R/C combination is
connected to the PIC12C5XX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
To Other
Devices
330
74AS04
74AS04
74AS04
PIC12C5XX
CLKIN
0.1 µF
XTAL
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 27
PIC12C5XX
FIGURE 7-6:
RC OSCILLATOR MODE
VDD
7.3
RESET
The device differentiates between various kinds of
reset:
Rext
OSC1
Internal
clock
a) Power on reset (POR)
b) MCLR reset during normal operation
N
Cext
PIC12C5XX
c) MCLR reset during SLEEP
d) WDT time-out reset during normal operation
VSS
e) WDT time-out reset during SLEEP
f) Wake-up from SLEEP on pin change
7.2.5
INTERNAL 4 MHZ RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock.
In addition, a calibration instruction is programmed into
the top of memory which indicates the calibration value
for the internal RC oscillator. This value, OSCCAL, is
programmed as a MOVLW XX instruction where XX is the
calibration value, and is placed at the reset vector. This
will load the W register with the calibration value upon
reset and the PC will then roll over to 0x000. The user
then has the option of writing the value to the OSCCAL
Register (05h) or ignoring it.
TABLE 7-3:
Some registers are not reset in any way; they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to “reset state” on poweron reset (POR), on MCLR or WDT reset during normal
operation . They are not affected by a WDT reset during
SLEEP or MCLR reset during SLEEP, since these
resets are viewed as resumption of normal operation.
The exceptions to this are TO, PD, and GPWUF bits.
They are set or cleared differently in different reset situations. These bits are used in software to determine
the nature of reset. See Table 7-3 for a full description
of reset states of all registers.
RESET CONDITIONS FOR REGISTERS
Register
Address
Power-on Reset
MCLR Reset
WDT time-out
Wake-up on Pin Change
W
—
qqqq xxxx (1)
qqqq uuuu (1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
?00? ?uuu (2)
FSR (12C508)
04h
111x xxxx
111u uuuu
FSR (12C509)
04h
110x xxxx
11uu uuuu
OSCCAL
05h
0111 ----
uuuu ----
GPIO
06h
--xx xxxx
--uu uuuu
OPTION
—
1111 1111
1111 1111
TRIS
—
--11 1111
--11 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, ? = value depends on condition.
Note 1:
Bits <7:4> of W register contain oscillator calibration (OSCCAL) values due to MOVLW XX instruction at
top of memory.
Note 2:
See Table 7-6 for reset value for specific conditions
DS40139A-page 28
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
1111 1111
MCLR reset during normal operation
000u uuuu
1111 1111
MCLR reset during SLEEP
0001 0uuuu
1111 1111
WDT reset during SLEEP
0000 0uuu
1111 1111
WDT reset normal operation
0000 1uuu
1111 1111
Wake-up from SLEEP on pin change
1001 0uuu
1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.
7.3.1
MCLR ENABLE
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD, and the pin is assigned to be a GPIO. See
Figure 7-7.
FIGURE 7-7:
MCLR SELECT
A power-up example where MCLR is tied to VSS is
shown in Figure 7-9. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
MCLRE
WEAK
PULL-UP
GP3/MCLR/VPP
7.4
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the onchip reset signal.
INTERNAL MCLR
Power-On Reset (POR)
The PIC12C5XX family incorporates on-chip PowerOn Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, tie the MCLR pin directly
to VDD. An internal weak pull-up resistor is implemented using a transistor. Refer to Table 10-5 for the
pull-up resistor ranges. This will eliminate external RC
components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified. See
Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
In Figure 7-10, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The
VDD is stable before the start-up timer times out and
there is no problem in getting a proper reset. However,
Figure 7-11 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the GP3/MCLR/VPP pin, and when
the GP3/MCLR/VPP pin (and VDD) actually reach their
full value, is too long. In this situation, when the startup timer times out, VDD has not reached the VDD (min)
value and the chip is, therefore, not guaranteed to
function correctly. For such situations, we recommend
that external RC circuits be used to achieve longer
POR delay times (Figure 7-10).
Note:
When the device starts normal operation
(exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
For additional information refer to Application Notes
“Power-Up Considerations” - AN522 and “Power-up
Trouble Shooting” - AN607.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-8.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 29
PIC12C5XX
FIGURE 7-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
Pin Change
Wake-up on
pin change
SLEEP
GP3/MCLR/VPP
WDT Time-out
MCLRE
RESET
On-Chip
DRT OSC
8-bit Asynch
Ripple Counter
(Start-Up Timer)
S
Q
R
Q
CHIP RESET
DS40139A-page 30
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 31
PIC12C5XX
7.5
Device Reset Timer (DRT)
7.6
In the PIC12C5XX, the DRT runs any time the device
is powered up. DRT runs from RESET only in XT and
LP modes. It is disabled from RESET in INTRC and
EXTRC modes.
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after the voltage on the GP3/MCLR/VPP pin has
reached a logic high (VIHMC) level. Thus, external RC
networks connected to the MCLR input are not
required in most cases, allowing for savings in costsensitive and/or space restricted applications.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the clock on the GP5/OSC1/
CLKIN and GP4/OSC2 pins have been stopped, for
example, by execution of a SLEEP instruction. During
normal operation or SLEEP, a WDT reset or wake-up
reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 7.1). Refer to the PIC12C5XX Programming
Specifications to determine how to access the
configuration word.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog
Timer time-out (only in XT and LP modes). This is
particularly important for applications using the WDT
to wake from SLEEP mode automatically.
DS40139A-page 32
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
7.6.1
7.6.2
WDT PERIOD
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, time-out a
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-topart process variations (see DC specs).
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
1
Watchdog
Timer
M
U
X
Postscaler
Postscaler
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
EPROM Bit
To Timer0 (Figure 6-4)
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 7-5:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
Value on
Power-On
Reset
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
1111 1111
PS0
Value on
MCLR and
WDT Reset
Value on
Wake-up on
Pin Change
1111 1111
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as '0', u = unchanged
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 33
PIC12C5XX
7.7
Time-Out Sequence, Power Down,
and Wake-up from SLEEP Status Bits
(TO/PD/GPWUF)
The TO, PD, and GPWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset, or a MCLR or WDT
reset.
TABLE 7-6:
TO/PD/GPWUF STATUS
AFTER RESET
GPWUF
TO
PD
0
0
0
0
0
1
0
1
0
0
1
1
0
u
u
1
1
0
Legend:
RESET caused by
WDT wake-up from
SLEEP
WDT time-out (not from
SLEEP)
MCLR wake-up from
SLEEP
Power-up
MCLR not during SLEEP
Wake-up from SLEEP on
pin change
Legend: u = unchanged
Note 1: The TO, PD, and GPWUF bits maintain their status (u) until a reset
occurs. A low-pulse on the MCLR
input does not change the TO, PD,
and GPWUF status bits.
These STATUS bits are only affected by events listed
in Table 7-7.
TABLE 7-7:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
GPWUF
TO
PD
Power-up
WDT Time-out
0
1
1
0
0
u
SLEEP instruction
CLRWDT
instruction
Wake-up from
SLEEP on pin
change
u
1
0
u
1
1
1
1
0
Reset on Brown-Out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and
then recovers. The device should be reset in the event
of a brown-out.
To reset PIC12C5XX devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 7-13 and Figure 7-14.
FIGURE 7-13: BROWN-OUT PROTECTION
CIRCUIT 1
VDD
VDD
33k
10k
Q1
MCLR
40k* PIC12C5XX
This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
*Refer to Figure 7-7 and Table 10-5 for internal weak pullup on MCLR.
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
VDD
R1
Remarks
Q1
MCLR
No effect
on PD
Legend: u = unchanged
A WDT time-out will occur regardless of the status of the
TO bit. A SLEEP instruction will be executed, regardless of
the status of the PD bit. Table 7-6 reflects the status of TO
and PD after the corresponding event.
Table 7-4 lists the reset conditions for the special
function registers, while Table 7-3 lists the reset
conditions for all the registers.
DS40139A-page 34
7.8
R2
40k
PIC12C5XX
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
VDD •
R1
R1 + R2
= 0.7V
*Refer to Figure 7-7 and Table 10-5 for internal weak
pull-up on MCLR.
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
7.9
Power-Down Mode (SLEEP)
7.10
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
Program Verification/Code Protection
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
7.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other codeidentification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as '1's.
It should be noted that a RESET generated by a WDT
time-out does not drive the GP3/MCLR/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level (VIHMC) if
MCLR is enabled.
7.9.2
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
An external reset input on GP3/MCLR/VPP pin.
A Watchdog Timer time-out reset (if WDT was
enabled).
A change on input pin GP0, GP1, or GP3
These events cause a device reset. The TO, PD, and
GPWUF bits can be used to determine the cause of
device reset.. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
SLEEP at pins GP0, GP1, or GP3 (since the last time
there was a file or bit operation on GP port).
Caution: Right before entering SLEEP, read the
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before
reentering SLEEP, a wake up will occur
immediately even if no pins change while
in SLEEP mode.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 35
PIC12C5XX
7.12
In-Circuit Serial Programming
The PIC12C5XX microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC12C5XX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1
Data I/O
GP0
After reset, a 6-bit command is then supplied to the
device. Depending on the command, 14-bits of program data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC12C5XX Programming Specifications.
VDD
To Normal
Connections
A typical in-circuit serial programming connection is
shown in Figure 7-15.
DS40139A-page 36
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
8.0
INSTRUCTION SET SUMMARY
Each PIC12C5XX instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC12C5XX
instruction set summary in Table 8-2 groups the
instructions into byte-oriented, bit-oriented, and literal
and control operations. Table 8-1 shows the opcode
field descriptions.
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.
The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
TABLE 8-1:
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
Label name
TOS
Top of Stack
PC
Program Counter
WDT
Watchdog Timer Counter
TO
Time-Out bit
PD
Power-Down bit
11
6
OPCODE
5
d
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
8 7
5 4
b (BIT #)
f (FILE #)
0
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTO instruction
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
Destination, either the W register or the specified
register file location
[ ]
Options
( )
Contents
→
Assigned to
<>
Register bit field
∈
Byte-oriented file register operations
Literal and control operations (except GOTO)
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
label
GENERAL FORMAT FOR
INSTRUCTIONS
b = 3-bit bit address
f = 5-bit file register address
W
italics
FIGURE 8-1:
Description
Register file address (0x00 to 0x7F)
dest
0xhhh
where 'h' signifies a hexadecimal digit.
OPCODE
f
d
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
11
OPCODE FIELD
DESCRIPTIONS
Field
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
In the set of
User defined term (font is courier)
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 37
PIC12C5XX
TABLE 8-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f,d
f,d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
Cycles MSb
LSb
Status
Affected Notes
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C,DC,Z
None
Z
1,2,4
2,4
4
1
1
1 (2)
1 (2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2,4
2,4
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
2,4
2,4
2,4
2,4
2,4
2,4
1,4
2,4
2,4
1,2,4
2,4
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
k
k
k
–
f
k
AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W
1
3
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except forGOTO.
(Section 4.5)
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5, 6, or 7 causes the contents of the W register to be written to the tristate
latches of GPIO. A '1' forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40139A-page 38
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
0001
11df
f,d
Encoding:
ffff
0001
f,d
01df
ffff
Description:
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'.
Description:
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Example:
ADDWF
FSR, 0
Before Instruction
W
=
FSR =
Cycles:
1
Example:
ANDWF
W =
FSR =
0x17
0xC2
After Instruction
W
=
FSR =
W
=
FSR =
0xD9
0xC2
And literal with W
BCF
Syntax:
[ label ] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W).AND. (k) → (W)
Status Affected:
Z
Encoding:
1110
Description:
kkkk
1
Cycles:
1
Example:
ANDLW
0x5F
Before Instruction
W
=
0xA3
After Instruction
W
k
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Words:
=
1
Before Instruction
0x17
0xC2
After Instruction
ANDLW
FSR,
0x17
0x02
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
0 → (f<b>)
Status Affected:
None
Encoding:
0100
f,b
bbbf
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example:
BCF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
0x03
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 39
PIC12C5XX
BSF
Bit Set f
Syntax:
[ label ] BSF
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operands:
0 ≤ f ≤ 31
0≤b<7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0101
f,b
bbbf
Encoding:
ffff
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Example:
BSF
FLAG_REG,
FLAG_REG = 0x8A
Words:
1
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0≤b≤7
Before Instruction
Operation:
skip if (f<b>) = 0
After Instruction
Status Affected:
None
Encoding:
Description:
PC
bbbf
0110
ffff
If bit 'b' in register 'f' is 0 then the next
instruction is skipped.
If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
BTFSC
GOTO
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and an NOP is
executed instead, making this a 2 cycle
instruction.
Before Instruction
After Instruction
bbbf
Description:
7
FLAG_REG = 0x0A
0111
If FLAG<1>
PC
if FLAG<1>
PC
BTFSS
GOTO
•
•
•
FLAG,1
PROCESS_CODE
=
address (HERE)
=
=
=
=
0,
address (FALSE);
1,
address (TRUE)
FLAG,1
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address (HERE)
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
After Instruction
if FLAG<1>
PC
if FLAG<1>
PC
DS40139A-page 40
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
CALL
Subroutine Call
CLRW
Clear W
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
(PC) + 1→ Top of Stack;
k → PC<7:0>;
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Operation:
00h → (W);
1→Z
Status Affected:
Z
Status Affected:
None
Encoding:
Description:
1001
kkkk
kkkk
Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a
two cycle instruction.
1
Cycles:
2
Example:
HERE
CALL
0000
The W register is cleared. Zero bit (Z)
is set.
Words:
1
Cycles:
1
Example:
CLRW
Before Instruction
W
=
0x5A
After Instruction
address (THERE)
address (HERE + 1)
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 31
Operation:
00h → (f);
1→Z
Status Affected:
Z
0000
f
011f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
Status Affected:
TO, PD
Words:
1
Cycles:
1
Example:
CLRF
FLAG_REG
Before Instruction
=
0x5A
=
=
0x00
1
After Instruction
1996 Microchip Technology Inc.
0000
0000
0100
Description:
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if the
prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
set.
Words:
1
Cycles:
1
Example:
CLRWDT
ffff
The contents of register 'f' are cleared
and the Z bit is set.
FLAG_REG
Z
0x00
1
Encoding:
Description:
FLAG_REG
=
=
THERE
address (HERE)
Encoding:
0100
Description:
W
Z
Before Instruction
PC =
TOS =
0000
After Instruction
Words:
PC =
Encoding:
Before Instruction
WDT counter =
?
After Instruction
WDT counter
WDT prescale
TO
PD
Advance Information
=
=
=
=
0x00
0
1
1
DS40139A-page 41
PIC12C5XX
COMF
Complement f
Syntax:
[ label ] COMF
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d;
Status Affected:
Z
Status Affected:
None
Encoding:
0010
f,d
01df
Encoding:
ffff
Description:
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
Words:
1
Cycles:
1
Example:
COMF
REG1
=
0x13
After Instruction
REG1
W
=
=
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – 1 → (dest)
Status Affected:
Z
Encoding:
Description:
0000
1
Cycles:
1
Example:
DECF
Before Instruction
CNT
Z
=
=
0x01
0
After Instruction
CNT
Z
=
=
Words:
1
Cycles:
1(2)
Example:
HERE
DECFSZ
GOTO
CONTINUE •
•
•
CNT, 1
LOOP
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
11df
CNT,
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
address (HERE+1)
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded
and an NOP is executed instead making it a two cycle instruction.
0x13
0xEC
DECF
11df
Description:
REG1,0
Before Instruction
0010
skip if result = 0
GOTO
Unconditional Branch
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 511
Operation:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
Status Affected:
None
1
Encoding:
101k
GOTO k
kkkk
kkkk
Description:
GOTO is an unconditional branch. The
9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>. GOTO is a
two cycle instruction.
Words:
1
Cycles:
2
Example:
GOTO THERE
0x00
1
After Instruction
PC =
DS40139A-page 42
Advanced Information
address (THERE)
1996 Microchip Technology Inc.
PIC12C5XX
INCF
Increment f
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(f) + 1 → (dest)
(W) .OR. (k) → (W)
Operation:
Status Affected:
Z
Status Affected:
Z
Encoding:
Encoding:
Description:
INCF f,d
0010
10df
ffff
Words:
1
Cycles:
1
Example:
INCF
CNT,
=
=
kkkk
kkkk
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Cycles:
1
Example:
IORLW
0x35
Before Instruction
1
W
Before Instruction
CNT
Z
1101
Description:
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
IORLW k
=
0x9A
After Instruction
0xFF
0
W
Z
=
=
0xBF
0
After Instruction
CNT
Z
=
=
0x00
1
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
IORWF
f,d
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W).OR. (f) → (dest)
Status Affected:
Z
Operation:
(f) + 1 → (dest), skip if result = 0
Encoding:
Status Affected:
None
Description:
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
1
Cycles:
1
Example:
IORWF
Encoding:
Description:
0011
INCFSZ f,d
11df
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, then the next instruction, which is already fetched, is discarded and an NOP is executed
instead making it a two cycle instruction.
0001
00df
ffff
RESULT, 0
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
Words:
1
Cycles:
1(2)
Example:
HERE
INCFSZ
GOTO
CONTINUE •
•
•
CNT,
LOOP
1
RESULT =
W
=
Z
=
0x13
0x93
0
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 43
PIC12C5XX
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
Status Affected:
Z
Encoding:
Encoding:
0010
Description:
MOVF f,d
00df
ffff
The contents of register 'f' is moved to
destination 'd'. If 'd' is 0, destination is
the W register. If 'd' is 1, the destination
is file register 'f'. 'd' is 1 is useful to test
a file register since status flag Z is
affected.
MOVWF
Move W to f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
Operation:
(W) → (f)
Status Affected:
None
1
Cycles:
1
Example:
MOVF
MOVLW
Move data from the W register to register 'f'.
Words:
1
Cycles:
1
Example:
MOVWF
TEMP_REG
TEMP_REG
W
FSR,
=
=
0xFF
0x4F
=
=
0x4F
0x4F
After Instruction
0
TEMP_REG
W
value in FSR register
NOP
No Operation
Move Literal to W
Syntax:
[ label ]
NOP
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
No operation
Operation:
k → (W)
Status Affected:
None
Status Affected:
None
MOVLW k
Encoding:
0000
0000
Description:
No operation.
The eight bit literal 'k' is loaded into the
W register. The don’t cares will assemble as 0s.
Words:
1
Cycles:
1
Words:
1
Example:
NOP
Cycles:
1
Example:
MOVLW
Encoding:
1100
Description:
ffff
Description:
After Instruction
=
001f
f
Before Instruction
Words:
W
0000
MOVWF
kkkk
kkkk
0000
0x5A
After Instruction
W
=
0x5A
DS40139A-page 44
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
OPTION
Load OPTION Register
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ] RLF
Operands:
None
Operands:
Operation:
(W) → OPTION
0 ≤ f ≤ 31
d ∈ [0,1]
Status Affected:
None
Operation:
See description below
Status Affected:
C
Encoding:
0000
OPTION
0000
0010
Description:
The content of the W register is loaded
into the OPTION register.
Words:
1
Cycles:
1
Example
Encoding:
Description:
OPTION
0011
=
After Instruction
0x07
RETLW
Return with Literal in W
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
k → (W);
TOS → PC
Status Affected:
None
Encoding:
1000
Description:
RLF
Example:
CALL TABLE ;W contains
;table offset
;value.
•
;W now has table
•
;value.
•
ADDWF PC
;W = offset
RETLW k1
;Begin table
RETLW k2
;
•
•
•
RETLW kn
; End of table
Before Instruction
0x07
After Instruction
value of k8
REG1,0
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
kkkk
2
=
Example:
REG1
W
C
Cycles:
W
1
After Instruction
1
=
Cycles:
REG1
C
Words:
W
1
Before Instruction
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
TABLE
Words:
RETLW k
kkkk
ffff
register 'f'
C
0x07
OPTION =
01df
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
Before Instruction
W
f,d
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
Status Affected:
C
Encoding:
Description:
0011
RRF f,d
00df
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
register 'f'
C
Words:
1
Cycles:
1
Example:
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
1996 Microchip Technology Inc.
Advance Information
=
=
=
1110 0110
0111 0011
0
DS40139A-page 45
PIC12C5XX
SLEEP
Enter SLEEP Mode
SUBWF
Subtract W from f
Syntax:
[label]
Syntax:
[label]
Operands:
None
Operands:
Operation:
00h → WDT;
0 → WDT prescaler;
1 → TO;
0 → PD
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – (W) → (dest)
Status Affected:
C, DC, Z
Status Affected:
Encoding:
TO, PD, GPWUF
Encoding:
Description:
SLEEP
0000
0000
Words:
1
Cycles:
1
Example:
SLEEP
10df
ffff
Description:
Subtract (2’s complement method) the
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
Cycles:
1
Example 1:
SUBWF
0011
Time-out status bit (TO) is set. The
power down status bit (PD) is cleared.
GPWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into SLEEP mode
with the oscillator stopped. See section on SLEEP for more details.
0000
SUBWF f,d
REG1, 1
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
REG1
W
C
=
=
=
1
2
1
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
DS40139A-page 46
Advanced Information
=
=
=
FF
2
0
; result is negative
1996 Microchip Technology Inc.
PIC12C5XX
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[label]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Status Affected:
None
Encoding:
XORLW k
1111
kkkk
kkkk
Description:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Cycles:
1
Words:
1
Example:
XORLW
Cycles:
1
Example
SWAPF
Encoding:
0011
Description:
10df
ffff
REG1,
W
0
=
=
0xB5
After Instruction
Before Instruction
REG1
0xAF
Before Instruction
W
0xA5
=
0x1A
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
f,d
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
Operation:
(W) .XOR. (f) → (dest)
Operands:
f=6
Status Affected:
Z
Operation:
(W) → TRIS register f
Encoding:
Status Affected:
None
Encoding:
0000
f
0000
TRIS register 'f' (f = 6) is loaded with the
contents of the W register
Words:
1
Cycles:
1
Example
TRIS
GPIO
Before Instruction
W
=
Note:
=
ffff
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
Cycles:
1
Example
XORWF
REG,1
Before Instruction
0XA5
After Instruction
TRIS
10df
Description:
0fff
Description:
0001
0XA5
f = 6 for PIC12C5XX only.
1996 Microchip Technology Inc.
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
Advance Information
=
=
0x1A
0xB5
DS40139A-page 47
PIC12C5XX
NOTES:
DS40139A-page 48
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH−MP)
• The PIC12C508 and PIC12C509 are supported
by the systems shown in Table 9-1.
9.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC16C5X,
PIC16CXX and PIC17CXX families. PICMASTER is
supplied with the MPLAB Integrated Development
Environment (IDE), which allows editing, “make” and
download, and source debugging from a single environment.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
9.3
ICEPIC: Low-cost PIC16CXX In-Circuit
Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
9.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
9.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART Plus supports all PIC16/17 devices with up
to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 49
PIC12C5XX
9.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
9.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
9.8
PICDEM-3 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features
DS40139A-page 50
include an RS-232 interface, push-button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12
segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an
additional RS-232 interface and Windows 3.1 software
for showing the demultiplexed LCD signals on a PC. A
simple serial interface allows the user to construct a
hardware demultiplexer for the LCD signals. PICDEM3 will be available in the 3rd quarter of 1996.
9.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
9.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC16C5X, PIC16CXX, and
PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
Advanced Information
1996 Microchip Technology Inc.
PIC12C5XX
MPASM allows full symbolic debugging from
the Microchip Universal Emulator System
(PICMASTER).
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
MPASM has the following features to assist in developing software for specific use applications.
9.14
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal
source and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source
code shorter and more maintainable.
9.11
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
9.15
SEEVAL Evaluation and
Programming System
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break,
or in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
9.12
MP-DriveWay – Application Code
Generator
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment
for
Microchip’s
PIC16/17
family
of
microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with
other compilers.
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
9.16
TrueGauge Intelligent Battery
Management
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
9.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 51
SW006005
SW006005
SW006005
SW007002
SW007002
SW007002
SW007002
PIC16C61
PIC16C62, 62A,
64, 64A
PIC16C620, 621, 622
1996 Microchip Technology Inc.
SW006005
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
PIC16C71
PIC16C710, 711
PIC16C72
PIC16F83
PIC16C84
Advance Information
PIC16F84
PIC16C923, 924*
SW006006
SW006006
SW006006
SW006006
SW006006
SW006006
SW006006
—
SW006006
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
—
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
—
—
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
—
Product
All 2 wire and 3 wire
Serial EEPROM's
MTA11200B
HCS200, 300, 301 *
SEEVAL Designers Kit
DV243001
N/A
N/A
TRUEGAUGE Development Kit
N/A
DV114001
N/A
PIC17C42,
SW007002
SW006005
SW006006
42A, 43, 44
*Contact Microchip Technology for availability date
**MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and
MPASM Assembler
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW007002
PIC16C63, 65, 65A,
73, 73A, 74, 74A
PIC16C642, 662*
SW006006
SW006006
SW006006
—
SW006006
—
MP-DriveWay
Applications
Code
Generator
—
N/A
PG306001
Hopping Code Security Programmer Kit
N/A
N/A
DM303001
Hopping Code Security Eval/Demo Kit
N/A
****PRO MATE PICSTART Lite PICSTART Plus
ICEPIC
*** PICMASTER/
Low-Cost
Ultra Low-Cost
II Universal
Low-Cost
PICMASTER-CE
Universal
Dev. Kit
Microchip
In-Circuit
In-Circuit
Dev. Kit
Programmer
Emulator
Emulator
EM167015/
—
DV007003
—
DV003001
EM167101
EM147001/
—
DV007003
—
DV003001
EM147101
EM167015/
EM167201
DV007003
DV162003
DV003001
EM167101
EM167033/
—DV007003
—
DV003001
EM167113
EM167021/
EM167205
DV007003
DV162003
DV003001
N/A
EM167025/
EM167203
DV007003
DV162002
DV003001
EM167103
EM167023/
EM167202
DV007003
DV162003
DV003001
EM167109
EM167025/
EM167204
DV007003
DV162002
DV003001
EM167103
EM167035/
—DV007003
DV162002
DV003001
EM167105
EM167027/
EM167205
DV007003
DV162003
DV003001
EM167105
EM167027/
—
DV007003
DV162003
DV003001
EM167105
EM167025/
—
DV007003
DV162002
DV003001
EM167103
EM167029/
—
DV007003
DV162003
DV003001
EM167107
EM167029/
EM167206
DV007003
DV162003
DV003001
EM167107
EM167029/
—
DV007003
DV162003
DV003001
EM167107
EM167031/
—
DV007003
—
DV003001
EM167111
EM177007/
—
DV007003
—
DV003001
EM177107
***All PICMASTER and PICMASTER-CE ordering part numbers above include
PRO MATE II programmer
****PRO MATE socket modules are ordered separately. See development systems
ordering guide for specific ordering part numbers
TABLE 9-1:
SW006005
SW006005
SW007002
PIC16C52, 54, 54A,
55, 56, 57, 58A
PIC16C554, 556, 558
SW006005
SW006005
MPLAB C
Compiler
SW007002
** MPLAB
Integrated
Development
Environment
SW007002
PIC14000
PIC12C508, 509
Product
PIC12C5XX
DEVELOPMENT TOOLS FROM MICROCHIP
DS40139A-page 52
PIC12C5XX
10.0
ELECTRICAL CHARACTERISTICS - PIC12C5XX
Absolute Maximum Ratings†
Ambient Temperature under bias ............................................................................................................. –40˚C to +85˚C
Storage Temperature.............................................................................................................................. –65˚C to +150˚C
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5 V
Voltage on MCLR with respect to VSS(2) .......................................................................................................... 0 to +14 V
Voltage on all other pins with respect to VSS ............................................................................... –0.6 V to (VDD + 0.6 V)
Total Power Dissipation(1) ................................................................................................................................... 700 mW
Max. Current out of VSS pin.................................................................................................................................. 200 mA
Max. Current into VDD pin .................................................................................................................................... 150 mA
Max. Current into VDD pin (Vclamp active)........................................................................................................... 100 mA
Input Clamp Current, IIK (VI < 0 or VI > VDD).....................................................................................................................±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD).............................................................................................................±20 mA
Max. Output Current sunk by any I/O pin ............................................................................................................... 25 mA
Max. Output Current sourced by any I/O pin.......................................................................................................... 25 mA
Max. Output Current sourced by I/O port (PORTA).............................................................................................. 100 mA
Max. Output Current sourced by I/O port with VDD clamp active(PORTA)............................................................. 50 mA
Max. Output Current sunk by I/O port (PORTA ) .................................................................................................. 100 mA
Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus,
a series resistor of 50 to 100W should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to Vss.
†NOTICE:
Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DS40139A-page 53
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
10.1
DC CHARACTERISTICS:
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
Power Supply Pins
Characteristic
PIC12508/509 (Commercial)
PIC12508/509 (Industrial)
Typ(1)
Sym
Min
Supply Voltage
VDD
2.5
RAM Data Retention
Voltage(2)
VDR
VDD Start Voltage to ensure
Power-on Reset
VPOR
VDD Rise Rate to ensure
Power-on Reset
SVDD
0.05*
IDD
—
1.8
—
Supply Current(3)
Power-Down Current (5)
WDT Enabled
WDT Disabled
Max
Units
Conditions
5.5
V
FOSC = DC to 4 MHz
1.5*
V
Device in SLEEP mode
VSS
V
See section on Power-on Reset for details
V/ms
See section on Power-on Reset for details
2.4
mA
1.8
2.4
mA
—
15
27
µA
—
19
35
µA
XT and EXTRC options (Note 4)
FOSC = 4 MHz, VDD = 5.5 V
INTRC Option
FOSC = 4 MHz, VDD = 5.5 V
LP OPTION, Commercial Temperature
FOSC = 32 kHz, VDD = 3.0 V, WDT disabled
LP OPTION, Industrial Temperature
FOSC = 32 kHz, VDD = 3.0 V, WDT disabled
—
—
—
—
4
5
0.25
0.3
12
14
4
5
µA
µA
µA
µA
IPD
VDD = 3.0 V, Commercial
VDD = 3.0 V, Industrial
VDD = 3.0 V, Commercial
VDD = 3.0 V, Industrial
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
DS40139A-page 54
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
10.2
DC CHARACTERISTICS:
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1.
DC Characteristics
All Pins Except
Power Supply Pins
Characteristic
PIC12508/509 (Commercial)
PIC12508/509 (Industrial)
Sym
Min
Typ(1)
Max
Units
VSS
VSS
VSS
VSS
0.2 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
2.0
0.2VDD+1V
0.85 VDD
0.85 VDD
0.7 VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
Conditions
VIL
Input Low Voltage
I/O ports
MCLR
OSC1
OSC1
Input High Voltage
I/O ports
VIH
MCLR (Schmitt Trigger)
OSC1 (Schmitt Trigger)
Input Leakage Current(2,3)
I/O ports
IIL
Pin at hi-impedance
EXTRC option only(4)
XT and LP options
4.0 V< VDD ≤ 5.5 V(5)
Full VDD range(5)
EXTRC option only(4)
XT and LP options
For VDD ≤ 5.5 V
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS + 0.25 V(2)
VPIN = VDD
VSS ≤ VPIN ≤ VDD,
XT and LP options
–1
0.5
+1
µA
MCLR
20
OSC1
–3
130
0.5
0.5
250
+5
+3
µA
µA
µA
0.6
V
IOL = 8.7 mA, VDD = 4.5 V
V
IOH = –5.4 mA, VDD = 4.5 V
Output Low Voltage
I/O ports
Vol
(3,4)
Output High Voltage
I/O ports
VOH
VDD –0.7
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For PIC12C5XX devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12C5XX be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 55
PIC12C5XX
10.3
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase subscripts (pp) and their meanings:
pp
2
to
mc
MCLR
ck
CLKOUT
osc
oscillator
cy
cycle time
os
OSC1
drt
device reset timer
t0
T0CKI
io
I/O port
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
Fall
P
Period
H
High
R
Rise
I
Invalid (Hi-impedance)
V
Valid
L
Low
Z
Hi-impedance
FIGURE 10-1: LOAD CONDITIONS - PIC12C5XX
Pin
CL = 50 pF for all pins except OSC2
CL
VSS
DS40139A-page 56
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
10.4
Timing Diagrams and Specifications
FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC12C5XX
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
TABLE 10-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C5XX
AC Characteristics
Parameter
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
Operating Voltage VDD range is described in Section 10.1
Sym
FOSC
Characteristic
External CLKIN Frequency(2)
(2)
Oscillator Frequency
1
TOSC
(2)
External CLKIN Period
Oscillator Period(2)
2
Tcy
Instruction Cycle Time(3)
Min
Typ(1)
Max
DC
—
4
MHz EXTRC osc mode
DC
—
4
MHz XT osc mode
DC
—
200
DC
—
4
MHz EXTRC osc mode
0.1
—
4
MHz XT osc mode
Units
kHz
Conditions
LP osc mode
DC
—
200
kHz
250
—
—
ns
LP osc mode
EXTRC osc mode
250
—
—
ns
XT osc mode
5
—
—
ms
LP osc mode
250
—
—
ns
EXTRC osc mode
250
—
10,000
ns
XT osc mode
5
—
—
ms
LP osc mode
—
4/FOSC
—
—
—
ns
XT oscillator
3
TosL, TosH Clock in (OSC1) Low or High Time
50*
—
2*
—
—
ms
LP oscillator
4
TosR, TosF Clock in (OSC1) Rise or Fall Time
—
—
25*
ns
XT oscillator
—
—
50*
ns
LP oscillator
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 57
PIC12C5XX
FIGURE 10-3:
I/O TIMING - PIC12C5XX
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-2:
TIMING REQUIREMENTS - PIC12C5XX
AC Characteristics
Parameter
No.
Sym
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Characteristic
Min
Typ(1)
Max
Units
17
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid(3)
—
—
100*
ns
18
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1↑
(I/O in setup time)
TBD
—
—
ns
20
TioR
Port output rise time(3)
—
10
25**
ns
21
TioF
Port output fall time(3)
—
10
25**
ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 10-1 for loading conditions.
DS40139A-page 58
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C5XX
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT and LP modes.
TABLE 10-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C5XX
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1
Parameter
No.
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
31
Twdt
32
34
Min
Typ(1)
Max
Units
2000*
—
—
ns
VDD = 5 V
Watchdog Timer Time-out Period
(No Prescaler)
9*
18*
30*
ms
VDD = 5 V (Commercial)
TDRT
Device Reset Timer Period(2)
9*
18*
30*
ms
VDD = 5 V (Commercial)
TioZ
I/O Hi-impedance from MCLR Low
—
—
100*
ns
Conditions
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested
2: DRT runs only on power-up and in normal execution in EXTRC and INTRC modes, and never runs in test
modes. (i.e. does not run on wake-up from sleep)
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 59
PIC12C5XX
FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC12C5XX
T0CKI
40
41
42
TABLE 10-4:
TIMER0 CLOCK REQUIREMENTS - PIC12C5XX
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 10.1.
Parameter
Sym Characteristic
No.
40
Min
Tt0H T0CKI High Pulse Width - No Prescaler
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
- With Prescaler
41
Tt0L
T0CKI Low Pulse Width - No Prescaler
42
Tt0P T0CKI Period
Typ(1) Max Units Conditions
- With Prescaler
10*
—
—
ns
20 or TCY + 40*
N
—
—
ns
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 10-5:
*
MCLR PULL-UP RESISTOR RANGES
VDD (Volts)
Temperature (°C)
Min
Typ
Max
Units
2.5
2.5
2.5
5.5
5.5
5.5
-40
25
85
-40
25
85
43*
47*
50*
25
30*
32
66
74
79
36
42
46
100*
111*
119*
48
56*
63
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
These parameters are characterized but not tested.
DS40139A-page 60
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
FIGURE 10-6: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.5V)
Frequency (MHz)
4.5
4.0
3.5
-40
Note:
25
Temperature (°C)
85
Altering calibration value by 1 is approximately a 4ns change.
FIGURE 10-7: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 2.5V)
Frequency (MHz)
4.5
4.0
TYPICAL
3.5
-40
Note:
25
Temperature (°C)
85
Altering calibration value by 1 is approximately a 4ns change.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 61
PIC12C5XX
FIGURE 10-8: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. VDD
AT TEMPERATURE = -40°C
Frequency (MHz)
4.5
4.0
3.5
2.5
3.5
4.5
5.5
VDD
Note:
Altering calibration value by 1 is approximately a 4ns change.
FIGURE 10-9: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. VDD
AT TEMPERATURE = 25°C
Frequency (MHz)
4.5
4.0
3.5
2.5
3.5
4.5
5.5
VDD
Note:
DS40139A-page 62
Altering calibration value by 1 is approximately a 4ns change.
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
FIGURE 10-10: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. VDD
AT TEMPERATURE = 85°C
Frequency (MHz)
4.5
4.0
3.5
2.5
3.5
4.5
5.5
VDD
Note:
Altering calibration value by 1 is approximately a 4ns change.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 63
PIC12C5XX
NOTES:
DS40139A-page 64
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
11.0
PACKAGING INFORMATION
11.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
TO BE DETERMINED
8-Lead SOIC (200 mil)
Example
TO BE DETERMINED
Legend: MM...M
XX...X
AA
BB
C
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in
QTP price.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 65
PIC12C5XX
11.2
8-Lead Plastic Dual In-line (300 mil)
N
α
C
E1 E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
e1
B
A1 A2 A
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.381
3.048
0.355
1.397
0.203
9.017
7.620
7.620
6.096
2.489
7.620
7.874
3.048
8
0.889
0.254
DS40139A-page 66
Inches
Notes
Min
Max
10°
0°
10°
4.064
–
3.810
0.559
1.651
0.381
10.922
7.620
8.255
7.112
2.591
7.620
9.906
3.556
8
–
–
–
0.015
0.120
0.014
0.055
0.008
0.355
0.300
0.300
0.240
0.098
0.300
0.310
0.120
8
0.035
0.010
0.160
–
0.150
0.022
0.065
0.015
0.430
0.300
0.325
0.280
0.102
0.300
0.390
0.140
8
–
–
Typical
Reference
Typical
Reference
Advance Information
Notes
Typical
Reference
Typical
Reference
1996 Microchip Technology Inc.
PIC12C5XX
11.3
8-Lead Plastic Surface Mount (SOIC - Medium, 200 mil Body)
e
h x 45°
B
N
Index
Area
E
H
α
C
L
Chamfer
h x 45°
1
2
3
D
Seating
Plane
Base
Plane
CP
A1
A
Package Group: Plastic SOIC (SM)
Millimeters
Symbol
Min
Max
α
0°
A
A1
B
C
D
E
e
H*
h
L
N
CP
1.778
0.101
0.355
0.190
5.080
5.156
1.270
7.670
0.381
0.508
14
–
1996 Microchip Technology Inc.
Inches
Notes
Min
Max
8°
0°
8°
2.00
0.249
0.483
0.249
5.334
5.411
1.270
8.103
0.762
1.016
14
0.102
0.070
0.004
0.014
0.007
0.200
0.203
0.050
0.302
0.015
0.020
14
–
0.079
0.010
0.019
0.010
0.210
0.213
0.050
0.319
0.030
0.040
14
0.004
Reference
Advance Information
Notes
Reference
DS40139A-page 67
PIC12C5XX
NOTES:
DS40139A-page 68
Advance Information
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
PIC14000
20
)
(
4
x1
rd
wo
Memory
)
s
M
o
s)
e(
l
du
T)
R
SA
Peripherals
Features
4K
192
TMR0
ADTMR
y
or
—
I2C/
SMD
—
14
11
22
2.7-6.0
Yes
—
Internal Oscillator,
Bandgap Reference,
Temperature Sensor,
Calibration Factors,
Low Voltage Detector,
SLEEP, HIBERNATE,
Comparators with
Programmable References
(2)
ge
s
28-pin DIP, SOIC, SSOP
(.300 mil)
Pa
a
ck
TABLE A-1:
g
in
m
U
m
,
M
)
a
O
2C
em
r
ts
W
gr
s)
of
M
ol
I/I
/P
rt
rte els
te
ro
y
ip
V
s
e
P
y
o
e
c
(
)
P
m
r
v nn
P
et
l
a
ch
ce
(b
(S
(s
e
en
n
ra
s
r
a
p
i
u
e
)
a
e
g
o
y
g
n
e
r
v
o
ou
ul
C Ch
eq
R
O
or
t(s
an
om
la
Se
Pr
Fr
R
od
or
tS s
al s
ut
/D s)
/C
it
em
lS
p
o
P
m
e
M
M
e
A
u
e
e
n
r
u
l
on ure
u
l
M
i
r
g
c
r
i
l
r
n
O
e
r
u
t
a
r
a
i
P
e
im
ri
R
ra
ta
lt
di at
pt
op gh Inte
ow
m
-C
ax
Se
Pa
EP
I/O
Da
Vo
Sl (hi
Ti
Ad Fe
M
In
Br
Ca
r
pe
n
io
at
Hz
(M
Clock
PIC12C5XX
APPENDIX A:PIC16/17 MICROCONTROLLERS
PIC14XXX DEVICES
Advance Information
DS40139A-page 69
ax
im
Advance Information
20
PIC16CR58A
—
—
2K
—
2K
1K
512
RO
en
2K
—
2K
—
—
—
512
—
—
—
R
73
73
72
72
25
24
25
25
25
25
te
M
M
s)
y
or
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
)
12
12
20
20
12
20
12
12
12
12
Vo
lta
ns
2.5-6.25
2.0-6.25
2.5-6.25
2.5-6.25
2.5-6.25
2.5-6.25
2.0-6.25
2.0-6.25
2.5-6.25
2.5-6.25
33
33
33
33
33
33
33
33
33
33
s
s
lts
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
28-pin DIP, SOIC, SSOP
28-pin DIP, SOIC, SSOP
18-pin DIP, SOIC; 20-pin SSOP
28-pin DIP, SOIC, SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC
Features
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
20
PIC16C57
20
20
PIC16C56
PIC16C58A
20
PIC16C55
PIC16CR57B
20
20
PIC16CR54A
512
20
512
20
PIC16C54
M
PIC16C54A
um
qu
M
RO
384
ta
Fr
e
EP
4
PIC16C52
Da
AM
M
cy
o
fO
p
e
ra
tio
n
P
(
r
M
og
Hz
(x ram
)
12 M
w em
o
rd or
s) y
em
Peripherals
e
ng
(b
y
Ti
m
er
)
r
(V
o
Nu
m
be
(s
le
od
u
tr
ns
of
I
Memory
Pi
I/O
Ra
ge
on
uc
ti
Pa
DS40139A-page 70
ge
TABLE A-2:
ck
a
Clock
PIC12C5XX
PIC16C5X FAMILY OF DEVICES
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
Advance Information
20
20
20
20
20
PIC16C556
PIC16C558
PIC16C620
PIC16C621
PIC16C622
2K
1K
512
2K
1K
512
128
80
80
128
80
80
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
2
2
2
—
—
—
Yes
Yes
Yes
—
—
—
4
4
4
3
3
3
13
13
13
13
13
13
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Yes
Yes
Yes
—
—
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
et
es
R
s
t
R
ou
ge
ge
nka
tl a
c
w
o
Pa
Vo
Br
2.5-6.0
— 18-pin DIP, SOIC; 20-pin SSOP
ge
an
)
lts
o
(V
Features
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
20
PIC16C554
(M
Peripherals
y
or
em s)
M rd
ge
ra
m o
ta
pe
ol
ra 4 w
O
)
g
V
f
s
o
o x1
e
te
y
Pr (
nc
es
nc
by
s)
(
e
)
rc
re
u
e(
y
s
u
l
e
q
r
(
f
r
u
e
o
So
to
Fr
Re
od
em
ra
pt
M
M
al
ns
a
u
um
M
r
n
r
O
p
r
r
Pi
e
a
im
e
e
t
R
m
x
t
t
m
a
a
In
In
I/O
D
Ti
EP
M
Co
n
tio
Memory
TABLE A-3:
)
Hz
Clock
PIC12C5XX
PIC16CXXX FAMILY OF DEVICES
DS40139A-page 71
DS40139A-page 72
Advance Information
20
20
20
20
20
PIC16CR63(1)
PIC16C64
PIC16C64A(1)
PIC16CR64(1)
PIC16C65
Features
—
4K
4K
—
2K
2K
—
4K
—
2K
2K
4K
—
—
2K
—
—
4K
—
2K
—
—
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
H
2 SPI/I2C, Yes
USART
11
11
11
2 SPI/I2C, Yes
USART
2 SPI/I2C, Yes
USART
8
8
8
10
10
7
7
7
Yes
1 SPI/I2C
Yes
Yes
1 SPI/I2C
1 SPI/I2C
—
—
2 SPI/I2C,
USART
2 SPI/I2C,
USART
—
—
—
1 SPI/I2C
1 SPI/I2C
1 SPI/I2C
33
33
33
33
33
33
22
22
22
22
22
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
28-pin SDIP, SOIC, SSOP
40-pin DIP;
44-pin PLCC, MQFP
40-pin DIP;
44-pin PLCC, MQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 28-pin SDIP, SOIC
Yes 28-pin SDIP, SOIC
Yes 28-pin SDIP, SOIC, SSOP
Yes 28-pin SDIP, SOIC, SSOP
—
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability.
All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
20
20
PIC16C63
PIC16CR65(1)
20
PIC16CR62(1)
20
20
PIC16C62A(1)
PIC16C65A(1)
20
s)
Peripherals
TABLE A-4:
PIC16C62
(M
Memory
y
(
or
le
T)
m )
g
du
e
s
o
in
i
AR
t
M
d
a
M
r
m
S
r
o
m
e
U
m
M
p
a w
,
)
a
O
)
2C
W
gr 4
ts
gr
of
ol
/I
/P
t
es
ro (x1
ro
I
t
r
y
e
V
P
y
s
P
r
o
P
)
(
et
e
l
nc
S
P
(b
(s
pa
rc
ge
e
ue
es
y
ria
)(
le
u
r
m
q
v
n
s
e
R
u
o
e
o
a
la
rt(
So
Fr
R
ut
tS
od
/C
es
em
lS
ui
pt ins
e
M
M
-o
Po
re
e
c
M
l
um
u
l
g
n
ag
r
u
l
r
O
r
i
t
a
a
k
e
r
P
m
a
a
w
i
M
t
i
R
p
t
l
c
r
r
C
o
m
te
ax
Se
Da
In
In
Br
Pa
Ca
EP
RO
Ti
Pa
Vo
I/O
M
on
z)
Clock
PIC12C5XX
PIC16C6X FAMILY OF DEVICES
1996 Microchip Technology Inc.
(M
14
rd
wo
Memory
M
e(
ul
od
R
SA
T)
Peripherals
s)
ls
ne
n
ha
Features
1996 Microchip Technology Inc.
1K
20
20
20
20
20
20
PIC16C72
PIC16C73
PIC16C73A(1)
PIC16C74
Advance Information
PIC16C74A(1)
—
—
—
8
8
192 TMR0,
2 SPI/I2C, Yes
TMR1, TMR2
USART
192 TMR0,
2 SPI/I2C, Yes
TMR1, TMR2
USART
5
5
5
4
4
4
—
192 TMR0,
2 SPI/I2C,
TMR1, TMR2
USART
—
—
—
—
192 TMR0,
2 SPI/I2C,
TMR1, TMR2
USART
—
—
—
—
TMR0
TMR0
TMR0
128 TMR0,
1 SPI/I2C
TMR1, TMR2
68
36
36
12
12
11
11
8
4
4
4
33
33
22
22
22
13
13
13
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
18-pin DIP, SOIC
28-pin SDIP, SOIC
40-pin DIP;
44-pin PLCC, MQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 28-pin SDIP, SOIC
—
Yes 28-pin SDIP, SOIC, SSOP
Yes 18-pin DIP, SOIC;
20-pin SSOP
—
Yes 18-pin DIP, SOIC;
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
4K
4K
4K
4K
2K
1K
20
PIC16C71
PIC16C711
512
20
PIC16C710
y
or
(x
g
in
m
U
m
,
M 2C
C
)
a
O
ts
W
it)
gr
s)
em
of
ol
/P PI/I
rt
te
-b
ro
y
M
V
s
e
y
o
c
8
(
)
P
r
(
S
P
et
l
ce
(b
(s
en
am
pa s) (
e
ge
er
y
es
ur
le
ria
t
gr
qu
r
v
n
r
m
o
u
(
e
o
e
R
o
t
a
o
la
ve
Pr
Fr
R
od
or
tS s
es
ut
tS
/C
em
lS
M
e
M
ui
on rup
-o
n
re al P
ag
um
le
M
i
g
c
r
O
l
n
C
r
u
k
r
a
i
i
m
P
e
R
i
c
r
ra
ta
lt
pt
D
te
ow
m
-C
ax
EP
Pa
Se
In
A/
Pa
I/O
Vo
Da
Ti
M
In
Br
Ca
p
a
er
n
tio
s)
TABLE A-5:
)
Hz
Clock
PIC12C5XX
PIC16C7X FAMILY OF DEVICES
DS40139A-page 73
Advance Information
10
10
10
10
PIC16F84(1)
PIC16CR84(1)
PIC16F83(1)
PIC16CR83(1)
F
—
512
—
1K
—
—
—
—
—
1K
512
—
1K
—
—
(M
36
36
68
68
Da
64
64
64
64
ta
Da
em
64
ta
y
or
Ti
TMR0
TMR0
TMR0
TMR0
TMR0
EE
er
o
M
4
4
4
4
4
Peripherals
)
lts
o
(V
Features
13
13
13
13
13
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
s
ce
ge
ur
o
an
S
R
es
pt ins
ge
ag
ru
a
k
r
P
t
l
c
te
In
Pa
Vo
I/O
s)
e(
l
du
s)
te
y
(b
Memory
m
M
O
PR
s)
e
yt
(b
y
or
em
M
M
am
r
og
Pr
36
M
RO
M
O
PR
EE
o
ra
pe
fO
n
tio
)
Hz
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and
high I/O current capability.
All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
10
PIC16C84
a
M
um
xim
cy
n
ue
q
re
h
DS40139A-page 74
as
TABLE A-6:
Fl
Clock
PIC12C5XX
PIC16C8X FAMILY OF DEVICES
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
Advance Information
p
O
og
r
)
M
PW
/
re
M
e
T)
R
SA
,U
ul
od
t)
bi
(8
Peripherals
)
(s
C
ls
ne
n
ha
es
)
lts
o
(V
m
Features
g
in
4K
8
PIC16C924
es
t
by
176 TMR0,
1 SPI/I2C
TMR1, TMR2
176 TMR0,
1 SPI/I2C
TMR1, TMR2
Pr
—
—
5
—
2
/I
I
SP
C
4 Com
32 Seg
4 Com
32 Seg
t
r
Po
9
8
25
25
27
27
3.0-6.0
3.0-6.0
Yes
Yes
—
—
64-pin SDIP(1), TQFP,
68-pin PLCC, DIE
64-pin SDIP(1), TQFP,
68-pin PLCC, DIE
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7.
1: Please contact your local Microchip representative for availability of this package.
4K
8
PIC16C923
Note
of
am
o
em
M
Memory
m
ra
og
r
t
s)
lP
(
e
r
se
rc
pa s) (
ia
ue
e(
ry
ve
ng
rte
m
le
ou
ul
(
er
eq
Re
o
a
t
a
r
e
o
l
u
d
r
S
s
t
S
s
v
F
R
S
o
o
u
t
n
/C
od
em
pt ins
ge
e
M
ui
on
M
-o
el
Pi
re al P
u
a
um
l
M
M
g
c
r
l
r
n
C
t
O
r
u
k
r
i
P
e
im
c
D
ri
ra
ta
R
lta
pt
D
te
pu
ow
m
-C
ax
Pa
Se
In
A/
LC
Pa
I/O
In
Da
Vo
Ti
EP
M
In
Br
Ca
y
nc
er
n
io
at
ry
TABLE A-7:
)
Hz
(M
Clock
PIC12C5XX
PIC16C9XX FAMILY OF DEVICES
DS40139A-page 75
Advance Information
25
25
25
25
25
PIC17C42A
PIC17CR42
PIC17C43
PIC17CR43
PIC17C44
im
8K
—
4K
—
2K
u
eq
4K
—
2K
—
—
RO
EP
O
RO
n
454
454
454
232
232
232
M
of
y
en
c
M
io
at
pe
r
Pr
R
y
or
em
(M
)
Hz
og
r
am
M
Da
AM
Fr
um
2K
m
em
M
)
)
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
ta
ds
(W
or
(
y
or
)
es
by
t
er
M
Ti
(s
le
od
u
er
ia
S
Yes
Yes
Yes
Yes
Yes
Yes
C
a
p
P tur
W
e
M s
s
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
ly
11
11
11
11
11
11
33
33
33
33
33
33
Vo
es
2.5-6.0
2.5-6.0
2.5-6.0
2.5-5.5
2.5-5.5
4.5-5.5
58
58
58
58
58
55
Features
ns
)
U
ax
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, MQFP
40-pin DIP;
44-pin PLCC, MQFP
40-pin DIP;
44-pin PLCC, MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
25
M
PIC17C42
o
rt(
s
lP
T)
M
re
s
pt
tip
In
al
In
)(
r
Ha
ru
te
r
ru
te
r
SA
R
dw
a
pt
So
u
Peripherals
lta
ge
Ra
N
ts
ol
r
ul
er
n
xt
E
ng
e
(V
um
tr
ns
of
I
be
rc
ns
Pi
I/O
io
uc
t
P
Memory
es
DS40139A-page 76
ag
TABLE A-8:
ac
k
Clock
PIC12C5XX
PIC17CXX FAMILY OF DEVICES
1996 Microchip Technology Inc.
PIC12C5XX
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE A-9:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509
8-pin
PIC16C54, PIC16C54A,
PIC16CR54A,
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622,
PIC16C710, PIC16C71, PIC16C711,
PIC16C83, PIC16CR83,
PIC16C84, PIC16C84A, PIC16CR84
18-pin
(20-pin)
PIC16C55,
PIC16C57, PIC16CR57B
28-pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
28-pin
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
40-pin
PIC17C42, PIC17C43, PIC17C44
40-pin
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 77
PIC12C5XX
NOTES:
DS40139A-page 78
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
INDEX
A
RC .............................................................................. 26
XT ............................................................................... 26
ALU ...................................................................................... 7
Applications.......................................................................... 3
Architectural Overview ......................................................... 7
Assembler .......................................................................... 50
P
C Compiler (MP-C) ............................................................ 51
Carry .................................................................................... 7
Clocking Scheme ............................................................... 10
Code Protection ........................................................... 25, 35
Configuration Bits............................................................... 25
Configuration Word
PIC16C54A/CR57A/C58A ......................................... 25
Package Marking Information............................................. 65
Packaging Information........................................................ 65
PC....................................................................................... 16
PICDEM-1 Low-Cost PIC16/17 Demo Board ............... 49, 50
PICDEM-2 Low-Cost PIC16CXX Demo Board............. 49, 50
PICDEM-3 Low-Cost PIC16C9XXX Demo Board .............. 50
PICMASTER RT In-Circuit Emulator ............................... 49
PICSTART Low-Cost Development System.................... 49
Pin Compatible Devices ..................................................... 77
POR
Device Reset Timer (DRT) ................................... 25, 32
PD............................................................................... 34
Power-On Reset (POR).............................................. 25
TO............................................................................... 34
PORTA ............................................................................... 19
Power-Down Mode ............................................................. 35
Prescaler ............................................................................ 24
PRO MATE Universal Programmer ................................. 49
Program Counter ................................................................ 16
D
Q
Development Support ........................................................ 49
Development Tools ............................................................ 49
Device Varieties ................................................................... 5
Digit Carry ............................................................................ 7
Q cycles.............................................................................. 10
B
Block Diagram
On-Chip Reset Circuit ................................................
Timer0........................................................................
TMR0/WDT Prescaler................................................
Watchdog Timer.........................................................
Brown-Out Protection Circuit .............................................
30
21
24
33
34
C
F
Family of Devices
PIC14XXX.................................................................. 69
PIC16C5X .................................................................. 70
PIC16C62X ................................................................ 71
PIC16C7X .................................................................. 73
PIC16C8X .................................................................. 74
Features............................................................................... 1
FSR.................................................................................... 17
Fuzzy Logic Dev. System (fuzzyTECH-MP) .............. 49, 51
I
I/O Interfacing .................................................................... 19
I/O Ports............................................................................. 19
I/O Programming Considerations....................................... 20
ID Locations ................................................................. 25, 35
INDF................................................................................... 17
Indirect Data Addressing.................................................... 17
Instruction Cycle ................................................................ 10
Instruction Flow/Pipelining ................................................. 10
Instruction Set Summary.................................................... 38
L
Loading of PC .................................................................... 16
M
Memory Organization......................................................... 11
Data Memory ............................................................. 12
Program Memory ....................................................... 11
MPASM Assembler...................................................... 49, 50
MP-C C Compiler ............................................................... 51
MPSIM Software Simulator.......................................... 49, 51
R
RC Oscillator ...................................................................... 27
Read Modify Write .............................................................. 20
Register File Map
PIC16C54A/CR54A/CR54B/CR56 ............................. 12
PIC16C58A/CR58A/CR58B ....................................... 12
Registers
Special Function ......................................................... 13
Reset .................................................................................. 25
Reset on Brown-Out ........................................................... 34
S
SLEEP .......................................................................... 25, 35
Software Simulator (MPSIM) .............................................. 51
Special Features of the CPU .............................................. 25
Special Function Registers................................................. 13
Stack................................................................................... 16
STATUS ............................................................................... 7
STATUS Register ............................................................... 14
T
Timer0
Switching Prescaler Assignment ................................ 24
Timer0 ........................................................................ 21
Timer0 (TMR0) Module .............................................. 21
TMR0 with External Clock .......................................... 23
Timing Diagrams and Specifications .................................. 57
Timing Parameter Symbology and Load Conditions .......... 56
TRIS Registers ................................................................... 19
W
Wake-up from SLEEP ........................................................ 35
Watchdog Timer (WDT)................................................ 25, 32
Period ......................................................................... 33
Programming Considerations ..................................... 33
O
Z
One-Time-Programmable (OTP) Devices............................ 5
OPTION Register............................................................... 15
OSC Selection ................................................................... 25
Oscillator Configurations.................................................... 26
Oscillator Types
HS .............................................................................. 26
LP............................................................................... 26
Zero bit ................................................................................. 7
1996 Microchip Technology Inc.
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DS40139A-page 79
PIC12C5XX
LIST OF EXAMPLES
Figure 10-7:
Example 3-1: Instruction Pipeline Flow ............................ 10
Example 4-1: Indirect Addressing .................................... 17
Example 4-2: How To Clear RAM Using Indirect
Addressing................................................. 17
Example 5-1: Read-Modify-Write Instructions on an
I/O Port ...................................................... 20
Example 6-1: Changing Prescaler (Timer0→WDT .........) 24
Example 6-2: Changing Prescaler (WDT→Timer0 .........) 24
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 5-1:
Figure 5-2:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 7-8:
Figure 7-9:
Figure 7-10:
Figure 7-11:
Figure 7-12:
Figure 7-13:
Figure 7-14:
Figure 7-15:
Figure 8-1:
Figure 10-1:
Figure 10-2:
Figure 10-3:
Figure 10-4:
Figure 10-5:
Figure 10-6:
PIC12C5XX Block Diagram ......................... 8
Clock/Instruction Cycle .............................. 10
Program Memory Map and Stack for the
PIC12C5XX ............................................... 11
PIC12C508 Register File Map ................... 12
PIC12C509 Register File Map ................... 12
STATUS Register (Address:03h)............... 14
OPTION Register....................................... 15
Loading of PC Branch Instructions PIC12C508/C509....................................... 16
Direct/Indirect Addressing.......................... 17
Equivalent Circuit for a Single I/O Pin........ 19
Successive I/O Operation .......................... 20
Timer0 Block Diagram ............................... 21
Timer0 Timing: Internal Clock/
No Prescale ............................................... 22
Timer0 Timing: Internal Clock/
Prescale 1:2............................................... 22
Timer0 Timing With External Clock ........... 23
Block Diagram of the Timer0/
WDT Prescaler .......................................... 24
Configuration Word for PIC12C508 or
PIC12C509 ................................................ 25
Crystal Operation (or Ceramic Resonator)
(XT or LP OSC Configuration) ................... 26
External Clock Input Operation
(XT or LP OSC Configuration) ................... 26
External Parallel Resonant Crystal
Oscillator Circuit......................................... 27
External Series Resonant Crystal
Oscillator Circuit ......................................... 27
RC Oscillator Mode.................................... 28
MCLR Select.............................................. 29
Simplified Block Diagram of
On-Chip Reset Circuit................................ 30
Time-Out Sequence on Power-Up
(MCLR Pulled Low).................................... 31
Time-Out Sequence on Power-Up
(MCLR Tied to Vdd): Fast Vdd Rise Time . 31
Time-Out Sequence on Power-Up
(MCLR Tied to VDD): Slow Vdd Rise Time 31
Watchdog Timer Block Diagram ................ 33
Brown-Out Protection Circuit 1 .................. 34
Brown-Out Protection Circuit 2 .................. 34
Typical In-Circuit Serial Programming
Connection................................................. 36
General Format for Instructions ................. 37
Load Conditions - PIC12C5XX .................. 56
External Clock Timing - PIC12C5XX ......... 57
I/O Timing - PIC12C5XX........................... 58
Reset, Watchdog Timer, and Device
Reset Timer Timing - PIC12C5XX ............. 59
Timer0 Clock Timings - PIC12C5XX ......... 60
Calibrated Internal RC Frequency
Range vs. Temperature (VDD = 5.5V)........ 61
DS40139A-page 80
Calibrated Internal RC Frequency Range
vs. Temperature (VDD = 2.5V)................... 61
Figure 10-8: Calibrated Internal RC Frequency Range
vs. VDD at Temperature = -40°C ............... 62
Figure 10-9: Calibrated Internal RC Frequency Range
vs. VDD at Temperature = 25°C................. 62
Figure 10-10: Calibrated Internal RC Frequency Range
vs. VDD at Temperature = 85°C................ 63
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 4-1:
Table 5-1:
Table 6-1:
Table 7-1:
Table 7-2:
Table 7-3:
Table 7-4:
Table 7-5:
Table 7-6:
Table 7-7:
Table 8-1:
Table 8-2:
Table 9-1:
Table 10-1:
Table 10-2:
Table 10-3:
Table 10-4:
Table 10-5:
Advanced Information
PIC12C5XX Family of Devices.................... 4
PIC12C5XX Pinout Description................... 9
Special Function Register Summary ......... 13
Summary of Port Registers ....................... 19
Registers Associated With Timer0 ............ 22
Capacitor Selection For Ceramic
Resonators - PIC12C5XX ......................... 26
Capacitor Selection For Crystal
Oscillator - PIC12C5XX............................. 26
Reset Conditions For Registers ................ 28
Reset Condition For Special Registers ..... 29
Summary of Registers Associated with
the Watchdog Timer .................................. 33
TO/PD/GPWUF Status After Reset........... 34
Events Affecting TO/PD Status Bits .......... 34
OPCODE Field Descriptions ..................... 37
Instruction Set Summary ........................... 38
Development Tools From Microchip.......... 52
External Clock Timing Requirements PIC12C5XX ............................................... 57
Timing Requirements - PIC12C5XX.......... 58
Reset, Watchdog Timer, and Device
Reset Timer - PIC12C5XX ........................ 59
Timer0 Clock Requirements PIC12C5XX ............................................... 60
MCLR Pull-up Resistor Ranges ................ 60
1996 Microchip Technology Inc.
PIC12C5XX
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel
for you to use in extending your technical staff with
microcontroller and memory experts.
To provide you with the most responsive service possible, the Microchip systems team monitors the BBS,
posts the latest component data and software tool
updates, provides technical help and embedded systems insights, and discusses how Microchip products
provide project solutions.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp.mchip.com/biz/mchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
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available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the
address:
mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense.
The Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
1996 Microchip Technology Inc.
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
The following connect procedure applies in most locations.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
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are accepted from the user community in general to
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Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER, and are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB, PRO MATE, and fuzzyLAB, are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of
their respective companies.
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DS40139A-page 81
PIC12C5XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Application (optional):
Would you like a reply?
Device: PIC12C5XX
Y
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Literature Number: DS40139A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40139A-page 82
Advance Information
1996 Microchip Technology Inc.
PIC12C5XX
PIC12C5XX PRODUCT IDENTIFICATION SYSTEM
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
Package:
SM
P
a)
PIC12C508-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
b)
PIC12C508-04I/SM
Industrial Temp., SOIC
package, 4 MHz, normal
VDD limits
c)
PIC12C509-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
= 200 mil SOIC
= 300 mil PDIP
Temperature
Range:
I
= 0°C to +70°C
= -40°C to +85°C
Frequency
Range:
04
= 4 MHz
Device
PIC12C508
PIC12C509
PIC12C508T (Tape & reel for SOIC only)
PIC12C509T (Tape & reel for SOIC only)
Please contact your local sales office for exact ordering procedures.
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 83
WORLDWIDE SALES & SERVICE
AMERICAS
AMERICAS (continued)
EUROPE
Corporate Office
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com/
New York
Microchip Technology Inc.
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Tel: 516 273-5305
Fax: 516 273-5335
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Italy
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ASIA/PACIFIC
Hong Kong
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Korea
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JAPAN
Microchip Technology Intl. Inc.
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3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166
Fax: 81 45 471 6122
5/10/96
All rights reserved. 1996, Microchip Technology Incorporated, USA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty
is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property
rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip.
No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40139A - page 84
1996 Microchip Technology Inc.