MICROCHIP MCP6V08T-E/SN

MCP6V06/7/8
300 µA, Auto-Zeroed Op Amps
Features
Description
• High DC Precision:
- VOS Drift: ±50 nV/°C (maximum)
- VOS: ±3 µV (maximum)
- AOL: 125 dB (minimum)
- PSRR: 125 dB (minimum)
- CMRR: 120 dB (minimum)
- Eni: 1.7 µVP-P (typical), f = 0.1 Hz to 10 Hz
- Eni: 0.54 µVp-p (typical), f = 0.01 Hz to 1 Hz
• Low Power and Supply Voltages:
- IQ: 300 µA/amplifier (typical)
- Wide Supply Voltage Range: 1.8V to 5.5V
• Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 1.3 MHz (typical)
- Unity Gain Stable
- Available in Single and Dual
- Single with Chip Select (CS): MCP6V08
• Extended Temperature Range: -40°C to +125°C
The Microchip Technology Inc. MCP6V06/7/8 family of
operational amplifiers has input offset voltage
correction for very low offset and offset drift. These
devices have a wide gain bandwidth product (1.3 MHz,
typical) and strongly reject switching noise. They are
unity gain stable, have no 1/f noise, and have good
PSRR and CMRR. These products operate with a
single supply voltage as low as 1.8V, while drawing
300 µA/amplifier (typical) of quiescent current.
Typical Applications
•
•
•
•
•
Portable Instrumentation
Sensor Conditioning
Temperature Measurement
DC Offset Correction
Medical Instrumentation
Design Aids
•
•
•
•
•
•
SPICE Macro Models
FilterLab® Software
Mindi™ Circuit Designer & Simulator
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Related Parts
The Microchip Technology Inc. MCP6V06/7/8 op amps
are offered in single (MCP6V06), single with Chip
Select (CS) (MCP6V08), and dual (MCP6V07). They
are designed in an advanced CMOS process.
Package Types (top view)
MCP6V06
2x3 TDFN *
MCP6V06
SOIC
NC 1
8 NC
NC 1
VIN– 2
7 VDD
VIN– 2
VIN+ 3
VSS 4
6 VOUT
5 NC
VIN+ 3
VINA– 2
VINA+ 3
VSS 4
8 VDD
7 VDD
6 VOUT
5 NC
MCP6V07
4x4 DFN *
VOUTA
7 VOUTB V –
INA
6 VINB– V +
INA
5 VINB+ V
SS
MCP6V08
SOIC
EP
9
VSS 4
MCP6V07
SOIC
VOUTA 1
8 NC
8 VDD
1
2
3
EP
9
7 VOUTB
6 VINB–
5 VINB+
4
MCP6V08
2x3 TDFN *
NC 1
NC 1
8 CS
VIN– 2
7 VDD
VIN– 2
VIN+ 3
VSS 4
6 VOUT
5 NC
VIN+ 3
VSS 4
8 CS
EP
9
7 VDD
6 VOUT
5 NC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
• MCP6V01/2/3: Spread clock, lower offset
© 2008 Microchip Technology Inc.
DS22093B-page 1
MCP6V06/7/8
Typical Application Circuit
VIN
R1
R2
R2
VDD/2
R3
VOUT
C2
3 kΩ
MCP6XXX
MCP6V06
Offset Voltage Correction for Power Driver
DS22093B-page 2
© 2008 Microchip Technology Inc.
MCP6V06/7/8
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings †
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† ... VSS – 1.0V to VDD+1.0V
All other Inputs and Outputs ............ VSS – 0.3V to VDD+0.3V
Difference Input voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, MM) ................≥ 4 kV, 300V
1.2
†† See Section 4.2.1 “Rail-to-Rail Inputs”.
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
VOS
-3
—
+3
µV
Input Offset Voltage Drift with Temperature
(linear Temp. Co.)
TC1
-50
—
+50
nV/°C
Input Offset Voltage Quadratic Temp. Co.
TC2
—
±0.15
—
PSRR
125
142
—
Input Bias Current
IB
—
+6
—
pA
Input Bias Current across Temperature
IB
—
+140
—
pA
TA = +85°C
IB
—
+1500
+5000
pA
TA = +125°C
IOS
—
-85
—
pA
Power Supply Rejection
TA = +25°C (Note 1)
TA = -40 to +125°C
(Note 1)
nV/°C2 TA = -40 to +125°C
dB
(Note 1)
Input Bias Current and Impedance
Input Offset Current
IOS
—
-85
—
pA
TA = +85°C
IOS
-1000
-190
1000
pA
TA = +125°C
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||6
—
Ω||pF
Common-Mode Input Voltage Range
VCMR
VSS − 0.20
—
VDD + 0.20
V
(Note 2)
Common-Mode Rejection
CMRR
120
136
—
dB
VDD = 1.8V,
VCM = -0.2V to 2.0V
(Note 1, Note 2)
CMRR
130
147
—
dB
VDD = 5.5V,
VCM = -0.2V to 5.7V
(Note 1, Note 2)
AOL
125
147
—
dB
VDD = 1.8V,
VOUT = 0.2V to 1.6V (Note 1)
AOL
135
158
—
dB
VDD = 5.5V,
VOUT = 0.2V to 5.3V (Note 1)
Input Offset Current across Temperature
Common Mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Note 1:
2:
Set by design and characterization. Due to thermal junction and other effects in the production environment, these
parts can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”).
Figure 2-18 shows how VCMR changed across temperature for the first three production lots.
© 2008 Microchip Technology Inc.
DS22093B-page 3
MCP6V06/7/8
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Sym
Min
Typ
Max
Units
Conditions
VOL, VOH
ISC
VSS + 15
—
VDD − 15
mV
G = +2, 0.5V input overdrive
—
±7
—
mA
VDD = 1.8V
ISC
—
±22
—
mA
VDD = 5.5V
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
VDD
1.8
—
5.5
V
IQ
200
300
400
µA
VPOR
1.15
—
1.65
V
Supply Voltage
Quiescent Current per amplifier
POR Trip Voltage
Note 1:
2:
IO = 0
Set by design and characterization. Due to thermal junction and other effects in the production environment, these
parts can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”).
Figure 2-18 shows how VCMR changed across temperature for the first three production lots.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Amplifier AC Response
Gain Bandwidth Product
GBWP
—
1.3
—
MHz
Slew Rate
SR
—
0.5
—
V/µs
Phase Margin
PM
—
65
—
°
Eni
—
0.54
—
µVP-P
f = 0.01 Hz to 1 Hz
Eni
—
1.7
—
µVP-P
f = 0.1 Hz to 10 Hz
eni
—
82
—
nV/√Hz f < 2.5 kHz
eni
—
52
—
nV/√Hz f = 100 kHz
ini
—
0.6
—
fA/√Hz
IMD
—
32
—
µVPK
VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 1.8V
IMD
—
25
—
µVPK
VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 5.5V
Start Up Time
tSTR
—
500
—
µs
VOS within 50 µV of its final value
Offset Correction Settling Time
tSTL
—
300
—
µs
G = +1, VIN step of 2V,
VOS within 50 µV of its final value
Output Overdrive Recovery Time
tODR
—
100
—
µs
G = -100, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 2)
G = +1
Amplifier Noise Response
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC)
Amplifier Step Response
Note 1:
2:
These parameters were characterized using the circuit in Figure 1-7. Figure 2-37 and Figure 2-38 show both an IMD
tone at DC and a residual tone at1 kHz; all other IMD and clock tones are spread by the randomization circuitry.
tODR includes some uncertainty due to clock edge timing.
DS22093B-page 4
© 2008 Microchip Technology Inc.
MCP6V06/7/8
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Sym
Min
Typ
Max
Units
Conditions
RPD
3
5
—
MΩ
CS Logic Threshold, Low
VIL
VSS
—
0.3VDD
V
CS Input Current, Low
ICSL
—
5
—
pA
CS Logic Threshold, High
VIH
0.7VDD
—
VDD
V
CS Input Current, High
ICSH
—
VDD/RPD
—
pA
CS = VDD
ISS
—
-0.7
—
µA
CS = VDD, VDD = 1.8V
ISS
—
-2.3
—
µA
CS = VDD, VDD = 5.5V
—
20
—
pA
CS = VDD
CS Pull-Down Resistor (MCP6V08)
CS Pull-Down Resistor
CS Low Specifications (MCP6V08)
CS = VSS
CS High Specifications (MCP6V08)
CS Input High, GND Current per
amplifier
Amplifier Output Leakage, CS High IO_LEAK
CS Dynamic Specifications (MCP6V08)
CS Low to Amplifier Output On
Turn-on Time
tON
—
11
100
µs
CS Low = VSS+0.3 V, G = +1 V/V,
VOUT = 0.9 VDD/2
CS High to Amplifier Output High-Z
tOFF
—
10
—
µs
CS High = VDD – 0.3 V, G = +1 V/V,
VOUT = 0.1 VDD/2
VHYST
—
0.25
—
V
Internal Hysteresis
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-2x3 TDFN
θJA
—
41
—
°C/W
Thermal Resistance, 8L-4x4 DFN
θJA
—
44
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
150
—
°C/W
Conditions
Temperature Ranges
(Note 1)
Thermal Package Resistances
Note 1:
2:
(Note 2)
Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).
Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
© 2008 Microchip Technology Inc.
DS22093B-page 5
MCP6V06/7/8
1.3
Timing Diagrams
1.4
1.8V to 5.5V
1.8V
VDD 0V
tSTR
VOS + 50 µV
VOS
Test Circuits
The circuits used for the DC and AC tests are shown in
Figure 1-5 and Figure 1-6. Lay the bypass capacitors
out as discussed in Section 4.3.8 “Supply Bypassing
and Filtering”. RN is equal to the parallel combination
of RF and RG to minimize bias current effects.
VDD
VOS – 50 µV
VIN
FIGURE 1-1:
Amplifier Start Up.
RISO
VIN
100 nF
RG
VOS + 50 µV
VOS
VOS + 50 µV
Offset Correction Settling
CL
RL
VL
RF
FIGURE 1-5:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
FIGURE 1-2:
Time.
VOUT
MCP6V0X
VDD/3
tSTL
1 µF
RN
1 µF
VDD/3 RN
RISO
VOUT
MCP6V0X
VIN
tODR
RG
VDD
VDD/2
VSS
FIGURE 1-3:
CS
Output Overdrive Recovery.
VIL
VIH
tON
IDD
tOFF
1 µA
(typical)
ISS -2 µA
(typical)
ICS V /5 MΩ
DD
(typical)
FIGURE 1-4:
DS22093B-page 6
VL
RF
20.0 kΩ 20.0 kΩ 50Ω
0.1%
0.1% 25 turn
VREF
High-Z
High-Z
300 µA
(typical)
300 µA
(typical)
5 pA
(typical)
RL
The circuit in Figure 1-7 tests the op amp input’s
dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s common
mode input voltage is VCM = VIN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
1 µA
(typical)
-2 µA
(typical)
VDD/5 MΩ
(typical)
Chip Select (MCP6V08).
VIN
2.49 kΩ 2.49 kΩ
VOUT
CL
FIGURE 1-6:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
tODR
VOUT
100 nF
VIN
VDD
1 µF
RISO
100 nF
MCP6V0X
VOUT
CL
RL
VL
20.0 kΩ 20.0 kΩ 24.9 Ω
0.1%
0.1%
FIGURE 1-7:
Input Behavior.
Test Circuit for Dynamic
© 2008 Microchip Technology Inc.
MCP6V06/7/8
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
DC Input Precision
4
80 Samples
TA = +25°C
VDD = 1.8V and 5.5V
Soldered on PCB
12%
10%
8%
6%
4%
2%
2
1
0
-1
-3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
4
Input Offset Voltage (µV)
20%
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCMR_L.
80 Samples
VDD = 1.8V and 5.5V
Soldered on PCB
15%
10%
5%
2
1
0
-1
-3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
20%
15%
10%
5%
Input Offset Voltage's Quadratic Temp Co;
2
TC2 (nV/°C )
FIGURE 2-3:
Input Offset Voltage
Quadratic Temp Co.
© 2008 Microchip Technology Inc.
0.4
0.2
0.0
-0.2
0%
Input Offset Voltage (µV)
25%
FIGURE 2-5:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCMR_H.
4
80 Samples
VDD = 1.8V and 5.5V
Soldered on PCB
-0.4
Percentage of Occurrences
30%
Input Offset Voltage Drift.
+125°C
+85°C
+25°C
-40°C
-2
Input Offset Voltage Drift; TC1 (nV/°C)
FIGURE 2-2:
VCM = VCMR_H
Representative Part
3
-4
50
40
30
20
10
0
-10
-20
-30
-40
0%
-50
Percentage of Occurrences
25%
Input Offset Voltage.
+125°C
+85°C
+25°C
-40°C
-2
Input Offset Voltage (µV)
FIGURE 2-1:
VCM = VCMR_L
Representative Part
3
-4
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
0%
-2.0
Percentage of Occurrences
14%
Input Offset Voltage (µV)
2.1
Representative Part
3
2
VDD = 5.5V
1
0
-1
VDD = 1.8V
-2
-3
-4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-6:
Output Voltage.
Input Offset Voltage vs.
DS22093B-page 7
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
6%
4%
2%
-3
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-4
FIGURE 2-11:
CMRR, PSRR (dB)
155
25%
VDD = 5.5V
20%
15%
10%
DC Open-Loop Gain.
160
39 Samples
TA = +25°C
Soldered on PCB
VDD = 1.8V
5%
VDD = 5.5V
VDD = 1.8V
150
145
140
135
CMRR
130
PSRR
125
1/CMRR (µV/V)
FIGURE 2-9:
DS22093B-page 8
CMRR.
0.4
0.3
0.2
0.2
0.1
0.0
-0.1
-0.2
-0.2
-0.3
0%
-0.4
Percentage of Occurrences
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 5.5V.
30%
0.4
1/AOL (µV/V)
Input Common Mode Voltage (V)
35%
0.3
VDD = 1.8V
0.3
-2
0.2
0
-1
VDD = 5.5V
0.1
1
40 Samples
TA = +25°C
Soldered on PCB
-0.1
2
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
PSRR.
-0.2
+125°C
+85°C
+25°C
-40°C
-0.3
Percentage of Occurrences
Input Offset Voltage (µV)
VDD = 5.5V
Representative Part
FIGURE 2-10:
0.0
FIGURE 2-7:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 1.8V.
3
0.2
1/PSRR (µV/V)
Input Common Mode Voltage (V)
4
0.1
0%
2.4
2.2
2.0
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-4
1.8
-3
1.6
-2
1.4
-40°C
+25°C
+85°C
+125°C
8%
0.0
-1
10%
-0.1
0
40 Samples
TA = +25°C
Soldered on PCB
-0.2
1
12%
-0.3
2
14%
-0.4
Percentage of Occurrences
VDD = 1.8V
Representative Part
3
1.2
Input Offset Voltage (µV)
4
120
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-12:
CMRR and PSRR vs.
Ambient Temperature.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
10,000
155
Input Bias, Offset Currents
(pA)
DC Open-Loop Gain (dB)
160
VDD = 5.5V
VDD = 1.8V
150
145
140
135
130
125
120
-25
0
25
50
75
Ambient Temperature (°C)
100
-IOS
100
10
125
IB
200
100
IB
50
0
-50
IOS
-100
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-150
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
1600
1400
1200
1000
800
600
400
200
0
-200
-400
1.E-02
10m
1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
Input Current Magnitude (A)
TA = +85°C
VDD = 5.5V
150
25
35
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-16:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = +5.5V.
FIGURE 2-13:
DC Open-Loop Gain vs.
Ambient Temperature.
Input Bias, Offset Currents
(pA)
1,000
1
-50
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-17:
Input Bias Current vs. Input
Voltage (below VSS).
TA = +125°C
VDD = 5.5V
IB
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
IOS
-0.5
Input Bias, Offset Currents
(pA)
VDD = 5.5V
Common Mode Input Voltage (V)
FIGURE 2-15:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
© 2008 Microchip Technology Inc.
DS22093B-page 9
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
Other DC Voltages and Currents
450
400
VDD = 5.5V
Supply Current (µA)
VDD = 1.8V
VDD – VOH
300
250
200
100
50
VOL – VSS
125
FIGURE 2-20:
Output Voltage Headroom
vs. Ambient Temperature.
DS22093B-page 10
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
15%
10%
5%
0%
1.7
100
20%
1.6
0
25
50
75
Ambient Temperature (°C)
93 Samples
3 Lots
TA = +25°C
1.5
VDD = 1.8V
25%
1.4
VDD – VOH
30%
Supply Current vs. Power
1.3
VDD = 5.5V
-25
FIGURE 2-22:
Supply Voltage.
1.2
RL = 20 kΩ
-50
Power Supply Voltage (V)
Percentage of Occurrences
FIGURE 2-19:
Output Voltage Headroom
vs. Output Current.
VOL – VSS
0.0
10
1.1
1
Output Current Magnitude (mA)
1.5
0
10
0.1
+125°C
+85°C
+25°C
-40°C
150
1.0
100
350
0.5
Output Voltage Headroom
(mV)
6.5
FIGURE 2-21:
Output Short Circuit Current
vs. Power Supply Voltage.
1000
Output Headroom (mV)
6.0
Power Supply Voltage (V)
FIGURE 2-18:
Input Common Mode
Voltage Headroom (Range) vs. Ambient
Temperature.
12
11
10
9
8
7
6
5
4
3
2
1
0
-40
125
5.5
0
25
50
75
100
Ambient Temperature (°C)
5.0
-25
4.5
-50
-30
4.0
Upper ( VDD – VCMR)
-0.35
3.5
-0.30
+125°C
+85°C
+25°C
-40°C
-20
3.0
-0.25
0
-10
2.5
Lower (VCMR – VSS)
-0.20
10
2.0
-0.15
20
1.5
-0.10
-40°C
+25°C
+85°C
+125°C
30
1.0
-0.05
40
0.5
3 Lots
0.00
0.0
0.05
Output Short Circuit Current
(mA)
Input Common Mode Voltage
Headroom (V)
2.2
POR Trip Voltage (V)
FIGURE 2-23:
Voltage.
Power On Reset Trip
© 2008 Microchip Technology Inc.
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
POR Trip Voltage (V)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-24:
Power On Reset Voltage vs.
Ambient Temperature.
© 2008 Microchip Technology Inc.
DS22093B-page 11
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
Frequency Response
PSRR+
PSRR-
100
1.0
90
0.8
80
0.6
70
0.4
PM
0.2
CMRR and PSRR vs.
-90
10
-150
| AOL |
0
-120
-180
-10
-210
-20
-240
10k
100k
1M
1.E+04
1.E+05
1.E+06
Frequency (Hz)
VDD = 5.5V
CL = 60 pF
50
0
-120
-150
-180
-210
-20
-240
-270
10M
1.E+07
FIGURE 2-27:
Open-Loop Gain vs.
Frequency with VDD = 5.5V.
DS22093B-page 12
80
70
0.4
60
0.2
1.6
-10
10k
100k
1M
1.E+04
1.E+05
1.E+06
Frequency (Hz)
90
0.6
1.8
-90
| AOL |
VDD = 1.8V
100
0.8
-30
30
10
1.0
0
-60
∠AOL
VDD = 5.5V
50
PM
40
FIGURE 2-29:
Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
40
20
110
1.2
Common Mode Input Voltage (V)
Open-Loop Phase (°)
60
120
1.4
0.0
-270
10M
1.E+07
130
GBWP
-0.5
0.0
20
1.6
Phase Margin (°)
30
∠AOL
1.8
-30
-60
40
125
FIGURE 2-28:
Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
0
40
-25
0
25
50
75 100
Ambient Temperature (°C)
50
130
GBWP
120
1.4
110
1.2
100
1.0
VDD = 1.8V
0.8
VDD = 5.5V
90
80
0.6
70
0.4
60
0.2
0.0
Phase Margin (°)
VDD = 1.8V
CL = 60 pF
-50
1M
1.E+06
60
VDD = 1.8V
3.0
3.5
4.0
4.5
5.0
5.5
6.0
100k
1.E+05
FIGURE 2-26:
Open-Loop Gain vs.
Frequency with VDD = 1.8V.
Open-Loop Gain (dB)
110
1.2
0.5
1.0
1.5
2.0
2.5
1k
10k
1.E+03
1.E+04
Frequency (Hz)
Gain Bandwidth Product
(MHz)
100
1.E+02
50
-30
1k
1.E+03
GBWP
1.4
120
VDD = 5.5V
0.0
60
-30
1k
1.E+03
130
1.6
Phase Margin (°)
CMRR
FIGURE 2-25:
Frequency.
Open-Loop Gain (dB)
Gain Bandwidth Product
(MHz)
1.8
Gain Bandwidth Product
(MHz)
110
100
90
80
70
60
50
40
30
20
10
0
10
1.E+01
Open-Loop Phase (°)
CMRR, PSRR (dB)
2.3
50
PM
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-30:
Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
10k
1.E+04
100
VDD = 1.8V
1k
1.E+03
100
1.E+02
G = 1 V/V
G = 10 V/V
G = 100 V/V
10
1.E+01
1
1.E+00
100k
1.0E+05
1M
10M
1.0E+06
1.0E+07
Frequency (Hz)
50
40
VDD = 1.8V
30
20
1M
1.E+06
Frequency (Hz)
10M
1.E+07
FIGURE 2-33:
Channel-to-Channel
Separation vs. Frequency.
Maximum Output Voltage
Swing (V P-P )
Open-Loop Output Impedance ( Ω)
VDD = 5.5V
60
10
1k
1.E+03
100
1.E+02
1.E+001
100k
1.0E+05
70
0
100k
1.E+05
100M
1.0E+08
VDD = 5.5V
10
1.E+01
80
10
FIGURE 2-31:
Closed-Loop Output
Impedance vs. Frequency with VDD = 1.8V.
1.E+04
10k
RTI
90
Channel-to-Channel
Separation (dB)
Open-Loop Output Impedance ( Ω)
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
G = 1 V/V
G = 10 V/V
G = 100 V/V
1M
10M
1.0E+06
1.0E+07
Frequency (Hz)
100M
1.0E+08
FIGURE 2-32:
Closed-Loop Output
Impedance vs. Frequency with VDD = 5.5V.
© 2008 Microchip Technology Inc.
VDD = 5.5V
1
0.1
1k
1.E+03
VDD = 1.8V
10k
100k
1.E+04
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-34:
Maximum Output Voltage
Swing vs. Frequency.
DS22093B-page 13
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
Input Noise and Distortion
100
eni
100
100
Eni(0 Hz to f)
IMD Spectrum, RTI (µV PK)
1,000
Input Noise Voltage Density
1 kHz
tone
VDD = 5.5V
100
80
VDD = 1.8V
60
40
20
1k
10k
1.E+03
1.E+04
Frequency (Hz)
VDD = 1.8V
NPBW = 10 Hz
NPBW = 1 Hz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.0
0.5
0.0
-0.5
0
0
10
20
30
40
Common Mode Input Voltage (V)
IMD Spectrum, RTI (µV PK)
100
IMD tone at DC
10
residual
1 kHz
tone
1
100
1.E+02
GDM = 1 V/V
VCM tone = 50 mVPK, f = 1 kHz
VDD = 5.5V
VDD = 1.8V
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
FIGURE 2-37:
Inter-Modulation Distortion
vs. Frequency with VCM Disturbance (see
Figure 1-7).
DS22093B-page 14
50 60
t (s)
70
80
90 100
FIGURE 2-39:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD =1.8V.
VDD = 5.5V
Input Noise Voltage; e ni(t)
(0.5 µV/div)
FIGURE 2-36:
Input Noise Voltage Density
vs. Input Common Mode Voltage.
100k
1.E+05
FIGURE 2-38:
Inter-Modulation Distortion
vs. Frequency with VDD Disturbance (see
Figure 1-7).
Input Noise Voltage; e ni(t)
(0.5 µV/div)
120
VDD = 5.5V
VDD = 1.8V
10
160
140
GDM = 1 V/V
VDD tone = 50 mVPK, f = 1 kHz
IMD tone at DC
1
100
1.E+02
10
10
10
100
1k
10k
100k
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
FIGURE 2-35:
vs. Frequency.
Input Noise Voltage Density;
eni (nV/√ Hz)
1000
VDD = 5.5V
VDD = 1.8V
1.5
Input Noise Voltage Density;
eni (nV/√Hz)
10,000
Input Noise Voltage;
Eni (µV P-P )
2.4
NPBW = 10 Hz
NPBW = 1 Hz
0
10
20
30
40
50 60
t (s)
70
80
90 100
FIGURE 2-40:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD =5.5V.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
Time Response
0
0
15
4.5
4.0
VDD
10
3.5
5
3.0
0
2.5
-5
2.0
VOS
-10
1.5
-15
1.0
-20
0.5
-25
Power Supply Voltage
(V)
Input Offset Voltage
(mV)
5.0
POR Trip
Point
20
0.0
VOUT
4
5
10
3
2
1
0
10 12
Time (µs)
14
16
18
20
15
20 25 30
Time (µs)
35
40
45
50
Non-inverting Large Signal
VDD = 5.5V
G = -1
Output Voltage (10 mV/div)
Input, Output Voltages (V)
5
8
Non-inverting Small Signal
FIGURE 2-45:
Step Response.
VDD = 5.5V
G=1
VIN
6
VDD = 5.5V
G=1
0
FIGURE 2-42:
Input Offset Voltage vs.
Time at Power Up.
6
4
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.2 0.4 0.6
Time
0.8(200
1.0 µs/div)
1.2 1.4 1.6 1.8 2.0
7
2
FIGURE 2-44:
Step Response.
FIGURE 2-41:
Input Offset Voltage vs.
Time with Temperature Change.
25
VDD = 5.5V
G=1
Output Voltage (10 mV/div)
50
45
40
35
TPCB
30
25
20
15
VOS
10
5
0
-5
-10
-15
20 40 60 80 100 120 140 160 180 200
Time (s)
Temperature increased by
using heat gun for 4 seconds.
Output Voltage (V)
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
PCB Temperature (°C)
Input Offset Voltage (µV)
2.5
-1
0
1
2
3
4
5
6
Time (ms)
7
8
9
10
FIGURE 2-43:
The MCP6V06/7/8 family
shows no input phase reversal with overdrive.
© 2008 Microchip Technology Inc.
0
1
2
FIGURE 2-46:
Response.
3
4
5
6
Time (µs)
7
8
9
10
Inverting Small Signal Step
DS22093B-page 15
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VDD = 5.5V
G = -1
Output Voltage (V)
5.0
5
10
FIGURE 2-47:
Response.
15
20 25 30
Time (µs)
35
40
45
VOUT
Inverting Large Signal Step
VDD = 5.5V
0.8
Rising Edge
0.7
0.6
0.5
VDD = 1.8V
0.4
Falling Edge
0.2
0.1
0.0
-50
-25
FIGURE 2-48:
Temperature.
DS22093B-page 16
0
25
50
75
Ambient Temperature (°C)
100
Slew Rate vs. Ambient
125
5
4.0
4
3.0
3
2.0
2
1.0
VOUT
G VIN
VDD = 5.5V
G = -100 V/V
0.5V Overdrive
-1.0
50
0.9
Slew Rate (V/µs)
G VIN
0.0
0
0.3
6
1
0
Input Voltage × G (V/V)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-1
Time (50 µs/div)
FIGURE 2-49:
Output Overdrive Recovery
vs. Time with G = -100 V/V.
Overdrive Recovery Time (µs)
Output Voltage (V)
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
1000
0.5V Output Overdrive
VDD = 5.5V
100
tODR, high
10
tODR, low
VDD = 1.8V
1
1
10
100
Inverting Gain Magnitude (V/V)
1000
FIGURE 2-50:
Output Overdrive Recovery
Time vs. Inverting Gain.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
Chip Select Response (MCP6V08 only)
2.0
2.5
3.0
3.5
4.0
4.5
Power Supply Voltage (V)
5.0
5.5
Power Supply Current (µA)
350
300
Op Amp
turns on
here
250
Op Amp
turns off
here
VDD = 1.8V
G=1
VIN = 0.9V
VL = 0V
200
150
Hysteresis
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
50
0
0.2
0.4
0.6 0.8 1.0 1.2 1.4
Chip Select Voltage (V)
1.6
1.8
FIGURE 2-52:
Power Supply Current vs.
Chip Select Voltage with VDD = 1.8V.
Power Supply Current (µA)
600
500
400
300
Op Amp
turns on
here
200
Op Amp
turns off
here
VDD = 5.5V
G=1
VIN = 2.75V
VL = 0V
Hysteresis
100
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-53:
Power Supply Current vs.
Chip Select Voltage with VDD = 5.5V.
© 2008 Microchip Technology Inc.
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
Chip Select Current vs. Chip
VOUT On
VOUT Off
VOUT Off
VDD = 1.8V
G = +1 V/V
VIN= VDD
RL = 10 kΩ tied to VDD/2
CS
Time (5 µs/div)
12
11
10
9
8
7
6
5
4
3
2
1
0
FIGURE 2-55:
Chip Select Voltage, Output
Voltage vs. Time with VDD = 1.8V.
Output Voltage (V)
0.0
VDD = 5.5V
FIGURE 2-54:
Select Voltage.
FIGURE 2-51:
Chip Select Current vs.
Power Supply Voltage.
400
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Chip Select Voltage (V)
1.5
Chip Select Current (µA)
CS = VDD
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
VOUT On
VOUT Off
VOUT Off
VDD = 5.5V
G = +1 V/V
VIN= VDD
RL = 10 kΩ tied to VDD/2
CS
0
5
39
36
33
30
27
24
21
18
15
12
9
6
3
0
Chip Select Voltage (V)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Output Voltage (V)
Chip Select Current (µA)
2.6
10 15 20 25 30 35 40 45 50
Time (5 µs/div)
FIGURE 2-56:
Chip Select Voltage, Output
Voltage vs. Time with VDD = 5.5V.
DS22093B-page 17
MCP6V06/7/8
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.
7
65%
VIH/VDD
Pull-down Resistor (MΩ)
VDD = 5.5V
60%
55%
50%
45%
40%
35%
VIL/VDD
VDD = 1.8V
4
3
2
1
FIGURE 2-58:
100
125
6.5
0
25
50
75
Ambient Temperature (°C)
6.0
-25
5.5
0.00
5.0
0.05
4.5
0.10
4.0
VDD = 1.8V
0.15
125
+125°C
+85°C
+25°C
-40°C
3.5
0.20
100
CS = VDD
Representative Part
3.0
VDD = 5.5V
0.25
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.5
0.35
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-60:
Chip Select’s Pull-down
Resistor (RPD) vs. Ambient Temperature.
Power Supply Current (µA)
0.40
-25
2.0
FIGURE 2-57:
Chip Select Relative Logic
Thresholds vs. Ambient Temperature.
0.30
-50
125
1.5
0
25
50
75
100
Ambient Temperature (°C)
1.0
-25
0.0
-50
Chip Select Hysteresis (V)
5
0
30%
-50
6
0.5
Relative Chip Select Logic
Levels; Low and High ( )
70%
Power Supply Voltage (V)
Chip Select Hysteresis.
FIGURE 2-61:
Quiescent Current in
Shutdown vs. Power Supply Voltage.
Chip Select Turn On Time
(µs)
16
14
12
VDD = 5.5V
10
8
6
VDD = 1.8V
4
2
0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-59:
Chip Select Turn On Time
vs. Ambient Temperature.
DS22093B-page 18
© 2008 Microchip Technology Inc.
MCP6V06/7/8
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6V06
MCP6V07
MCP6V08
Symbol
Description
TDFN
SOIC
DFN
SOIC
TDFN
SOIC
6
6
1
1
6
6
VOUT, VOUTA
Output (op amp A)
2
2
2
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
3
3
VIN+, VINA+
Non-inverting Input
(op amp A)
4
4
4
4
4
4
VSS
—
—
5
5
—
—
VINB+
Non-inverting Input
(op amp B)
Negative Power Supply
—
—
6
6
—
—
VINB–
Inverting Input (op amp B)
—
—
7
7
—
—
VOUTB
Output (op amp B)
7
7
8
8
7
7
VDD
Positive Power Supply
—
—
—
—
—
8
CS
Chip Select (op amp A)
1, 5, 8
1, 5, 8
—
—
1, 5, 8
1, 5
NC
No Internal Connection
9
—
9
—
9
—
EP
Exposed Thermal Pad (EP);
must be connected to VSS
3.1
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
3.4
Chip Select (CS) Digital Input
This pin (CS) is a CMOS, Schmitt-triggered input that
places the MCP6V08 op amps into a low power mode
of operation.
3.5
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
© 2008 Microchip Technology Inc.
DS22093B-page 19
MCP6V06/7/8
NOTES:
DS22093B-page 20
© 2008 Microchip Technology Inc.
MCP6V06/7/8
4.0
APPLICATIONS
4.1
The MCP6V06/7/8 family of auto-zeroed op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for low cost, low power and high
precision applications. Its low supply voltage, low
quiescent current and wide bandwidth makes the
MCP6V06/7/8 ideal for battery-powered applications.
Overview of Auto-zeroing
Operation
Figure 4-1 shows a simplified diagram of the
MCP6V06/7/8 auto-zeroed op amps. This will be used
to explain how the DC voltage errors are reduced in this
architecture.
VIN+
VIN–
Main
Amp.
CFW
NC
Output
Buffer
VOUT
VREF
Null
Input
Switches
φ1
Null
Output
Switches
Null
Amp.
CH
Null
Correct
Switches
φ2
φ1
φ2
POR
Oscillator
Digital
Control
Clock
Randomization
CS
FIGURE 4-1:
4.1.1
Simplified Auto-zeroed Op Amp Functional Diagram.
BUILDING BLOCKS
The Null Amp. and Main Amp. are designed for high
gain and accuracy using a differential topology. They
have an auxiliary input (bottom left) used for correcting
the offset voltages. Both inputs are added together
internally. The capacitors at the auxiliary inputs (CFW
and CH) hold the corrected values during normal
operation.
The Output Buffer is designed to drive external loads at
the VOUT pin. It also produces a single ended output
voltage (VREF is an internal reference voltage).
The internal POR ensures the part starts up in a known
good state. It also provides protection against power
supply brown out events.
The Chip Select input places the op amp in a low power
state when it is high. When it goes low, it powers the op
amp at its normal level and starts operation properly.
The Digital Control circuitry takes care of all of the
housekeeping details of the switching operation. It also
takes care of Chip Select and POR events.
All of these switches are make-before-break in order to
minimize glitch-induced errors. They are driven by two
clock phases (φ1 and φ2) that select between normal
mode and auto-zeroing mode.
The clock is derived from an internal R-C oscillator
running at a rate of fOSC1 = 650 kHz. The oscillator’s
output is divided down to the desired rate. It is also
randomized to minimize (spread) undesired clock
tones in the output.
© 2008 Microchip Technology Inc.
DS22093B-page 21
MCP6V06/7/8
4.1.2
AUTO-ZEROING ACTION
Figure 4-2 shows the connections between amplifiers
during the Normal Mode of operation (φ1). The hold
capacitor (CH) corrects the Null Amplifier’s input offset.
Since the Null Amplifier has very high gain, it
dominates the signal seen by the Main Amplifier. This
greatly reduces the impact of the Main Amplifier’s input
offset voltage on overall performance. Essentially, the
Null Amplifier and Main Amplifier behave as a regular
op amp with very high gain (AOL) and very low offset
voltage (VOS).
VIN+
VIN–
CFW
CH
Main
Amp.
NC
Output
Buffer
VOUT
VREF
Null
Amp.
Normal Mode of Operation (φ1); Equivalent Amplifier Diagram.
FIGURE 4-2:
Figure 4-3 shows the connections between amplifiers
during the Auto-zeroing Mode of operation (φ2). The
signal goes directly through the Main Amplifier, and the
flywheel capacitor (CFW) maintains a constant correction on the Main Amplifier’s offset.
Since these corrections happen every 50 µs, or so, we
also minimize slow errors, including offset drift with
temperature (ΔVOS/ΔTA), 1/f noise, and input offset
aging.
The Null Amplifier uses its own high open loop gain to
drive the voltage across CH to the point where its input
offset voltage is almost zero. Because the principal
input is connected to VIN+, the auto-zeroing action
corrects the offset at the current common mode input
voltage (VCM) and supply voltage (VDD). This makes
the DC CMRR and PSRR very high also.
VIN+
VIN–
CFW
CH
FIGURE 4-3:
4.1.3
Null
Amp.
Main
Amp.
NC
Output
Buffer
VOUT
VREF
Auto-zeroing Mode of Operation (φ2); Equivalent Diagram.
INTERMODULATION DISTORTION
(IMD)
The MCP6V06/7/8 op amps will show intermodulation
distortion (IMD), products when an AC signal is
present.
frequencies. IMD distortion tones are generated about
all of the square wave clock’s harmonics. See
Figure 2-37 and Figure 2-38.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the auto-zeroing circuitry’s non-linear
response to produce IMD tones at sum and difference
DS22093B-page 22
© 2008 Microchip Technology Inc.
MCP6V06/7/8
4.2
Other Functional Blocks
4.2.1
RAIL-TO-RAIL INPUTS
The input stage of the MCP6V06/7/8 op amps uses two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM,
which is approximately equal to VIN+ and VIN– in normal operation) and the other at high VCM. With this
topology, the input operates with VCM up to 0.2V past
either supply rail at +25°C (see Figure 2-18). The input
offset voltage (VOS) is measured at VCM = VSS – 0.2V
and VDD + 0.2V to ensure proper operation.
The transition between the input stages occurs when
VCM ≈ VDD – 0.9V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.
4.2.1.1
VDD
D1
V1
R1
Input Voltage and Current Limits
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VIN+ Bond
Pad
Input
Stage
Bond V –
IN
Pad
FIGURE 4-4:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-5 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
© 2008 Microchip Technology Inc.
VOUT
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-5:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-17. Applications that are high impedance may
need to limit the usable voltage range.
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V06/7/8
auto-zeroed op amps is VDD – 15 mV (minimum) and
VSS + 15 mV (maximum) when RL = 20 kΩ is
connected to VDD/2 and VDD = 5.5V. Refer to
Figure 2-19 and Figure 2-20 for more information.
These op amps are designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.2.3
VSS Bond
Pad
MCP6V0X
R2
4.2.2
VDD Bond
Pad
D2
V2
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-43 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
CHIP SELECT (CS)
The single MCP6V08 has a Chip Select (CS) pin.
When CS is pulled high, the supply current for the
corresponding op amp drops to about 1 µA (typical),
and is pulled through the CS pin to VSS. When this
happens, the amplifier is put into a high impedance
state. By pulling CS low, the amplifier is enabled. If the
CS pin is left floating, the internal pull-down resistor
(about 5 MΩ) will keep the part on. Figure 1-4 shows
the output voltage and supply current response to a CS
pulse.
DS22093B-page 23
MCP6V06/7/8
4.3
Application Tips
4.3.1
4.3.4
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic temperature coefficients (TC1 and TC2) of input offset voltage.
The input offset voltage, at any temperature in the
specified range, can be calculated as follows:
EQUATION 4-1:
V OS ( T A ) = V OS + TC 1 ΔT + TC 2 ΔT
2
Where:
ΔT
=
TA – 25°C
VOS(TA)
=
input offset voltage at TA
VOS
=
input offset voltage at +25°C
TC1
=
linear temperature coefficient
TC2
=
quadratic temperature
coefficient
4.3.2
DC GAIN PLOTS
SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match.
4.3.5
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These auto-zeroed op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-6)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the
bandwidth with no capacitive load.
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms
of the reciprocals (in units of µV/V) of CMRR, PSRR
and AOL, respectively. They represent the change in
input offset voltage (VOS) with a change in common
mode input voltage (VCM), power supply voltage (VDD)
and output voltage (VOUT).
4.3.3
SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
DS22093B-page 24
VOUT
CL
MCP6V0X
FIGURE 4-6:
Output Resistor, RISO,
Stabilizes Capacitive Loads.
Figure 4-7 gives recommended RISO values for
different capacitive loads and is independent of the
gain.
10000
10k
Recommended R ISO (Ω)
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise, not unstable behavior. We validate the op amps’
stability by making multiple measurements of VOS;
instability would manifest itself as a greater unexplained variability in VOS or as the railing of the output.
RISO
GN < 2
1k
1000
100
100
10
10
1p
1.E-12
GN = 5
GN = 10
10p
1.E-11
100p
1n
1.E-10
1.E-09
CL (F)
10n
1.E-08
100n
1.E-07
FIGURE 4-7:
Recommended RISO values
for Capacitive Loads.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6V06 SPICE macro model
(good for all of the MCP6V06/7/8 op amps) are helpful.
4.3.6
STABILIZING OUTPUT LOADS
This family of auto-zeroed op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
resistance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-8 shows one circuit example that has low
resistance near the part’s bandwidth. RF and CF set a
pole at 0.16 kHz, so the noise gain (GN) is 1 V/V at the
circuit’s bandwidth (roughly 1.3 MHz). The load seen
by the op amp’s output at 1.3 MHz is RG||RL (99Ω).
This is low enough to be a real concern.
VIN
RN
100Ω
MCP6V0X
RG
100Ω
RF
10.0 kΩ
VOUT
RL
10.0 kΩ
CF
0.1 µF
FIGURE 4-8:
Output Load Issue.
To solve this problem, increase the resistive load to at
least 3 kΩ. Methods to accomplish this task include:
• Increase RG
• Remove CF (relocate the filter)
• Add a 3 kΩ resistor at the op amp’s output that is
not in the signal path; see Figure 4-9
VIN
RN
100 Ω
MCP6V0X
RG
100 Ω
RF
10.0 kΩ
RX
3.01 kΩ
VOUT
RL
10.0 kΩ
CF
0.1 µF
FIGURE 4-9:
Load Issue.
4.3.7
REDUCING UNDESIRED NOISE
AND SIGNALS
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimizes random analog noise
- Reduces interfering signals
• Good PCB layout techniques:
- Minimizes crosstalk
- Minimizes parasitic capacitances and inductances that interact with fast switching edges
• Good power supply design:
- Isolation from other parts
- Filtering of interference on supply line(s)
4.3.8
SUPPLY BYPASSING AND
FILTERING
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.
Additional filtering of high frequency power supply
noise (e.g., switched mode power supplies) can be
achieved using resistors. The resistors need to be
small enough to prevent a large drop in VDD for the op
amp, which would cause a reduced output range and
possible load-induced power supply noise. The resistors also need to be large enough to dissipate little
power when VDD is turned on and off quickly. The circuit in Figure 4-10 gives good rejection out to 1 MHz for
switched mode power supplies. Smaller resistors and
capacitors are a better choice for designs where the
power supply is reasonably quiet.
VS_ANA
143Ω
1/4W
143Ω
1/10W
100 µF
100 µF
to other analog parts
FIGURE 4-10:
0.1 µF
MCP6V0X
Additional Supply Filtering.
One Solution To Output
© 2008 Microchip Technology Inc.
DS22093B-page 25
MCP6V06/7/8
4.3.9
PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring, and the
thermal environment has a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V06/7/8 op
amps minimum and maximum specifications.
4.3.9.1
Thermo-junctions
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermo-junction effect). This
effect is used in thermocouples to measure temperature. The following are examples of thermo-junctions
on a PCB:
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
4.3.9.2
Non-inverting and Inverting Amplifier
Layout for Thermo-junctions
Figure 4-11 shows the recommended non-inverting
and inverting gain amplifier circuits on one schematic.
Usually, to minimize the input bias current related offset, R1 is chosen to be R2||R3.
The guard traces (with ground vias at the ends) help
minimize the thermal gradients. The resistor layout
cancels the resistor thermal voltages, assuming the
temperature gradient is constant near the resistors:
EQUATION 4-2:
VOUT ≈ VPGP,
≈ -VMGM,
• Minimize thermal gradients
• Cancel thermo-junction voltages
• Minimize difference in thermal potential between
metals
VP = GND
Where:
GM
=
R3/R2, inverting gain magnitude
GP
=
1 + GM, non-inverting gain
magnitude
VOS is neglected
Typical thermo-junctions have temperature to voltage
conversion coefficients of 10 to 100 µV/°C (sometimes
higher).
There are three basic approaches to minimizing
thermo-junction effects:
VM = GND
R3
R2
VM
VP
U1
VOUT
R1
R2
R3
VM
U1
MCP6V06
VP
VOUT
R1
FIGURE 4-11:
PCB Layout and Schematic
for Single Non-inverting and Inverting Amplifiers.
Note:
DS22093B-page 26
Changing the orientation of the resistors
will usually cause a significant decrease in
the cancellation of the thermal voltages.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
4.3.9.3
Difference Amplifier Layout for
Thermo-junctions
Figure 4-12 shows the recommended difference amplifier circuit. Usually, we choose R1 = R2 and R3 = R4.
The guard traces (with ground vias at the ends) help
minimize the thermal gradients. The resistor layout
cancels the resistor thermal voltages, assuming the
temperature gradient is constant near the resistors:
VOUT ≈ VREF + (VP – VM)GDM
Where:
The dual op amp amplifiers shown in Figure 4-16 and
Figure 4-17 produce a non-inverting difference gain
greater than 1, and a common mode gain of 1 .They
can use the layout shown in Figure 4-13. The gain setting resistors (R2) between the two sides are not combined so that the thermal voltages can be canceled.
EQUATION 4-4:
Thermal voltages are approximately equal
=
Dual Non-inverting Amplifier Layout
for Thermo-junctions
The guard traces (with ground vias at the ends) help
minimize the thermal gradients. The resistor layout
cancels the resistor thermal voltages, assuming the
temperature gradient is constant near the resistors:
EQUATION 4-3:
GDM
4.3.9.4
R3/R1 = R4/R2, difference gain
VOS is neglected
Where:
(VOA – VOB) ≈ (VIA – VIB)GDM
(VOA + VOB)/2 ≈ (VIA + VIB)/2
Thermal voltages are approximately equal
R4
R2
VM
VP
VOUT
U1
=
1 + R3/R2, differential mode gain
1,
common mode gain
VOB
VOA
R3
R4
U1
MCP6V06
U1
R3
R2
VOUT
R2
R1
R1
VREF
R1
R3
FIGURE 4-12:
PCB Layout and Schematic
for Single Difference Amplifier.
Note:
GCM
VREF
VM
VP
=
VOS is neglected
R1
R3
R2
GDM
VIA
VIA
VIB
R1
VOA
½ MCP6V07
U1
Changing the orientation of the resistors
will usually cause a significant decrease in
the cancellation of the thermal voltages.
R2
R3
R2
R3
U1
½ MCP6V07
VIB
VOB
R1
FIGURE 4-13:
PCB Layout and Schematic
for Dual Non-inverting Amplifier.
Note:
© 2008 Microchip Technology Inc.
Changing the orientation of the resistors
will usually cause a significant decrease in
the cancellation of the thermal voltages.
DS22093B-page 27
MCP6V06/7/8
4.3.9.5
Other PCB Thermal Design Tips
In cases where an individual resistor needs to have its
thermo-junction voltage cancelled, it can be split into
two equal resistors as shown in Figure 4-14. To keep
the thermal gradients near the resistors as small as
possible, the layouts are symmetrical with a ring of
metal around the outside. Make R1A = R1B = R1/2 and
R2A = R2B = 2R2.
R1A R1B
R2A
R2B
R1A
R1B
R2A
R2B
FIGURE 4-14:
Resistors.
Note:
PCB Layout for Individual
Changing the orientation of the resistors
will usually cause a significant decrease in
the cancellation of the thermal voltages.
Minimize temperature gradients at critical components
(resistors, op amps, heat sources, etc.):
• Minimize exposure to gradients
- Small components
- Tight spacing
- Shield from air currents
• Align with constant temperature (contour) lines
- Place on PCB center line
• Minimize magnitude of gradients
- Select parts with lower power dissipation
- Use same metal junctions on thermo-junctions that need to match
- Use metal junctions with low temperature to
voltage coefficients
- Large distance from heat sources
- Ground plane underneath (large area)
- FR4 gaps (no copper for thermal insulation)
- Series resistors inserted into traces (adds
thermal and electrical resistance)
- Use heat sinks
4.3.9.6
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC performance. Non-linear distortion can convert these signals
to multiple tones, included a DC shift in voltage. When
the signal is sampled by an ADC, these AC signals can
also be aliased to DC, causing an apparent shift in
offset.
To reduce interference:
-
Keep traces and wires as short as possible
Use shielding (e.g., encapsulant)
Use ground plane (at least a star ground)
Place the input signal source near to the DUT
Use good PCB layout techniques
Use a separate power supply filter (bypass
capacitors) for these auto-zeroed op amps
4.3.9.7
Miscellaneous Effects
Keep the resistances seen by the input pins as small
and as near to equal as possible to minimize bias current related offsets.
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center or
(the tribo-electric effect). Make sure the bending radius
is large enough to keep the conductors and insulation
in full contact.
Mechanical stresses can make some capacitor types
(such as ceramic) to output small voltages. Use more
appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
Humidity can cause electro-chemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
Make the temperature gradient point in one direction:
• Add guard traces
- Constant temperature curves follow the
traces
- Connect to ground plane
• Shape any FR4 gaps
- Constant temperature curves follow the
edges
DS22093B-page 28
© 2008 Microchip Technology Inc.
MCP6V06/7/8
4.4
Typical Applications
4.4.1
4.4.2
WHEATSTONE BRIDGE
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
common mode noise large. Amplifier designs with high
differential gain are desirable.
RTD SENSOR
The ratiometric circuit in Figure 4-17 conditions a three
wire RTD. It corrects for the sensor’s wiring resistance
by subtracting the voltage across the middle RW. The
top R1 does not change the output voltage; it balances
the op amp inputs. Failure (open) of the RTD is
detected by an out-of-range voltage.
Figure 4-15 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single ended,
and there is a minimum of filtering, the CMRR is good
enough for moderate common mode noise.
0.01C
VDD
R
R
R
0.2R
R
3 kΩ
100R
VDD
½ MCP6V07
2.49 kΩ
VDD
RW
ADC
10 nF
RRTD
100Ω
0.2R
MCP6V06
FIGURE 4-15:
Simple Design.
R1
2.49 kΩ
1 µF
10 nF
RW
Figure 4-16 shows a higher performance circuit for
Wheatstone bridges. This circuit is symmetric and has
high CMRR. Using a differential input to the ADC helps
with the CMRR.
100 nF
RT
20 kΩ
R1
2.49 kΩ
RB
20 kΩ
R3
100 kΩ
R2
2.55 kΩ
VDD
R R
R3
100 kΩ
2.49 kΩ
½ MCP6V07
R R
3 kΩ
1 µF
200Ω
10 nF
VDD
ADC
3 kΩ
20 kΩ
1 µF
200 Ω
½ MCP6V07
FIGURE 4-16:
RTD Sensor.
The voltages at the input of the ADC can be calculated
with the following:
20 kΩ
200Ω
3 kΩ
100 nF
RW
FIGURE 4-17:
1 µF
10 nF
ADC
R2
2.55 kΩ
½ MCP6V07
200 Ω
3 kΩ
VDD
G RTD = 1 + 2 ⋅ R 3 ⁄ R 2
G W = G RTD – R 3 ⁄ R 1
V DM = G RTD ( V T – V B ) + G W V W
V T + V B + ( G RTD + 1 – G W )V W
V CM = -----------------------------------------------------------------------------2
Where:
VT
=
Voltage at the top of RRTD
VB
=
Voltage at the bottom of RRTD
VW
=
Voltage across top and middle
RW’s
VCM
=
ADC’s common mode input
VDM
=
ADC’s differential mode input
High Performance Design.
© 2008 Microchip Technology Inc.
DS22093B-page 29
MCP6V06/7/8
4.4.3
THERMOCOUPLE SENSOR
Figure 4-18 shows a simplified diagram of an amplifier
and temperature sensor used in a thermocouple
application. The type K thermocouple senses the
temperature at the hot junction (THJ), and produces a
voltage at V1 proportional to THJ (in °C). The amplifier’s
gain is is set so that V4/THJ is 10 mV/°C. V3 represents
the output of a temperature sensor, which produces a
voltage proportional to the temperature (in °C) at the
cold junction (TCJ), and with a 0.50V offset. V2 is set so
that V4 is 0.50V when THJ – TCJ is 0°C.
EQUATION 4-5:
V1 ≈ THJ(40 µV/°C)
V2 = (1.00V)
The MCP9700A senses the temperature at its physical
location. It needs to be at the same temperature as the
cold junction (TCJ), and produces V3 (Figure 4-16).
The MCP1541 produces a 4.10V output, assuming
VDD is at 5.0V. This voltage, tied to a resistor ladder of
4.100(RTH) and 1.3224(RTH), would produce a Thevenin equivalent of 1.00V and 250(RTH). The
1.3224(RTH) resistor is combined in parallel with the
top right RTH resistor (in Figure 4-18), producing the
0.5696(RTH) resistor.
V4 should be converted to digital, then corrected for the
thermocouple’s non-linearity. The ADC can use the
MCP1541 as its voltage reference. Alternately, an
absolute reference inside a PICmicro® can be used
instead of the MCP1541.
V3 = TCJ(10 mV/°C) + (0.50V)
4.4.4
V4 = 250V1 + (V2 – V3)
Figure 4-20 shows a MCP6V06 correcting the input
offset voltage of another op amp. R2 and C2 integrate
the offset error seen at the other op amp’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3).
≈ (10 mV/°C) (THJ – TCJ) + (0.50V)
(hot junction RTH = Thevenin Equivalent Resistance
at THJ)
(RTH)
(RTH)
V2
40 µV/°C
C
Type K
Thermocouple (RTH)/250
MCP6V06
V1
V4
(RTH)/250
(cold junction
C
at TCJ)
V3
(RTH)
(RTH)
FIGURE 4-18:
Simplified Circuit.
Thermocouple Sensor;
VIN
R1
R3
R2
VOUT
C2
3 kΩ
R2
VDD/2
MCP6XXX
MCP6V06
FIGURE 4-20:
4.4.5
Figure 4-19 shows a more complete implementation of
this circuit. The dashed red arrow indicates a thermally
conductive connection between the thermocouple and
the MCP9700A; it needs to be very short and have low
thermal resistance.
OFFSET VOLTAGE CORRECTION
Offset Correction.
PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V06/7/8 as a
comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
MCP6V06
RTH = Thevenin Equivalent Resistance (e.g., 10 kΩ)
VDD
4.100(RTH) 0.5696(RTH)
MCP1541
C
(R
)/250
TH
Type K
MCP6V06
V1
VDD
VIN
R1
R2
FIGURE 4-19:
DS22093B-page 30
R5
1 kΩ
VOUT
MCP6541
C
(RTH)
R4
VDD/2
(RTH)/250
MCP9700A
R3
(RTH)
3 kΩ
V4
FIGURE 4-21:
Precision Comparator.
Thermocouple Sensor.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6V06/7/8 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6V06/7/8
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the Filter-Lab design tool provides full schematic diagrams of
the filter circuit with component values. It also outputs
the filter circuit in SPICE format, which can be used
with the macro model to simulate actual filter performance.
5.3
Mindi™ Circuit Designer &
Simulator
5.5
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their corresponding user’s guides and technical information, visit the
Microchip web site at www.microchip.com/analog
tools.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP
Evaluation Board
5.6
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams, and
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
5.4
“Signal Chain Design Guide”, DS21825
Microchip Advanced Part Selector
(MAPS)
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data sheets, Purchase and Sampling of
Microchip parts.
© 2008 Microchip Technology Inc.
DS22093B-page 31
MCP6V06/7/8
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example
8-Lead DFN (4x4) (MCP6V07)
XXXXXX
XXXXXX
YYWW
NNN
6V07
e3
E/MD^^
0823
256
Example:
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
MCP6VO6E
SN e3 0823
256
NNN
Example:
8-Lead TDFN (2x3) (MCP6V06, MCP6V08)
XXX
YWW
NN
Device
Code
MCP6V06
AAC
MCP6V08
AAD
AAC
838
25
Note: Applies to 8-Lead
2x3 TDFN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS22093B-page 32
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
MCP6V06/7/8
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© 2008 Microchip Technology Inc.
DS22093B-page 33
MCP6V06/7/8
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DS22093B-page 34
© 2008 Microchip Technology Inc.
MCP6V06/7/8
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@
1RWH
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© 2008 Microchip Technology Inc.
DS22093B-page 35
MCP6V06/7/8
/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH01±[[PP%RG\>7')[email protected]
1RWH
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DS22093B-page 36
© 2008 Microchip Technology Inc.
MCP6V06/7/8
/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH01±[[PP%RG\>7')[email protected]
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
© 2008 Microchip Technology Inc.
DS22093B-page 37
MCP6V06/7/8
NOTES:
DS22093B-page 38
© 2008 Microchip Technology Inc.
MCP6V06/7/8
APPENDIX A:
REVISION HISTORY
Revision B (December 2008)
The following is the list of modifications:
1.
2.
3.
4.
5.
Added the 8-lead, 2x3 TDFN package for the
MCP6V01 and MCP6V03 devices.
Added 8-lead, 2x3 TDFN package information to
Thermal Characteristic table.
Added information on the Exposed Thermal Pad
(EP) for the 8-lead, 2x3 TDFN and 8-lead, 4x4
DFN packages.
Added Section 4.3.6 “Stabilizing Output
Loads”.
Other minor typographical corrections.
Revision A (June 2008)
• Original Release of this Document.
© 2008 Microchip Technology Inc.
DS22093B-page 39
MCP6V06/7/8
APPENDIX B:
OFFSET RELATED
TEST SCREENS
We use production screens to ensure the quality of our
outgoing products. These screens are set at wider limits to eliminate any fliers; see Table B-1.
Input offset voltage related specifications in the DC
spec table (Table 1-1) are based on bench measurements (see Section 2.1 “DC Input Precision”). These
measurements are much more accurate because:
•
•
•
•
More compact circuit
Soldered parts on the PCB
More time spent averaging (reduces noise)
Better temperature control
- Reduced temperature gradients
- Greater accuracy
TABLE B-1:
OFFSET RELATED TEST SCREENS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters
Sym
Min
Max
Units
Conditions
Input Offset Voltage
VOS
-10
+10
Input Offset Voltage Drift with Temperature
(linear Temp. Co.)
TC1
—
—
PSRR
115
—
dB
(Note 1)
CMRR
106
—
dB
VDD = 1.8V, VCM = -0.2V to 2.0V (Note 1)
CMRR
116
—
dB
VDD = 5.5V, VCM = -0.2V to 5.7V (Note 1)
AOL
114
—
dB
VDD = 1.8V, VOUT = 0.2V to 1.6V (Note 1)
AOL
122
—
dB
VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1)
Input Offset
Power Supply Rejection
µV
TA = +25°C (Note 1, Note 2)
nV/°C TA = -40 to +125°C (Note 3)
Common Mode
Common Mode Rejection
Open-Loop Gain
DC Open-Loop Gain (large signal)
Note 1:
2:
3:
Due to thermal junctions and other errors in the production environment, these specifications are only screened in
production.
VOS is also sample screened at +125°C.
TC1 is not measured in production.
DS22093B-page 40
© 2008 Microchip Technology Inc.
MCP6V06/7/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XXX
Device
Temperature
Range
Package
Device:
MCP6V06
Single Op Amp
MCP6V06T Single Op Amp
(Tape and Reel for 2x3 TDFN and SOIC)
MCP6V07
Dual Op Amp
MCP6V07T Dual Op Amp
(Tape and Reel for 4×4 DFN and SOIC)
MCP6V08
Single Op Amp with Chip Select
MCP6V08T Single Op Amp with Chip Select
(Tape and Reel for SOIC)
Temperature Range:
E
Package:
MD
Examples:
a)
b)
a)
MCP6V06T-E/SN: Extended temperature,
8LD SOIC package.
MCP6V06-E/MNY: Extended temperature,
8LD 2x3 TDFN package.
b)
Extended temperature,
8LD 4x4 DFN package..
MCP6V07T-E/SN: Tape and Reel,
Extended temperature,
8LD SOIC package.
a)
MCP6V08-E/SN:
b)
MCP6V07-E/MD:
Extended temperature,
8LD SOIC package.
MCP6V08-E/MNY:Extended temperature,
8LD 2x3 TDFN package.
= -40°C to +125°C
= Plastic Dual Flat, No-Lead (4×4x0.9 mm), 8-lead
(MCP6V07 only)
MNY * = Plastic Dual Flat, No-Lead (2×3x0.75 mm), 8-lead
(MCP6V06, MCP6V08)
SN
= Plastic SOIC (150mil Body), 8-lead
* Y = nickel palladium gold manufacturing designator. Only
available on the TDFN package.
© 2008 Microchip Technology Inc.
DS22093B-page 41
MCP6V06/7/8
NOTES:
DS22093B-page 42
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS22093B-page 43
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01/02/08
DS22093B-page 44
© 2008 Microchip Technology Inc.