W78E54B/W78E054B Data Sheet 8-BIT MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. BLOCK DIAGRAM ...................................................................................................................... 6 6. FUNCTIONAL DESCRIPTION ................................................................................................... 7 7. 8. 9. 6.1 Timers 0, 1, and 2........................................................................................................... 7 6.2 New Defined Peripheral.................................................................................................. 7 6.2.1 INT2 / INT3 ...................................................................................................................7 6.2.2 PORT4 .............................................................................................................................8 6.2.3 Reduce EMI Emission ......................................................................................................8 6.3 Power-off Flag ................................................................................................................ 9 6.4 Watchdog Timer ............................................................................................................. 9 6.5 Clock ............................................................................................................................. 11 6.6 Power Management...................................................................................................... 11 6.7 Reset............................................................................................................................. 11 ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 11 7.1 Read Operation ............................................................................................................ 11 7.2 Output Disable Condition.............................................................................................. 11 7.3 Program Operation ....................................................................................................... 11 7.4 Program Verify Operation ............................................................................................. 12 7.5 Erase Operation............................................................................................................ 12 7.6 Erase Verify Operation ................................................................................................. 12 7.7 Program/Erase Inhibit Operation .................................................................................. 12 SECURITY BITS ....................................................................................................................... 13 8.1 Lock Bit ......................................................................................................................... 13 8.2 MOVC Inhibit................................................................................................................. 13 8.3 Encryption ..................................................................................................................... 13 ELECTRICAL CHARACTERISTICS......................................................................................... 14 9.1 Absolute Maximum Ratings .......................................................................................... 14 9.2 D.C. Characteristics...................................................................................................... 14 9.3 A.C. Characteristics ...................................................................................................... 16 -1- Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B 10. 11. 12. 13. 9.3.1 Clock Input Waveform ....................................................................................................16 9.3.2 Program Fetch Cycle......................................................................................................16 9.3.3 Data Read Cycle ............................................................................................................17 9.3.4 Data Write Cycle.............................................................................................................17 9.3.5 Port Access Cycle ..........................................................................................................17 9.3.6 Program Operation .........................................................................................................17 TIMING WAVEFORMS ............................................................................................................. 18 10.1 Program Fetch Cycle .................................................................................................... 18 10.2 Data Read Cycle........................................................................................................... 19 10.3 Data Write Cycle........................................................................................................... 19 10.4 Port Access Cycle......................................................................................................... 20 10.5 Program Operation ....................................................................................................... 20 TYPICAL APPLICATION CIRCUITS ........................................................................................ 21 11.1 Expanded External Program Memory and Crystal ....................................................... 21 11.2 Expanded External Data Memory and Oscillator ......................................................... 22 PACKAGE DIMENSIONS ......................................................................................................... 23 12.1 40-pin DIP ..................................................................................................................... 23 12.2 44-pin PLCC ................................................................................................................. 23 12.3 44-pin PQFP ................................................................................................................. 24 REVISION HISTORY ................................................................................................................ 25 -2- W78E54B/W78E054B 1. GENERAL DESCRIPTION The W78E54B is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78E54B is fully compatible with the standard 8051. The W78E54B contains an 16K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78E54B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E54B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. FEATURES • Fully static design 8-bit CMOS microcontroller • Wide supply voltage of 4.5V to 5.5V • 256 bytes of on-chip scratchpad RAM • 16 KB electrically erasable/programmable Flash EPROM • 64 KB program memory address space • 64 KB data memory address space • Four 8-bit bi-directional ports • One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC/QFP package) • Three 16-bit timer/counters • One full duplex serial port(UART) • Watchdog Timer • Eight sources, two-level interrupt capability • EMI reduction mode • Built-in power management • Code protection mechanism • Packages: − − − − − − DIP 40: W78E54B-40 PLCC 44: W78E54BP-40 PQFP 44: W78E54BF-40 Lead Free (RoHS) DIP 40: W78E054B40DL Lead Free (RoHS) PLCC 44: W78E054B40PL Lead Free (RoHS) PQFP 44: W78E054B40FL -3- Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B 3. PIN CONFIGURATIONS 40-Pin DIP (W78E54B) T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 44-Pin PLCC (W78E54BP) T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 / I A N T T D 2 3 0 , , , P P P 1 4 V 0 . . D . 0 2 D 0 P 3 . 7 , / R D X T A L 2 X V P P T S 4 2 A S . . L 0 0 1 , A 8 P 2 . 1 , A 9 P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin QFP (W78E54BF) A D 1 , P 0 . 1 A D 2 , P 0 . 2 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 A D 3 , P 0 . 3 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R VDD P1.5 P1.6 P1.7 RST RXD, P3.0 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE INT2, P4.3 TXD, P3.1 INT0, P3.2 PSEN P2.7, A15 P2.6, A14 P2.5, A13 INT1, P3.3 T0, P3.4 T1, P3.5 P 2 . 4 , A 1 2 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 1 2 P 3 . 6 , / W R -4- T 2 , P 1 . 0 / I A N D T 0 3 , , P P 4 V 0 . D . 2 D 0 P 3 . 7 , / R D X T A L 2 X V P P T S 4 2 A S . . L 0 0 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 W78E54B/W78E054B 4. PIN DESCRIPTION SYMBOL DESCRIPTIONS EA EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be presented on the bus if EA pin is high and the program counter is within on-chip ROM area. PSEN PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/ data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. RST RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS GROUND: Ground potential VDD POWER SUPPLY: Supply voltage for operation. P0.0−P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory. The Port 0 is also an opendrain port and external pull-ups need to be connected while in programming. P1.0−P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture control P2.0−P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate functions, which are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output P3.0−P3.7 INT0 (P3.2) : External Interrupt 0 INT1 (P3.3) : External Interrupt 1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input WR (P3.6) :External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe P4.0−P4.3 PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O port or external interrupt input sources ( INT2 / INT3 ). -5- Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B 5. BLOCK DIAGRAM P1.0 ~ P1.7 Port 1 Port 1 Latch B ACC INT2 Port 0 Latch Interrupt INT3 T2 T1 Timer 2 Timer 0 Port 0 P0.0 ~ P0.7 Port 2 P2.0 ~ P2.7 DPTR PSW Stack Pointer ALU Temp Reg. Timer 1 PC Incrementor UART Addr. Reg. P3.0 ~ P3.7 Port 3 Port 3 Latch SFR RAM Address Instruction Decoder & Sequencer 256 bytes RAM & SFR ROM Port 2 Latch Bus & Clock Controller P4.0 ~ P4.3 Port 4 Port 4 Latch Watchdog Timer Oscillator Reset Block XTAL1 XTAL2 ALE PSEN RST -6- Power control Vcc Vss W78E54B/W78E054B 6. FUNCTIONAL DESCRIPTION The W78E54B architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. 6.1 Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. 6.2 New Defined Peripheral In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt INT2 , INT3 has been added to either the PLCC or QFP 44-pin package. And description follows: 6.2.1 INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software -7- Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B Eight-source interrupt information VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 - External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 - Serial Port 23H 4 IE.4 - Timer/Counter 2 2BH 5 IE.5 - External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3 INTERRUPT SOURCE 6.2.2 PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 , INT3 ). Example: P4 MOV MOV SETB CLR 6.2.3 REG 0D8H P4, #0AH ; Output data "A" through P4.0−P4.3. A, P4 ; Read P4 status to Accumulator. P4.0 ; Set bit P4.0 P4.1 ; Clear bit P4.1 Reduce EMI Emission Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. The AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation circuitry, W78E54B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. -8- W78E54B/W78E054B ***AUXR - Auxiliary register (8EH) - - - - - - - AO POF GF1 GF0 PD IDL AO: Turn off ALE output. 6.3 Power-off Flag ***PCON - Power control (87H) POF: - - Power off flag. Bit is set by hardware when power on reset. It can be cleared by software to determine chip reset is a warm boot or cold boot. GF1, GF0: These two bits are general-purpose flag bits for the user. PD: Power down mode bit. Set it to enter power down mode. IDL: Idle mode bit. Set it to enter idle mode. The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. 6.4 Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will be disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 6 5 4 3 2 1 0 ENW CLRW WIDL - - PS2 PS1 PS0 Mnemonic: WDTC Address: 8FH ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows: -9- Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B PS2 PS1 PS0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 PRESCALER SELECT 0 0 1 1 0 1 0 1 2 4 8 16 32 64 128 256 The time-out period is obtained using the following equation: 1 × 2 14 × PRESCALER × 1000 × 12 mS OSC Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. ENW WIDL IDLE EXTERNAL RESET OSC PRESCALER 1/12 14-BIT TIMER CLEAR CLRW Watchdog Timer Block Diagram Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD 0 0 0 19.66 mS 0 1 0 39.32 mS 0 0 1 78.64 mS 0 1 1 157.28 mS 1 0 0 314.57 mS 1 0 1 629.14 mS 1 1 0 1.25 S 1 1 1 2.50 S - 10 - INTERNAL RESET W78E54B/W78E054B 6.5 Clock The W78E54B is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78E54B relatively insensitive to duty cycle variations in the clock. The W78E54B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. 6.6 Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a reset. 6.7 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E54B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. 7. ON-CHIP FLASH EPROM CHARACTERISTICS The W78E54B has several modes to program the on-chip Flash EPROM. All these operations are configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0, P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these operations. 7.1 Read Operation This operation is supported for customer to read their code and the Security bits. The data will not be valid if the Lock bit is programmed to low. 7.2 Output Disable Condition When the OE is set to high, no data output appears on the D7..D0. 7.3 Program Operation - 11 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B This operation is used to program the data to Flash EPROM and the security bits. Program operation is done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high. 7.4 Program Verify Operation All the programming data must be checked after program operations. This operation should be performed after each byte is programmed; it will ensure a substantial program margin. 7.5 Erase Operation An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash EPROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to Vep level, CE set to low, and OE set to high. 7.6 Erase Verify Operation After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase margin. This operation will be done after the erase operation if Vpp = Vep (14.5V), CE is high and OE is low. 7.7 Program/Erase Inhibit Operation This operation allows parallel erasing or programming of multiple chips with different data. When P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So, except for the P3.6 and P3.7 pins, the individual chips may have common inputs. P3.0 OPERATIONS P3.1 P3.2 P3.3 (A9 (A13 (A14 (OE CTRL) CTRL) CTRL) CTRL) P3.6 P3.7 EA P2, P1 P0 ( CE ) ( OE ) (VPP) (A15..A0) (D7..D0) Read 0 0 0 0 0 0 1 Output Disable 0 0 0 0 0 1 1 X Hi-Z Program 0 0 0 0 0 1 VCP Address Data In Program Verify 0 0 0 0 1 0 VCP Address Data Out Erase 1 0 0 0 0 1 VEP A0:0, others: X Erase Verify 1 0 0 0 1 0 VEP Address Data Out Program/Erase Inhibit X 0 0 0 1 1 VCP/ VEP Address Data Out Notes: 1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH. 2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss. 3. The program verify operation follows behind the program operation. 4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits. 5. The erase verify operation follows behind the erase operation. - 12 - NOTE X Data In 0FFH X @3 @4 @5 W78E54B/W78E054B 8. SECURITY BITS During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those operations on it are described below. The W78E54B has a Security Register which can not be accessed in normal mode. These registers can only be accessed from the Flash EPROM operation mode. Those bits of the Security Register can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by address #0FFFFh. 16KB On-chip ROM 0000h Program Memory B7 Reserved B2 B1 B0 3FFFh Security Bits Reserved B0 : Lock bit, logic 0 : active B1 : MOVC inhibit, logic 0 : the MOVC instruction in external memory cannot access the code in internal memory. logic 1 : no restriction. B2 : Encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable B7 : Osillator Control logic 0 : 1/2 gain logic 1 : Full gain Default 1 for all security bits. Security Register 0FFFFh Reserved bits must be kept in logic 1. Special Setting Register 8.1 Lock Bit This bit is used to protect the customer's program code in the W78E54B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data and Special Setting Register can not be accessed again. 8.2 MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. 8.3 Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. - 13 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B +5V +5V V DD A0 to A7 P0 P1 V IL P3.0 V IL P3.1 V IL V IL V IL P3.2 P3.3 V IH P3.7 EA/Vpp V DD PGM DATA V CP ALE V IL RST V IH PSEN V IH P3.6 X'tal1 P2 A0 to A7 V IL V IL P3.0 V IL V IL P3.2 P3.3 V IH V IL P3.6 EA/Vpp P3.1 P3.7 X'tal2 Vss Vss Programming Configuration V CP ALE V IL RST V IH PSEN V IH X'tal1 A8 to A15 X'tal2 PGM DATA P0 P1 A8 to A15 P2 Programming Verification 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX. UNIT VDD−VSS -0.3 +7.0 V Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 D.C. Characteristics (VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.) PARAMETER SYMBOL TEST CONDITIONS Operating Voltage VDD - Operating Current IDD IIDLE Idle Current Power Down Current Input Current P1, P2, P3, P4 Logical 1-to-0 Transition Current P1, P2, P3 (*1), P4 IPWDN PECIFICATION UNIT MIN. MAX. 4.5 5.5 V No load, VDD = 5.5V, RST = 1 - 20 mA Idle mode VDD = 5.5V - 6 mA Power-down mode VDD = 5.5V - 50 µA IIN1 VDD = 5.5V VIN = 0V or VDD -50 +10 µA ITL VDD = 5.5V VIN = 2.0V (*1) -550 - µA - 14 - W78E54B/W78E054B DC Characteristics, continued PARAMETER Input Current RST (*2) Input Leakage Current P0, EA Output Low Voltage P1, P2, P3, P4 Output Low Voltage ALE, PSEN , P0 (*3) Output High Voltage P1, P2, P3, P4 Output High Voltage (*3) ALE, PSEN , P0 Input Low Voltage (Except RST) Input Low Voltage RST (*4) Input Low Voltage XTAL1 (*4) Input High Voltage (Except RST) Sink Current P1, P2, P3, P4 Input High Voltage RST (*4) Input High Voltage XTAL1 (*4) Sink Current P0, ALE, PSEN Source Current P1, P2, P3, P4 Source Current (*3) P0, ALE, PSEN (*3) SYMBOL TEST CONDITIONS SPECIFICATION MIN. MAX. UNIT IIN2 VDD = 5.5V VIN = VDD -10 +300 µA ILK VDD = 5.5V 0V < VIN < VDD -10 +10 µA VOL1 VDD = 4.5V IOL1 = +2 mA - 0.45 V VOL2 VDD = 4.5V IOL2 = +4 mA - 0.45 V VOH1 VDD = 4.5V IOH1 = -100 µA 2.4 - V VOH2 VDD = 4.5V IOH2 = -400 µA 2.4 - V VIL1 VDD = 4.5V 0 0.8 V VIL2 VDD = 4.5V 0 0.8 V VIL3 VDD = 4.5V 0 0.8 V VIH1 VDD = 4.5V 2.4 VDD +0.2 V ISK1 VDD = 4.5V Vs = 0.45V 4 12 mA VIH2 VDD = 4.5V 0.67 VDD VDD +0.2 V VIH3 VDD = 4.5V 0.67 VDD VDD +0.2 V ISK2 VDD = 4.5V Vs = 0.45V 8 16 mA ISR1 VDD = 4.5V Vs = 2.4V -100 -250 uA ISR2 VDD = 4.5V Vs = 2.4V -8 -14 mA Notes: *1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. *2. RST pin has an internal pull-down resistor. *3. P0, ALE, PSEN are in the external access memory mode. *4. XTAL1 is a CMOS input and RST is a Schmitt trigger input. - 15 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B 9.3 A.C. Characteristics The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers. 9.3.1 Clock Input Waveform XTAL1 T CH T CL F OP, PARAMETER TCP SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. 9.3.2 Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP -∆ - - nS 4 Address Hold from ALE Low TAAH 1 TCP -∆ - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP -∆ - - nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP -∆ 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP -∆ 3 TCP - nS 4 Notes: 1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "∆" (due to buffer driving delay and wire loading) is 20 nS. - 16 - W78E54B/W78E054B 9.3.3 Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP -∆ - 3 TCP +∆ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP -∆ 6 TCP - nS 2 Notes: 1. Data memory access time is 8 TCP. 2. "∆" (due to buffer driving delay and wire loading) is 20 nS. 9.3.4 Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP -∆ - 3 TCP +∆ nS Data Valid to WR Low TDAD 1 TCP -∆ - - nS Data Hold from WR High TDWD 1 TCP -∆ - - nS WR Pulse Width TDWR 6 TCP -∆ 6 TCP - nS Note: "∆" (due to buffer driving delay and wire loading) is 20 nS. 9.3.5 Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. 9.3.6 Program Operation PARAMETER SYMBOL MIN. TYP. MAX. UNIT VPP Setup Time TVPS 2.0 - - µS Data Setup Time TDS 2.0 - - µS Data Hold Time TDH 2.0 - - µS Address Setup Time TAS 2.0 - - µS Address Hold Time TAH 0 - - µS - 17 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B Program Operation, continued PARAMETER SYMBOL MIN. TYP. MAX. UNIT CE Program Pulse Width for Program Operation TPWP 290 300 310 µS OECTRL Setup Time TOCS 2.0 - - µS OECTRL Hold Time TOCH 2.0 - - µS OE Setup Time TOES 2.0 - - µS OE High to Output Float TDFP 0 - 130 nS Data Valid from OE TOEV - - 150 nS Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and the PSEN pin must pull in VIH status. 10. TIMING WAVEFORMS 10.1 Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH TPDA TPDH, TPDZ PORT 0 Code A0-A7 Data A0-A7 - 18 - Code A0-A7 Data A0-A7 S6 W78E54B/W78E054B Timing Waveforms, continued 10.2 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 A8-A15 DATA A0-A7 PORT 0 T DAR T DDA T DDH, T DDZ RD T DRD 10.3 Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 PORT 0 A8-A15 A0-A7 DATA OUT T DWD TDAD WR T DAW T DWR - 19 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B Timing Waveforms, continued 10.4 Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS T PDA T PDH DATA OUT PORT INPUT SAMPLE 10.5 Program Operation Program P2, P1 VIH (A15... A0) VIL P3.6 VIH (CE) VIL P3.3 (OECTRL) VIH P3.7 VIH (OE) VIL P0 (A7... A0) VIH Vpp Program Verify TPWP TAH TOCS TOCH TOES TDFP TDH D OUT Data In TDS Vcp VIH Address Valid Address Stable TAS VIL VIL Read Verify TOEV TVPS - 20 - Data Out W78E54B/W78E054B 11. TYPICAL APPLICATION CIRCUITS 11.1 Expanded External Program Memory and Crystal VDD VDD 31 19 10 u CRYSTAL 8.2 K XTAL1 R 18 XTAL2 9 C1 EA RST C2 12 13 14 15 INT0 INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 A15 GND 1 RD WR PSEN ALE TXD RXD 17 16 29 30 11 10 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 11 G 74373 2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND 20 CE 22 OE 27512 W78E54B Figure A CRYSTAL C1 C2 R 16 MHz 30P 30P - 24 MHz 15P 15P - 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 4.7K Above table shows the reference values for crystal applications (full gain). Note: C1, C2, R components refer to Figure A. - 21 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B Typical Application Circuits, continued 11.2 Expanded External Data Memory and Oscillator VDD VDD 31 XTAL1 18 XTAL2 9 RST 12 13 14 15 INT0 10 u OSCILLATOR 8.2 K EA 19 1 2 3 4 5 6 7 8 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 38 37 36 35 34 33 32 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 RD 17 16 29 30 11 10 WR PSEN ALE TXD RXD AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 11 G 74373 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 20 22 27 CE OE WR 20256 W78E54B Figure B - 22 - D0 11 D1 12 D2 13 D3 15 D4 16 D5 17 D6 18 D7 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 W78E54B/W78E054B 12. PACKAGE DIMENSIONS 12.1 40-pin DIP Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 E1 a A1 Base Plane Seating Plane L B e1 eA a B1 0.155 0.160 3.81 3.937 0.016 0.018 0.022 0.406 0.457 0.559 0.048 0.050 0.054 1.219 1.27 1.372 0.008 0.010 0.014 0.203 2.055 2.070 4.064 0.254 0.356 52.20 52.58 0.610 14.986 15.24 15.494 0.590 0.600 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794 0.120 0.130 0.140 3.048 3.302 3.556 15 0 0.670 16.00 16.51 17.01 0.630 0.650 15 0.090 2.286 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . parting line. are determined at the mold 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. c A A2 0.150 Notes: E S 0.254 0 eA S 20 1 5.334 0.210 0.010 12.2 44-pin PLCC HD D 6 1 44 40 7 Symbol 39 E 17 HE GE 29 18 28 c L b b1 4.699 0.508 3.81 3.937 0.66 0.711 0.813 0.406 0.457 0.559 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 3.683 1.27 BSC 16.00 0.590 0.610 0.630 14.99 15.49 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 0.10 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ e 0.185 0.020 Notes: A2 A Seating Plane A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. A1 y GD - 23 - Publication Release Date: August 14, 2006 Revision A6 W78E54B/W78E054B Package Dimensions, continued 12.3 44-pin PQFP HD D Symbol 34 44 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e b 22 Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 13.45 0.510 0.520 0.530 12.95 13.2 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 0.08 0.003 0 7 0 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. A2 A Seating Plane See Detail F A1 y θ L L1 Detail F - 24 - --- 0.025 Notes: c Max. --- --- 7 W78E54B/W78E054B 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A3 December, 2000 - Formerly issued A4 June, 2004 3 Revise part number in the item of packages A5 April 20, 2005 25 Add Important Notice A6 August 14, 2006 3 Add lead-free(RoHS) parts Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 25 - Publication Release Date: August 14, 2006 Revision A6